Vishay DG884AM 8 x 4 wideband video crosspoint array Datasheet

DG884
Vishay Siliconix
8 x 4 Wideband Video Crosspoint Array
FEATURES
BENEFITS
Routes Any Input to Any Output
Wide Bandwidth: 300 MHz
Low Crosstalk: −85 dB @ 5 MHz
Double Buffered TTL-Compatible
Latches with Readback
D Low rDS(on): 45 D Optional Negative Supply
D
D
D
D
D
D
D
D
D
D
D
APPLICATIONS
Reduced Board Space
Improved System Bandwidth
Improved Channel Off-Isolation
Simplified Logic Interfacing
Allows Bipolar Signal Swings
Reduced Insertion Loss
High Reliability
D Wideband Signal Routing and
Multiplexing
D High-End Video Systems
D NTSC, PAL, SECAM Switchers
D Digital Video Routing
D ATE Systems
DESCRIPTION
The DG884 contains a matrix of 32 T-switches configured in
an 8
4 crosspoint array. Any of the IN/OUT pins may be
used as an input or output. Any of the IN pins may be switched
to any or simultaneously to all OUT pins.
The DG884 is built on a proprietary D/CMOS process that
combines low capacitance switching DMOS FETs with low
power CMOS control logic and drivers. The ground lines
between adjacent signal input pins help to reduce crosstalk.
The low on-resistance and low on-capacitance of the DG884
make it ideal for video and wideband signal routing.
Control data is loaded individually into four Next Event latches.
When all Next Event latches have been programmed, data is
transferred into the Current Event latches via a SALVO
command. Current Event latch data readback is available to
poll array status.
Output disable capabilities make it possible to parallel multiple
DG884s to form larger switch arrays. DIS outputs provide
control signals used to place external buffers in a power saving
mode.
For additional information see applications note AN504
(FaxBack document number 70610).
FUNCTIONAL BLOCK DIAGRAM
IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8
OUT1
OUT2
8 4 Switch Matrix
OUT3
OUT4
Decode Logic, Switch Drivers
Current Event Latches
WR
CS
B1
RS
SALVO
I/O Control
Logic
Next Event Latches
B0
I/O A3
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
4 Disable Outputs
A2 A1
A0
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1
DG884
Vishay Siliconix
IN2
3
2
OUT4
GND
4
OUT3
GND
GND
5
OUT2
GND
IN 1
6
OUT1
GND
GND
PIN CONFIGURATION AND ORDERING INFORMATION
1 44 43 42 41 40
7
39
DGND
GND
8
38
VL
IN3
9
37
RS
GND
10
36
SALVO
IN4
11
35
WR
GND
12
PLCC and CLCC
34
A3
IN5
13
33
A2
GND
Top View
14
32
A1
IN6
15
31
A0
GND
16
30
CS
17
29
I/O
IN7
ORDERING INFORMATION
Temp Range
Package
Part Number
−40 to 85_C
44-Pin PLCC
DG884DN
−55 to 125_C
44-Pin CLCC
DG884AM/883
B1
B0
V+
DIS 4
DIS 3
DIS 2
DIS 1
V−
IN8
GND
GND
18 19 20 21 22 23 24 25 26 27 28
TRUTH TABLE I
RS
I/O
CS
WR
1
0
1
1
0
0
1
0
0
1
0
0
1
0
X
1
1
0
0
X
1
0
X
1
1
0
0
0
0
Both next and Current Event latches are transparent
1
1
1
1
1
A0, A1, A2, A3 − High impedance
1
1
0
1
1
A0, A1, A2, A3 become outputs and reflect the contents of the Current Event latches. B0, B1
determine which Current Event latches are being read
0
X
X
1
1
All crosspoints opened (but data in Next Event latches is preserved)
0
SALVO
Actions
1
No change to Next Event latches
1
Next Event latches loaded as defined in table below
1
Next Event latches are transparent.
1
Next Event data latched-in
Data in all Next Event latches is simultaneously loaded into the Current Event latches, i.e., all
new crosspoint addresses change simultaneously when SALVO goes low.
0
Current Event latches are transparent
Current Event data latched-in
All other states are not recommended.
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Document Number: 70071
S-52433—Rev. G, 20-Dec-04
DG884
Vishay Siliconix
TRUTH TABLE II
WR
B1
0
0
B0
0
1
A3
A2
A1
A0
Next Event Latches
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN1 to OUT1 Loaded
IN2 to OUT1 Loaded
IN3 to OUT1 Loaded
IN4 to OUT1 Loaded
IN5 to OUT1 Loaded
IN6 to OUT1 Loaded
IN7 to OUT1 Loaded
IN8 to OUT1 Loaded
0
X
X
X
Turn Off OUT1 Loaded
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN1 to OUT2 Loaded
IN2 to OUT2 Loaded
IN3 to OUT2 Loaded
IN4 to OUT2 Loaded
IN5 to OUT2 Loaded
IN6 to OUT2 Loaded
IN7 to OUT2 Loaded
IN8 to OUT2 Loaded
0
X
X
X
Turn Off OUT2 Loaded
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN1 to OUT3 Loaded
IN2 to OUT3 Loaded
IN3 to OUT3 Loaded
IN4 to OUT3 Loaded
IN5 to OUT3 Loaded
IN6 to OUT3 Loaded
IN7 to OUT3 Loaded
IN8 to OUT3 Loaded
0
X
X
X
Turn Off OUT3 Loaded
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN1 to OUT4 Loaded
IN2 to OUT4 Loaded
IN3 to OUT4 Loaded
IN4 to OUT4 Loaded
IN5 to OUT4 Loaded
IN6 to OUT4 Loaded
IN7 to OUT4 Loaded
IN8 to OUT4 Loaded
0
X
X
X
Turn Off OUT4 Loaded
0
1
1
Note:
0
1
When WR = 0 Next Event latches are transparent. Each crosspoint is addressed individually, e.g., to connect IN1 to OUT1 thru OUT4
requires A0, A1, A2 = 0 to be latched with each combination of B0, B1. When RS = 0, all four DIS outputs pull low simultaneously.
ABSOLUTE MAXIMUM RATINGS
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 21 V
V+ to V− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 21 V
V− to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 0.3 V
VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to (V+) + 0.3 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V−) − 0.3 V to (VL) + 0.3 V
or 20 mA, whichever occurs first
VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V−) − 0.3 V to (V−) + 14 V
or 20 mA, whichever occurs first
CURRENT (any terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
CURRENT (S or D) Pulsed 1 ms 10% duty . . . . . . . . . . . . . . . . . . . . . . 40 mA
Storage Temperature
(A Suffix) . . . . . . . . . . . . . . . . . . . . −65 to 150_C
(D Suffix) . . . . . . . . . . . . . . . . . . . . −65 to 125_C
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
Operating Temperature
(A Suffix) . . . . . . . . . . . . . . . . . . . . −55 to 125_C
(D Suffix) . . . . . . . . . . . . . . . . . . . . . −40 to 85_C
Power Dissipation (Package)a
44-Pin Quad J Lead PLCCb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
44-Pin Quad J Lead Hermetic CLCCc . . . . . . . . . . . . . . . . . . . . . . . . 1200 mW
Notes:
a. All leads soldered or welded to PC board.
b. Derate 6 mW/_C above 75_C.
c. Derate 16 mW/_C above 75_C.
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DG884
Vishay Siliconix
SPECIFICATIONSa
Test Conditions
Unless Specified
Parameter
Symbol
V+ = 15 V, V− = −3 V
VL = 5 V, RS = 2.0 V
SALVO, CS, WR, I/O = 0.8 V
VANALOG
V− = −5 V
Tempb
Typc
A Suffix
D Suffix
−55 to 125_C
−40 to 85_C
Mind
Maxd
Mind
8
−5
Maxd
Unit
8
V
Analog Switch
Analog Signal Rangee
Drain-Source On-Resistance
rDS(on)
Full
−5
Room
Full
45
90
120
90
120
Room
3
9
9
rDS(on)
IS = −10 mA, VD = 0 V
VAIH = 2
2.0
0V
V, VAIL = 0.8
08V
Sequence Each Switch On
Source Off Leakage Current
IS(off)
VS = 8 V, VD = 0 V,
RS = 0.8 V
Room
Full
−20
−200
20
200
−20
−200
20
200
Drain Off Leakage Current
ID(off)
VS = 0 V, VD = 8 V,
RS = 0.8 V
Room
Full
−20
−200
20
200
−20
−200
20
200
Total Switch On
Leakage Current
ID(on)
VS = VD = 8 V
Room
Full
−20
−2000
20
2000
−20
−200
20
200
2
Resistance Match
Between Channels
nA
Digital Input/Output
Input Voltage High
VAIH
Full
Input Voltage Low
VAIL
Full
Address Input Current
Address Output Current
DIS Pin Sink Current
2
0.8
IAI
VAI = 0 V or 2 V or 5 V
Room
Full
0.1
IAO
VAO = 2.7 V, See Truth Table
Room
−600
VAO = 0.4 V, See Truth Table
Room
1500
Room
1.5
1 In to 1 Out, See Figure 11
Room
30
1 In to 4 Out, See Figure 11
Room
120
Room
8
20
20
Room
10
20
20
IDIS
−1
−10
1
10
0.8
−1
−10
−200
500
V
1
10
−200
A
500
mA
Dynamic Characteristics
On State Input Capacitancee
CS(on)
Off State Input Capacitancee
CS(off)
Off State
Output Capacitancee
CD(off)
Transition Time
tTRANS
Break-Before-Make Interval
tOPEN
SALVO, WR Turn On Time
tON
SALVO, WR Turn Off Time
tOFF
Charge Injection
See Figure 11
See Figure 5
RL= 1 k , CL = 35 pF
50% Control to 90% Output
See Figure 3
10
10
Room
Full
300
500
300
Room
Full
175
300
175
Room
−100
Matrix Disabled Crosstalk
XTALK(DIS)
RIN = RL = 75 f = 5 MHz, See Figure 10
Room
−82
Adjacent Input Crosstalk
XTALK(AI)
RIN = 10 , RL = 10 k
f = 5 MHz, See Figure 9
Room
−85
All Hostile Crosstalk
XTALK(AH)
RIN = 10 , RL = 10 k
f = 5 MHz, See Figure 8
Room
−66
BW
RL = 50 , See Figure 7
Room
300
4
pF
300
Full
See Figure 6
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160
Room
Q
Bandwidth
40
ns
pC
dB
MHz
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
DG884
Vishay Siliconix
SPECIFICATIONSa
Test Conditions
Unless Specified
Parameter
V+ = 15 V, V− = −3 V
VL = 5 V, RS = 2.0 V
SALVO, CS, WR, I/O = 0.8 V
A Suffix
D Suffix
−55 to 125_C
−40 to 85_C
Tempb
Typc
Room
Full
1.5
Room
Full
−1.5
−3
−5
−3
−5
IDG
Full
−275
−750
−750
IL
Full
200
Symbol
Mind
Maxd
Mind
Maxd
Unit
Power Supplies
Positive Supply Current
I+
Negative Supply Current
I−
Digital GND Supply Current
Logic Supply Current
V+ to V−
Functional O
Operating S
Supply Voltage Rangee
V− to GND
V+ to GND
All Inputs At GND or 2 V
RS = 2 V
See Operating Voltage Range
((Typical
yp
Characteristics))
page 6
3
6
3
6
500
500
Full
13
20
13
20
Full
−5.5
0
−5.5
0
Full
10
20
10
20
mA
A
V
Minimum Input Timing Requirements
Address Write Time
tAW
Full
20
50
50
Minimum WR Pulse Width
tWP
Full
50
100
100
Write Address Time
tWA
Full
−10
10
10
Chip Select Write Time
tCW
Full
50
100
100
Write Chip Select Time
tWC
Full
25
75
75
Minimum SALVO
Pulse Width
tSP
Full
50
100
100
SALVO Write Time
tSW
Full
−10
10
10
Write SALVO Time
tWS
Room
20
Input Output Time
tIO
Room
150
200
200
Address Output Time
tAO
Room
150
200
200
Chip Select Output Time
tCO
Room
150
200
200
Chip Select Address Time
tCA
Room
60
Reset to SALVO
tRS
Full
I/O Address Input Time
tIA
Room
See Figure 1
ns
50
100
50
50
50
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
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DG884
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Adjacent Input Crosstalk
120
100
X TALK(DIS)(−dB)
100
X TALK(AI) (−dB)
Matrix Disabled Crosstalk
120
80
60
40
80
60
40
20
20
1
10
100
1
10
f − Frequency (MHz)
All Hostile Crosstalk
100
Operating Voltage Area
21
19
V+ − Positive Supply (V)
X TALK(AH) (−dB)
80
60
40
20
17
15
Operating Voltage Area
13
11
0
1
10
f − Frequency (MHz)
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6
100
f − Frequency (MHz)
100
9
0
−1
−2
−3
−4
−5
−6
V− − Negative Supply (V)
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
DG884
Vishay Siliconix
TIMING DIAGRAMS
CS for
Device A
Presetting Device A
Don’t Care
CS for
Device B
Address
B0 − B1
Select Output 1
Address
A0 − A3
Don’t Care
Presetting Device B
tCA
Input
Select Output 2
Output N
Select Input
Input
Select Input
tAW
WR
tIA
tWA
tWP
tAW
tWA
SALVO
tCW
tWA
tAW
tWS
tSW
tSW
tWC
tWS
tCW
tSP
I/O
tSP
RS
Reset Occuring at Any Time Results In All Current Event Latches Being Cleared
tRS
FIGURE 1. Input Timing Requirements
CS for
Device A
Interrogating Device A
CS for
Device B
Interrogating Device B
tC
Address
B0 − B1
O
tC
Select Current
Event Latch 1
Latch N
tAO
Address
A0 − A3
Output
tAO
Address Output 1
tCA
O
tC
A
Select Current
Event Latch
tAO
Out N
tAO
Address Output
WR
SALVO
tIO
tIA
I/O
RS
Reset Occuring at Any Time Results In All Current Event Latches Being Cleared
FIGURE 2. Output Timing Requirements
PARAMETER DEFINITIONS
Symbol
Parameter
TAW
Address to Write
Minimum time address must be valid before WR goes high
Description
Minimum time address must remain valid after WR pulse goes high
TWA
Write to Address
TWP
WR Pulse
TCW
Chip Select to WR
Minimum time chip select must be valid before a WR pulse
TWC
WR to Chip Select
Minimum time chip select must remain valid after WR pulse
TSP
SALVO Pulse
Minimum time of SALVO pulse width
TWS
WR to SALVO
Minimum time from WR pulse to SALVO to load new address
TSW
SALVO to WR
Minimum time from SALVO pulse to WR to load current address
TIA
I/O to Address In
TRS
RS to SALVO
Minimum time RS must be valid before SALVO pulse
TIO
I/O to Output
Minimum time I/O must be valid before address output valid
TAO
Address to Output
TCO
CS to Output
TCA
CS to Address In
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
Minimum time of WR pulse width to write address into Next Event latches
Minimum time I/O must be valid before address applied
Minimum time address BX must be valid until address AX output valid
Minimum time CS must be valid until AX output is valid
Minimum time CS must be valid before address applied if I/O is high
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DG884
Vishay Siliconix
TEST CIRCUITS
−3 V
VL
V−
1V
5V
15 V
V+
IN1
VO
3V
OUT1
GND
DGND
IN2 − IN8
1 k
DG884
A0, A1, A2
0V
SALVO
3V
35 pF
0V
50%
50%
1V
90%
VO
SALVO
A0, A1, A2
B0 B1 I/O CS WR A3 RS
90%
tOFF
tON
3V
FIGURE 3. SALVO Turn On/Off Time
−3 V
VL
V−
1V
5V
15 V
V+
IN1
3V
VO
OUT1
GND
DGND
IN2 − IN8
1 k
DG884
WR
A0, A1, A2
B0 B1 I/O CS SALVO
1V
V−
IN1
3V
50%
50%
35 pF
90%
1V
A3 RS
90%
tON
tOFF
FIGURE 4. WR Turn On/Off Time
15 V
V+
3V
VO
OUT1
GND
A0, A1, A2
0V
VO
DGND
IN8
WR
VO
5V
VL
0V
0V
3V
−3 V
A0, A1, A2
1 k
DG884
50%
90%
IN2 − IN7
tTRANS
WR
A0, A1, A2
B0 B1 I/O CS SALVO
tBBM
A3 RS
3V
FIGURE 5. Transition Time and Break-Before-Make Interval
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Document Number: 70071
S-52433—Rev. G, 20-Dec-04
DG884
Vishay Siliconix
TEST CIRCUITS
−3 V
5V
VL
V−
IN1
15 V
−3 V
V+
VO
OUT1
GND
DGND
A3
Signal
Generator
50 15 V
VL
V−
IN8
V+
VO
OUT1
GND
35 pF
DG884
5V
DGND
50 DG884
WR
WR
A0,
A1,
A2 B B I/O CS SALVO RS
0
1
A0 − A3
B0 B1 I/O CS SALVO WR RS
A3
VO
5V
5V
Q = V0 CL
FIGURE 6. Charge Injection
Any one input to any one
output—all remaining
inputs connected to
remaining outputs
FIGURE 7. −3 dB Bandwidth
Any input or output pin to
adjacent input or output
pin
VO
Outputs
10 k
RL
10 k
RL
10 k
RIN
10 Vn − 1
Vn
RIN
10 Inputs
Signal
Generator
75 V
Signal
Generator
75 X TALK(AH) + 20 log 10
V OUT
RIN
10 X TALK(AI) + 20 log10
V
FIGURE 8. All Hostile Crosstalk
All crosspoints open
Vn + 1
Vn – 1
Vn
or 20 log10
Vn ) 1
Vn
FIGURE 9. Adjacent Input Crosstalk
VO
Outputs
IN3
DG884
5V
−3 V
15 V
CS
“0” = Off-State
“1” = On-State
V OUT
V
FIGURE 10. Matrix Disabled Crosstalk
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
V+
X TALK(DIS) + 20 log10
I/O
V−
Signal
Generator
75 IN7
VL
RS
IN 8
IN6
GND
DGND
IN4
IN5
V
OUT 4
OUT 3
IN2
OUT 2
HP4192A
Impedance
Analyzer
or Equivalent
OUT 1
Meter
Inputs
IN 1
RL
75 FIGURE 11. On-State and Off-State Capacitances
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DG884
Vishay Siliconix
PIN DESCRIPTION
Pin
Symbol
1, 3, 4, 6, 8, 10, 12, 14, 16,
18, 20, 41, 43
GND
39
DGND
26
V+
Positive Supply Voltage
21
V−
Negative Supply Voltage
38
VL
Logic Supply Voltage—generally 5 V
5, 7, 9, 11, 13, 15, 17, 19
IN1 to IN8
2, 40, 42, 44
OUT1 to OUT4
29
I/O
Determines whether data is being written into the Next Event latches or read from the Current Event latches
Chip Select—a logic input
30
CS
31, 32, 33, 34
A0, A1, A2, A3
27, 28
B0, B1
35
WR
36
SALVO
37
RS
22, 23, 24, 25
DIS1 to DIS4
Description
Analog Signal Ground
Digital Ground
8 Analog Input Channels
4 Analog Output Channels
IN Address—logic inputs or outputs as defined by I/O pin, select one of eight IN channels
OUT Address—logic inputs, select one of four OUT channels
Write command that latches A0, A1, A2, A3 into the Next Event latches
Master write command, that in one action, transfers all the data from Next Event latches into
Current Event latches
Reset—a low will clear the Current Event latches
Open drain disable outputs—these outputs pull low when the corresponding OUT channel is off
DEVICE DESCRIPTION
The DG884 is the world’s first monolithic wideband crosspoint
array that operates from dc to >100 MHz. The DG884 offers
the ability to route any one of eight input signals to any one of
four OUT pins. Any input can be routed to one, two, three or
four OUTs simultaneously with no risk of shorting inputs
together (guaranteed by design).
Upon completing all crosspoint connections that are to be
changed in a single device, other DG884s can be similarly
preset by taking the CS pin low on the appropriate device.
When all DG884s are preset, the Current Event latches are
simultaneously changed by a single SALVO command applied
to all devices. In this manner the crosspoint configuration of
any number of devices can be simultaneously updated.
Each crosspoint is configured as a “T” switch in which DMOS
FETs are used due to their excellent low resistance and low
capacitance characteristics. Each OUT line has a series
switch that minimizes capacitive loading when the OUT is off.
DIS Outputs
Interfacing
Four open drain disable OUTs are provided to control external
line drivers or to provide visual or electrical signaling. For
example, any or all of the DIS OUTs can directly interface with
a CLC410 Video Amplifier to place it into a high impedance,
low-power standby mode when the corresponding OUT is not
being used. (See Figure 15). The DIS outputs are low and sink
to V− when corresponding OUT is open or RS is low.
The DG884 was designed to allow complex matrices to be
developed while maintaining a simple control interface. The
status of the I/O pin determines whether the DG884 is being
written to or read from (see Figures 1 and 2).
In order to WRITE to an individual latch, CS and I/O need to
be low, while RS, WR and SALVO must be high. The IN to OUT
path is selected by using address A0 through A3 to define the
IN line and address B0 and B1 to define the OUT line. That is,
The IN defined by A0 through A3 is electrically connected to the
OUT defined by B0, B1. This chosen path is loaded into the
Next Event latches when WR goes low and returns high again.
This operation is repeated up to three more times if other
crosspoint connections need to be changed.
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10
Reset
The reset function (RS) allows the resetting of all crosspoints
to a known state (open). At power up, the reset facility may be
used to guarantee that all switches are open. It should be
noted that RS clears the Current Event latches, but the Next
Event latches remain unchanged. This useful facility allows
the user to return the matrix to its previous state (prior to reset)
by simply applying the SALVO command. Alternatively, the
user can reprogram the Next Event latches, and then apply the
SALVO command to reconfigure the matrix to a new state.
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
DG884
Vishay Siliconix
DEVICE DESCRIPTION
monitor the state of the matrix. If a power loss to the controller
occurs, the readback feature helps the matrix to recover
rapidly. It also offers a means to perform PC board diagnostics
both in production and in system operation.
Readback
The I/O facility enables the user to write data to the Next Event
latches or to read the contents of the Current Event latches.
This feature permits the central controller to periodically
8 Analog Inputs
CMOS Output Buffers
EN
4
/
Data
Buffers
Mux 2
EN
4
7
/
Latch 3
Current Event
Next Event
Latch 3
4
/
Q0 − Q3
Decoders/
Drivers
9
/
8 T-Switches
1 Series Switch
OUT3
8
B0
B1
CS
Mux 4
WR
OUT2
8
RS
A0
A1
A2
A3
OUT1
8
/
I/O
Mux 1
OUT4
DIS3
Open Drain
Output
Mux 3 Decoder
SALVO
One of Four Blocks of Logic/Latches Shown
FIGURE 12. Control Circuitry
APPLICATIONS
WR
Two—Si584
Quad Unity-Gain Buffers
IN1
SALVO
CLC410
x2
x1
75 IN2
75 OUT1
DIS1
x1
x2
OUT2
x2
OUT3
x2
OUT4
DIS2
DG884
DIS3
IN8
x1
DIS4
RS
RESET
B0 B1 A0 A1 A2 A3
Note: DIS outputs are used to
power down the Si582 amplifiers.
FIGURE 13. Fully Buffered 8 X 4 Crosspoint
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
www.vishay.com
11
DG884
Vishay Siliconix
APPLICATIONS
+5 V
+15 V
51 51 6
+
C1
+
C1
VL
C2
5
V th − Logic Threshold (V)
C2
V+
DG884
V−
C1
C2
−3 V
3
2
1
+
51 4
0
0
C1 = 1 F Tantalum
C2 = 100 nF Ceramic
A useful feature of the DG884 is its power supply flexibility. It
can be operated from dual supplies, or a single positive supply
(V− connected to 0 V) if required. Allowable operating voltage
ranges are shown in Operating Voltage Range (Typical
Characteristics) graph, page 6.
4
6
8
10
12
14
16
18
VL − Logic Supply (V)
FIGURE 14. DG884 Power Supply Decoupling
Power Supplies and Decoupling
2
FIGURE 15. Switching Threshold Voltage vs. VL
of the DG884 is adversely affected by poor decoupling of
power supply pins. Also, since the substrate of the device is
connected to the negative supply, proper decoupling of this pin
is essential.
Rules:
Note that the analog signal must not go below V− by more than
0.3 V (see absolute maximum ratings). However, the addition
of a V− pin has a number of advantages:
1)
Decoupling capacitors should be incorporated on all
power supply pins (V+, V−, VL ).
2)
They should be mounted as close as possible to the
device pins.
1)
It allows flexibility in analog signal handling, i.e. with
V− = −5 V and V+ = 15 V, up to "5-V ac signals can be
accepted.
3)
Capacitors should have good high frequency characteristics—tantalum bead and/or monolithic ceramic
disc types are suitable.
2)
The value of on-capacitance [CS(on) ] may be reduced
by increasing the value of V−. It is useful to note that
optimum video differential phase and gain occur when
V− is −3 V. Note that V+ has no effect on CS(on) .
3)
V− eliminates the need to bias an ac analog signal
using potential dividers and large decoupling capacitors.
It is established RF design practice to incorporate sufficient
bypass capacitors in the circuit to decouple the power supplies
to all active devices in the circuit. The dynamic performance
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12
Recommended decoupling capacitors are 1- to 10-F
tantalum bead, in parallel with 100-nF monolithic ceramic.
4)
Additional high frequency protection may be provided
by 51- carbon film resistors connected in series with
the power supply pins (see Figure 14).
The VL pin permits interface to various logic types. The device
is primarily designed to be TTL or CMOS logic compatible with
+5 V applied to VL. The actual logic threshold can be raised
simply by increasing VL.
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
DG884
Vishay Siliconix
APPLICATIONS
A typical switching threshold versus VL is shown in Figure 15.
Layout
These devices feature an address readback facility whereby
the last address written to the device may be read by the
system. This allows improved status monitoring and hand
shaking without additional external components.
The PLCC package pinout is optimized so that large
crosspoint arrays can be easily implemented with a minimum
number of PCB layers (see Figure 16). Crosstalk is minimized
and off-isolation is optimized by having ground pins located
adjacent to each input and output signal pins. Optimum
off-isolation and low crosstalk performance can only be
achieved by the proper use of RF layout techniques: avoid
sockets, use ground planes, avoid ground loops, bypass the
power supplies with high frequency type capacitors (low ESR,
low ESL), use striplines to maintain transmission line
impedance matching.
When the I/O assigns the address output condition, the AX
address pins can sink or source current for logic low and high,
respectively. Note that VL is the logic high output condition.
This point must be respected if VL is varied for input logic
threshold shifting.
Video
Out Bus
Address Bus
Video
Out Bus
Address Bus
Note: Even though these devices are designed to be latchup
resistant, VL must not exceed V+ by more than 0.3 V in
operation or during power supply on/off sequencing.
Video
In Bus
Video
In Bus
Video
In Bus
Video
In Bus
Video
Out Bus
Video
Out Bus
FIGURE 16. 16 X 8 Expandable Crosspoint Matrix Using DG884
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
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13
Legal Disclaimer Notice
Vishay
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc.,
or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Vishay for any damages resulting from such improper use or sale.
Document Number: 91000
Revision: 08-Apr-05
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1