ON NCV8851-1 Automotive grade synchronous buck controller Datasheet

NCV8851-1
Automotive Grade
Synchronous Buck
Controller
The NCV8851−1 is an adjustable output, synchronous buck
controller, which drives dual N−channel MOSFETs, ideal for high
power applications. Average current mode control is employed for
very fast transient response and tight regulation over wide input
voltage and output load ranges. The IC incorporates an internal fixed
6.0 V low−dropout linear regulator (LDO), which supplies charge to
the switch mode power supply’s (SMPS) bottom gate driver, limiting
the power lost to excess gate drive. The IC is designed for operation
over a wide input voltage range (4.5 V to 40 V) and is capable of 10 to
1 voltage conversion at 500 kHz.
Additional controller features include undervoltage lockout,
internal soft−start, low quiescent current sleep mode, programmable
frequency, SYNC function, average current limiting, cycle−by−cycle
overcurrent protection and thermal shutdown.
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TSSOP−20
SUFFIX DB
CASE 948E
MARKING DIAGRAM
Features
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V88
51−1
ALYWG
G
Average Current Mode Control
0.8 V ±2% Reference Voltage
Wide Input Voltage Range of 4.5 V to 40 V
Operates through Load Dump Conditions
6.0 V Low−dropout Linear Regulator (LDO)
Input UVLO (Undervoltage Lockout)
Internal Soft−start
1.0 mA Maximum Quiescent Current in Sleep Mode
Adaptive Non−overlap Circuitry
180 ns Minimum High−side Gate Off−time
Programmable Fixed Frequency – 170 kHz to 500 kHz
External Clock Synchronization up to 600 kHz
Average Current Limiting (ACL)
Cycle−by−Cycle Overcurrent Protection (OCP)
Thermal Shutdown (TSD)
This is a Pb−Free Device
V8851−1 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
NCV8851−1DBR2G TSSOP−20
(Pb−Free)
Shipping†
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
• Automotive Systems Requiring High Current
• Pre−regulated Supply for Low−voltage SMPSs and LDOs
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 2
1
Publication Order Number:
NCV8851−1/D
NCV8851−1
VIN 12
EN 11
VIN_IC
3
SYNC
1
ROSC 20
Enable
TSD Fault
UVLO Logic
LDO
Enable
Fault
Soft Start
VSS
Fixed−Frequency
Oscillator
Ramp
Clock
Max
Duty
BST
5
GH
6
VSW
7
GL
8
PGND
2
VIN_CS
Nonoverlap
6VOUT
OCP
BST
VOCP
CEA
4
VREF
Min
On
Time
R
Q
Reset
Dominant
PWM
Fault
CCOMP 15
6VOUT
+
Q
S
9
LDO
ILIMIT
+
19 CSP
CSA
CFB 16
18 CSN
CSOUT 17
+
VEA
VCOMP 14
VREF
VACL
+
VSS
ACL
10 AGND
VFB 13
VCLAMP
Figure 1. Functional Block Diagram
VIN
VIN
EN
VIN_IC
SYNC
ROSC
12
9
11
6VOUT
+
DBST
3
4
1
+
VIN
BST
Q1
GH
−
CBST
5
20
ROSC
6
VSW
Q2
7
8
CCOMP
19
CC1
RC1
CFB
CC2
RC2
CSOUT
18
13
14
10
C
VIN_CS
−
CSP
CSN
RF1
VFB
CV2
VCOMP
RV1
CV1
AGND
Figure 2. Application Schematic
Note: This part is recommended for synchronous use only.
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2
+
VOUT
PGND
16
17
RS
GL
2
15
+
L
RF0
NCV8851−1
PACKAGE PIN DESCRIPTIONS − 20 Lead TSSOP
Package Pin#
Pin Symbol
Function
1
SYNC
External clock synchronization input.
2
VIN_CS
Supply input for the internal current sense amplifier.
3
VIN_IC
Supply input for internal logic and analog circuitry.
4
BST
Supply input for the floating top gate driver. An external diode, DBST, from 6VOUT and a
0.1 mF to 1 mF capacitor, CBST, to VSW forms a boost circuit.
5
GH
Gate driver output for the external high−side NMOS FET.
6
VSW
Switch−node. This pin connects to the source of the high−side MOSFET and drain of the
low−side MOSFET. This pin serves as the switch output to the inductor.
7
GL
8
PGND
Gate driver output for the external low−side NMOS FET.
Power Ground. Ground reference for the high−current path including the NMOS FETs and
output capacitor.
9
6VOUT
Output of internal fixed 6.0 V LDO.
10
AGND
Analog Ground. Ground reference for the internal logic and analog circuitry as well as ROSC
and the compensators.
11
EN
Enable input. When disabled, the LDO, internal logic and analog circuitry and gate drivers
enter sleep mode, drawing under 1 mA.
12
VIN
Supply input for the SMPS.
13
VFB
SMPS’s voltage feedback. Inverting input to the voltage error amplifier. Connect to VOUT
through a resistive divider.
14
VCOMP
SMPS’s voltage error amplifier output and non−inverting input to the current error amplifier.
15
CCOMP
SMPS’s current error amplifier output and inverting input to the PWM comparator.
16
CFB
17
CSOUT
18
CSN
Differential current sense amplifier inverting input.
19
CSP
Differential current sense amplifier non−inverting input.
20
ROSC
Oscillator’s frequency adjust pin. Resistor to ground sets the oscillator frequency.
SMPS’s current feedback. Inverting input to the current error amplifier.
Single−ended output of the differential current sense amplifier. Connect to CFB through a
resistor. Non−inverting input to the cycle−by−cycle overcurrent comparator.
MAXIMUM RATINGS (Voltages are with respect to AGND unless otherwise indicated.)
Rating
Dc Supply Voltage (VIN)
Peak Transient Voltage (Load Dump)
Dc Supply Voltage (VIN_CS)
Dc Supply Voltage (VIN_IC)
Value
Unit
−0.3 to 40
45
V
46
V
6.5
V
−0.7 to 40.7
−2
V
46 wrt PGND
7 wrt VSW
V
Pin Voltage (GL)
−0.3 to 7 wrt PGND
V
Pin Voltage (EN)
−0.3 to 40
V
Pin Voltage (CSP, CSN)
−0.3 to 10
V
Pin Voltage (VFB, VCOMP, CSOUT, CFB, CCOMP, SYNC, ROSC, 6VOUT)
−0.3 to 7
V
Pin Voltage (VSW)
t ≤ 50 ns
Pin Voltage (BST, GH)
Pin Voltage (PGND)
−0.3 to 0.3
V
Operating Junction Temperature
−40 to 150
°C
Storage Temperature Range
−65 to 150
°C
265 peak
°C
Peak Reflow Soldering Temperature: Lead−free 60 to 150 seconds at 217°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
NCV8851−1
ATTRIBUTES
Characteristic
Value
ESD Capability
Human Body Model (Boost, VIN_CS)
Human Body Model (All Others)
Machine Model
Charge Device Model
≥ 1.0 kV
≥ 1.5 kV
≥ 200 V
≥ 1.0 kV
Package Thermal Resistance
Junction–to–Ambient, RqJA (Note 1)
Junction–to–Ambient, RqJA (Note 2)
156°C/W
108°C/W
1. 50 mm2, 1.0 oz copper on FR4 board.
2. 500 mm2, 1.0 oz copper on FR4 board.
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 4.5 V < VIN < 40 V, 4.5 V < BST < 46 V, ROSC = 51.1 kW, unless otherwise specified)
Conditions
Min
Typ
Max
Unit
VIN = 13.2 V, EN = 0 V, Sleep Mode
−40°C < TA < 125°C
−
−
1
mA
VIN = 13.2 V, VFB = 1 V
EN = 5 V, No Switching
−
2.0
3.0
mA
VIN = 13.2 V, VFB = 0 V
EN = 5 V, Switching
−
3.2
5.0
mA
VIN = 13.2 V, VFB = 0 V, EN = 5 V
Switching, 3.3 nF on GH and GL
−
10
20
mA
Thermal Shutdown
Guaranteed by Design
150
180
210
°C
Thermal Shutdown Hysteresis
Guaranteed by Design
−
10
20
°C
Undervoltage Lockout (VIN_IC)
VIN_IC increasing
4.1
4.3
4.5
V
50
125
200
mV
0.784
0.8
0.816
V
110
180
250
ns
Static Operating
−
140
200
ns
ROSC = 51.1 kW
ROSC = 23.2 kW
ROSC = 16.2 kW
153
306
425
170
360
500
187
414
575
kHz
kHz
kHz
0.9
1.1
1.3
V
Characteristic
GENERAL
Quiescent Current
(IVIN + IVIN_CS + IBST)
LDO Current
Undervoltage Lockout Hysteresis
SWITCHING REGULATOR
Reference Voltage
Minimum GH Off Time
Minimum GH Pulse Width
OSCILLATOR
Switching Frequency
Ramp Voltage Amplitude
VOLTAGE ERROR AMPLIFIER
DC Gain
Guaranteed by Design
70
73
−
dB
Gain−Bandwidth Product
Guaranteed by Design
8.0
10
−
MHz
Charge Currents
Source, VCOMP = 0 V
2
4
−
mA
Sink, VCOMP = 1.75 V
1.3
3
−
mA
Guaranteed by Design
−
0.1
1.0
mA
0
−
10.0
V
−
1
−
V/V
FB Bias Current
CURRENT SENSE AMPLIFIER
Common−Mode Range
Amplifier Gain
0 ≤ (CSP−CSN) ≤ 100 mV
0 V ≤ CSN ≤ 10.0 V
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4
NCV8851−1
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 4.5 V < VIN < 40 V, 4.5 V < BST < 46 V, ROSC = 51.1 kW, unless otherwise specified)
Characteristic
Conditions
Min
Typ
Max
Unit
CURRENT ERROR AMPLIFIER
DC Gain
Guaranteed by Design
70
73
−
dB
Gain−Bandwidth Product
Guaranteed by Design
8.0
10
−
MHz
Source, CCOMP = 1.75 V
2
4
−
mA
Sink, CCOMP = 1.75 V
1.3
3
−
mA
Guaranteed by Design
−
0.1
1.0
mA
2.7
3.5
−
V
80
100
125
mV
115
165
215
mV
−
200
−
ns
20
−
−
mV
FSW
−
600
kHz
VSYNC = 0 V
VSYNC = 5.0 V
−
−
0.1
10
0.2
20
mA
Logic Low
Logic High
−
2.0
−
−
0.8
−
V
Output Voltage
IOUT = 20 mA
5.8
6.0
6.2
V
Dropout Voltage
IOUT = 20 mA
−
−
200
mV
30
75
120
mA
VGH = 2 V, VIN_IC = 6 V, Guaranteed by Design
VGH = 4 V, VIN_IC = 6 V, Guaranteed by Design
−
1.5
−
A
−
1.5
−
A
VIN_IC = 6 V
VGL = 1.0 V
Guaranteed by Design
−
1.5
−
A
−
1.5
−
A
GH to GL Delay
VIN = 13.2 V
−
40
70
ns
GL to GH Delay
VIN = 13.2 V
−
40
70
ns
FSW = 170 kHz
−
14
−
ms
Input Threshold
Logic Low
Logic High
−
2.0
−
−
0.8
−
V
Input Current
EN = 2.0 V
−
3.0
10
mA
−
−
20
ms
Charge Currents
FB Bias Current
Clamping Voltage
CURRENT LIMIT
Average Current Limit Threshold
1.2 V ≤ CSN ≤ 10.0 V
Cycle−by−Cycle Current Limit
Threshold Voltage
Cycle−by−Cycle Current Limit
Response Time
Guaranteed by Design
Cycle−by−Cycle and Average Current Limit Threshold Difference
SYNC
SYNC Frequency Range
SYNC Pin Bias Current
SYNC Threshold Voltage
6.0 V LDO
Current Limit
GATE DRIVERS
GH Sink Current
GH Source Current
GL Sink Current
GL Source Current
SOFT START
Time
ENABLE (EN)
Minimum Disable Time
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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5
NCV8851−1
TYPICAL CHARACTERISTICS
(TA = +25°C, VIN = 13.2 V, ROSC = 51.1 kW, unless otherwise noted)
100%
90%
4.0
20
3.5
18
3.0
16
Top Gate
Bottom Gate
70%
60%
50%
Fall Time (ns)
Driver Current (mA)
Soft Start Time (%)
80%
2.5
2.0
1.5
40%
30%
170
12
10
1.0
220
270
320
370
420
470
8
170
Switching Frequency (kHz)
Top Gate
220
270
320
370
420
470
0
1
2
Switching Frequency (kHz)
Figure 3. Soft−start Time vs.
Frequency
38
14
Figure 4. Driver Quiescent
Current vs. Frequency
Switching
105%
Bottom Gate
33
3
4
Load Capacitance (nF)
Figure 5. Driver Fall Time vs. Load
Capacitance
No Switching
1
95%
0.8
Operating Current (%)
Rise Time (ns)
23
18
Shutdown Current (μA)
85%
28
75%
65%
0.4
0.2
55%
13
45%
8
0
1
2
3
0
−50
4
0
50
100
150
−50
Ambient Temperature (°C)
Load Capacitance (nF)
0
50
100
Figure 7. Operating Quiescent
Current vs. Temperature
Figure 8. Sleep Mode Quiescent
Current vs. Temperature
101%
101%
100.5%
99%
98%
100%
100.0%
V REF
100%
99%
99.5%
98%
97%
−50
0
50
100
150
Ambient Temperature (°C)
Figure 9. Average Current−Limit
Threshold vs. Temperature
150
Ambient Temperature (°C)
Figure 6. Driver Rise Time vs.
Load Capacitance
Cycle−by−Cycle OCP Threshold (%)
Average Current Limit Threshold (%)
0.6
99.0%
−50
0
50
100
Ambient Temperature (°C)
Figure 10. Cycle−by−Cycle
Overcurrent Protection
Threshold vs. Temperature
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6
150
−50
0
50
100
Ambient Temperature (°C)
Figure 11. VREF vs. Temperature
150
NCV8851−1
TYPICAL CHARACTERISTICS
(TA = +25°C, VIN = 13.2 V, ROSC = 51.1 kW, unless otherwise noted)
170 kHz
102%
360 kHz
500 kHz
70
GH to GL
108%
GL to GH
65
101%
106%
60
Minimum Pulse Width (%)
50
Delay (ns)
Switching Frequency (%)
55
100%
99%
45
40
98%
35
30
104%
102%
100%
97%
25
20
96%
−50
0
50
100
98%
−50
150
0
50
100
−50
150
Figure 12. Oscillator Frequency
vs. Temperature
(Ω)
120
100
110
Dropout Voltage (mV)
Output Capacitor ESR
99.75%
150
130
UNSTABLE
100.00%
100
Figure 14. GH Minimum Pulse
Width vs. Temperature
1000
100.25%
50
Ambient Temperature (°C)
Figure 13. Non−Overlap Delay vs.
Temperature
100.50%
6V OUT (V)
0
Ambient Temperature (°C)
Ambient Temperature (°C)
STABLE
10
1
100
90
80
70
UNSTABLE
(0.1uF only)
60
99.50%
0.00
0.1
5.00
10.00
15.00
20.00
50
0
5
LDO Load Current (mA)
15
20
Figure 16. LDO Stability Region
93%
80
60
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Load Current (A)
Figure 18. Efficiency vs. Load
Current 5 V, 170 kHz Demo Board
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7
0
50
100
150
Figure 17. LDO Dropout Voltage vs.
Temperature
100
0.0
−50
Ambient Temperature (°C)
LDO Load Current (mA)
Efficiency (%)
Figure 15. LDO Load Regulation
10
NCV8851−1
DETAILED OPERATING DESCRIPTION
General
inductor current is limited via average current limiting
(ACL) and cycle−by−cycle overcurrent protection (OCP).
Thermal shutdown (TSD) is also implemented to protect the
device from overheating.
The NCV8851−1 is a synchronous buck controller with
internal 1.5 A gate drivers designed to drive NMOS FETs.
The internal gate drivers simplify design, improve
performance and efficiency and minimize board area. The
controller uses an 800 mV, 2.0% reference, allowing for a
wide range of precise output voltage programmability.
The NCV8851−1 also provides a programmable fixed
frequency range of 170 kHz to 500 kHz, allowing more
design flexibility in compromising efficiency versus
components’ size and cost. This frequency is conveniently
set with an external resistor to ground. An external clock
signal can also be used to synchronize the NCV8851−1 to a
higher operating frequency during operation.
To protect against possible damage of external
power−stage components, excessive inrush of current
during start−up is prevented by an internal soft−start, and
Average Current Mode Control
The NCV8851−1 employs an average current mode
control (ACMC) architecture to regulate the output voltage.
ACMC uses two loops, as seen in Figure 19. Through the
current error amplifier (CEA), the inner current loop
monitors the inductor current with the unity gain current
sense amplifier (CSA). The current loop responds to input
voltage changes, affecting the line transient response. Using
the voltage error amplifier (VEA), the outer voltage loop
monitors the output voltage, responding to output load
changes, affecting the load transient response. Feedback
resistors in the voltage loop select the output voltage.
Outer Voltage Loop
VSW
VOUT
C
−
Inner
Current
Loop
+
PWM
and
Gate Drivers
RS
L
RL
CSA
Gain=1
−
−
CEA
+
VEA
+
VREF
Figure 19. ACMC Loops
CEA. The voltage loop also has a pair of feedback resistors
from VOUT to set the output voltage and gain of the VEA.
Unlike voltage mode control (VMC) of buck regulators,
which almost always require the extra components of a
Type−III compensation network for adequate transient
response, ACMC buck regulators use Type−II
compensation. This greatly simplifies the compensator
design and optimization process, while offering much faster
transient response than a Type−I compensation network.
Additionally, the two−loop system separates the effects of
output components between the two loops, further
simplifying the compensation process.
Type−II compensation places a zero and two poles in each
of the error loops to offset the effects of the inherent
open−loop response. This compensation requires a resistor
and two capacitors in the feedback loop for each of the error
amplifiers, shown as complex impedances in Figure 19. An
input resistor from the CSA to the CEA sets the gain of the
Enable
The enable input (EN) is a TTL−compatible input used to
activate the internal LDO. The NCV8851−1 is disabled
when the EN pin is pulled below the enable input logic low
threshold voltage, causing a normal shutdown to occur,
putting the part into a low quiescent current sleep mode.
Once the device has been disabled it must remain disabled
for the minimum disable time (20 ms) or abnormal startup
behavior may be observed after enable is asserted. When the
EN pin is pulled above the enable input logic high threshold
voltage, the part is enabled, the LDO output is brought up
and then the internal soft−start begins.
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8
NCV8851−1
VIN
to support the internal rails and power the controller. The IC
will start up when enabled and VIN_IC surpasses the UVLO
threshold and will shutdown when VIN_IC drops below the
UVLO threshold minus the UVLO hysteresis. While VIN is
less than the set point for VOUT, the output will run at max
duty cycle, after soft−start, once VIN_IC surpasses the
UVLO threshold. If EN is high and not tied to VIN, the
output will begin to rise up while in UVLO, if a minimum
output load of 1 kW is not met.
REN
EN
Internal
Enable
125 kΩ
DZEN2
22 V
DZEN1
5.4 V
Thermal Shutdown
The NCV8851−1 provides Thermal Shutdown (TSD),
which monitors the die temperature and turns off the top and
bottom gate drivers if an over temperature condition is
detected, for added protection. The internal soft−start
capacitor is also discharged. A normal soft−start will occur
when the die temperature falls below the TSD threshold
minus the TSD hysteresis.
Figure 20. Enable Pin Equivalent Structure
The EN pin can be tied to VIN in order to enable the part.
If EN is above 22 V, DZEN2 will be conducting, as well as
DZEN1. The current to DZEN1 is limited by an internal
125 kW resistor. If DZEN2 is conducting, it is recommended
at least 250 mA is pulled through this diode. The resistor REN
must be used if VIN can go above 20 V as follows.
R EN(max) +
Duty Cycle and Maximum Pulse Width Limits
In steady state dc operation, the duty cycle will stabilize
at an operating point defined by the ratio of the input to the
output voltage. There is a built in minimum off−time which
ensures that the bootstrap supply is charged every cycle,
determining the maximum duty cycle at a given frequency.
The NCV8851−1 can achieve at least a 95% duty cycle
while operating at frequencies up to 200 kHz (89% at up to
500 kHz).
VZ
250 mA
Where VZ is the amount of volts where DZEN2 is conducting,
but not yet supplied with 250 mA. For example, setting VZ
to 1 V means REN must be less than 4 kW for DZEN2 to have
at least 250 mA when VIN is at least 23 V; for the range of VIN
between 22 V and 23 V, DZEN2 will be conducting, but not
with the recommended 250 mA current.
Internal Soft−Start
The NCV8851−1 features an internal soft−start function,
which reduces inrush current and overshoot of the output
voltage. Figures 21 and 22 show a typical soft−start
sequence.
UVLO
Undervoltage Lockout (UVLO) is provided to ensure that
unexpected behavior does not occur when VIN_IC is too low
VIN
UVLO
Threshold
Soft−start Time
VSW
6VOUT
and
VIN_IC
90%*VOUT
t
VOUT
Figure 22. Switch−node in Soft−Start
10%*VOUT
Soft−start Delay
t
Figure 21. Normal Start−up
causing the soft−start time to be inversely related to the
frequency set by ROSC. The internal soft−start capacitor is
discharged when the part is disabled, enters TSD or enters
UVLO, ensuring a proper start−up when the part is
re−enabled, leaves TSD or leaves UVLO.
Soft−start is achieved by ramping up the internal soft−start
voltage (VSS), which is applied to the non−inverting input of
the voltage error amplifier, effectively limiting the slew rate
of VOUT rising. This ramp is generated by charging an
internal soft−start capacitor based on the internal oscillator,
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9
NCV8851−1
The 6VOUT pin should be externally connected through a
low leakage (< 100 mA at Tmax) diode to the BST pin,
charging the BST capacitor during off−time to generate a
voltage for the high−side driver. When the part is enabled
and VIN is below the LDO regulated value, the LDO is in
dropout and it tracks VIN. The LDO regulates its output once
VIN is above the output set point plus the dropout voltage.
An external bypass capacitor must be connected from
6VOUT to ground. A short to ground or overcurrent
condition on the 6VOUT pin will be mitigated by the LDO
current limit and internal thermal shutdown (TSD) circuitry
which disables all outputs. A normal soft−start will occur
when the die temperature falls below the TSD threshold.
This sequence begins once VIN_IC surpasses its UVLO
threshold when the part is enabled and the LDO output has
risen. After an initial delay to assure a clean start−up,
switching begins, the output initially rises quickly and then
rises monotonically. The duty cycle is gradually increased
until VOUT has reached its set point or until maximum duty
cycle is reached.
Normal Shutdown Behavior and Sleep Mode
Normal shutdown occurs when the IC stops switching
because the input supply drops below the UVLO threshold,
the part enters TSD or the part is disabled. When disabled,
the part enters sleep mode.
In sleep mode, the LDO turns off and its output capacitor
discharges, causing switching to stop, the internal soft−start
capacitor to discharge and GH and GL to go low. The switch
node enters a high impedance state and the output inductor
and capacitors discharge through the load. The supply
current reduces to the sleep mode quiescent current.
Drivers
The NCV8851−1 includes 1.5 A gate drivers to switch
external N−Channel MOSFETs. This allows the
NCV8851−1 to address high−power, as well as low−power
conversion requirements. The gate drivers also include
adaptive non−overlap circuitry. The non−overlap circuitry
increases efficiency, which minimizes power dissipation, by
minimizing the body diode conduction time, while
protecting against cross−conduction (shoot−through) of the
MOSFETs. A detailed block diagram of the non−overlap
and gate drive circuitry used in the chip and related external
components is shown in Figure 23.
Internal Linear Regulator (LDO)
The NCV8851−1 has an onboard low−dropout linear
regulator (LDO) internally connected to drive the low−side
gate. The 6VOUT pin should be externally connected to the
VIN_IC pin to power the internal rails. Typically, a RC filter
is used from 6VOUT to VIN_IC to further decrease noise on
the internal rails.
BST
MainFault
GH
GL to GH
Delay
VSW
VSW
GL
Threshold
VSW
Threshold
GH to GL
Delay
PWM
Output
6VOUT
GL
Main
Fault
PGND
Figure 23. Gate Driver Block Diagram
Since the BST capacitor only recharges when the
low−side MOSFET is on, pulling VSW down to ground, the
NCV8851−1 has a minimum off−time. This also means that
the BST capacitor cannot be arbitrarily large, since 6VOUT
needs to be able to charge it up during this minimum
off−time so the high−side gate driver doesn’t run out of
headroom. 6VOUT needs to supply charge both to the BST
capacitor and also the low−side driver, so the LDO capacitor
must be sufficiently larger than the BST capacitor. A 1 mF
LDO capacitor is recommended.
A capacitor is placed from VSW to BST and a diode is
placed from 6VOUT to BST to create a bootstrap supply on
the BST pin for the high−side floating gate driver. This
ensures that the voltage on BST is about 6VOUT higher than
VSW, less a diode drop, yielding a gate drive voltage high
enough to enhance the high−side MOSFET. The BST
capacitor supplies the charge used by the gate driver to
charge up the input capacitance of the high−side MOSFET,
and is typically chosen to be at least a decade larger than this
capacitance. A 0.1 mF BST capacitor is recommended.
www.onsemi.com
10
NCV8851−1
above the ACL threshold. This causes the PWM pulse to be
terminated very quickly and disables the part from switching
back on until the current through the inductor has dropped
below the OCP threshold. Once the inductor current is below
the OCP threshold, the part will begin switching again and
the current will be limited by ACL, until the inductor current
drops below the ACL threshold.
An advantage of this current limiting scheme is that the
NCV8851−1 will limit large transient currents yet resume
normal operation on the following cycle. Additionally, the
current will not run away, nor will the part latch off in case
of a short, which is typical of other current limiting schemes
employing high−side current sensing.
Careful selection and layout of external components is
required to realize the full benefit of the onboard drivers.
The capacitors between VIN and GND and between BST
and VSW must be placed as close as possible to the IC. The
current paths for the GH and GL connections must be
optimized, minimizing parasitic resistance and inductance.
Current Limiting and Overcurrent Protection
The NCV8851−1 contains average current limiting
(ACL) and cycle−by−cycle overcurrent protection (OCP) to
protect the power switches, inductor, current sense resistor
and other external components. The current through the
inductor is continuously sensed using the CSP and CSN
pins. A sense resistor is placed between these pins to
translate the output current to a proportional voltage. This
voltage is compared to a fixed internal voltage threshold.
When the differential voltage exceeds the ACL threshold,
the PWM pulse is terminated for this cycle, limiting the
current through the inductor. In steady−state operation,
decreasing the load resistance while in ACL will cause the
duty cycle and VOUT to decrease proportionally without
skipping pulses or jitter.
There is also a fast OCP path which is tripped when the
differential voltage exceeds the OCP threshold, which is
SYNC Feature
An external clock signal can synchronize the NCV8851−1
to a higher frequency. The rising edge of the SYNC pulse
turns on the power switch to start a new switching cycle, as
shown in Figure 24. There is a 0.5 ms delay between the
rising edge of the SYNC pulse and rising edge of the VSW
pin voltage. The SYNC threshold is TTL logic compatible,
and duty cycle of the SYNC pulses can vary from 10% to
90%. The SYNC frequency must be higher than the internal
oscillator frequency set by ROSC.
Figure 24. Synchronization from 170 kHz to an external 600 kHz signal
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11
NCV8851−1
APPLICATIONS INFORMATION
Design Methodology
leading to decreased efficiency, especially noticeable at light
loads.
Typically, the switching frequency is selected to avoid
interfering with signals of known frequencies. Often, in this
case, the frequency can be programmed to a lower value
with ROSC and then a higher−frequency signal can be
applied to the SYNC pin to increase the frequency
dynamically to avoid given frequencies. A spread spectrum
signal could also be used for the SYNC input, as long as the
lowest frequency in the range is above the programmed
frequency set by ROSC. Additionally, the highest SYNC
frequency must not exceed maximum switching frequency
limits.
There are two limits on the maximum allowable switching
frequency: minimum off−time and minimum on−time.
These set two different maximum switching frequencies, as
follows:
Choosing external components for the NCV8851−1
encompasses the following design process:
1. Define operational parameters
2. Select switching frequency
3. Select current sensor
4. Select output inductor
5. Select output capacitors
6. Select input capacitors
7. Select compensator components
(1) Operational Parameter Definition
Before proceeding with the rest of the design, certain
operational parameters must be defined. These are
application−dependent and include the following:
VIN: input voltage, range from minimum to
maximum with a typical value [V]
VOUT: output voltage [V]
IOUT: output current, range from minimum to
maximum with initial start−up value [A]
ICL: desired typical current−limit [A]
A number of basic calculations must be performed
up−front to use in the design process, as follows:
V OUT
V IN(typ)
D MAX +
1 * D MAX
T MinOff
F SW(max)2 +
D MIN
T MinOn
Where: FSW(max)1: maximum switching frequency due to
minimum off−time [Hz]
TMinOff: minimum off−time [s]
FSW(max)2: maximum switching frequency due to
minimum on−time [Hz]
TMinOn: minimum on−time [s]
Alternatively, the minimum and maximum operational
input voltage can be calculated as follows:
V OUT
D MIN +
V IN(max)
D+
F SW(max)1 +
V OUT
V IN(min)
Where: DMIN: minimum duty cycle (ideal) [%]
VIN(max): maximum input voltage [V]
D: typical duty cycle (ideal) [%]
VIN(typ): typical input voltage [V]
DMAX: maximum duty cycle (ideal) [%]
VIN(min): minimum input voltage [V]
It should be noted that these are the ideal duty cycles; the
actual duty cycles will be marginally higher than these
calculated values. The actual duty cycles are dependent on
load due to voltage drops in the MOSFETs, inductor and
current sensor.
V IN(min) +
V OUT
1 * T MinOff @ F SW
V IN(max) +
V OUT
T MinOn @ F SW
Where: FSW: switching frequency [Hz]
The switching frequency is programmed by selecting the
resistor connected between the ROSC pin and ground. The
grounded side of this resistor should be directly connected
to the AGND pin. Avoid running any noisy signals under the
resistor, since injected noise could cause frequency jitter.
The graph in Figure 25 shows the required resistance to
program the frequency. From 150 to 450 kHz, the following
formula is accurate to within 3%:
(2) Switching Frequency Selection
Selecting the switching frequency is a trade−off between
component size and power losses. Operation at higher
switching frequencies allows the use of smaller inductor and
capacitor values to achieve the same inductor current ripple
and output voltage ripple. However, increasing the
frequency increases the switching losses of the MOSFETs,
R OSC + 8687000
F SW
Where: ROSC: frequency program resistor [W]
Some specific values for switching frequency with
standard 1% resistors can be seen in Table 1.
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12
NCV8851−1
600
perspective, smaller inductor values generally correspond to
smaller physical size. Since the inductor is often one of the
largest components in the power supply, a minimum
inductor value is particularly important in space−
constrained applications. From an electrical perspective, an
inductor is chosen for a set amount of current ripple and to
assure adequate transient response.
Larger inductor values limit the switcher’s ability to slew
current through the output inductor in response to output load
transients, impacting the dynamic response. While the
inductor is slewing current during this time, output capacitors
must supply the load current. Therefore, decreasing the
inductance allows for less output capacitance to hold the
output voltage up during a load step. Load transient
simulation is a powerful tool in anticipating this response.
For switchers with both cycle−by−cycle overcurrent
protection (OCP) and average current limiting (ACL), the
OCP and ACL references are compared to the sensed current
via sense resistance, RS. A minimum inductance is required
to prevent the OCP from tripping during the onset of ACL
during typical operation as follows:
FSW (kHz)
500
400
300
200
100
0
10
20
30
40
50
60
70
80
90
ROSC (kW)
Figure 25. Frequency vs. ROSC
Table 1. Frequency vs. ROSC
FSW (kHz)
ROSC (kW)
170
51.1
250
34.8
300
28.7
360
23.2
500
16.2
L MIN +
Where: LMIN: minimum inductance to assure OCP and ACL
do not both trip [H]
The soft−start time can be estimated as follows:
T SS [
DVCL: difference between OCP and ACL threshold
voltages [V]
For switchers that use the current signal of the inductor for
control purposes, the voltage ripple over the sense resistance
must be sufficient in magnitude to counteract the
contribution due to inherent comparator offsets and other
errors, as follows:
F0
@ T SS0
F SW
Where: TSS: soft−start time [s]
F0: specified frequency [Hz]
TSS0: soft−start time at specified frequency [s]
(3) Current Sensor Selection
L MAX +
Current sensing for average current mode control relies on
the inductor current signal. This is translated into a voltage
via a current sensor, which is then measured differentially by
the current sense amplifier, generating a single−ended
output to use as a control signal. The easiest means of
implementing this transresistance is through the use of a
sense resistor in series with the output inductor and
capacitors. A sense resistor should be selected as follows:
RS +
V OUT(1 * D)
RS
@
2 @ F SW
DV CL
V OUT @ (1 * D MAX)
RS
@
F SW
Ë L @ V CL
Where: LMAX: maximum inductance to assure adequate
voltage ripple over the sense resistance [H]
κL: inductor peak−to−peak current ripple to current
limit ratio [%]
VCL: threshold voltage for the current limit [V]
As a rule of thumb, ensuring that κL is at least 5% to 10%
has been empirically sufficient.
Smaller values of inductance increase the regulator’s
maximum achievable slew rate and decrease the necessary
capacitance, at the expense of higher ripple current, which
causes higher output voltage ripple. The peak−to−peak
ripple current is given by the following equation:
V CL
I CL
Where: RS: sense resistor [W]
VCL: current limit threshold voltage [V]
ICL: desired current limit [A]
Alternative methods, such as lossless inductor current
sensing, are feasible but beyond the scope of this document.
iL +
(4) Output Inductor Selection
V OUT @ (1 * D)
L @ F SW
Where: iL: peak−to−peak output current ripple [App]
Both mechanical and electrical considerations influence
the selection of an output inductor. From a mechanical
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13
NCV8851−1
(5) Output Capacitor Selection
The ripple current is at a maximum when the duty cycle
is at a minimum value and vice versa, as follows:
The output capacitor is a basic component for the fast
response of the power supply. During a load step, for the first
few microseconds, it supplies the current to the load. The
controller immediately recognizes the load step and
increases the duty cycle, but the current slope is limited by
the inductor’s slew rate. During a load release, the output
voltage will overshoot. The capacitance will dampen this
undesirable response, decreasing the amount of voltage
overshoot.
In the case of stepping into a short, the inductor current
approaches zero with the worst case initial current at the
current limit and the initial voltage at the output voltage set
point, calculating the voltage overshoot as follows:
V
@ (1 * D MIN)
i L(max) + OUT
L @ F SW
i L(min) +
V OUT @ (1 * D MAX)
L @ F SW
Where: iL(max): maximum inductor current ripple [App]
iL(min): minimum inductor current ripple [App]
From this equation it is clear that the ripple current
increases as L decreases, emphasizing the trade−off between
dynamic response and ripple current. The peak and valley
values of the triangular current waveform are as follows:
iL
2
i
I L(vly) + I OUT * L
2
I L(pk) + I OUT )
DV OS +
ǸL @CI
CL
2
) V OUT 2 * V OUT
Accordingly, a minimum amount of capacitance can be
chosen for a maximum allowed output voltage overshoot:
Where: IL(pk): peak (maximum) value of ripple current [A]
IL(vly): valley (minimum) value of ripple current [A]
Saturation current is specified by inductor manufacturers
as the current at which the inductance value has dropped a
certain percentage from the nominal value, typically 10%.
For stable operation, the output inductor must be chosen so
that the inductance is close to the nominal value even at the
peak output current, IL(pk). It is recommended to choose an
inductor with saturation current sufficiently higher than the
peak output current, such that the inductance is very close to
the nominal value at the peak output current. This introduces
a safety factor and allows for more optimized compensation.
Inductor efficiency is another consideration when
selecting an output inductor. Inductor losses include dc and
ac winding losses and core losses. Core losses include eddy
current losses, which are very low due to high core
resistance, and magnetic hysteresis losses, which increase
with peak−to−peak ripple current. Core losses also increase
as switching frequency increases.
Ac winding losses are based on the ac resistance of the
winding and the RMS ripple current through the inductor,
which is much lower than the dc current. The ac winding
losses are due to skin and proximity effects and are typically
much less than the dc losses, but increase with frequency. Dc
winding losses account for a large percentage of output
inductor losses and are the dominant factor at switching
frequencies at or below 500 kHz. The dc winding losses in
the inductor can be calculated with the following equation:
C MIN +
L @ I CL 2
(V OUT ) DV OS(max)) 2 * V OUT 2
Where: CMIN: minimum amount of capacitance to minimize
voltage overshoot to DVOS(max) [F]
DVOS(max): maximum allowed voltage overshoot
during a short [V]
A maximum amount of capacitance can be found based on
the inrush current and current limit. To calculate the input
startup current, the following equation can be used:
I INRUSH +
C OUT @ V OUT
) I OUT(i)
t SS
Where: IINRUSH: input current during startup
IOUT(i): initial output current
If the inrush current is higher than the steady−state input
current with the maximum load, then the input fuse should
be rated accordingly, if one is used. During soft−start, the
inductor current must provide current to the load, as well as
current to charge the output capacitor. The maximum current
which the inductor is allowed to conduct is the current limit.
Setting the inrush current to the current limit, this puts a limit
on the maximum capacitor size, as follows:
C MAX +
(I CL * I OUT(i)) @ t SS
V OUT
Where: CMAX: maximum output capacitance [F]
Capacitors should also be chosen to provide acceptable
output voltage ripple with a dc load, in addition to limiting
voltage overshoot during a dynamic response. Key
specifications are equivalent series resistance (ESR) and
equivalent series inductance (ESL). The output capacitors
must have very low ESL for best transient response. The
PCB traces will add to the ESL, but by putting the output
capacitors close to the load, this effect can be minimized and
ESL neglected in determining output voltage ripple.
P L(dc) + I OUT 2 @ R dc
Where: PL(dc) : dc winding losses in the output inductor
Rdc: dc resistance of the output inductor (DCR)
As can be seen from the above equation, to minimize
inductor losses, an inductor with very low DCR should be
chosen.
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14
NCV8851−1
capacitors must be rated to handle a ripple current of
one−half the maximum output current at the switching
frequency.
ESR is the majority cause of losses in the input capacitors.
Losses in the input capacitors can be calculated with the
following equation:
The capacitance itself causes a voltage ripple due to the
current ripple. This is as follows:
VQ + iL @
D
C @ F SW
Where: vQ: output voltage ripple due to output capacitance
[Vpp]
Also, the ripple current through the inductor causes a
voltage ripple over the output capacitor due to its ESR as
follows:
P CIN + I IN(RMS) 2 @ R ESR(CIN)
Where: PCIN = power loss in the input capacitors
RESR(CIN) = effective series resistance of the input
capacitance
Due to large current transients through the input
capacitors, electrolytic, polymer or ceramics should be used.
If a tantalum must be used, it must be surge protected, to
prevent against capacitor failure. Due to the large ripple
current, it is common to put small ceramic capacitors in
parallel with the bulk input capacitors, which will handle a
significant portion of the ripple current. A value of 0.01 mF
to 0.1 mF placed near the MOSFETs is recommended.
V ESR + i L @ R ESR
Where: vESR: output voltage ripple due to the effects of ESR
[Vpp]
RESR: total ESR of output capacitors [W]
Typically, the ripple due to ESR dominates, having the
largest effect on output voltage ripple. The total output
voltage ripple in steady−state operation can be calculated as
follows:
V OUT + V Q ) V ESR + Ë C @ V OUT
(7) Compensator Design
Where: vOUT: total output voltage ripple [Vpp]
κC: percent output voltage ripple [%]
Typically, the voltage ripple percentage is a performance
parameter used to decide on the desired output capacitor.
The maximum total effective ESR of the output capacitors
is calculated as follows:
R ESR(max) +
The purpose of the compensators is to stabilize the
dynamic response of the converter. By optimizing the
compensators, stable regulation with fast input line and
output load transient response is achieved.
Compensator design is related to the placement of zeros
and poles in the closed loop, in order to assure stability with
optimized transient response. The general approach is to use
some rule of thumb values and then tune them through
simulation to optimize load step response, while assuring
stability over line and load variations.
Type−II compensators are used with the two error
amplifiers in average current mode control. The CEA closes
the inner current−loop and the VEA closes the outer
voltage−loop. As a rule of thumb, a zero is placed in each
loop with the intent to compensate the effects of the double
pole from the output inductor and capacitor. Additionally, a
pole is placed at origin, due to the negative feedback, and a
pole is also placed in each loop with the intent to compensate
the effects of the double right−half−plane zero from the
current sampling function.
The crossover frequency is then set so that gain limitations
of the error amplifier are not exceeded. The compensator
must assure there is adequate phase margin in the total
closed−loop response, which can be analyzed on a
small−signal basis. Further reduction in loop gain, via
decreasing the crossover frequency, may be required to
avoid large−signal clamping limitations; this effect can be
seen in simulation and taken care of in the compensator
tuning process.
V OUT * V Q
i L(max)
Where: RESR(max): maximum allowable total ESR of output
capacitors
It should be noted that these values of ESR are at the
switching frequency and ESR decreases as frequency
increases. The steady−state power lost due to the ESR of the
output capacitor can be calculated as follows:
P C(ESR) + 1 i L 2 @ R ESR
3
(6) Input Capacitor Selection
The input capacitors have to sustain the ripple current
produced during the on time of the high−side MOSFET and
must have a low ESR to minimize the losses. The RMS value
of this ripple is:
I IN(RMS) + I OUT ǸD @ (1 * D)
Where: IIN(RMS) = input RMS current
The large majority of the ripple spectrum will be at the
switching frequency. The above equation reaches its
maximum value with D = 0.5, IIN(RMS) = IOUT/2. The input
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15
NCV8851−1
Equations for placement of pole, zero and crossover frequency follow:
Current−loop Compensator
w iz +
Voltage−loop Compensator
1
ǸL @ C
w vz +
F SW @ p
4
w ip +
w vp +
2
ǸL @ C
F SW @ p
4
w v + 2 @ w vp
w i + 2 @ w ip
feedback capacitors (CC1, CV1) in series with feedback
resistor are chosen, on the order of less than 3 nF. The values
are calculated as follows:
The implementation of the above compensators is through
a resistance on the negative input (RC2, RF1), resistor (RC1,
RV1) and capacitor (CC1, CV1) in series in feedback and
another capacitor (CC2, CV2) in feedback of an opamp. The
Current−loop Compensator
Voltage−loop Compensator
R C1 +
1
w iz @ C C1
R V1 +
1
w vz @ C V1
C CE +
1
w ip @ R C1
C VE +
1
w vp @ R V1
C C2 +
C C1
C
C
R C2 +
C1
CE
C V2 +
*1
C
1
w i @ (C C1 ) C C2)
R F1 +
The resistor divider on the negative input of the VEA also
sets the output voltage. This resistor divider is composed of
a resistor from the output voltage to the negative input of the
VEA (RF1) and a resistor from the negative input of the VEA
to ground (RF0). The bottom resistor value is calculated as
follows:
R F0 +
C V1
C
V1
VE
*1
1
w v @ (C V1 ) C V2)
Where: QTG: total high−side MOSFET gate charge at VBST
VBST: BST pin voltage
The low−side synchronous rectifier MOSFET gate driver
losses are:
P BG + Q BG @ F SW @ V CC
Where: QBG: total low−side MOSFET gate charge at VIN
The junction temperature of the controller can then be
calculated as follows:
R F1 V REF
V OUT * V REF
T J + T A ) P IC @ R qJA
Thermal Considerations
The power dissipation of the NCV8851−1 varies with the
MOSFETs used, VIN and the boost voltage (VBST). The
average MOSFET gate current typically dominates the
control IC power dissipation. The IC power dissipation can
be estimated as follows:
Where: TJ = junction temperature of the IC
TA = ambient temperature
RqJA = junction−to−ambient thermal resistance of
the IC package
The package thermal resistance (RqJA) can be obtained
from the specifications section of this data sheet and a
calculation can be made to determine the IC junction
temperature. It should be noted that the physical layout of
the board, the proximity of other heat sources such as
MOSFETs and inductors and the amount of metal connected
to the IC impact the temperature of the device. Use these
calculations as a guide, but measurements should be taken
in the actual application.
P IC + V IN @ I Q ) P HS ) P L
Where: PIC: control IC power dissipation
IQ: IC measured supply current (quiescent current)
PTG: high−side MOSFET gate driver losses
PBG: low−side MOSFET gate driver losses
The high−side switching MOSFET gate driver losses are:
P TG + Q TG @ F SW @ V BST
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16
NCV8851−1
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
L
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
17
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
NCV8851−1
ON Semiconductor and
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reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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