Newhaven NHD-2.23-12832UMB3 Oled display module Datasheet

NHD‐2.23‐12832UMB3
OLED Display Module
NHD‐
2.23‐
12832‐
UM‐
B‐
3‐
Newhaven Display
2.23” diagonal size
128 x 32 pixel resolution
Model – includes Multi‐Font chip
Emitting Color: Blue
+3V power supply
Functions and Features
•
•
•
•
•
•
128 x 32 pixel resolution
Built‐in SSD1305 controller
Parallel or serial MPU interface
Single, low voltage power supply
RoHS compliant
Multi‐Language Fonts built‐in
Newhaven Display International, Inc.
2511 Technology Drive, Suite 101
Elgin IL, 60124
Ph: 847‐844‐8795
Fax: 847‐844‐8796
www.newhavendisplay.com
[email protected]
[email protected]
[1]
Table of Contents
1. Document Revision History
2. Mechanical Drawing
3. Interface Description
3.1. Parallel Interface
3.2. Serial Interface
3.3. I2C Interface
3.4. MPU Interface Pin Selections
3.5. MPU Interface Pin Assignment Summery
4. Wiring Diagrams
5. Electrical Characteristics
6. Optical Characteristics
7. Font Content Address Table
8. Supported Languages
9. OLED controller Instruction Table
10. OLED controller to MPU interface
10.1.
6800‐MPU Parallel Interface
10.2.
8080‐MPU Parallel Interface
10.3.
Serial Interface
10.4.
I2C Interface
11. Example OLED Initialization Program code
12. Multi‐Font IC to MPU interface
12.1.
Serial Interface
12.2.
Communication Protocol
12.3.
Timing Characteristics
13. Font Tables (see file: www.newhavendisplay.com/app_notes/MultiFont.pdf )
14. Font Data Arrangement Format (see file: www.newhavendisplay.com/app_notes/MultiFont.pdf )
15. Calculation of Font Addresses (see file: www.newhavendisplay.com/app_notes/MultiFont.pdf )
16. Multi‐Font program code example
17. Quality Information
1. Document Revision History
Revision
0
1
Date
10/15/2012
11/5/2012
Description
Preliminary Release
Initial Product Release
[2]
Changed by
‐
‐
L
A
I
2. Mechanical Drawing
1
2
3
4
A
Rev
E
D
I
C6
B
16
D
6
F
N
O
C
2
Date
PIN ASSIGNMENT
1
VSS
2
VDD
3
NC
4
D/C
5
R/W (/WR)
6
E (/RD)
7
DB0
8
DB1
9
DB2
10
DB3
11
DB4
12
DB5
13
DB6
14
DB7
15
/RES
16
/CS
17
BS2
18
BS1
19
MF_SCLK
20
MF_SI
21
/MF_CS2
22
MF_SO
23
NC
24
NC
11.5 MAX
Notes:
1. Color: Blue
2. Controller IC: SSD1305
3. Interface: 8-bit 68xx/80xx Parallel, 4-wire SPI
4. RoHS Compliant
1
6
Description
T
N
φ 6.34
C
5
C6
A
B
C
D
Date
11/21/12
3
4
Gen. Tolerance
Unit
±0.3mm
mm
5
Model:
NHD-2.23-12832UMB3
6
The drawing contained herein is the exclusive property of Newhaven Display International, Inc. and shall not be copied, reproduced, and/or disclosed in any format without permission.
[3]
3. Interface Description
3.1.
Parallel Interface:
Pin No.
Symbol
External
Connection
Power Supply
Power Supply
‐
MPU
MPU
1
2
3
4
5
VSS
VDD
NC
D/C
R/W or /WR
6
E or /RD
MPU
7‐14
15
16
17
18
19
20
21
22
23
24
DB0 – DB7
/RES
/CS
BS2
BS1
MF_SCLK
MF_SI
/MF_CS2
MF_SO
NC
NC
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
‐
‐
3.2.
Function Description
Ground
Supply Voltage for OLED and logic.
No Connect
Register select signal. D/C=0: Command, D/C=1: Data
6800‐interface:
Read/Write select signal, R/W=1: Read R/W: =0: Write
8080‐interface:
Active LOW Write signal.
6800‐interface:
Operation enable signal. Falling edge triggered.
8080‐interface:
Active LOW Read signal.
8‐bit Bi‐directional data bus lines.
Active LOW Reset signal.
Active LOW Chip Enable signal.
MPU Interface Select signal.
MPU Interface Select signal.
Multi‐font IC Serial Clock Input
Multi‐font IC Serial Data Input
Multi‐font IC Active LOW Chip Enable signal.
Multi‐font IC Serial Data Output
No Connect
No Connect
Serial Interface:
Pin No.
1
2
3
4
5‐6
7
8
9
10‐14
15
16
17
18
19
20
21
22
23
24
Symbol
VSS
VDD
NC
D/C
VSS
SCLK
SDIN
NC
VSS
/RES
/CS
BS2
BS1
MF_SCLK
MF_SI
/MF_CS2
MF_SO
NC
NC
External
Connection
Power Supply
Power Supply
‐
MPU
Power Supply
MPU
MPU
‐
Power Supply
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
‐
‐
Function Description
Ground
Supply Voltage for OLED and logic.
No Connect
Register select signal. D/C=0: Command, D/C=1: Data
Ground
Serial Clock signal.
Serial Data Input signal.
No Connect
Ground
Active LOW Reset signal.
Active LOW Chip Enable signal.
MPU Interface Select signal.
MPU Interface Select signal.
Multi‐font IC Serial Clock Input
Multi‐font IC Serial Data Input
Multi‐font IC Active LOW Chip Enable signal.
Multi‐font IC Serial Data Output
No Connect
No Connect
[4]
I2C Interface:
3.3.
Pin No.
Symbol
1
2
3
4
5‐6
7
8
9
10‐14
15
16
17
18
19
20
21
22
23
24
3.4.
Function Description
Ground
Supply Voltage for OLED and logic.
No Connect
Slave Address Selection signal.
Ground
Serial Clock signal.
Serial Data input signal (pins 8 and 9 can be tied together).
Serial Data output signal (pin9 can be no connect).
Ground
Active LOW Reset signal.
Active LOW Chip Enable signal.
MPU Interface Select signal.
MPU Interface Select signal.
Multi‐font IC Serial Data Input
Multi‐font IC Serial Clock Input
Multi‐font IC Active LOW Chip Enable signal.
Multi‐font IC Serial Data Output
No Connect
No Connect
MPU Interface Pin Selections
Pin
Name
BS2
BS1
3.5.
VSS
VDD
NC
SA0
VSS
SCL
SDAIN
SDAOUT
VSS
/RES
/CS
BS2
BS1
MF_SI
MF_SCLK
/MF_CS2
MF_SO
NC
NC
External
Connection
Power Supply
Power Supply
‐
MPU
Power Supply
MPU
MPU
MPU
Power Supply
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
‐
‐
6800 Parallel
8‐bit interface
1
0
8080 Parallel
8‐bit interface
1
1
Serial
Interface
0
0
I2C
Interface
0
1
MPU Interface Pin Assignment Summery
Bus
Interface
8‐bit 6800
8‐bit 8080
SPI
I2C
D7
Data/Command Interface
D6 D5 D4 D3
D2
D1
D[7:0]
D[7:0]
Tie LOW
NC
SDIN
Tie LOW
SDAIN
SDAOUT
[5]
D0
SCLK
SCL
Control Signals
E
R/W /CS D/C
E
R/W /CS D/C
/RD /WR /CS D/C
Tie LOW
/CS D/C
Tie LOW
SA0
/RES
/RES
/RES
/RES
/RES
4. Wiring Diagrams
[6]
[7]
5. Electrical Characteristics
Item
Operating Temperature Range
Storage Temperature Range
Symbol
Top
Tst
Supply Voltage
Supply Current (logic)
VDD
IDD
Supply Current (display)
ICC
Sleep Mode Current
“H” Level input
“L” Level input
“H” Level output
“L” Level output
Condition
Absolute Max
Absolute Max
Ta=25°C, VDD=2.8V
VDD=2.8V, 50% ON
VDD=2.8V, 100% ON
IDD+ICCSLEEP
Vih
Vil
Voh
Vol
Min.
‐20
‐40
Typ.
‐
‐
Max.
+70
+90
Unit
⁰C
⁰C
2.4
‐
‐
‐
‐
0.8*VDD
VSS
0.9*VDD
VSS
2.8
0.195
20
28
3
‐
‐
‐
‐
3.5
15.4
25
35
30
VDD
0.2*VDD
VDD
0.1VDD
V
mA
mA
mA
µA
V
V
V
V
Min.
80
80
80
80
2000:1
‐
‐
100
10,000
Typ.
‐
‐
‐
‐
‐
10
10
120
‐
Max.
‐
‐
‐
‐
‐
‐
‐
‐
‐
6. Optical Characteristics
Item
Viewing Angle – Vertical (top)
Viewing Angle – Vertical (bottom)
Viewing Angle – Horizontal (left)
Viewing Angle – Horizontal (right)
Contrast Ratio
Response Time (rise)
Response Time (fall)
Brightness
Lifetime
Symbol
AV
AV
AH
AH
Cr
Tr
Tf
Condition
Unit
⁰
⁰
⁰
⁰
‐
us
us
cd/m2
Hrs
‐
‐
50% checkerboard
Ta=25°C, 50%
checkerboard
Note: Lifetime at typical temperature is based on accelerated high‐temperature operation. Lifetime is tested at
average 50% pixels on and is rated as Hours until Half‐Brightness. The Display OFF command can be used to
extend the lifetime of the display.
Luminance of active pixels will degrade faster than inactive pixels. Residual (burn‐in) images may occur. To avoid
this, every pixel should be illuminated uniformly.
[8]
7. Font Content Address Table
#
Type
Font Content
Character Set
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ASCII
5x7 ASCII
7x8 ASCII
8x16 BOLD ASCII
Width‐adjusted Arial ASCII
8x16 Latin
8x16 Latin
8x16 Latin
8x16 Latin
8x16 Latin
8x16 Greek
8x16 Cyrillic
8x16 Hebrew
8x16 Thai
Width‐adjusted Latin
Width‐adjusted Latin
Width‐adjusted Latin
Width‐adjusted Latin
Width‐adjusted Latin
Width‐adjusted Greek
Width‐adjusted Cyrillic
Width‐adjusted Arabic
GB2312
KSC5605
JIS0208
5x7 ISO8859
LCM 5x10
ASCII
ASCII
ASCII
ASCII
Basic
Supplement
Extended A
Extended B
Extended Additional
Basic
Basic
Basic
Basic
Basic
Supplement
Extended A
Extended B
Extended Additional
Basic
Basic
Basic
UNICODE
CJK
LCM
[9]
Number of
Characters
96
96
96
96
96
96
128
80
96
96
208
112
128
96
96
128
80
96
96
208
576
7,614
6,500
7,999
1,792
1,792
Base Address
(decimal)
0
768
1,536
3,072
6,336
7,872
9,408
11,456
12,736
14,272
15,808
19,136
20,928
22,976
26,240
29,504
33,856
36,576
39,840
43,104
50,176
69,760
379,744
490,624
946,992
961,328
Base Address
(hex)
000000
000300
000600
000C00
0018C0
001EC0
0024C0
002CC0
0031C0
0037C0
003DC0
004AC0
0051C0
0059C0
006680
007340
008440
008EE0
009BA0
00A860
00C400
011080
05CB60
077C80
0E7330
0EAB30
8. Supported Languages
Language
Family
Area
Europe
Country
United Kingdom
Ireland
USA
Canada
North
America
South Africa
Language
Family
Language
English
Area
Country
Language
Europe
France
Belgium
Monaco
French
French, Dutch
French, Italian
North
America
Haiti
French
English
English, French
Belize
Jamaica
Trinidad and Tobago
Bahamas
Antigua and Barbuda
Dominica
St. Vincent
St. Lucia
Grenada
St. Kitts‐Nevis
English
Guyana
English
Latin (French)
Africa
Australia
New Zealand
Tonga
Latin (English)
Australia
Fiji
Palau
Solomon
Vanuatu
Kiribati
Nauru
Marshall Islands
South Africa
Zimbabwe
Gambia
English
Europe
English, Dutch
Sierra Leone
Africa
Europe
South
America
Latin
(Portuguese)
Africa
Liberia
Ghana
Nigeria
Uganda
Zambia
Malawi
Seychelles
Mauritius
Botswana
Namibia
Lesotho
Portugal
Europe
Cape Verde
Guinea‐Bissau
Sao Tome and
Principe
Angola
Mozambique
Germany
Austria
Luxembourg
Latin (Dutch)
Europe
South
English
Latin (Spanish)
South
America
Brazil
Switzerland
Latin (German)
North
America
Liechtenstein
Holland
Surinam
Senegal
Mali
Burkina Faso
Guinea
Cote d’Ivoire
Togo
Benin
Niger
Cameroon
Chad
Central African
Republic
Djibouti
Burundi
Republic of
Democratic
Congo
Congo
Gabon
Comoros
Madagascar
Spain
Andorra
Mexico
Guatemala
Costa Rica
Panama
Dominican
Republic
El Salvador
Honduras
Nicaragua
Puerto Rico
Cuba
Venezuela
Colombia
Peru
Argentina
Ecuador
Chile
Uruguay
French
Spanish, Catalan
Spanish
Spanish
Spanish
Paraguay
Portuguese
Africa
German
German,
French
German
German,
French
German
Latin (Nordic
Europe)
Dutch
[10]
Europe
Bolivia
New Guinea
Ceuta and
Melilla
Denmark
Norway
Sweden
Danish
Norwegian
Swedish
Faroes
Faroese
Greenland
Greenlandic
Iceland
Icelandic
Finland
Estonia
Latvia
Finnish, Swedish
Estonian
Latvian
Spanish
America
Latin (Central
Europe)
Latin (Southern
Europe)
Latin (Southeast
Asia)
Europe
Europe
Asia
Czech
Slovakia
Poland
Hungary
Romania
Slovenia
Croatia
Italy
San Marino
Vatican
Turkey
Malta
Albania
Vietnam
Malaysia
Brunei
Indonesia
East Timor
Philippines
Arabic (Africa)
Arabic (Asia)
Africa
Asia
Egypt
Tunisia
Libya
Morocco
Algeria
Sudan
Somalia
Djibouti
Mauritania
Syria
United Arab Emirates
Lebanon
Yemen
Kuwait
Qatar
Bahrain
Oman
Jordan
Iraq
Saudi Arabia
Palestine
Iran
Pakistan
Afghanistan
Czech
Slovak
Polish
Hungarian
Romanian
Slovenian
Crotian
Cyrillic (Eastern
Europe)
Europe
Italian
Turkish
Maltese
Albanian
Vietnamese
Cyrillic (Asia)
Asia
Indonesian
Greek
Europe
English,
Tagalog
Latin (Africa)
Africa
Malaysian
Arabic
Arabic
Farsi
Urdu, Arabic
Pashto
[11]
Hebrew
Thai
Japan
Korea
Asia
Asia
Asia
Asia
China
Asia
Lithuania
Russia
Belarus
Ukraine
Bulgaria
Moldova
Yugoslavia
Barbados
Macedonia
Azerbaijan
Kirghizstan
Tajikistan
Turkmenistan
Uzbekistan
Kazakhstan
Mongolia
Greece
Cyprus
Kenya
Tanzania
Israel
Thailand
Japan
Korea
China
Singapore
Lithuanian
Russian
Russian Ukrainian
Bulgarian
Russian
Serbian
Macedonian
Azeri
Kyrgyz
Tajik
Turkmen
Uzbek
Kazakh
Mongolian
Greek
Kiswahili
Hebrew
Thai
Japanese
Korean
Chinese
9. OLED controller Instruction Table (Built‐In SSD1305 Controller/Driver)
Instruction
Set Lower Column
Start Address
Set Higher
Column Start
Address
Set Memory
Addressing Mode
Code
DB5 DB4
0
0
D/C
0
HEX
00~ 0F
DB7
0
DB6
0
0
10~1F
0
0
0
0
20
A[1:0]
0
*
0
*
21
A[7:0]
B[7:0]
22
A[2:0]
B[2:0]
40~7F
0
A7
B7
0
*
*
0
81
A[7:0]
82
A[7:0]
91
X[5:0]
A[5:0]
B[5:0]
C[5:0]
Set Column
Address
0
Set Page Address
0
Set Display Start
Line
Set Contrast
Control
Set Brightness
0
0
Set Look‐Up Table
0
0
DB3
X3
DB2
X2
DB1
X1
DB0
X0
1
X3
X2
X1
1
*
0
*
0
*
0
*
0
A6
B6
0
*
*
1
1
A5
B5
1
*
*
X5
0
A4
B4
0
*
*
X4
0
A3
B3
0
*
*
X3
1
A7
1
A7
1
*
*
*
*
0
A6
0
A6
0
*
*
*
*
0
A5
0
A5
0
X5
A5
B5
C5
0
A4
0
A4
1
X4
A4
B4
C4
Description
RESET
value
Set the lower nibble of the column start address register for Page
Addressing Mode.
0
X0
Set the higher nibble of the column start address register for Page
Addressing Mode.
0
0
A1
0
A0
0
A2
B2
0
A2
B2
X2
0
A1
B1
1
A1
B1
X1
1
A0
B0
0
A0
B0
X0
A[1:0] = 00b, Horizontal Addressing Mode
A[1:0] = 01b, Vertical Addressing Mode
A[1:0] = 10b, Page Addressing Mode
A[1:0] = 11b, Invalid
Setup column start and end address
A[7:0]: Column start address. Range: 0‐131d
B[7:0]: Column end address. Range: 0‐131d
0
A3
0
A3
0
X3
A3
B3
C3
0
A2
0
A2
0
X2
A2
B2
C2
0
A1
1
A1
0
X1
A1
B1
C1
1
A0
0
A0
1
X0
A0
B0
C0
Set Bank Color of
Bank1 to Bank16
(Page 0)
0
92
A[7:0]
B[7:0]
C[7:0]
D[7:0]
1
A7
B7
C7
D7
0
A6
B6
C6
D6
0
A5
B5
C5
D5
1
A4
B4
C4
D4
0
A3
B3
C3
D3
0
A2
B2
C2
D2
1
A1
B1
C1
D1
0
A0
B0
C0
D0
Set Bank Color of
Bank17 to Bank32
0
93
A[7:0]
1
A7
0
A6
0
A5
1
A4
0
A3
0
A2
1
A1
1
A0
[12]
10b
0
131d
Setup page start and end address
A[2:0]: Page start address. Range: 0‐7d
B[2:0]: Page end address. Range: 0‐7d
0
7d
Set display RAM display start line register from 0‐63d.
0
Double byte command to select 1 out of 256 contrast steps. Contrast
increases as the value increases.
0x80
Double byte command to select 1 out of 256 brightness steps.
Brightness increases as the value increases.
0x80
Set current drive pulse width of Bank 0, Color A, B and C.
Bank 0: X[5:0] = 31 to 63. Pulse width set to 32 to 64 clocks.
Color A: X[5:0] = 31 to 63. Pulse width set to 32 to 64 clocks.
Color B: X[5:0] = 31 to 63. Pulse width set to 32 to 64 clocks.
Color C: X[5:0] = 31 to 63. Pulse width set to 32 to 64 clocks.
Note: Color D pulse width is fixed at 64 clocks.
Sets the bank color of Bank1~Bank16 to any one of the 4 colors A,B,C,
and D.
A[1:0] : 00b, 01b, 10b, or 11b for Color = A, B, C, or D of BANK1.
A[3:2] : 00b, 01b, 10b, or 11b for Color = A, B, C, or D of BANK2.
.
.
.
D[5:4] : 00b, 01b, 10b, or 11b for Color = A, B, C, or D of BANK15.
D[7:6] : 00b, 01b, 10b, or 11b for Color = A, B, C, or D of BANK16.
Sets the bank color of Bank17~Bank32 to any one of the 4 colors
A,B,C, and D.
A[1:0] : 00b, 01b, 10b, or 11b for Color = A, B, C, or D of BANK17.
0x31
0x3F
0x3F
0x3F
(Page 1)
B[7:0]
C[7:0]
D[7:0]
B7
C7
D7
B6
C6
D6
B5
C5
D5
B4
C4
D4
B3
C3
D3
B2
C2
D2
B1
C1
D1
B0
C0
D0
Set Segment
Remap
Entire Display ON
0
A0/A1
1
0
1
0
0
0
0
X0
0
A4/A5
1
0
1
0
0
1
0
X0
Set Normal/
Inverse Display
Set Multiplex
Ratio
Dim mode setting
0
A6/A7
1
0
1
0
0
1
1
X0
0
A8
A[5:0]
AB
A[3:0]
B[7:0]
C[7:0]
1
*
1
*
B7
C7
0
*
0
*
B6
C6
1
A5
1
*
B5
C5
0
A4
0
*
B4
C4
1
A3
1
A3
B3
C3
0
A2
0
A2
B2
C2
0
A1
1
A1
B1
C1
0
A0
1
A0
B0
C0
Master
configuration
Set Display ON/
OFF
0
1
1
1
0
0
0
1
0
1
0
0
0
1
1
1
1
1
1
0
1
A1
1
0
A0
Set Page Start
Address
Set COM Output
Scan Direction
Set Display Offset
0
AD
AE
AC/
AE/
AF
B0~B7
1
0
1
1
0
X2
X1
X0
0
C0/C8
1
1
0
0
X3
0
0
0
0
D3
A[5:0]
D5
A[7:0]
1
*
1
A7
1
*
1
A6
0
A5
0
A5
1
A4
1
A4
0
A3
0
A3
0
A2
1
A2
1
A1
0
A1
D8
X[5:0]
1
0
1
0
0
X5
1
X4
1
0
0
X2
D9
A[7:0]
DA
1
A7
1
1
A6
1
0
A5
0
1
A4
1
1
A3
1
0
A2
0
Set Display Clock
Divide Ratio /
Oscillator
Frequency
Set Area Color
Mode ON/OFF &
Low Power
Display Mode
Set Pre‐charge
Period
Set COM pins
0
0
0
0
0
0
A[3:2] : 00b, 01b, 10b, or 11b for Color = A, B, C, or D of BANK18.
.
.
.
D[5:4] : 00b, 01b, 10b, or 11b for Color = A, B, C, or D of BANK31.
D[7:6] : 00b, 01b, 10b, or 11b for Color = A, B, C, or D of BANK32.
X[0] = 0; Column address 0 is mapped to SEG0
X[0] = 1; Column address 131 is mapped to SEG0
X[0] = 0; Resume RAM content display. Output follows RAM content.
X[0] = 1; Entire display ON. Output ignores RAM content.
X[0] = 0; Normal display.
X[0] = 1; Inverse display.
Set MUX ratio to N+1 MUX
N=A[5:0]; from 16MUX to 64MUX (0 to 14 are invalid)
0
0
0
64
A[3:0] = reserved. Set as 0000b
B[7:0] = Set contrast for BANK0. Range 0‐255d. Refer to command
81h.
C[7:0] = Set brightness for color bank. Range 0‐255d. Refer to
command 82h.
Selects external VCC supply
AEh
ACh = Display ON in dim mode
AEh = Display OFF (sleep mode)
AFh = Display ON in normal mode
AEh
Set GDRAM Page Start Address for Page Addressing Mode using X[2:0].
PAGE0~PAGE7
X[3] = 0; Normal mode. Scan from COM0 to COM[N‐1]
X[3] = 1; Remapped mode. Scan from COM[N‐1] to COM0
0
1
A0
1
A0
Set vertical shift by COM from 0~63.
0
0
0
0
X0
X[5:4] = 00b; Monochrome mode
X[5:4] = 11b; Area Color mode
X[2] = 0 and X[0] = 0; Normal power mode
X[2] = 1 and X[0] = 1; Set low power display mode
0
A1
1
1
A0
0
A[3:0] = Phase 1 period of up to 15 DCLK clocks. 0 is invalid.
A[7:4] = Phase 2 period of up to 15 DCLK clocks. 0 is invalid.
[13]
A[3:0] = Define the divide ratio of the display clocks.
Divide ratio = A[3:0] +1
A[7:4] = Set the Oscillator Frequency. Frequency increases with the
value of A[7:4]. Range 0000b~1111b.
X[4] = 0; Sequential COM pin configuration
0000b
0111b
00
00
2h
2h
Set VCOMH
Deselect Level
0
Enter Read
Modify Write
mode
NOP
Exit Read Modify
Write mode
0
E0
1
1
1
0
0
0
0
0
X[4] = 1; Alternative COM pin configuration
X[5] = 0; Disable COM Left/Right remap
X[5] = 1; Enable COM Left/Right remap
A[5:2] = 0000b; VCOMH = ~0.43*VCC
A[5:2] = 1101b; VCOMH = ~0.77*VCC
A[5:2] = 1111b; VCOMH = ~0.83*VCC
Enter the Read/Modify/Write mode.
0
0
E3
EE
1
1
1
1
1
1
0
0
0
1
0
1
1
1
1
0
Command for No Operation
Exit the Read/Modify/Write mode.
Hardware
configuration
X[5:4]
0
0
X5
X4
0
0
1
0
DB
A[5:2]
1
0
1
0
0
A5
1
A4
1
A3
0
A2
1
0
1
0
For detailed instruction information, see datasheet: http://www.newhavendisplay.com/app_notes/SSD1305.pdf
[14]
1
1
1101
10.OLED Controller ‐> MPU Interface
For detailed timing information, see datasheet: http://www.newhavendisplay.com/app_notes/SSD1305.pdf
10.1.
6800‐MPU Parallel Interface
The parallel interface consists of 8 bi‐directional data pins, R/W, D/C, E, and /CS.
A LOW on R/W indicates write operation, and HIGH on R/W indicates read operation.
A LOW on D/C indicates “Command” read or write, and HIGH on D/C indicates “Data” read or write.
The E input serves as data latch signal, while /CS is LOW. Data is latched at the falling edge of E signal.
Function
Write Command
Read Status
Write Data
Read Data
10.2.
E
↓
↓
↓
↓
R/W
0
1
0
1
/CS
0
0
0
0
D/C
0
0
1
1
8080‐MPU Parallel Interface
The parallel interface consists of 8 bi‐directional data pins, /RD, /WR, D/C, and /CS.
A LOW on D/C indicates “Command” read or write, and HIGH on D/C indicates “Data” read or write.
A rising edge of /RS input serves as a data read latch signal while /CS is LOW.
A rising edge of /WR input serves as a data/command write latch signal while /CS is LOW.
Function
Write Command
Read Status
Write Data
Read Data
/RD
1
↑
1
↑
/WR
↑
1
↑
1
/CS
0
0
0
0
D/C
0
0
1
1
Alternatively, /RD and /WR can be kept stable while /CS serves as the data/command latch signal.
Function
Write Command
Read Status
Write Data
Read Data
/RD
1
0
1
0
/WR
0
1
0
1
/CS
↑
↑
↑
↑
D/C
0
0
1
1
[15]
10.3.
Serial Interface
The serial interface consists of serial clock SCLK, serial data SDIN, D/C, and /CS.
D0 acts as SCLK and D1 acts as SDIN. D2 should be left open. D3~D7, E, and R/W should be connected to GND.
Function
Write Command
Write Data
/RD
0
0
/WR
0
0
/CS
0
0
D/C
0
1
D0
↑
↑
SDIN is shifted into an 8‐bit shift register on every rising edge of SCLK in the order of D7, D6,…D0.
D/C is sampled on every eighth clock and the data byte in the shift register is written to the GDRAM or
command register in the same clock.
Note: Read is not available in serial mode.
10.4.
I2C Interface
The I2C interface consists of a slave address bit SA0, I2C‐bus data signal SDA, and I2C‐bus clock signal SCL.
D1 and D2 can be tied together, and act as SDA. D0 acts as SCL. Both the data and clock signals must be
connected to pull‐up resistors. /RES is used to initialize the device.
Note: SA0 bit allows the device to have a slave address of either “0111100” or “0111101”.
Note: Data and acknowledgement are sent through the SDA. The ITO track resistance and the pull‐up
resistance at SDA becomes a voltage potential divider. As a result, it may not be possible to attain a valid logic
“0” level on SDA for the ACK signal. SDAIN must be connected, but SDAOUT may be disconnected and the ACK
signal will be ignored on the I2C bus.
For detailed protocol information, see datasheet: http://www.newhavendisplay.com/app_notes/SSD1305.pdf
[16]
11.Example Initialization Sequence:
Set_Display_On_Off(0x00);
Set_Display_Clock(0x10);
Set_Multiplex_Ratio(0x1F);
Set_Display_Offset(0x00);
Set_Start_Line(0x00);
Set_Master_Config(0x00);
Set_Area_Color(0x05);
Set_Addressing_Mode(0x02);
Set_Segment_Remap(0x01);
Set_Common_Remap(0x08);
Set_Common_Config(0x10);
Set_LUT(0x3F,0x3F,0x3F,0x3F);
Set_Contrast_Control(Brightness);
Set_Area_Brightness(Brightness);
Set_Precharge_Period(0xD2);
Set_VCOMH(0x08);
Set_Entire_Display(0x00);
Set_Inverse_Display(0x00);
Fill_RAM(0x00);
Set_Display_On_Off(0x01);
// Display Off (0x00/0x01)
// Set Clock as 160 Frames/Sec
// 1/32 Duty (0x0F~0x3F)
// Shift Mapping RAM Counter (0x00~0x3F)
// Set Mapping RAM Display Start Line (0x00~0x3F)
// Disable Embedded DC/DC Converter (0x00/0x01)
// Set Monochrome & Low Power Save Mode
// Set Page Addressing Mode (0x00/0x01/0x02)
// Set SEG/Column Mapping (0x00/0x01)
// Set COM/Row Scan Direction (0x00/0x08)
// Set Alternative Configuration (0x00/0x10)
// Define All Banks Pulse Width as 64 Clocks
// Set SEG Output Current
// Set Brightness for Area Color Banks
// Set Pre‐Charge as 13 Clocks & Discharge as 2 Clock
// Set VCOM Deselect Level
// Disable Entire Display On (0x00/0x01)
// Disable Inverse Display On (0x00/0x01)
// Clear Screen
// Display On (0x00/0x01)
[17]
12.Multi‐Font IC ‐> MPU Interface
12.1.
Serial Interface
The serial interface consists of serial clock MF_SCLK, serial data in MF_SI, serial data out MF_SO, chip enable
/MF_CS2.
Function
Send Font Address
Read Font Data
MF_SCLK
↑
↓
MF_SI
DATA
X
MF_SO
X
DATA
/MF_CS2
0
0
The Multi‐Font device is enabled by a high‐to‐low transition on /MF_CS2. /MF_CS2 must remain LOW for the
duration of any command‐in or data‐out sequence.
The Font Address is shifted in on the MF_SI line on the rising edge of MF_SCLK.
The Font Data is shifted out on the MF_SO line on the falling edge of MF_SCLK.
[18]
12.2.
Communication Protocol
Font data can be accessed and read by using the READ command instruction.
Instruction
READ
Description
Read Data (30MHz MAX)
Instruction
Code
0Bh
Address
Bytes
3
Dummy
Bytes
1
Data
Bytes
1~∞
READ mode supports up to 30MHz frequency on MF_SCLK.
READ mode outputs the data starting from the specified address location. The data output stream is
continuous through all addresses until terminated by a low‐to‐high transition on /MF_CS2. The internal
address pointer will automatically increment after each byte is read.
READ instruction is initiated by executing an 8‐bit command [0x0B] on the MF_SI line, followed by the desired
font address bits [A23‐A0], and followed by an 8‐bit dummy write [0x00]. The font data will then be output on
MF_SO line, MSB first.
/MF_CS2 must remain active LOW for the duration of the read cycle.
[19]
12.3.
Timing Characteristics
Symbol
Fc
tCH
tCL
tCLCH
tCHCL
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ
tCLQV
tCLQX
Parameter
Clock Frequency
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
/MF_CS2 Active Setup Time
/MF_CS2 Not Active Hold Time
Data IN Setup Time
Data IN Hold Time
/MF_CS2 Active Hold Time
/MF_CS2 Not Active Setup Time
/MF_CS2 Deselect Time
Output Disable Time
Clock Low to Output Valid
Output Hold Time
Condition
peak to peak
peak to peak
relative to MF_SCLK
relative to MF_SCLK
relative to MF_SCLK
relative to MF_SCLK
13.Font Tables
see file: www.newhavendisplay.com/app_notes/MultiFont.pdf
14.Font Data Arrangement
see file: www.newhavendisplay.com/app_notes/MultiFont.pdf
15.Calculation of Font Addresses
see file: www.newhavendisplay.com/app_notes/MultiFont.pdf
16.Multi‐Font program code example
[20]
Min.
‐
15
15
0.1
0.1
5
5
2
5
5
5
100
‐
‐
0
Max.
30
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
9
9
‐
Unit
MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17.Quality Information
Test Item
Content of Test
High Temperature storage
Test the endurance of the display at high
storage temperature.
Test the endurance of the display at low
storage temperature.
Test the endurance of the display by
applying electric stress (voltage & current)
at high temperature.
Test the endurance of the display by
applying electric stress (voltage & current)
at low temperature.
Test the endurance of the display by
applying electric stress (voltage & current)
at high temperature with high humidity.
Test the endurance of the display by
applying electric stress (voltage & current)
during a cycle of low and high
temperatures.
Test the endurance of the display by
applying vibration to simulate
transportation and use.
Low Temperature storage
High Temperature
Operation
Low Temperature
Operation
High Temperature /
Humidity Operation
Thermal Shock resistance
Vibration test
Atmospheric Pressure test
Static electricity test
Test Condition
Test the endurance of the display by
applying atmospheric pressure to simulate
transportation by air.
Test the endurance of the display by
applying electric static discharge.
Note
+90⁰C , 240hrs
2
‐40⁰C , 240hrs
1,2
+85⁰C 240hrs
2
‐40⁰C , 240hrs
1,2
+60⁰C , 90% RH , 240hrs
1,2
‐40⁰C,30min ‐> 25⁰C,5min ‐>
85⁰C,30min = 1 cycle
100 cycles
10‐22Hz , 15mm amplitude.
22‐500Hz, 1.5G
30min in each of 3 directions
X,Y,Z
115mbar, 40hrs
3
3
VS=800V, RS=1.5kΩ, CS=100pF
One time
Note 1: No condensation to be observed.
Note 2: Conducted after 2 hours of storage at 25⁰C, 0%RH.
Note 3: Test performed on product itself, not inside a container.
Evaluation Criteria:
1: Display is fully functional during operational tests and after all tests, at room temperature.
2: No observable defects.
3: Luminance >50% of initial value.
4: Current consumption within 50% of initial value
Precautions for using OLEDs/LCDs/LCMs
See Precautions at www.newhavendisplay.com/specs/precautions.pdf
Warranty Information and Terms & Conditions
http://www.newhavendisplay.com/index.php?main_page=terms
Newhaven Display International, Inc. reserves the right to alter this product or specification at any time without notification.
[21]
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