Freescale Semiconductor Technical Data Document Number: MC34702 Rev 6.0, 2/2007 3.0 A Switch-Mode Power Supply with Linear Regulator 34702 The 34702 provides the means to efficiently supply the Freescale Power QUICC™ I, II, and other families of Freescale microprocessors and DSPs. The 34702 incorporates a highperformance switching regulator, providing the direct supply for the microprocessor’s core, and a low dropout (LDO) linear regulator control circuit providing the microprocessor I/O and bus voltage. The switching regulator is a high-efficiency synchronous buck regulator with integrated N-channel power MOSFETs to provide protection features and to allow space-efficient, compact design. The 34702 incorporates many advanced features; e.g., precisely maintained up/down power sequencing, ensuring the proper operation and protection of the CPU and power system. POWER SUPPLY INTEGRATED CIRCUIT Features • • • • • • • • • EK (PB-FREE) SUFFIX 98AARH99137A 32-PIN SOICW Operating Voltage from 2.8 V to 6.0 V High-Accuracy Output Voltages Fast Transient Response Switcher Output Current Up to 3.0 A Undervoltage Lockout and Overcurrent Protection Enable Inputs and Programmable Watchdog Timer Voltage Margining via I2C™ Bus Reset with Programmable Power-ON Delay Pb-Free Packaging Designated by Suffix Code EK ORDERING INFORMATION I2C is a trademark of Philips Corporation. Device Temperature Range (TA) Package MC34702EK/R2 -40 to 85°C 32 SOICW 2.8 V to 6.0 V Input 34702 VIN2 VIN1 VBD VBST LDRV CS RT Optional VDDH (I/Os) LFB MPC8xxx SDA SCL GND CLKSEL Adjustable: 0.8 V to VIN Dropout LDO ADDR EN1 EN2 CLKSYN Other Circuits PORESET RST BOOT VBST Adjustable: 0.8 V to VIN Dropout SW VOUT PGND FREQ INV VDDI Figure 1. 34702 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2007. All rights reserved. VDDL (Core) INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VIN1 VIN VDDI Internal Supply VDDI VDDI 8.0 V VBST VBST VBST - VREF Power Enable LDRV VDDI VDDI + VBD Q5 Boost Control VREF VREF Bandgap Voltage Reference Linear Regulator Control CS To Reset Control LDO ILim VREF LFB VDDI LCMP Power Sequencing EN2 Reset RST Q6 RT Power Seq VLDO EN1 Reset Control POR Timer I2C Control Power Down VOUT VBST SysCon BOOT Current Limit I 2C VIN2 (2) VDDI Control Thermal Limit VBST Voltage Margining Watchdog Timer INV LFB UVLO Q4 SysCon Buck HS and LS Driver Buck Control Logic SoftSt Q1 SW (2) Q2 ADDR SDA I2C Interface PGND (2) SCL PWM Comp Switcher Oscillator 300 kHz - CLKSYN FREQ 0.8 V + To Reset Control - INV VOUT Ramp Gen. CLKSEL + Error Amp Power Seq VOUT Q3 GND (4) Figure 2. 34702 Simplified Internal Block Diagram 34702 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS FREQ INV VOUT VIN2 VIN2 SW SW GND GND PGND PGND VBD VBST BOOT SDA SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 CLKSYN CLKSEL RST RT EN2 EN1 ADDR GND GND VDD1 VIN1 LDRV CS LDO LFB LCMP Figure 3. Pin Connections Table 1. Pin Function Description A functional description of each pin can be found in the Functional Pin Description section beginning on page 16. Pin Pin Name Formal Name Definition 1 FREQ Oscillator Frequency This switcher frequency selection pin can be adjusted by connecting external resistor RF to the FREQ pin. The default switching frequency (FREQ pin left open or tied to VDDI) is set to 300 kHz. 2 INV Inverting Input Buck Controller Error Amplifier inverting input. 3 VOUT Output Voltage Output voltage of the buck converter. Input pin of the switching regulator power sequence control circuit. 4, 5 VIN2 Input Voltage 2 Buck regulator power input. Drain of the high-side power MOSFET. 6, 7 SW Switch Buck regulator switching node. This pin is connected to the inductor. 8, 9 24, 25 GND Ground Analog ground of the IC, thermal heatsinking. 10, 11 PGND Power Ground 12 VBD Boost Drain 13 VBST Boost Voltage 14 BOOT Bootstrap 15 SDA Serial Data I2C bus pin. Serial data. 16 SCL Serial Clock I2C bus pin. Serial clock. 17 LCMP Linear Compensation 18 LFB Linear Feedback Linear regulator feedback pin. 19 LDO Linear Regulator Input pin of the linear regulator power sequence control circuit. Buck regulator power ground. Drain of the internal boost regulator power MOSFET. Internal boost regulator output voltage. The internal boost regulator provides a 20 mA output current to supply the drive circuits for the integrated power MOSFETs and the external N-channel power MOSFET of the linear regulator. The voltage at the VBST pin is 7.75V nominal. Bootstrap capacitor input. Linear regulator compensation pin. 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. Pin Function Description (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 16. Pin Pin Name Formal Name Definition 20 CS Current Sense Current sense pin of the LDO. Overcurrent protection of the linear regulator external power MOSFET. The voltage drop over the LDO current sense resistor RS is sensed between the CS and LDO pins. The LDO current limit can be adjusted by selecting the proper value of the current sensing resistor RS. 21 LDRV Linear Drive 22 VIN1 Input Voltage 1 The input supply pin for the integrated circuit. The internal circuits of the IC are supplied through this pin. 23 VDDI Power Supply Internal supply voltage. A ceramic low ESR 1uF 6V X5R or X7R capacitor is recommended. 26 ADDR Address I2C address selection. This pin can either be left open, tied to VDDI, or grounded through a 10 kΩ resistor. 27 EN1 Enable 1 Enable 1 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs determines operation mode and type of power sequencing of the IC. 28 EN2 Enable 2 Enable 2 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs determines operation mode and type of power sequencing of the IC. 29 RT Reset Timer This pin allows programming of the Power-ON Reset delay by means of an external RC network. 30 RST Reset Output (Active LOW) The Reset Control circuit monitors both the switching regulator and the LDO feedback voltages. It is an open drain output and has to be pulled up to some supply voltage (e.g., the output of the LDO) by an external resistor. 31 CLKSEL Clock Selection This pin sets the CLKSYN pin as either an oscillator output or a synchronization input pin. The CLKSEL pin is also used for the I2C address selection. 32 CLKSYN Clock Synchronization LDO gate drive of the external pass N-channel MOSFET. Oscillator output/synchronization input pin. 34702 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Value Unit VIN1, VIN2 -0.3 to 7.0 V VSW -1.0 to 7.0 V VIN(BOOT) -0.3 to 8.5 V Boost Regulator Output Voltage VBST -0.3 to 8.5 V Boost Regulator Drain Voltage VBD -0.3 to 9.5 V RST Drain Voltage VRST -0.3 to 7.0 V Enable Pin Voltage at EN1, EN2 VEN -0.3 to 7.0 V VLOG -0.3 to 7.0 V LDO, VOUT, RST VOUT -0.3 to 7.0 LDRV, LCMP, CS VLIN -0.3 to 8.5 VLOGIC -0.3 to 3.6 VESD ±2000 ELECTRICAL RATINGS Supply Voltage Switching Node Voltage Buck Regulator Bootstrap Input Voltage (BOOT - SW) Logic Pin Voltage at SDA, SCL Analog Pin Voltage Pin Voltage at CLKSEL, ADDR, RT, FREQ, VDDI, CLKSYN, INV, LFB V ESD Voltage (1) Human Body Model Machine Model V V ±200 Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model. 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Value Unit TSTG -65 to 150 °C TPPRT Note 3 °C TJMAX 125 °C THERMAL RATINGS Storage Temperature Peak Package Reflow Temperature During Reflow (2) (3) , Maximum Junction Temperature °C/W RθJA Thermal Resistance (4) (5) 70 Junction to Ambient (Four Layers) (4), (5) 55 Junction to Ambient (Single Layer) , Thermal Resistance, Junction to Base (6) Operational Package Temperature (Ambient Temperature) RθJB 18 °C/W TA -40 to 85 °C Notes 2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.. 4. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board and board thermal resistance. 5. Per JEDEC JESD51-6 with the board horizontal 6. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 34702 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions -40°C ≤ TA ≤ 85°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 33) unless otherwise noted. Characteristic Symbol Min Typ Max Unit Operating Voltage Range (VIN1, VIN2) VIN 2.8 – 6.0 V Start-Up Voltage Threshold (Boost Switching) VST – 1.6 1.8 V VBST_UVLO 5.5 – 6.5 V VBST_UVLO_HYS 0.5 – 1.5 V Input DC Supply Current (Normal Operation Mode, Enabled), Unloaded Outputs IIN – 60 – mA VIN1 Pin Input Supply Current (EN1 = EN2 = 0) IIN1 – 10 – mA VIN2 Pin Input Leakage Current (EN1 = EN2 = 0) IIN2 – 100 – µA VDDI Internal Supply Voltage VDDI 2.9 – 3.3 V VDDI Maximum Output Current (Externally Loaded) IDDI – – -10 mA 0.784 0.800 0.816 VMVO – 1.0 – % Buck Converter Voltage Margining Highest Positive Value VMP 5.9 7.0 7.9 % Buck Converter Voltage Margining Lowest Negative Value VMN -7.9 7.0 -5.9 % -1.0 – 1.0 -1.0 – 1.0 – 3.5 – GENERAL VBST Undervoltage Lockout (VBST rising) VBST Undervoltage Lockout Hysterisis BUCK CONVERTER Buck Converter Feedback Voltage (7), (8) Buck Converter Voltage Margining Step Size Buck Converter Line Regulation (7), (8) REGLNVO VIN1 = VIN2 = 2.8 V to 6.0 V, I VOUT = 15 mA to 3.0 A Buck Converter Load Regulation (7), (8) % mA IVOUTLK VOUT = 5.25 V INV Input Leakage Current % REGLDVO VIN1 = VIN2 = 2.8 V to 6.0 V, I VOUT = 15 mA to 3.0 A VOUT Input Leakage Current V VINV I VOUT = 15 mA to 3.0 A. Includes Load Regulation Error INVLEAK -1.0 1.0 µA INV = 0.8 V Notes 7. Design information only. This parameter is not production tested. 8. VOUT refers to load current on output switcher. 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions -40°C ≤ TA ≤ 85°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 33) unless otherwise noted. Characteristic Symbol Min Typ Max – 60 – Unit BUCK CONVERTER (CONTINUED) High-Side Power MOSFET Q1 RDS(ON) (9),(10) ID = 500 mA, TA = 25°C, VBST = 8.0 V Low-Side Power MOSFET Q2 RDS(ON) (9),(10) VOUT Pulldown MOSFET Q3 Current Limit – 65 – -7.0 -4.7 -4.0 0.75 – 2.0 – – 1.9 TSD 150 170 190 °C TSDHYS – 10 – °C ILIMH Thermal Shutdown (VOUT Pull-down MOSFET Q3) (9) Thermal Shutdown Hysteresis (9) Ω RDS(ON) ID = 1.0 A, VBST = 8.0 V A A IM3_LIM TA = 25°C, VBST = 8.0 V VOUT Pull-down MOSFET Q3 RDS(ON)(10) mΩ RDS(ON) ID = 500 mA, TA = 25°C, VBST = 8.0 V Buck Converter Peak Current Limit (High Level) mΩ RDS(ON) Notes 9. Design information only. This parameter is not production tested. 10. ID refers to the MOSFET drain current 34702 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions -40°C ≤ TA ≤ 85°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 33) unless otherwise noted. Characteristic Symbol Min Typ Max Unit ROUT – 150 – Ω AVOL – 80 – dB GBW – 35 – MHz SR – 200 – V/µs – 2.0 – – 0.4 – VSCRamp – 0.5 – V VSCRamp – 0.5 – V VOSC_OL – – 0.4 V VOSC_OH VDDI ERROR AMPLIFIER (BUCK CONVERTER) Input Impedance (11) Output Impedance (11) DC Open Loop Gain (11) Gain Bandwidth Product (11) Slew Rate (11) V VEA_OH Output Voltage – High Level Output Voltage – Low Level IOEA = -1.0 mA V VEA_OL VIN1 > 3.3 V, IOEA = -1.0 mA (11), (12) (11), (12) Oscillator Ramp (11) OSCILLATOR CLKSYN Pin (open) Low Level Output Voltage IOL = +1.0 mA (13) CLKSYN Pin (open) High Level Output Voltage IOH = -1.0 mA (14) CLKSYN Pin (grounded) Input Voltage Threshold CLKSYN Pin Pullup Resistance Frequency Adjusting Reference Voltage V - 0.4 V – – VOSC_IH 1.2 – 2.0 V RPU 60 – 240 kΩ VFREQ – 1.26 – V 7.3 7.7 8.3 BOOST REGULATOR Regulator Output Voltage Power MOSFET Q5 RDS(ON)(11) Regulator Recommended Output Capacitor Maximum ESR Notes 11. 12. 13. 14. mΩ RDS(ON) IBD = 500 mA, TA = 25°C Regulator Recommended Output Capacitor V VBST IBST = 20 mA, VIN1 = VIN2 = 2.8 V to 6.0 V – 650 1000 CBST – 10 – µF ESRCBST – 100 – mΩ Design information only. This parameter is not production tested. IOEA Refers to Error Amplifier Output Current. IOL Refers to IO Low Level Threshold Voltage Current IOH Refers to IO High Level Threshold Voltage Current 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions -40°C ≤ TA ≤ 85°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 33) unless otherwise noted. Characteristic Symbol Min Typ Max Unit LINEAR REGULATOR (LDO) LDO Feedback Voltage (16) VLFB VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 10 mA to 1000 mA. Includes Load Regulation Error V 0.784 0.800 0.816 VMLDO – 1.0 – % LDO Voltage Margining Highest Positive Value VMP 5.9 7.0 7.9 % LDO Voltage Margining Lowest Negative Value VMN -7.9 7.0 -5.9 % -1.0 – 1.0 LDO Voltage Margining Step Size LDO Line Regulation (16) LDO Load Regulation (16) % REGLDVLDO ILDO = 10 mA to 1000 mA LDO Ripple Rejection, Dropout Voltage % REGLNVLDO VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 1000 mA (16) -1.0 – 1.0 – 40 – dB VLDO_RR VDO = 1.0 V, VRIPPLE = +1.0 V p-p Sinusoidal, f = 300 kHz, ILDO = 500 mA (15) LDO Maximum Dropout Voltage (VIN - VLDO), using IRL2703 (16) mV VDO VLDO = 2.5 V, ILDO = 1000 mA – 50 75 VCSTH 35 50 65 mV LDO Pin Input Current, VLDO = 5.25 V ILDO 1.0 1.9 4.0 mA LDO Feedback Input Current (LFB Pin), VLFB = 0.8 V ILFB -1.0 – 1.0 µA LDO Drive Output Current (LDRV Pin), VLDRV = 0 V ILDRV -5.0 -3.3 -2.0 mA CS Pin Input Leakage Current ICSLK 50 – 200 0.75 – 2.0 – – 1.9 CLDO – 10 – µF ESRCLDO – 5.0 – mΩ TSD 150 170 190 °C TSDHYS – 10 – °C LDO Current Sense Comparator Threshold Voltage (VCS - VLDO) µA VCS = 5.25 V LDO Pulldown MOSFET Q4 Current Limit LDO Pulldown MOSFET Q4 RDS(ON) A IM4_LIM TA = 25°C, VBST = 8.0 V (LDO Pin) LDO Recommended Output Capacitance LDO Recommended Output Capacitor ESR Thermal Shutdown (LDO Pull-down MOSFET Q4) (15) Thermal Shutdown Hysteresis (15) Ω RDS(ON) ID = 1.0 A, VBST = 8.0 V Notes 15. Design information only. This parameter is not production tested. 16. IDO refers to Load Current on External LDOFET - IRL2703 is the Intersil MOSFET IRL2703 34702 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions -40°C ≤ TA ≤ 85°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 33) unless otherwise noted. Characteristic Symbol Min Typ Max Unit VTH_EN 1.0 1.5 2.0 V Enable (EN1, EN2) Pulldown Resistance RPU 30 55 90 kΩ RST Low-Level Output Voltage, IOL = 5.0 mA VOL – – 0.4 V ILKG-RST – – 10 µA VOUTI Th -14 – -0.5 % RST Overvoltage Threshold on VOUT (∆VOUT/VOUT) (17) VOUTI Th 0.5 – 14 % RST Undervoltage Threshold on VLDO (∆VLDO/VLDO) (17) VLDOI Th -12 – -4.0 % VLDOI Th 4.0 – 12 % VTH-RT 1.0 1.2 1.5 V IS-RT -17 – -34 mA RST Timer Leakage Current ILKG-RT -1.0 – 1.0 µA RST Timer Saturation Voltage, Reset Timer Current = 300 µA VSAT-RT – 35 100 mV Maximum Recommended Value of the Reset Timer Capacitor Ct – – 47 µF CLKSEL Threshold Voltage VTHCLKS 1.2 1.6 2.0 V CLKSEL Pullup Resistance RPU-CLKS 60 120 240 kΩ ADDR Threshold Voltage (17) VTHADDR 1.2 1.6 2.0 V ADDR Pullup Resistance RPU-ADDR 60 120 240 kΩ TLIM 150 170 190 °C TLIMHYS – 10 – °C Input Threshold Voltage (Pin SCL), Rising Edge (17) VLTH 1.3 – 1.7 V Input Threshold Voltage (Pin SDA) VLTH 1.3 – 1.7 V II – 1.0 10 µA VOL – – 0.4 V CINPUT – 7.0 10 pF CONTROL AND SUPERVISORY CIRCUITS Enable (EN1, EN2) Input Voltage Threshold RST Leakage Current, OFF State, Pulled Up to 5.25 V RST Undervoltage Threshold on VOUT (∆VOUT/VOUT) RST Overvoltage Threshold on VLDO (∆VLDO/VLDO) (17) (17) RST Timer Voltage Threshold RST Timer Source Current (RT pin at 0 V) Thermal Shutdown (IC sensor) (17) Thermal Shutdown Hysteresis (17) SDA, SCL PINS I2C BUS (STANDARD) SDA, SCL Input Current, Input Voltage = 5.25 V (VIN1) SDA Low-Level Output Voltage, 3.0 mA Sink Current SDA, SCL Capacitance (17) Notes 17. Design information only. This parameter is not production tested. 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40°C ≤ TA ≤ 85°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figures 33) unless otherwise noted. Characteristic Symbol Min Typ Max Unit D 0 – 95 % BUCK CONVERTER Duty Cycle Range (Normal Operation) (18) Switching Node SW Rise Time (18) VIN = 5.0 V, ILOAD = 1.0 A Switching Node SW Fall Time (18) Maximum Deadtime (18) tD (18) 7.0 – – 17 – – 35 – ns Soft Start Duration (Power Sequencing Disabled, EN1 = 1, EN2 = 1) (18) Fault Condition Time-Out (18) (18) ns ns tPD VINV < 0.8 V to VSW > 90% of High Level or VINV > 0.8 V to VSW < 10% of Low Level Retry Timer Cycle – tFALL VIN = 5.0 V, ILOAD = 1.0 A Buck Control Loop Propagation Delay ns tRISE – 50 – tSS 200 350 800 µs tFAULT – 10 – ms tRet – 100 – ms OSCILLATOR Oscillator Center Frequency(20) RF = 11.3 kΩ 270 Oscillator Frequency Range Oscillator Frequency Adjusting Resistor Range Oscillator Frequency Adjustment kHz fOSC (19), (20) fOSC 200 RFREQ 7.0 330 400 kHz – 22 kΩ 400 – – – – 200 – 300 – 40 50 60 1.0 – – kHz fOSC RF = 7.0 kΩ Oscillator Frequency Adjustment (19), (20) 300 kHz fOSC RF = 22 kΩ Oscillator Default Frequency (Switching Frequency), FREQ Pin Open fOSC Oscillator Output Signal Duty Cycle (Square Wave, 180° Out-of-Phase with the Internal Suitable Oscillator) DOSC Synchronization Pulse Minimum Duration (18) tSYNC kHz % µs Notes 18. Design information only. This parameter is not production tested. 19. see Figure 4 for more details 20. RF = RFREQ resistor connected to the FREQ pin. 34702 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions -40°C ≤ TA ≤ 85°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figures 33) unless otherwise noted. Characteristic Symbol Min Typ Max Unit tON – 24 – µs tBST_PD – 50 – ns – 5.0 – 3.0 tFAULT 8.0 10 12 ms tRet 80 100 120 ms Monitoring LFB Pin Delay tD_RST_LFB 12 – 28 µs Monitoring INV Pin Delay tD_RST_INV 12 – 28 µs SCL Clock Frequency (21) fSCL – – 100 kHz Bus Free Time Between a STOP and a START Condition (21) tBUF 4.7 – – µs 4.0 – – BOOST REGULATOR Boost Regulator MOSFET Maximum ON Time (21) Boost Regulator Control Loop Propagation Delay (21) Boost Switching Node VBD Rise Time (21) Boost Switching Node VBD Fall Time (21) ns tB_RISE IBST = 20 mA ns tB_FALL IBST = 20 mA LINEAR REGULATOR (LDO) Fault Condition Time-Out Retry Timer Cycle Reset Monitor (RST) SCA, SCL PIN, I2C BUS (STANDARD) Hold Time (Repeated) START Condition (After this period, the first clock µs tHD-STA pulse is generated.) (21) Low Period of the SCL Clock (21) tLOW 4.7 – – µs High Period of the SCL Clock (21) tHIGH 4.0 – – µs – – 250 SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10 pF to 400 tF pF, 3.0 mA Sink Current (21), (23) ns Setup Time for a Repeated START Condition (21) tSU-STA 4.7 – – µs Data Hold Time for I2C Bus Devices (21), (22) tHD-DAT 0.0 – – µs Data Setup Time (21) tSU-DAT 250 – – ns Setup Time for STOP Condition (21) tSU-STO 4.0 – – µs CB – – 400 pF Capacitive Load for Each Bus Line (21) Notes 21. Design information only. This parameter is not production tested. 22. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. 23. VIH = High level voltage on I²C bus and VIL = Low level voltage on I²C bus 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS TIMING DIAGRAM TIMING DIAGRAM tHD-STA tHD-STA tSU-STO tSU-STA tSU-DAT tHD-DAT Note: Refer to the latest I2C bus specification for further details. Figure 4. Definition of Time on the I2C Bus ELECTRICAL PERFORMANCE CURVES fOSC (kHz) (kHz) Oscillator frequency fOSC (kHz) fOSC (kHz) Fosc Fosc (kHz) (kHz) 300 300 295 295 290 290 285 285 280 280 -50 -50 0 50 0 50 Temperature (°C) Temperature (°C) Temperature (C°) Figure 5. fOSC vs. Temperature 100 100 450 400 350 300 250 200 150 100 7 12 17 22 Rf(k (kOhm Rf Ω) ) Figure 6. fOSC vs. Rf 34702 14 Analog Integrated Circuit Device Data Freescale Semiconductor 0.83 100 90 80 70 60 50 40 30 20 10 0 0.82 Vin=3.3V, Vin=3.3V, Vin=5.0V, Vin=5.0V, VREF Vref(V) (V) Switcher Efficiency [%] ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES Vout=1.2V Vout=1.8V Vout=1.2V Vout=1.8V 0.81 0.80 0.79 0.78 0.77 -50 0 0.5 1 1.5 2 2.5 3 3.5 0 50 100 TTemperature e m p e r atu r e(C°) (°C) Load Current [A] Figure 7. Switcher Efficiency vs. Load Current 5.00 4.75 4.50 4.25 4.00 3.75 3.50 3.25 3.00 Timer (ms) Switcher I LIM (A) Figure 9. VREF vs. Temperature -50 0 50 Temperature (C°) Figure 8. Switcher ILIM vs. Temperature 100 25 23 21 19 17 15 13 11 9 7 5 0 100 200 300 RT (kOhm) with CT = 33nF RT (k Ω) with CT = 33 nF Figure 10. Timer (ms) vs. RT 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 34702 power supply integrated circuit provides the means to efficiently supply the Freescale Power QUICC and other families of Freescale microprocessors. It incorporates a high-performance synchronous buck regulator, supplying the microprocessor’s core, and a low dropout (LDO) linear regulator providing the microprocessor I/O and bus voltages. This device incorporates many advanced features; e.g., precisely maintained up/down power sequencing, ensuring the proper operation and protection of the CPU and power system. At the same time, it provides high flexibility of configuration, allowing the maximum optimization of the power supply system. FUNCTIONAL PIN DESCRIPTION OSCILLATOR FREQUENCY PIN (FREQ) This switcher frequency selection pin can be adjusted by connecting external resistor RF to the FREQ pin. The default switching frequency (FREQ pin left open or tied to VDDI) is set to 300 kHz. BOOTSTRAP PIN (BOOT) Bootstrap capacitor input. SERIAL DATA PIN (SDA) I2C bus pin. Serial data. INVERTING INPUT PIN (INV) Buck Controller Error Amplifier inverting input. OUTPUT VOLTAGE PIN (VOUT) Output voltage of the buck converter. Input pin of the switching regulator power sequence control circuit. SERIAL CLOCK PIN (SCL) I2C bus pin. Serial clock. LINEAR COMPENSATION PIN (LCMP) Linear regulator compensation pin. INPUT VOLTAGE 2 PINS (VIN2) Buck regulator power input. Drain of the high-side power MOSFET. SWITCH PINS (SW) Buck regulator switching node. This pin is connected to the inductor. GROUND PINS (GND) Analog ground of the IC, thermal heatsinking. POWER GROUND PINS (PGND) Buck regulator power ground. BOOST DRAIN PIN (VBD) Drain of the internal boost regulator power MOSFET. BOOST VOLTAGE PIN (VBST) Internal boost regulator output voltage. The internal boost regulator provides a 20 mA output current to supply the drive circuits for the integrated power MOSFETs and the external N-channel power MOSFET of the linear regulator. The voltage at the VBST pin is 7.75V nominal. LINEAR FEEDBACK PIN (LFB) Linear regulator feedback pin. LINEAR REGULATOR PIN (LDO) Input pin of the linear regulator power sequence control circuit. CURRENT SENSE PIN (CS) Current sense pin of the LDO. Overcurrent protection of the linear regulator external power MOSFET. The voltage drop over the LDO current sense resistor RS is sensed between the CS and LDO pins. The LDO current limit can be adjusted by selecting the proper value of the current sensing resistor RS. LINEAR DRIVE PIN (LDRV) LDO gate drive of the external pass N-channel MOSFET. INPUT VOLTAGE 1 PIN (VIN1) The input supply pin for the integrated circuit. The internal circuits of the IC are supplied through this pin. 34702 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION POWER SUPPLY PIN (VDDI) RESET TIMER PIN (RT) Internal supply voltage. A ceramic low ESR 1uF 6V X5R or X7R capacitor is recommended. The Reset Timer power-up delay (RT) pin is used to set the delay between the time when the LDO and switcher outputs are active and stable and the RST output is released. An external resistor and capacitor are used to program the timer. The power-up delay can be obtained by using the following formula: t D = 10 ms + R tC t Where R t is the Reset Timer programming resistor and C t is the Reset Timer programming capacitor, both connected in parallel from RT to ground. Note Observe the maximum C t value and expect reduced accuracy if R t is less than 10 kΩ. ADDRESS PIN (ADDR) The ADDR pin is used to set the address of the device when used in an I2C communication. This pin can either be tied to VDDI or grounded through a 10 kΩ resistor. Refer to I2C Bus Operation on page 26 for more information on this pin. ENABLE 1 AND 2 PINS (EN1 AND EN2) These two pins permit positive logic control of the Enable function and selection of the Power Sequencing mode concurrently. Table 5 depicts the EN1 and EN2 function and Power Sequencing mode selection. Both EN1 and EN2 pins have internal pull-down resistors and both can withstand a short circuit to the supply voltage, 6.0 V. Table 5. Operating Mode Selection EN1 EN2 Operating Mode 0 0 Regulators Disabled 0 1 Standard Power Sequencing 1 0 Inverted Power Sequencing 1 1 No Power Sequencing, Regulators Enabled RESET OUTPUT PIN (RST) The Reset Control circuit monitors both the switching regulator and the LDO feedback voltages. It is an open drain output and has to be pulled up to some supply voltage (e.g., the output of the LDO) by an external resistor. The Reset Control circuit supervises both output voltages—the linear regulator output VLDO and the switching regulator output VOUT. When either of these two regulators is out of regulation (high or low), the RST pin is pulled low. There is a 20 µs delay filter preventing erroneous resets. During power-up sequencing, RST is held low until the Reset Timer times out. CLOCK SELECTION PIN (CLKSEL) This pin sets the CLKSYN pin as either an oscillator output or a synchronization input pin. The CLKSEL pin is also used for the I2C address selection. CLOCK SYNCHRONIZATION PIN (CLKSYN) Oscillator output/synchronization input pin. 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION INTRODUCTION The 34702 incorporates a high-performance synchronous buck regulator, supplying the microprocessor’s core, and a low dropout (LDO) linear regulator providing the microprocessor I / O and bus voltages. This device incorporates many advanced features; e.g., precisely maintained up / down power sequencing, ensuring the proper operation and protection of the CPU and power system. Boost Regulator Power Sequencing Voltage Margining Watchdog Timer UVLO Buck Control Logic I2C Interface Reset Control POR Timer Buck HS and LS Driver VDDI Internal Supply Bandgap Bandgap Voltage Voltage Reference Reference Switcher Oscillator 300 kHz Linear Regulator Control ILIM Thermal Shutdown Figure 11. 34702 Functional Internal Block Diagram BOOST REGULATOR A boost regulator provides a high voltage necessary to properly drive the buck regulator power MOSFETs, especially during the low input voltage condition. The LDO regulator external N-channel MOSFET gate is also powered from the boost regulator. In order to properly enhance the high-side MOSFETs when only a +3.3 V supply rail powers the integrated circuit, the boost regulator provides an output voltage of 7.75 V nominal value. The 34702 boost regulator uses a simple hysteretic current control technique, which allows fast power-up and does not require any compensation. When the boost regulator main power switch (low side) is turned on, the current in the inductor starts to ramp up. After the inductor current reaches the upper current limit (nominally set at 1.0 A), the low-side switch is turned off and the current charges the output capacitor through the internal rectifier. When the inductor current falls below the valley current limit value (nominally 600 mA), the low-side switch is turned on again, starting the next switching cycle. After the boost regulator output capacitor reaches approximately 6.0 volts, the peak and valley current limit levels are proportionally scaled down to approximately one fifth of their original values. When the boost regulator reaches its regulation limit (7.75 V typical), the low-side switch is turned off until the output voltage falls below the regulation limit again. The higher current limit values in the beginning of the boost regulator start-up sequence allow fast power up of the whole IC, while the normal operation with reduced current limit greatly reduces the switching noise and therefore improves the overall EMC performance. See Figure 12 for the boost regulator output voltage and inductor current waveforms (picture not to scale). 34702 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION 7.75V Booster Output Voltage Fault Timer t FAULT = 10 ms t FAULT = 10 ms I pk Cu rrent Limit Ip k 6.0 V 0.5 I pk 0.5 Ipk Retry Timer t Ret = 10 0 ms 0A 0V Ipk = 1 A typ. Booster Inductor Current 0.6 A typ. 0.2 A typ. 0.1 A typ. Figure 12. Boost Regulator Startup (Not To Scale) SWITCHING REGULATOR The switching regulator is a high-frequency (300 kHz default, adjustable in the range from 200 kHz to 400 kHz), synchronous buck converter driving integrated high-side and low-side N-channel power MOSFETs. The switching regulator output voltage is adjustable by means of an external resistor divider to provide the required output voltage within ±2.0% accuracy, and is intended to directly power the core of the microprocessor. The buck controller uses a PWM Voltage Mode Control topology with Feed-Forward to achieve excellent line and load regulation. The 34702 integrated boost regulator provides a 7.75 V rail which is used to properly bias the switcher’s MOSFET. In addition, the boost structure has a very low start up voltage (Typically 1.6 V), hence ensuring very low input voltage functionality. A typical bootstrap technique is used to provide voltage necessary to properly enhance the high-side MOSFET gate. When the regulator is supplied only from lowinput voltage (e.g., single +3.3 V supply rail), the bootstrap capacitor is charged from the internal boost regulator output VBST through an external diode. This arrangement allows the 34702 to operate from very low input voltage and also comply with the power sequencing requirements of the supplied microcontroller. Figure 13. Switching Regulator Current Limit (Not To Scale) To avoid destruction of the supplied circuits, the switching regulator has a current limit with retry capability. When an overcurrent condition occurs and the switch current reaches the peak current limit value, the main (high-side) switch is turned off until the inductor current decays to the valley value, which is one-half of the peak current limit. If an overcurrent condition exists for 10 ms, the buck regulator control circuit shuts the switcher OFF and the switcher retry timer starts to time out. When the timer expires after 100 ms, the switcher engages the start-up sequence and runs for 10 ms, repeatedly checking for the overcurrent condition. Figure 13 describes the switching regulator overcurrent condition and current limit. During the current limited operation (e.g., in case of short circuit on the switching regulator output), the switching regulator operation is not synchronized to the oscillator frequency. Figure 14 (respectively Figure 15) depicts the current limit with a retry capability feature of the switcher (respectively LDO). Figure 14. Switching Converter Overcurrent Protection 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION 100 ms, the LDO tries to power up again for 10 ms, repeatedly checking for the overcurrent condition. The current limit of the LDO can be set by using the following formula: ILIM = 50 mV / RS Figure 15. LDO Converter Overcurrent Protection The output voltage VOUT can be adjusted by means of an external resistor divider connected to the feedback control pin INV. The switching regulator output voltage can be adjusted in the range of 0.8 V to VIN - buck dropout voltage. Power-up, power-down, and fault management are coordinated with the linear regulator. SWITCHER OSCILLATOR A 300 kHz (default) oscillator sets the switching frequency of the buck regulator. The frequency of the oscillator can be adjusted between 200 kHz and 400 kHz by an optional external resistor RF connected from the FREQ pin of the integrated circuit to ground. See Figure 6 on page 14 for frequency resistor selection. The CLKSYN pin can be configured as either an oscillator output when the CLKSEL pin is left open or as a synchronization input when the CLKSEL pin is grounded. The oscillator output signal is a square wave logic signal with 50% duty cycle, 180 degrees out-of-phase with the internal clock signal. This allows opposite phase synchronization of two 34702 devices. When the CLKSYN pin is used as a synchronization input (CLKSEL pin grounded), the external resistor RF chosen from the chart in Figure 6 should be used to synchronize the internal slope compensation ramp to the external clock. Operation is only recommended between 200 kHz and 400 kHz. The supplied synchronization signal does not need to be 50% duty cycle. Minimum pulse width is 1.0 µs. LOW DROPOUT LINEAR REGULATOR (LDO) The adjustable low dropout linear regulator (LDO) is capable of supplying a 1.0 A output current. It has a current limit with retry capability. When the voltage measured across the current sense resistor reaches the 50 mV threshold, the control circuit limits the current for 10 ms. If the overcurrent condition still exists, the linear regulator is turned off and the retry timer starts to time out. When the timer expires after Where RS is the LDO current sense resistor, connected between the CS pin and the LDO pin output (see Figure 33 on page 34), and 50 mV is the typical value of the LDO current sense comparator threshold voltage. When no current sense resistor is used, it is still possible to detect the overcurrent condition by tying the current sense pin CS to the VBST voltage. In this case, the overcurrent condition is sensed by saturation of the linear regulator driver buffer. The output voltage of the LDO can be adjusted by means of an external resistor divider connected to the feedback control pin LFB. The linear regulator output voltage can be adjusted in the range of 0.8 V to VIN - LDO dropout voltage. Power-up, power-down, and fault management are coordinated with the switching regulator. POWER SEQUENCING VOLTAGE MARGINING WATCHDOG TIMER A watchdog function is available via I2C bus communication. It is possible to select either window watchdog or time-out watchdog operation, as illustrated in Figure 16. Watchdog time-out starts when the watchdog function is activated via I2C bus sending a Watchdog Programming command byte, thus determining watchdog operation (window or time-out) and period duration (refer to Table 8, page 27). If the watchdog is cleared by receiving a new Watchdog Programming command through the I2C bus, the watchdog timer is reset and the new time-out period begins. If the watchdog time expires, the RST will become active (LOW) for a time determined by the RC components of the RT timer plus 10 ms. After a watchdog time-out, the function is no longer active. Watchdog Closed No Watchdog Clear Allowed Window Open for Watchdog Clear 50% of Watchdog Period Watchdog Period Timing Selected via 12C Bus – See Table 4 Window Watchdog Window Open for Watchdog Clear Watchdog Period Timing Selected via I2C Bus – See Table 4 Time-Out Watchdog Figure 16. Watchdog Operation 34702 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION When the Window Watchdog function is selected, the timer cannot be cleared during the Closed Window time, which is 50% of the total watchdog period. When the watchdog is cleared, the timer is reset and starts a new timeout period. If the watchdog is not cleared during the Open Window time, the RST will become active (LOW) for a time determined by the RC components of the RT timer plus 10 ms. 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES THERMAL SHUTDOWN POWER SEQUENCING MODES To increase the overall safety of the system designed with the 34702, an internal thermal shutdown function has been incorporated into the switching regulator circuit. The 34702 senses the temperature of the buck regulator main switching MOSFET (high-side MOSFET M1; see Figure 2 on page 2), the low-side (synchronous MOSFET M2), and control circuit. If the temperature of any of the monitored components exceeds the limit of safe operation (thermal shutdown), the switching regulator and the LDO shut down. After the temperature falls below the value given by the thermal shutdown hysteresis window, the switcher tries again to operate. The VOUT pull-down MOSFET M3 has an independent thermal shutdown control. If the M3 temperature exceeds the thermal shutdown limit, the M3 is turned off without affecting the switcher operation. The power sequencing of the two outputs of this power supply IC is in compliance with the Freescale Power QUICC and other 32-bit microprocessor requirements. When the input voltage is applied, the switcher and linear regulator outputs follow the supply rail voltage during power-up and power-down in the limits given by the microcontroller power sequencing specification, illustrated in Figures 17 through 19. There are two possible power sequencing modes, Standard and Inverted, as explained in more detail below. The third mode of operation is Power Sequencing Disabled. 3.3 V Input 2.5 V 34702 VIN2 VIN1 VBD VBST LDRV CS The LDO pull-down MOSFET M4 has an independent thermal shutdown control. If the M4 temperature exceeds the thermal shutdown limit, the M4 will be turned off without affecting the LDO operation. ADDR SOFT START SDA SCL GND RT A switching regulator soft start feature is incorporated in the 34702. The soft start is active each time the IC is enabled, VIN is reapplied, or after a fault retry. Other transient events do not activate the soft start. EN1 EN2 CLKSYN CLKSEL FREQ Optional VDDL (Core) LFB MCU RST BOOT VBST 1.5 V VDDH (I/Os) SW VOUT PGND INV VDDI VOLTAGE MARGINING The 34702 includes a voltage margining feature accessed through the I2C bus. Voltage margining allows for independent adjustment of the Switcher VOUT voltage and the linear output VLDO. Each can be adjusted up and down in 1.0% steps to a range of ±7.0%. This feature allows for worst case system validation; i.e., determining the design margin. Margining details are described in the section entitled I2C Bus Operation, beginning on page 26 of this datasheet. 3.3 V LDO Other Circuits 3.3 V Input Supply (I/O Voltage) 1.8V Start-Up Slope 1.0 V/ms (typ.) ∆V = 2.1 V Max. Lead 1.5 V Core Voltage ∆V = 2.1 V Max. Lead ∆V = 0.4 V Max. Lag Figure 17. Standard Power Up / Down Sequence in +3.3 V Supply System 34702 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES 5.0 V Input 5.0 V Input 34702 34702 VIN2 VIN1 VBD VBST LDRV CS Optional VIN1 VBD VBST LDRV CS ADDR SDA SCL GND RST SDA SCL GND EN1 BOOT MCU EN2 CLKSYN VOUT CLKSEL PGND FREQ VBST 5.0 V 1.5 V VDDL (Core) SW Optional INV MCU EN1 EN2 BOOT CLKSYN VOUT CLKSEL PGND VBST SW FREQ 3.3 V VDDH (I/Os) INV 5.0 V Input Supply 3.3 V I/O Voltage (VOUT) 5.0 V Input Supply ∆V = 2.1 V Max. Lead 3.3 V I/O Voltage (VLDO) 1.5 V Core Voltage ∆V = 0.4 V Max. Lag LFB VDDI ∆V = 2.1 V Max. Lead 1.8V Start-Up VDDL (Core) RST VDDI ∆V = 2.1 V Max. Lead 1.5 V LDO RT VDDH (I/Os) LFB ADDR 5.0 V 3.3 V LDO RT VIN2 (VOUT) ∆V = 0.4 V Max. Lag Figure 18. Standard Power Up / Down Sequence in +5.0 V Supply System STANDARD POWER SEQUENCING When the power supply IC operates in the Standard Power Sequencing mode, the switcher output provides the core voltage for the microprocessor. This situation and operating conditions are illustrated in Figures 17 and 18. Table 5, page 17, shows the Power Sequencing mode selection. INVERTED POWER SEQUENCING When the power supply IC is operating in the Inverted Power Sequencing mode, the linear regulator (LDO) output provides the core voltage for the microprocessor, as illustrated in Figure 19. Table 5 shows the Power Sequencing mode selection. 1.8V Start-Up ∆V = 2.1 V Max. Lead 1.5 V Core Voltage (VLDO) ∆V = 0.4 V Max. Lag ∆V = 0.4 V Max. Lag Figure 19. Inverted Power Up / Down Sequence in +5.0 V Supply System ASSUMED REQUIREMENTS 1. I/O supply voltage not to exceed core voltage by more than 2.0 V. 2. Core supply voltage not to exceed I/O voltage by more than 0.4 V. Methods of Control The 34702 has several methods of monitoring and controlling the regulator output voltages, as described in the paragraphs below. Power sequencing control is also achieved through the intrinsic operation of the regulators. The EN1 and EN2 pins can be used to select the proper power sequencing mode required by the powered system or to disable the power sequencing (refer to Table 5). Intrinsic Operation For both the LDO and switcher, whenever the output voltage is below the regulation point, the LDO external Pass MOSFET is on, or the Buck High-Side MOSFET is on at a duty cycle controlled by the switcher. Because these devices are MOSFETs, current can flow in either direction, balancing the voltages via the common supply pin. The ability to maintain the MOSFETs on is dependent on the available gate voltage, and thus the size of the boost regulator storage capacitor. 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Standard Power Sequencing Control Comparators monitor voltage differences between the LDO (LDO pin) and the switcher (VOUT pin) outputs as follows: 1. LDO > VOUT + 1.9 V, turn off LDO. The LDO can be forced off. This occurs whenever the LDO output voltage exceeds the switcher output voltage by more than 1.9 V. 2. LDO > VOUT + 2.0 V, shunt LDO to ground. If turning off the LDO is insufficient and the LDO output voltage exceeds the switcher output voltage by more than 2.0 V, a 1.5 Ω shunt MOSFET is turned on that discharges the LDO load capacitor to ground. The shunt MOSFET is used for switcher output shorts to ground and for power down in case of VIN1 ≠ VIN2 with the switcher output falling faster than the LDO. 3. LDO < VOUT + 1.9 V cancel (2). VOUT output voltage is less than 1.8 V above the LDO output voltage. 4. VOUT < LDO + 2.0 V, cancel (2) 5. VOUT < LDO - 0.2 V, turn off LDO. The LDO can be forced off. This occurs whenever the VOUT is less than VLDO - 0.2 V. 6. VOUT < LDO - 0.3 V, turn on the 1.5 Ω LDO sink MOSFET. This occurs when the LDO output voltage exceeds the VOUT output by more than 300 mV. 7. VOUT < LDO - 0.2 V, cancel (6). 8. VOUT < LDO - 0.1 V, cancel (5). Normal operation resumes when VOUT > LDO - 0.1 V. STANDARD OPERATING MODE Single 3.3 V Supply, VIN = VIN1 = VIN2 = 3.3 V 4. LDO < VOUT + 1.8 V, cancel (1) above, re-enable LDO. Normal operation resumes when the LDO output voltage is less than 1.8 V above the switcher output voltage. The 3.3 V supplies the microprocessor I/O voltage, the switcher supplies core voltage (e.g., 1.5 V nominal), and the LDO operates independently (see Figure 17, page 22). Power sequencing depends only on the normal switcher intrinsic operation to control the Buck High-Side MOSFET. 5. LDO < VOUT - 0.1 V, turn off switcher. The switcher can be forced off. This occurs whenever the LDO is less than VOUT - 0.1 V. Power-Up 6. LDO < VOUT - 0.3 V, turn on Sync (LS) MOSFET and 1.5 Ω VOUT sink MOSFET. The Buck High-Side MOSFET is forced off and the Sync MOSFET is forced on. This occurs when the switcher output voltage exceeds the LDO output by more than 300 mV. When VIN is rising, initially VOUT is below the regulation point and the Buck High-Side MOSFET is on. In order not to exceed the 2.1 V differential requirement between the I/O (VIN) and the core (VOUT), the switcher must start up at 2.1 V or less and be able to maintain the 2.1 V or less differential. The maximum slew rate for VIN is 1.0 V/ms. 7. LDO > VOUT - 0.3 V, cancel (6). 8. LDO > VOUT - 0.1 V, cancel (5). Normal operation resumes when LDO < VOUT - 0.1 V. Inverted Power Sequencing Control Comparators monitor voltage differences between the switcher (VOUT pin) and LDO (LDO pin) outputs as follows: 1. VOUT > LDO + 1.8 V, turn off VOUT . The switcher VOUT can be forced off. This occurs whenever the VOUT output voltage exceeds the LDO output voltage by more than 1.8 V. 2. VOUT > LDO + 2.0 V, shunt VOUT to ground. If turning off the switcher VOUT is insufficient and the VOUT output voltage exceeds the LDO output voltage by more than 2.0 V, a 1.5 Ω shunt MOSFET and the switcher synchronous MOSFET are turned on to discharge the VOUT load capacitor to ground. The shunt MOSFET and synchronous MOSFET are used for LDO output shorts to ground and for power-down in case of VIN1 ≠ VIN2 with LDO output falling faster than the VOUT . 3. VOUT < LDO + 1.8 V, cancel (1) and (2) above, reenable VOUT . Normal operation resumes when the Power-Down When VIN is falling, VOUT falls below the regulation point; therefore, the Buck High-Side MOSFET is on. In the case where VOUT is falling faster than VIN, the Buck High-Side MOSFET attempts to maintain VOUT. In the case where VIN is falling faster than VOUT, the Buck High-Side MOSFET is also on, and the VOUT load capacitor is discharged through the Buck High-Side MOSFET to VIN. Thus, provided VIN does not fall too fast, the core voltage (VOUT) does not exceed the I/O voltage (VIN) by more than a maximum of 0.4 V. Shorted Load 1. VOUT shorted to ground. This causes the I/O voltage to exceed the core voltage by more than 2.1 V. No load protection. 2. VIN shorted to ground. Until the switcher load capacitance is discharged, the core voltage exceeds the I/O voltage by more than 0.4 V. By the intrinsic operation of the switcher, the load capacitor is discharged rapidly through the Buck High-Side MOSFET to VIN. 3. VOUT shorted to supply. No load protection. 34702 is protected by current limit and thermal shutdown. 34702 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Single 5.0 V Supply, VIN1 = VIN2, or Dual Supply VIN1 ≠ VIN2 The LDO supplies the microprocessor I/O voltage. The switcher supplies the core (e.g., 1.5 V nominal) (see Figure 18, page 23). Power-Up This condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the VIN1 and VIN2 supplies. There are two cases: 1. LDO rises faster than VOUT . The LDO uses control methods (1) and (2) described in the section Methods of Control on page 23. 2. VOUT rises faster than LDO. The switcher uses control methods (5) and (6) described in the section Methods of Control on page 23. Power-Down This condition depends upon the regulator load current and capacitance and the relative fall times of the VIN1 and VIN2 supplies. There are two cases: 1. VOUT falls faster than LDO. The LDO uses control methods (1) and (2) described in the section Methods of Control on page 23. In the case VIN1 = VIN2, the intrinsic operation turns on both the Buck High-Side MOSFET and the LDO external Pass MOSFET, and discharges the LDO load capacitor into the VIN supply. 2. LDO falls faster than VOUT . The switcher uses control methods (5) and (6) described in the section Methods of Control on page 23. Shorted Load 1. VOUT shorted to ground. The LDO uses method (1) and (2) described in the section Methods of Control on page 23. 2. LDO shorted to ground. The switcher uses control methods (5) and (6) described in the section Methods of Control on page 23. 3. VIN1 shorted to ground. Device is not working. 4. VIN2 shorted to ground with VIN1 and VIN2 different. This is equivalent to the switcher output shorted to ground. 5. VOUT shorted to supply. No load protection. 34702 is protected by current limit and thermal shutdown. 6. LDO shorted to supply. No load protection. 34702 is protected by current limit and thermal shutdown. INVERTED OPERATING MODE Single 3.3 V Supply, VIN = VIN1 = VIN2 = 3.3 V The 3.3 V supplies the microprocessor I/O voltage, the LDO supplies core voltage (e.g., 1.5 V nominal), and the switcher VOUT operates independently. Power sequencing depends only on the normal LDO intrinsic operation to control the Pass MOSFET. Power-Up When VIN is rising, initially LDO is below the regulation point and the Pass MOSFET is on. In order not to exceed the 2.1 V differential requirement between the I/O (VIN) and the core (LDO), the LDO must start up at 2.1 V or less and be able to maintain the 2.1 V or less differential. The maximum slew rate for VIN is 1.0 V/ms. Power-Down When VIN is falling, LDO falls below the regulation point; therefore, the Pass MOSFET is on. In the case where LDO is falling faster than VIN, the Pass MOSFET attempts to maintain LDO. In the case where VIN is falling faster than LDO, the Pass MOSFET is also on, and the LDO load capacitor is discharged through the Pass MOSFET to VIN. Thus, provided VIN does not fall too fast, the core voltage (LDO) does not exceed the I/O voltage (VIN) by more than maximum of 0.4 V. Shorted Load 1. LDO shorted to ground. This will cause the I/O voltage to exceed the core voltage by more than 2.1 V. No load protection. 2. VIN shorted to ground. Until the LDO load capacitance is discharged, the core voltage exceeds the I/O voltage by more than 0.4 V. By the intrinsic operation of the LDO, the load capacitor is discharged rapidly through the Pass MOSFET to VIN. 3. LDO shorted to supply. No load protection. Single 5.0 V Supply, VIN1 = VIN2, or Dual Supply VIN1 ≠ VIN2 The switcher VOUT supplies the microprocessor I/O voltage. The LDO supplies the core (e.g., 1.5 V nominal) (see Figure 19, page 23). Power-Up This condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the VIN1 and VIN2 supplies. There are two cases: 1. VOUT rises faster than LDO. The switcher VOUT uses control methods (1) and (2) described in the section Methods of Control on page 23. 2. LDO rises faster than VOUT . The LDO uses control methods (5) and (6) described in the section Methods of Control on page 23. Power-Down This condition depends upon the regulator load current and capacitance and the relative fall times of the VIN1 and VIN2 supplies. There are two cases: 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS 1. LDO falls faster than VOUT . The VOUT uses control methods (4) and (5) described in the section Methods of Control on page 23. In the case VIN1 = VIN2, the intrinsic operation turns on both the Buck High-Side MOSFET and the LDO external Pass MOSFET, and discharges the VOUT load capacitor into the VIN supply. 2. VOUT falls faster than LDO. The LDO uses control methods (5) and (6) described in the section Methods of Control on page 23. Shorted Load 1. LDO shorted to ground. The VOUT uses methods (1) and (2) described in the section Methods of Control on page 23. 2. VOUT shorted to ground. The LDO uses control methods (5) and (6) described in the section Methods of Control on page 23. 3. VIN1 shorted to ground. Device is not working. 4. VIN2 shorted to ground. This is equivalent to the switcher VOUT output shorted to ground. 5. LDO shorted to supply. No load protection. 34702 is protected by current limit and thermal shutdown. 6. VOUT shorted to supply. No load protection. 34702 is protected by current limit and thermal shutdown. LOGIC COMMANDS AND REGISTERS I2C BUS OPERATION I2C The 34702 device is compatible with the interface standard. SDA and SCL pins are the Serial Data and Serial Clock pins of the I2C bus. assure its unique address. Figure 21 illustrates the flexible addressing feature for a 7-bit address. Table 6 provides the definition of the selectable portion of the device address. When the ADDR pin is used and put to low level, pull the ADDR pin to ground through a 10 kΩ resistor. I2C COMMAND AND DATA FORMATS Communication starts with a START condition, followed by the slave device unique address. The Read/Write (R/W) bit defines whether the data should be read from or written to the device (the 34702 operates only as a slave device; therefore, the R/W bit should always be set to 0). The 34702 responds by sending the Acknowledge bit (Ack) to the master device. Figure 20 illustrates the beginning of an I2C communication for a 7-bit slave address. S 7-Bit Address Bits MSB Communication Start R/W 5 4 3 2 1 1 1 0 1 A1 A0 1 0 Figure 21. Address Bit Definition for 7-Bit Address Table 6. Definition of Selectable Portion of Device Address CLKSEL Pin ADDR Pin A1 A0 Low Low 0 0 Low High (Open) 0 1 High (Open) Low 1 0 High (Open) High (Open) 1 1 Figure 20. Communication Start Using 7-Bit Address 34702 has the two least significant address bits (LSB) defined by the state of the CLKSEL pin (A1) and the ADDR pin (A0). Note The state of the CLKSEL pin also defines the configuration of the oscillator synchronization CLKSYN pin. Leaving the CLKSEL pin open or pulling it high defines the CLKSYN pin as an oscillator output. When the CLKSEL pin is pulled low, the CLKSYN pin is configured as a synchronization input for the external clock signal. This feature allows up to four 34702 ICs to communicate in the same I2C bus, all of them sharing the same high-order address bits. A different combination of the two LSB address bits A1 and A0 can be assigned to each individual part to 6 Fixed Address Selectable Address Ack Slave Address Definition LSB Writing Data Into the Slave Device After the address acknowledgment by the slave, DATA can be written into the slave registers. The R/W bit must be set to 0 to allow DATA to be written into the 34702. Figure 22 shows the data write sequence. Actions performed by the slave device are grayed. S 7-Bit Address 0 Ack DATA Ack (Write) Figure 22. Data Transfer for Write Operations 34702 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS DATA Definition Table 8. The DATA field in the single Data Transfer contains one or several Command Bytes. The Command Byte identifies the kind of operation required by the master to be performed and has two fields, as illustrated in Figure 23: Command Byte Definitions Watchdog Programming (As a 2nd Command Byte) 1. Address field 0 1 1 0 0 0 0 0 1st Command 0 1 1 0 0 0 0 0 WD OFF (24) 0 1 1 0 1 0 0 0 WD 1280 ms Wind. OFF 0 1 1 0 1 0 0 1 WD 320 ms Wind. OFF 0 1 1 0 1 0 1 0 WD 80 ms Wind. OFF 0 1 1 0 1 0 1 1 WD 20 ms Wind. OFF 0 1 1 0 1 1 0 0 WD 1280 ms Wind. ON 0 1 1 0 1 1 0 1 WD 320 ms Wind. ON 0 1 1 0 1 1 1 0 WD 80 ms Wind. ON 0 1 1 0 1 1 1 1 WD 20 ms Wind. ON 2. Value field The address field is selected from the list in Table 7. Bits MSB 7 6 5 4 LSB 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Address Field Value Field Figure 23. Command Byte Table 7. Address Field Definitions Address Field Operation Write 001 Voltage Margining W 011 Watchdog W Refer to Table 8, page 27, which summarizes the value field definitions for the entire set of operation options. Notes 24. The Watchdog timer is turned ON automatically after receiving any other valid command byte changing watchdog time. Table 8. Security in Writing Commands Command Byte Definitions Operation Address Value Action To improve the security level, a so-called first command is defined to initiate each write communications. The first command identifies the operation, which is executed by the following Command Byte. A first command has the address field equal to the related operation one, followed by a null value field (all zeros). Table 9 summarizes first command definitions. The master sends the first command before the Command Byte for the intended operation. Voltage Margining 0 0 1 0 0 0 0 0 1st Command (As a 2nd Command Byte) 0 0 1 x 0 0 0 0 Output Nominal 0 0 1 x 0 0 0 1 + 1.0% 0 0 1 x 0 0 1 0 + 2.0% 0 0 1 x 0 0 1 1 + 3.0% 0 0 1 x 0 1 0 0 + 4.0% LDO Output: x = 0 0 0 1 x 0 1 0 1 + 5.0% Switcher Output x=1 0 0 1 x 0 1 1 0 + 6.0% 0 0 1 x 0 1 1 1 + 7.0% 0 0 1 x 1 0 0 0 - 1.0% VOLTAGE MARGINING OPERATION 0 0 1 x 1 0 0 1 - 2.0% 0 0 1 x 1 0 1 0 - 3.0% 0 0 1 x 1 0 1 1 - 4.0% 0 0 1 x 1 1 0 0 - 5.0% 0 0 1 x 1 1 0 1 - 6.0% After starting the communication in Writing mode, the master sends the first command followed by the specific Command Byte to set the required voltage margining for either the LDO or the switcher (see Figure 24). To achieve a simultaneous set for both LDO and switcher, two specific commands must be issued in sequence after the first command, one for each supply. 0 0 1 x 1 1 1 0 - 7.0% Table 9. First Command Definitions First Command Operation 001 00000 Voltage Margining 011 00000 Watchdog Programming 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS 0 0 1 0 0 0 0 0 Ack 0 0 1 x x x x x First Byte for Voltage Margining Command Byte Figure 24. Voltage Margining Programming (One Supply Only) Note: x bits, which set the voltage margining value are defined in Table 8. WATCHDOG PROGRAMMING OPERATION For watchdog operation control, the master periodically sends a watchdog first command followed by a command byte selecting, or confirming, the watchdog period according to the options listed in Table 8. See Figure 25 for the watchdog timer programming command example. The internal watchdog timer is turned ON by receiving a valid Watchdog Programming command (after receiving the Watchdog Programming First Command), and it is cleared each time the next Watchdog Programming command is written into the device, provided it arrives during the window open time. Thus, the Watchdog Programming command clears the timer and sets the new timing conditions at the same time. The Watchdog Programming First Command 01100000 sent twice shuts the timer OFF, and the watchdog function is disabled. Any other valid watchdog command turns the timer ON again. address acknowledge sent by 34702. I2C bus protocol defines this circumstance as a master-transmitter and slavereceiver configuration. Figure 27 illustrates a communication beginning with the slave address, the first command for voltage margining, and a third byte containing the address field 001 and the value field 00101 corresponding with the LDO fifth setting (LDO output voltage = +5% above its nominal value). If a simultaneous setting for switcher is needed, a fourth byte should be included before the STOP condition (P); for instance, 001 11100 to set the switcher in its twelfth setting (switcher output voltage = -5% below its nominal value) - see Figure 28. The example of data transfer setting the Watchdog timer is shown in the Figure 26. S A6 A5 A4 A3 A2 A1 A0 0 Ack START Write Slave Address 0 1 1 0 0 0 0 0 Ack First Command for Watchdog Programming 0 1 1 0 1 0 0 1 Ack P STOP Address Field Value Field: Time-out WD = 320 ms (Window OFF) 0 1 1 0 0 0 0 0 Ack 0 1 1 x x x x x First Byte for Watchdog Programming Command Byte Figure 25. Watchdog Timer Programming Note: x bits, which set the watchdog timer value are defined in Table 8, page 27. Communication Stop Only the master can terminate the data transfer by issuing a STOP condition. The slave waits for this condition to resume its initial state waiting for the next START condition (see Figure 26). Figure 26. Data Transfer Example - Watch Dog Timer Setting. S A6 A5 A4 A3 A2 A1 A0 0 Ack START Write Slave Address 0 0 1 0 0 0 0 0 Ack First Command for Voltage Margining 0 0 1 0 0 1 0 1 Ack P STOP COMPLETE DATA TRANSFER EXAMPLES The master device controlling the I2C bus always starts addressing a 34702 slave IC in writing mode (R/W = 0) to enable it to write a Command Byte just after receiving the Address Field Value Field = LDO 5th Setting Figure 27. Data Transfer Example - LDO Voltage Margining 34702 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS S A6 A5 A4 A3 A2 A1 A0 0 Ack START Write Slave Address 0 0 1 0 0 0 0 0 Ack First Command for Voltage Margining 0 0 1 0 0 1 0 1 Ack Address Field Value Field: LDO VLDO = Nom. + 5% 0 0 1 1 1 1 0 0 Ack P STOP Address Field Value Field: Switcher VOUT = Nom. - 5% Figure 28. Data Transfer Example - LDO and Switcher Voltage Margining 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 29 TYPICAL APPLICATIONS TYPICAL APPLICATIONS BUCK REGULATOR CONTROL CIRCUIT The 34702 buck regulator utilizes a PWM Voltage Mode topology with Feed-Forward to achieve an excellent line and load regulation. The control circuit block diagram is shown in Figure 29. L Figure 29. Buck Regulator Control Circuit The integrated 40 pF capacitor CF charged through the 1 external resistor R4 provides the feed-forward ramp f z ( c ) = --------------------------------------2πC2 ( R1 + R3 ) waveform, the amplitude of which is proportional to the input voltage, thus providing the feed-forward function. The Feed-Forward implemented by resistor R4 and Figure 30 shows the Bode plot of the 34702 buck regulator integrated capacitor CF creates a pole in the overall loop control loop gain and phase versus frequency. transfer function, the frequency of which can be calculated The first double pole on the Bode plot is created by the from the following formula. buck regulator output L-C filter, and its frequency can be calculated as: V IN 1 f p ( FF ) = ---------------------------------------------------------------- × --------------------( – V Ref ) V 2πR4C F 1 IN 1 ------- × -------------------------------- + V m1 f LC = ---------------------f sw R4C F 2π C O L Where CO is the value of the buck output capacitor and L is the inductance value of the output filter inductor L. The frequency of the compensating zero can be calculated as follows. Where VRef is the buck regulator reference voltage (VRef = 0.8 V typ.) at the INV pin, VIN is the buck regulator input voltage, Vm1 is the ramp generated by the internal ramp generator (Vm1 = 0.5 V typ.). 34702 30 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS . G ain [dB] 20 1 R2 = V Ref × ----------------------------------------------------------------------------------------( V O + I O × R L ) – V Ref V O – V Ref -------------------------------------------------------- + ------------------------R4 R1 fLC fz(c) Where VRef is the buck regulator reference voltage (VRef = 0.8 V typ.) at the INV pin, VO is the selected output voltage, IO is the output load current, RL is the DC resistance of the inductor L. It is apparent that the buck regulator output voltage is affected by the voltage drop caused by the inductor serial resistance and the regulator output current. In those applications which do not require precise output voltage, setting the formula for calculating selected output voltage can be simplified as follows: f BW 0 fz(E SR) fp (FF) fp(c) -20 -40 -180 Pha se [Deg.] 1 R2 = V Ref × --------------------------------------------------------------( R1 + R4 ) ( V O – V Ref ) × ------------------------R1 × R4 -2 70 Linear Regulator Output Voltage Φm -3 60 1.0 The output voltage of the linear regulator (LDO) can be set by a simple resistor divider according to the following formula: R V LDO = V Ref × ⎛⎝ 1 + ------U-⎞⎠ RL 10 100 10 00 10000 Frequency [k Hz ] Figure 30. Buck Control Loop Bode Plot The frequency of the zero created by the ESR of the output capacitor CO is calculated as: 1 f z ( ESR ) = ------------------------2πC O ESR Where CO is the value of the buck regulator output capacitor, and ESR is the equivalent series resistance of the output capacitor. Where VRef is the linear regulator reference voltage (VRef = 0.8 V typ.) at the LFB pin, VLDO is the LDO selected output voltage, RU is the “upper” resistor of the LDO resistor divider, RL is the “lower” resistor of the LDO resistor divider. Figure 31 describes the 34702 linear regulator circuit with the resistor divider RU, RL setting the output voltage VLDO. 2.8 V to 6.0 V Input MC34701 VIN1 The frequency of the compensating network pole can be calculated as follows: LDRV 1 f p ( c ) = ---------------------------------------R1R3 2πC2 ------------------------( R1 + R3 ) The well designed and compensated buck regulator should yield at least 45 deg. phase margin Φm of its overall loop as depicted in the Figure 30, page 31. Selecting Buck Regulator Output Voltage The 34702 buck regulator output voltage can be set by selecting the right value of the resistors R1, R2 and R4, and can be determined from the following formula (see Figure 29, page 30 for the component references): CS RS VLDO LDO RU LFB CLDO RL LCMP LDO Compensation Figure 31. 34702 Linear Regulator Circuit 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 31 TYPICAL APPLICATIONS Linear Regulator Current Limit As described in the Linear Regulator Functional Description section, the current limit of the linear regulator can be adjusted by means of an external current sense resistor RS. The voltage drop caused by the regulator output current flowing through the current sense resistor RS is sensed between the LDO and the CS pins. When the sensed voltage exceeds 50 mV (typical), the current limit timer starts to time out while the control circuit limits the output current. If the overcurrent condition lasts for more than 10 ms, the linear regulator is shut off and turned on again after 100 ms. This type of operation provides equivalent protection to the analog “current foldback” operation. It is important to keep in mind that the amount of capacitive load which can be supplied by the by the linear regulator is limited by the setting of the LDO current limit. During the power-up period, the linear regulator operates in the current limit, supplying the current into the load of the LDO, which includes all the capacitors connected to the regulator output. If the total amount load is so large that the regulator could not reach its regulation voltage in 10 ms during the power-up, it turns off and tries to power up again after 100 ms. This situation may lead to the power-up oscillations. NOTE: Freescale does not assume liability, endorse, or warrant components from external manufacturers referenced in figures or tables. Although Freescale offers component recommendations, it is the customer’s responsibility to validate their application. *When mounted to an FR4 using 0.5 sq.in. drain pad size The maximum power dissipation is limited by the maximum operating junction temperature TJmax. The allowed power dissipation in the given application can be calculated from the following expression: T Jmax – T A P D ( Q )max ≤ --------------------------------------------------------R thJC + R thCB + R thBA Where PD(Q)max is the power MOSFET maximum allowed dissipation, TJmax is the power MOSFET maximum operating junction temperature, TA is the ambient temperature, RthJC is the power MOSFET thermal resistance junction-to-case, RthCB is the thermal resistance case-to-board, RthBA is the thermal resistance board-to-ambient of the PC board. Linear Regulator External MOSFET The linear regulator uses an external N-channel power MOSFET to provide a pass element for the power path. The selection of the proper type of the external power MOSFET is critical for optimum performance and safe operation of the linear regulator. The power MOSFET’s threshold voltage, RDS(on), gate charge, capacitances and transconductance are important parameters for the stable operation of the linear regulator while the package of the power MOSFET determines the maximum power dissipation, and hence the maximum output current for the required input-to-output voltage drop. The power dissipation of the external MOSFET can be calculated from the simple formula: P D ( Q ) = I LDO × ( V IN – V LDO ) Where PD(Q) is the power MOSFET power dissipation VIN is the LDO input voltage, VLDO is the LDO output voltage, ILDO is the LDO output load current. Table 10 shows the recommended power MOSFET types for the 34702 linear regulator, their typical power dissipation, and thermal resistance junction-to-case. Table 10. Recommended Power MOSFETs Part No. Package Typ. PD RthJ-C IRL2703S D2PAK 2.0 W 3.3 °C/W MTD20N03HDL DPAK 1.75 W* 1.67 °C/W PCB Layout Considerations As with any power application, the proper PCB layout plays a critical role in the overall power regulator performance. While good careful printed circuit board layout significantly improves regulation parameters and electromagnetic compatibility (EMC) performance of the switching regulator, poor layout practices can lead not only to significant degradation of regulation and EMC parameters but even to total dysfunction of the whole regulator IC. Extreme care should be taken when laying out the ground of the regulator circuit. In order to avoid any inductive or capacitive coupling of the switching regulator noise into the sensitive analog control circuits, the noisy power ground and the clean quiet signal ground should be well separated on the printed circuit board, and connected only at one connection point. The power routing should be made by heavy traces or areas of copper. The power path and its return should be placed, if possible, atop each other on the different layers or opposite sides of the PC board. The switching regulator input and output capacitors should be physically placed very close to the power pins (VIN2, SW, PGND) of the 34702 switching regulator; and their ground pins, together with the 34702 power ground pins (PGND), should be connected by a single island of the power ground copper to create the “single-point” grounding. Figure 32 illustrates the 34702 switching regulator grounding concept. The bootstrap capacitor Cb should be tightly connected to the integrated circuit as well. 34702 32 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS VBST BOOT The same guidelines as those for the layout of the main switching buck regulator should be applied to the layout of the low power auxiliary boost regulator and to some extent, the power path of the linear regulator. Vin = 5.0 V Cb VIN2 Vout = 1.5 V SW To Load INV Vout Return PGND GND Power Ground Signal Ground Figure 32. 34702 Buck Regulator Layout 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 33 TYPICAL APPLICATIONS VIN1 +3.3V Supply Voltage VIN VDDI Internal Supply CIN 10uF VBST 8.0V Power Enable - 10uH Q5 Boost Control Vref Vref +3.3V or VLDO LDRV VDDI VDDI VBD Bandgap Voltage Reference Vref Linear Regulator Control LDO I-lim LFB RS 0.022 R 5.1k RST RESET to MCU Q6 RT VLDO Power Sequencing Reset Reset Control POR Timer Power Down Voltage Margining @1.0A INV SysCon Thermal Limit SoftSt ADDR SDA Buck Control Logic 6.8nF VBST VIN2 +3.3V Supply Voltage (2) Buck HS & LS Driver Q1 CIN 2 x 22 uF SW CB DB 0.1uF Error Amp. PWM Comp. + - Q2 To Reset 0.8V Control + FREQ 300k 39k 27k Q3 + (2) VOUT Pow. Seq. VOUT=1.8V CO 100 uF INV - Ramp Gen. CLKSYN L1 4.7 uH (2) PGND Switcher Oscillator 300kHz CLKSEL 1.5k BOOT I2C Interface SCL CLDO 5 x 2.2 uF VBST VDDI Ct Rpd UVLO VBST I2C Control LCMP 100pF Current Limit SysCon I2C Control Q4 VOUT W-dog Timer LFB 100nF Pow. Seq. VLDO=3.3V 4.7k 1.5k EN1 RST 10k QLDO CS VDDI EN2 Rt 100k 1.0 uF VBST + Vref LBST VDDI VBST 7.75V CBST 10uF VDDI Rb 300 VOUT 470pF (4) GND RF (Optional) Figure 33. Simplified Block Diagram and Basic Application 34702 34 Analog Integrated Circuit Device Data Freescale Semiconductor 1 GND VIN C36 1.0uF + C37 10uF Optional C37, L3 L3 3.3uH 1 2 RLF7030-3R3M4R1 C2 10uF 1 L2 D2 LL4148 C40 R18 4.7nF 2.2R VBD Optional 2 C40, R18 10uH SLF6025T C3 100uF + 13 12 4 5 23 26 31 C33 10uF/16V C18 1.0uF C39 1.0uF VIN2 27 28 15 16 32 1 MC34701 VDDI ADDR CLKSEL VBST VBD VIN2 VIN2 EN1 EN2 SDA SCL CLKSYN FREQ 7. C3, C10 = 100uF/6.3V, 10THB100ML POSCAP capacitor from Sanyo. 6. C2 = 10uF/10V, ceramic capacitor . 5. L3 = 3.3uH, RLF7030-3R3M4R1 from TDK or 1812PS-103M from Coilcraft. 4. L2 = 10uH, SLF6025T-100M1R3 from TDK or CDRH104R-4R7 from Sumida. 3. L1 = 4.7uH, DO3316P-472HC from Coilcraft R12 = 36K for Vout = 1.5V. R12 = 27K for Vout = 1.8V. 2. R12 = 16K for Vout = 2.5V 1. R11 can be adjusted according to the required LDO current limit. NOTES: 1 1 SDA SCL 1 VCC5V 1 CLKSY N BOOT U6 GND 8 R1 10k GND 9 GND 24 Analog Integrated Circuit Device Data Freescale Semiconductor GND 25 VIN2 VIN1 VOUT INV PGND PGND SW SW BOOT RT /RESET LCMP LFB LDO CS LDRV 3 2 10 11 6 7 14 29 30 17 18 C15 100nF R12 1.5k R17 C16 1.0uF Signal ground BOOT LCMP CS 20 19 LDRV 21 22 1 R10 300k R4 10k C7 33nF C34 10nF 6.8nF C35 L1 2 R8 39k Power ground R9 300R C17 470pF 4.7uH R11 0.022R R15 1.5k R13 4.7k 100uF C10 + 10nF C14 R19 510R 5 x 2.2 uF C23 10uF Q1 IRL2703S or MTD20N03HDL 5.1k R2 3.3V 1 1 1 VOUT RESET VLDO TYPICAL APPLICATIONS Figure 34. 34702 Typical Application Circuit 34702 35 PACKAGE DIMENSIONS PACKAGE DIMENSIONS Important: For the most current package revision, visit www.freescale.com and perform a “keyword” search for “98AARH99137A”. NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER–LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 10.3 7.6 7.4 C 5 B 2.65 2.35 9 30X 1 32 0.65 PIN 1 ID 4 B 9 B 16 11.1 10.9 CL 17 A 5.15 32X 2X 16 TIPS 0.3 SEATING PLANE A B 0.10 A C A ÇÇÇÇ ÉÉÉ ÇÇÇÇ ÉÉÉ ÇÇÇÇ (0.29) 0.25 0.19 A 6 0.13 BASE METAL (0.203) 0.38 0.22 M C A M R0.08 MIN 0.25 PLATING B GAUGE PLANE 0° MIN 0.29 0.13 8 SECTION A–A ROTATED 90_ CLOCKWISE 8° 0° 0.9 0.5 SECTION B–B 98AARH99137A CASE 1324–02 ISSUE A 34702 36 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 5.0 2/2006 • Changed Document Order No. 6.0 2/2007 • • • • Updated to the current Freescale form and style. Changed the status from Advance Information to Final. Added Peak Package Reflow Temperature During Reflow (2), (3) Added Notes (2) and (3) 34702 Analog Integrated Circuit Device Data Freescale Semiconductor 37 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http:// www.freescale.com/epp. USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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