2.5 V to 5.5 V, 500 μA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs AD5305/AD5315/AD5325 FEATURES GENERAL DESCRIPTION AD5305: 4 buffered 8-bit DACs in 10-lead MSOP A version: ±1 LSB INL, B version: ±0.625 LSB INL AD5315: 4 buffered 10-bit DACs in 10-lead MSOP A version: ±4 LSB INL, B version: ±2.5 LSB INL AD5325: 4 buffered 12-bit DACs in 10-lead MSOP A version: ±16 LSB INL, B version: ±10 LSB INL Low power operation: 500 μA @ 3 V, 600 μA @ 5 V 2-wire (I2C®-compatible) serial interface 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Power-down to 80 nA @ 3 V, 200 nA @ 5 V Three power-down modes Double-buffered input logic Output range: 0 V to VREF Power-on reset to 0 V Simultaneous update of outputs (LDAC function) Software clear facility Data readback facility On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +105°C The AD5305/AD5315/AD53251 are quad 8-, 10-, and 12-bit buffered voltage output DACs in a 10-lead MSOP that operate from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V. Their on-chip output amplifiers allow rail-to-rail output swing with a slew rate of 0.7 V/μs. A 2-wire serial interface that operates at clock rates up to 400 kHz is used. This interface is SMBus compatible at VDD < 3.6 V. Multiple devices can be placed on the same bus. The references for the four DACs are derived from one reference pin. The outputs of all DACs can be updated simultaneously using the software LDAC function. The parts incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write takes place to the device. There is also a software clear function to reset all input and DAC registers to 0 V. The parts contain a power-down feature that reduces the current consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V). The low power consumption of these parts in normal operation makes them ideally suited for portable battery-operated equipment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing to 1 μW in power-down mode. APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process control 1 Protected by U.S. Patent No. 5,969,657 and 5,684,481. FUNCTIONAL BLOCK DIAGRAM VDD REF IN LDAC SCL DAC REGISTER STRING DAC A BUFFER VOUTA INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB INPUT REGISTER DAC REGISTER STRING DAC C BUFFER VOUTC INPUT REGISTER DAC REGISTER STRING DAC D BUFFER VOUTD INTERFACE LOGIC A0 POWER-ON RESET AD5305/AD5315/AD5325 GND POWER-DOWN LOGIC 00930-001 SDA INPUT REGISTER Figure 1. Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD5305/AD5315/AD5325 TABLE OF CONTENTS Features .............................................................................................. 1 Read/Write Sequence................................................................. 16 Applications....................................................................................... 1 Pointer Byte Bits ......................................................................... 16 General Description ......................................................................... 1 Input Shift Register .................................................................... 16 Functional Block Diagram .............................................................. 1 Default Readback Condition .................................................... 17 Revision History ............................................................................... 2 Multiple-DAC Write Sequence................................................. 17 Specifications..................................................................................... 3 Multiple-DAC Readback Sequence ......................................... 17 AC Characteristics........................................................................ 5 Write Operation.......................................................................... 17 Timing Characteristics ................................................................ 5 Read Operation........................................................................... 17 Absolute Maximum Ratings............................................................ 7 Double-Buffered Interface ........................................................ 18 ESD Caution.................................................................................. 7 Power-Down Modes .................................................................. 18 Pin Configuration and Function Descriptions............................. 8 Applications..................................................................................... 20 Typical Performance Characteristics ............................................. 9 Typical Application Circuit....................................................... 20 Terminology .................................................................................... 13 Bipolar Operation....................................................................... 20 Functional Description .................................................................. 15 Multiple Devices on One Bus ................................................... 20 Digital-to-Analog Section ......................................................... 15 AD5305/AD5315/AD5325 as a Digitally Programmable Window Detector ....................................................................... 21 Resistor String ............................................................................. 15 DAC Reference Inputs ............................................................... 15 Coarse and Fine Adjustment Using the AD5305/AD5315/AD5325 ....................................................... 21 Output Amplifier........................................................................ 15 Power Supply Decoupling ......................................................... 21 Power-On Reset .......................................................................... 15 Outline Dimensions ....................................................................... 23 Serial Interface ............................................................................ 16 Ordering Guide .......................................................................... 23 REVISION HISTORY 5/06—Rev. F to Rev. G Updated Format..................................................................Universal Changes to Ordering Guide .......................................................... 24 10/04—Rev. E to Rev. F Changes to Figure 6........................................................................ 11 Changes to Pointer Byte Bits Section ........................................... 12 Changes to Figure 7........................................................................ 12 8/03—Rev. D to Rev. E Added A Version.................................................................Universal Changes to Features.......................................................................... 1 Changes to Specifications ................................................................ 2 Changes to Absolute Maximum Ratings ....................................... 5 Changes to Ordering Guide ............................................................ 5 Changes to TPC 21......................................................................... 10 Added Octals Section to Table II.................................................. 18 Updated Outline Dimensions....................................................... 19 4/01—Rev. C to Rev. D Edit to Features Section ....................................................................1 Edit to Figure 6 ..................................................................................1 Edits to Right/Left and Double Sections of Pointer Byte Bits Section........................................................... 11 Edit to Input Shift Register Section.............................................. 12 Edit to Multiple-DAC Readback Sequence Section................... 12 Edits to Figure 7.............................................................................. 12 Edits to Write Operation section.................................................. 13 Edits to Figure 8.............................................................................. 13 Edits to Read Operation section................................................... 14 Edits to Figure 9.............................................................................. 14 Edits to Power-Down Modes section .......................................... 15 Edits to Figure 12............................................................................ 16 Rev. G | Page 2 of 24 AD5305/AD5315/AD5325 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. Table 1. 2 Parameter DC PERFORMANCE 3, 4 AD5305 Resolution Relative Accuracy Differential Nonlinearity Min A Version 1 Typ Max Min B Version1 Typ Max Unit 8 ±0.15 ±0.02 ±1 ±0.25 8 ±0.15 ±0.02 ±0.625 ±0.25 Bits LSB LSB AD5315 Resolution Relative Accuracy Differential Nonlinearity 10 ±0.5 ±0.05 ±4 ±0.5 10 ±0.5 ±0.05 ±2.5 ±0.5 Bits LSB LSB AD5325 Resolution Relative Accuracy Differential Nonlinearity 12 ±2 ±0.2 ±16 ±1 12 ±2 ±0.2 ±10 ±1 Bits LSB LSB Offset Error Gain Error Lower Deadband ±0.4 ±0.15 20 ±3 ±1 60 ±0.4 ±0.15 20 ±3 ±1 60 % of FSR % of FSR mV Offset Error Drift 5 −12 −12 Gain Error Drift5 −5 −5 –60 200 –60 200 Power Supply Rejection Ratio5 DC Crosstalk5 DAC REFERENCE INPUTS5 VREF Input Range VREF Input Impedance Reference Feedthrough OUTPUT CHARACTERISTICS5 Minimum Output Voltage 6 Maximum Output Voltage6 DC Output Impedance Short-Circuit Current Power-Up Time 0.25 37 Conditions/Comments Guaranteed monotonic by design over all codes Guaranteed monotonic by design over all codes Guaranteed monotonic by design over all codes Lower deadband exists only if offset error is negative ppm of FSR/°C ppm of FSR/°C dB μV ∆VDD = ±10% RL = 2 kΩ to GND or VDD 45 >10 −90 V kΩ MΩ dB Normal operation Power-down mode Frequency = 10 kHz 0.001 0.001 V VDD − 0.001 0.5 25 16 2.5 VDD − 0.001 0.5 25 16 2.5 V Ω mA mA μs 5 5 μs VDD 45 >10 −90 0.25 37 VDD Rev. G | Page 3 of 24 A measure of the minimum and maximum drive capability of the output amplifier VDD = 5 V VDD = 3 V Coming out of power-down mode VDD = 5 V Coming out of power-down mode VDD = 3 V AD5305/AD5315/AD5325 2 Parameter LOGIC INPUTS (A0)5 Input Current Input Low Voltage, VIL Input High Voltage, VIH Pin Capacitance LOGIC INPUTS (SCL, SDA)5 Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIN Input Hysteresis, VHYST Min A Version 1 Typ Max ±1 0.8 0.6 0.5 2.4 2.1 2.0 Conditions/Comments ±1 0.8 0.6 0.5 μA V V V V V V pF VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 2.5 V VDD + 0.3 0.3 VDD ±1 V SMBus compatible at VDD < 3.6 V V μA V SMBus compatible at VDD < 3.6 V 3 VDD + 0.3 0.3 VDD ±1 0.7 VDD −0.3 0.05 VDD 0.7 VDD −0.3 0.05 VDD 8 LOGIC OUTPUT (SDA)5 Output Low Voltage, VOL VDD = 2.5 V to 3.6 V Unit 2.4 2.1 2.0 3 Input Capacitance, CIN Glitch Rejection Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 7 VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V Min B Version1 Typ Max 8 50 0.4 0.6 ±1 0.4 0.6 ±1 V V μA pF 5.5 V 8 2.5 pF ns 50 8 5.5 2.5 Input filtering suppresses noise spikes of less than 50 ns ISINK = 3 mA ISINK = 6 mA VIH = VDD and VIL = GND 600 500 900 700 600 500 900 700 μA μA 0.2 1 0.2 1 μA 0.08 1 0.08 1 μA 1 VIH = VDD and VIL = GND IDD = 4 μA (maximum) during 0 readback on SDA IDD = 1.5 μA (maximum) during 0 readback on SDA Temperature range (A, B version): −40°C to +105°C; typical at +25°C. See the Terminology section. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981). 5 Guaranteed by design and characterization, not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. 7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents. 2 Rev. G | Page 4 of 24 AD5305/AD5315/AD5325 AC CHARACTERISTICS VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. Table 2. 2, 3 Parameter Output Voltage Settling Time AD5305 AD5315 AD5325 Slew Rate Major-Code Transition Glitch Energy Digital Feedthrough Digital Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion A, B Version 1 Min Typ Max Unit 6 7 8 0.7 12 1 1 3 200 −70 μs μs μs V/μs nV-s nV-s nV-s nV-s kHz dB 8 9 10 Conditions/Comments VREF = VDD = 5 V ¼ scale to ¾ scale change (0×40 to 0×C0) ¼ scale to ¾ scale change (0×100 to 0×300) ¼ scale to ¾ scale change (0×400 to 0×C00) 1 LSB change around major carry VREF = 2 V ± 0.1 V p-p VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz 1 Temperature range (A, B version): −40°C to +105°C; typical at +25°C. Guaranteed by design and characterization, not production tested. 3 See the Terminology section. 2 TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1, 2 fSCL t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 t11 CB 4 Limit at TMIN, TMAX (A, B Version) 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 250 0 300 20 + 0.1 CB 4 400 Unit kHz max μs min μs min μs min μs min ns min μs max μs min μs min μs min μs min ns max ns min ns max ns min ns max ns min pF max Conditions/Comments SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD,STA, start/repeated start condition hold time tSU,DAT, data setup time tHD,DAT, data hold time tHD,DAT, data hold time tSU,STA, setup time for repeated start tSU,STO, stop condition setup time tBUF, bus-free time between a stop and a start condition tR, rise time of SCL and SDA when receiving tR, rise time of SCL and SDA when receiving (CMOS compatible) tF, fall time of SDA when transmitting tF, fall time of SDA when receiving (CMOS compatible) tF, fall time of SCL and SDA when receiving tF, fall time of SCL and SDA when transmitting Capacitive load for each bus line 1 See Figure 2. Guaranteed by design and characterization; not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. 2 Rev. G | Page 5 of 24 AD5305/AD5315/AD5325 SDA t9 t3 t11 t10 t4 SCL t6 t2 t7 t5 REPEATED START CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram Rev. G | Page 6 of 24 t1 t8 STOP CONDITION 00930-002 t4 START CONDITION AD5305/AD5315/AD5325 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter1 VDD to GND SCL, SDA to GND A0 to GND Reference Input Voltage to GND VOUTA to VOUTD to GND Operating Temperature Range Industrial (A, B Version) Storage Temperature Range Junction Temperature (TJ max) MSOP Power Dissipation θJA Thermal Impedance θJC Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating –0.3 V to +7 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −40°C to +105°C −65°C to +150°C 150°C (TJ max − TA)/θJA 206°C/W 44°C/W 220°C 10 sec to 40 sec Transient currents of up to 100 mA do not cause SCR latcth-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. G | Page 7 of 24 AD5305/AD5315/AD5325 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VOUTA 2 VOUTB 3 VOUTC 4 REFIN 5 AD5305/ AD5315/ AD5325 TOP VIEW (Not to Scale) 10 A0 9 SCL 8 SDA 7 GND 6 VOUTD 00930-003 VDD 1 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD VOUTA VOUTB VOUTC REFIN VOUTD GND SDA 9 SCL 10 A0 Description Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Reference Input Pin for All Four DACs. It has an input range from 0.25 V to VDD. Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift register. Clock rates of up to 400 kb/s can be accommodated in the 2-wire interface. Address Input. Sets the least significant bit of the 7-bit slave address. Rev. G | Page 8 of 24 AD5305/AD5315/AD5325 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 0.2 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 0.1 0 –0.1 –0.5 0 50 100 150 200 250 CODE –0.3 00930-006 –1.0 0 150 200 250 Figure 7. AD5305 Typical DNL Plot 3 0.6 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 2 0.4 1 0.2 DNL ERROR (LSB) 0 –1 –2 0 –0.2 –0.4 200 400 600 800 1000 CODE –0.6 00930-007 0 0 200 400 600 800 1000 CODE Figure 5. AD5315 Typical INL Plot 00930-010 INL ERROR (LSB) 100 CODE Figure 4. AD5305 Typical INL Plot –3 50 00930-009 –0.2 Figure 8. AD5315 Typical DNL Plot 12 1.0 TA = 25°C VDD = 5V TA = 25°C VDD = 5V 8 DNL ERROR (LSB) 0 –4 0 –0.5 –12 0 1000 2000 3000 CODE 4000 –1.0 0 1000 2000 3000 CODE Figure 6. AD5325 Typical INL Plot Figure 9. AD5325 Typical DNL Plot Rev. G | Page 9 of 24 4000 00930-011 –8 00930-008 INL ERROR (LSB) 0.5 4 AD5305/AD5315/AD5325 0.50 0.2 VDD = 5V TA = 25°C 0.25 GAIN ERROR 0 MAXINL MAXDNL ERROR (%) ERROR (LSB) TA = 25°C VREF = 2V 0.1 0 MIN DNL –0.25 –0.1 –0.2 –0.3 –0.4 OFFSET ERROR 0 1 2 3 4 5 VREF (V) –0.6 00930-012 –0.50 0 Figure 10. AD5305 INL and DNL Error vs. VREF 1 2 3 VDD (V) 4 5 6 00930-015 –0.5 MIN INL Figure 13. Offset Error and Gain Error vs. VDD 0.5 5 VDD = 5V VREF = 3V 0.4 0.3 5V SOURCE 4 MAX INL 3V SOURCE MAX DNL 0.1 3 VOUT (V) ERROR (LSB) 0.2 0 –0.1 2 MIN DNL –0.2 –0.3 1 MIN INL 3V SINK 5V SINK 0 40 TEMPERATURE (°C) 80 120 0 00930-013 –0.5 –40 0 1 2 3 4 5 6 SINK/SOURCE CURRENT (mA) 00930-016 –0.4 Figure 14. VOUT Source and Sink Current Capability Figure 11. AD5305 INL and DNL Error vs. Temperature 1.0 600 VDD = 5V VREF = 2V OFFSET ERROR 500 TA = 25°C VDD = 5V VREF = 2V 0.5 IDD (µA) 0 300 200 GAIN ERROR –0.5 –1.0 –40 0 40 TEMPERATURE (°C) 80 120 0 ZERO SCALE FULL SCALE CODE Figure 12. AD5305 Offset Error and Gain Error vs. Temperature Figure 15. Supply Current vs. DAC Code Rev. G | Page 10 of 24 00930-017 100 00930-014 ERROR (%) 400 AD5305/AD5315/AD5325 600 TA = 25°C VDD = 5V VREF = 5V –40°C 500 CH1 +25°C 400 VOUTA IDD (µA) +105°C 300 200 SCL CH2 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 Figure 16. Supply Current vs. Supply Voltage CH1 1V, CH2 5V, TIME BASE = 1µs/DIV 00930-021 0 2.5 00930-018 100 Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Change) 0.5 TA = 25°C VDD = 5V VREF = 2V 0.4 CH1 VDD IDD (µA) 0.3 –40°C 0.2 +25°C VOUTA CH2 0.1 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV 00930-019 0 2.5 Figure 17. Power-Down Current vs. Supply Voltage 00930-022 +105°C Figure 20. Power-On Reset to 0 V 750 TA = 25°C TA = 25°C VDD = 5V VREF = 2V DECREASING INCREASING VDD = 5V CH1 VOUTA IDD (µA) 650 550 SCL VDD = 3V 1 2 3 4 5 VLOGIC (V) CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV Figure 18. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage Increasing and Decreasing Figure 21. Exiting Power-Down to Midscale Rev. G | Page 11 of 24 00930-023 0 00930-020 450 CH2 AD5305/AD5315/AD5325 0.02 350 VDD = 5V 400 450 IDD (µA) 500 550 600 0.01 0 –0.01 –0.02 Figure 22. IDD Histogram with VDD = 3 V and VDD = 5 V 0 1 2 3 VREF (V) 4 5 6 00930-027 300 FULL SCALE ERROR (V) VDD = 3V 00930-024 FREQUENCY VDD = 5V TA = 25°C Figure 25. Full-Scale Error vs. VREF 2.50 VOUT (V) 1mV/DIV 2.49 2.47 1µs/DIV 50ns/DIV Figure 23. AD5325 Major-Code Transition Glitch Energy Figure 26. DAC-to-DAC Crosstalk 10 0 –10 (dB) –20 –30 –40 –60 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 00930-026 –50 Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response) Rev. G | Page 12 of 24 00930-028 00930-025 2.48 AD5305/AD5315/AD5325 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus code plots can be seen in Figure 4, Figure 5, and Figure 6. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL vs. code plots can be seen in Figure 7, Figure 8, and Figure 9. Offset Error This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V and VDD is varied ±10%. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in μV. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. Major-Code Transition Glitch Energy Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00, or 100 . . . 00 to 011 . . . 11). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device when the DAC output is not being updated. It is specified in nV-s and is measured with a worst-case change on the digital input pins, for example, from all 0s to all 1s or vice versa. Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV-s. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with the LDAC bit set low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in dB. Rev. G | Page 13 of 24 AD5305/AD5315/AD5325 GAIN ERROR PLUS OFFSET ERROR GAIN ERROR PLUS OFFSET ERROR ACTUAL OUTPUT VOLTAGE IDEAL IDEAL ACTUAL NEGATIVE OFFSET ERROR POSITIVE OFFSET DAC CODE DAC CODE Figure 28. Transfer Function with Positive Offset DEAD BAND CODES AMPLIFIER FOOTROOM (1mV) 00930-004 NEGATIVE OFFSET ERROR Figure 27. Transfer Function with Negative Offset Rev. G | Page 14 of 24 00930-005 OUTPUT VOLTAGE AD5305/AD5315/AD5325 FUNCTIONAL DESCRIPTION The AD5305/AD5315/AD5325 are quad resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. Each contains four output buffer amplifiers and is written to via a 2-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/μs. The four DACs share a single reference input pin. The devices have three programmable power-down modes, in which all DACs can be turned off completely with a high impedance output, or the outputs can be pulled low by on-chip resistors. R R TO OUTPUT AMPLIFIER R R 00930-030 R DIGITAL-TO-ANALOG SECTION The architecture of one DAC channel consists of a resistorstring DAC followed by an output buffer amplifier. The voltage at the REFIN pin provides the reference voltage for the DAC. Figure 29 shows a block diagram of the DAC architecture. Because the input coding to the DAC is straight binary, the ideal output voltage is given by VOUT = VREF × D 2N D = decimal equivalent of the binary code, which is loaded to the DAC register: There is a single reference input pin for the four DACs. The reference input is unbuffered. The user can have a reference voltage as low as 0.25 V and as high as VDD because there is no restriction due to headroom and footroom of any reference amplifier. OUTPUT AMPLIFIER 0 to 255 for AD5305 (8 bits) The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD when the reference is VDD. It is capable of driving a load of 2 kΩ to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in the plot in Figure 14. 0 to 1023 for AD5315 (10 bits) 0 to 4095 for AD5325 (12 bits) N = DAC resolution REFIN The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at eight bits) of 6 μs. RESISTOR STRING POWER-ON RESET VOUTA 00930-029 DAC REGISTER DAC REFERENCE INPUTS It is recommended to use a buffered reference in the external circuit (for example, REF192). The input impedance is typically 45 kΩ. where: INPUT REGISTER Figure 30. Resistor String OUTPUT BUFFER AMPLIFIER Figure 29. DAC Channel Architecture RESISTOR STRING The resistor string section is shown in Figure 30. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. The AD5305/AD5315/AD5325 are provided with a power-on reset function, so that they power up in a defined state. The power-on state is • Normal operation • Output voltage set to 0 V Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. Rev. G | Page 15 of 24 AD5305/AD5315/AD5325 READ/WRITE SEQUENCE 2 The AD5305/AD5315/AD5325 are controlled via an I C compatible serial bus. The DACs are connected to this bus as slave devices (that is, no clock is generated by the AD5305/ AD5315/AD5325 DACs). This interface is SMBus compatible at VDD < 3.6 V. The AD5305/AD5315/AD5325 have a 7-bit slave address. The 6 MSB are 000110 and the LSB is determined by the state of the A0 pin. The facility to make hardwired changes to A0 allows the user to use up to two of these devices on one bus. The 2-wire serial bus protocol operates as follows: The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data is read from or written to the slave device). The slave whose address corresponds to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. 2. 3. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a No Acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition. MSB LSB X 0 X 0 DACD DACC DACB DACA Figure 31. Pointer Byte POINTER BYTE BITS Table 6 explains the individual bits that make up the pointer byte. Table 6. Individual Bits of the Pointer Byte Bit X 0 DACD DACC DACB DACA Description Don’t care bits. Reserved bits. Must be set to 0. [1] The following data bytes are for DAC D. [1] The following data bytes are for DAC C. [1] The following data bytes are for DAC B. [1] The following data bytes are for DAC A. INPUT SHIFT REGISTER The input shift register is 16 bits wide. Data is loaded into the device as two data bytes on the serial data line, SDA, under the control of the serial clock input, SCL. The timing diagram for this operation is shown in Figure 2. The two data bytes consist of four control bits followed by 8, 10, or 12 bits of DAC data, depending on the device type. The first two bits loaded are the PD1 and PD0 bits that control the mode of operation of the device. See the Power-Down Modes section for a complete description. Bit 13 is CLR, Bit 12 is LDAC, and the remaining bits are left justified DAC data bits, starting with the MSB. See Figure 32. DATA BYTES (WRITE AND READBACK) MOST SIGNIFICANT DATA BYTE PD1 PD0 CLR PD0 CLR PD0 CLR MSB PD1 LDAC D7 D6 D5 D8 D7 D10 D9 10-BIT AD5315 MSB PD1 LEAST SIGNIFICANT DATA BYTE 8-BIT AD5305 MSB LDAC D9 12-BIT AD5325 LDAC D11 LSB MSB D4 D3 LSB MSB D6 D5 LSB MSB D8 D7 8-BIT AD5305 D2 D1 D4 D3 D6 D5 0 LSB 0 0 D0 0 D2 D1 10-BIT AD5315 D2 D1 D4 D3 0 LSB 0 LSB 12-BIT AD5325 Figure 32. Data Formats for Write and Readback Rev. G | Page 16 of 24 D0 D0 00930-032 1. In the case of the AD5305/AD5315/AD5325, all write access sequences and most read sequences begin with the device address (with R/W = 0) followed by the pointer byte. This pointer byte specifies the data format and determines which DAC is being accessed in the subsequent read/write operation (see Figure 31). In a write operation, the data follows immediately. In a read operation, the address is resent with R/W = 1 and then the data is read back. However, it is also possible to perform a read operation by sending only the address with R/W = 1. The previously loaded pointer settings are then used for the readback operation. See Figure 32 for a graphical explanation of the interface. 00930-031 SERIAL INTERFACE AD5305/AD5315/AD5325 Table 7. CLR and LDAC Bit Descriptions WRITE OPERATION Bit CLR When writing to the AD5305/AD5315/AD5325 DACs, the user must begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte is followed by the pointer byte, which is also acknowledged by the DAC. Two bytes of data are then written to the DAC, as shown in Figure 33. A stop condition follows. LDAC Description [0] All DAC registers and input registers are filled with 0s on completion of the write sequence. [1] Normal operation. [0] All four DAC registers and, therefore, all DAC outputs, are simultaneously updated on completion of the write sequence. [1] Only addressed input register is updated. There is no change in the contents of the DAC registers. READ OPERATION When reading data back from the AD5305/AD5315/AD5325 DACs, the user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte is usually followed by the pointer byte, which is also acknowledged by the DAC. Following this, there is a repeated start condition by the master and the address is resent with R/W = 1. This is acknowledged by the DAC indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC, as shown in Figure 34. A stop condition follows. DEFAULT READBACK CONDITION All pointer byte bits power up to 0. Therefore, if the user initiates a readback without writing to the pointer byte first, no single DAC channel has been specified. In this case, the default readback bits are all 0, except for the CLR bit, which is a 1. MULTIPLE-DAC WRITE SEQUENCE Because there are individual bits in the pointer byte for each DAC, it is possible to simultaneously write the same data and control bits to 2, 3, or 4 DACs by setting the relevant bits to 1. However, if the master sends an ACK and continues clocking SCL (no STOP is sent), the DAC retransmits the same two bytes of data on SDA. This allows continuous readback of data from the selected DAC register. MULTIPLE-DAC READBACK SEQUENCE If the user attempts to read back data from more than one DAC at a time, the part reads back the default, power-on reset conditions, that is, all 0s except for CLR, which is 1. Alternatively, the user can send a start followed by the address with R/W = 1. In this case, the previously loaded pointer settings are used and readback of data can commence immediately. SCL 0 SDA 0 START COND BY MASTER 0 1 1 0 A0 R/W X X ACK MSB BY AD53x5 ADDRESS BYTE LSB POINTER BYTE ACK BY AD53x5 SCL MSB MOST SIGNIFICANT DATA BYTE LSB MSB ACK BY AD53x5 LEAST SIGNIFICANT DATA BYTE Figure 33. Write Sequence Rev. G | Page 17 of 24 LSB ACK BY AD53x5 STOP COND BY MASTER 00930-033 SDA AD5305/AD5315/AD5325 SCL 0 SDA 0 0 1 START COND BY MASTER 1 0 A0 R/W X X ACK MSB BY AD53x5 ADDRESS BYTE LSB POINTER BYTE ACK BY AD53x5 SCL SDA 0 REPEATED START COND BY MASTER 0 0 1 1 0 A0 MSB R/W LSB ACK BY AD53x5 ADDRESS BYTE DATA BYTE ACK BY MASTER SCL MSB LSB LEAST SIGNIFICANT DATA BYTE NO ACK BY MASTER STOP COND BY MASTER NOTE: DATA BYTES ARE THE SAME AS THOSE IN THE WRITE SEQUENCE EXCEPT THAT DON’T CARES ARE READ BACK AS 0s. 00930-034 SDA Figure 34. Readback Sequence DOUBLE-BUFFERED INTERFACE The AD5305/AD5315/AD5325 DACs have double-buffered interfaces consisting of two banks of registers—input registers and DAC registers. The input register is directly connected to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC register contains the digital code used by the resistor string. Access to the DAC register is controlled by the LDAC bit. When the LDAC bit is set high, the DAC register is latched and, therefore, the input register can change state without affecting the contents of the DAC register. However, when the LDAC bit is set low, the DAC register becomes transparent and the contents of the input register are transferred to it. This is useful if the user requires simultaneous updating of all DAC outputs. The user can write to three of the input registers individually and then, by setting the LDAC bit low when writing to the remaining DAC input register, all outputs update simultaneously. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5305/AD5315/ AD5325, the part updates the DAC register only if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. POWER-DOWN MODES The AD5305/AD5315/AD5325 have very low power consumption, dissipating typically 1.5 mW with a 3 V supply and 3 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into one of three power-down modes, which are selected by Bit 15 and Bit 14 (PD1 and PD0) of the data byte. Table 8 shows how the state of the bits corresponds to the mode of operation of the DAC. Table 8. PD1/PD0 Operating Modes PD1 0 0 1 1 Rev. G | Page 18 of 24 PD0 0 1 0 1 Operating Mode Normal Operation Power-Down (1 kΩ load to GND) Power-Down (100 kΩ load to GND) Power-Down (three-state output) AD5305/AD5315/AD5325 RESISTOR STRING DAC VOUT AMPLIFIER POWER-DOWN CIRCUITRY RESISTOR NETWORK 00930-035 When both bits are set to 0, the DAC works normally with its normal power consumption of 600 μA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (80 nA at 3 V). Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has an advantageous because the output impedance of the part is known while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. There are three different options. The output is connected internally to GND through a 1 kΩ resistor, a 100 kΩ resistor, or it is left open-circuited (three-state). Resistor tolerance = ±20%. The output stage is illustrated in Figure 35. Figure 35. Output Stage During Power-Down The bias generator, the output amplifiers, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the DAC registers are unchanged when in power-down. The time to exit power-down is typically 2.5 μs for VDD = 5 V and 5 μs when VDD = 3 V. This is the time from the rising edge of the eighth SCL pulse to when the output voltage deviates from its powerdown voltage. See Figure 21 for a plot. Rev. G | Page 19 of 24 AD5305/AD5315/AD5325 APPLICATIONS TYPICAL APPLICATION CIRCUIT BIPOLAR OPERATION The AD5305/AD5315/AD5325 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0 V to VDD. More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780 and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference is the AD589, a 1.23 V band gap reference. Figure 36 shows a typical setup for the AD5305/ AD5315/AD5325 when using an external reference. Note that A0 can be high or low. The AD5305/AD5315/AD5325 have been designed for single supply operation, but a bipolar output range is also possible using the circuit in Figure 37. This circuit gives an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. R2 = 10kΩ 6V TO 12V 0.1µF VOUT REFIN 1µF AD5305/ AD5315/ AD5325 REFIN GND SCL SDA VOUTD SDA 00930-037 2-WIRE SERIAL INTERFACE VOUTC SCL Figure 37. Bipolar Operation with the AD5305 GND SERIAL INTERFACE 00930-036 A0 VOUTD VOUTB 1µF AD780/REF192 WITH VDD = 5V OR AD589 WITH VDD = 2.5V –5V VOUTB VOUTC A0 VOUTA VOUT ±5V The output voltage for any input code can be calculated as follows: ⎡ (REFIN × (D / 2 N ))× ( R1 + R2 ) ⎤ − REFIN × (R2 / R1)⎥ VOUT = ⎢ R 1 ⎣⎢ ⎦⎥ Figure 36. AD5305/AD5315/AD5325 Using External Reference If an output range of 0 V to VDD is required, the simplest solution is to connect the reference input to VDD. As this supply may not be very accurate and may be noisy, the AD5305/AD5315/AD5325 can be powered from the reference voltage; for example, using a 5 V reference such as the REF195. The REF195 outputs a steady supply voltage for the AD5305/ AD5315/AD5325. The typical current required from the REF195 is 600 μA supply current and approximately 112 μA into the reference input. This is with no load on the DAC outputs. When the DAC outputs are loaded, the REF195 also needs to supply the current to the loads. The total current required (with a 10 kΩ load on each output) is 712 μA + 4(5 V/10 kΩ) = 2.70 mA The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 5.4 ppm (27 μV) for the 2.7 mA current drawn from it. This corresponds to a 0.0014 LSB error at eight bits and 0.022 LSB error at 12 bits. where: D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. REFIN is the reference voltage input. with REFIN = 5 V, R1 = R2 = 10 kΩ, VOUT (10 × D/2N) − 5 V MULTIPLE DEVICES ON ONE BUS Figure 38 shows two AD5305 devices on the same serial bus. Each has a different slave address because the state of the A0 pin is different. This allows each of eight DACs to be written to or read from independently. VDD PULL-UP RESISTORS A0 AD5305 SDA SCL MICROCONTROLLER SDA SCL A0 AD5305 Figure 38. Multiple AD5305 Devices on One Bus Rev. G | Page 20 of 24 00930-038 VIN AD820/ OP295 VOUTA VDD AD5305 GND 10µF +5V AD1585 VIN EXT REF R1 = 10kΩ 10µF VDD = 2.5V TO 5.5V 0.1µF +5V AD5305/AD5315/AD5325 AD5305/AD5315/AD5325 AS A DIGITALLY PROGRAMMABLE WINDOW DETECTOR POWER SUPPLY DECOUPLING A digitally programmable upper/lower limit detector using two of the DACs in the AD5305/AD5315/AD5325 is shown in Figure 39. The upper and lower limits for the test are loaded to DAC A and DAC B, which, in turn, set the limits on the CMP04. If the signal at the VIN input is not within the programmed window, an LED indicates the fail condition. Similarly, DAC C and DAC D can be used for window detection on a second VIN signal. 5V 0.1µF VREF 10µF VIN 1kΩ 1kΩ FAIL PASS VDD REFIN VOUTA DIN 1/2 AD5305/ AD5315/ 1 SDA AD5325 SCL SCL 1/2 CMP04 PASS/FAIL VOUTB 1/6 74HC05 00930-039 GND 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 39. Window Detection COARSE AND FINE ADJUSTMENT USING THE AD5305/AD5315/AD5325 Two of the DACs in the AD5305/AD5315/AD5325 can be paired together to form a coarse and fine adjustment function, as shown in Figure 40. DAC A is used to provide the coarse adjustment while DAC B provides the fine adjustment. Varying the ratio of R1 and R2 changes the relative effect of the coarse and fine adjustments. With the resistor values and external reference shown in Figure 40, the output amplifier has unity gain for the DAC A output. As a result, the output range is 0 V to 2.5 V − 1 LSB. For DAC B, the amplifier has a gain of 7.6 × 10−3, giving DAC B a range equal to 19 mV. Similarly, DAC C and DAC D can be paired together for coarse and fine adjustment. In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5305/AD5315/AD5325 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5305/AD5315/AD5325 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The AD5305/ AD5315/AD5325 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5305/AD5315/AD5325 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the SDA and SCL lines helps reduce crosstalk between them (not required on a multilayer board as there is a separate ground plane, but separating the lines does help). Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. The circuit is shown with a 2.5 V reference, but reference voltages up to VDD can be used. The op amps indicated allows a rail-to-rail output swing. VDD = 5V VIN EXT V OUT REF GND 10µF 5V REFIN 1µF AD780/REF192 WITH VDD = 5V VDD VOUTA 1/2 AD5305/ AD5315/ AD53251 VOUTB GND 1ADDITIONAL R4 390Ω VOUT R1 390Ω AD820/ OP295 R2 51.2kΩ PINS OMITTED FOR CLARITY. 00930-040 0.1µF R3 51.2kΩ Figure 40. Coarse/Fine Adjustment Rev. G | Page 21 of 24 AD5305/AD5315/AD5325 Table 9. Overview of All AD53xx Serial Devices Part No. SINGLES AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 DUALS AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 QUADS AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 OCTALS AD5308 AD5318 AD5328 Resolution No. of DACs DNL Interface Settling Time (μs) Package Pins 8 10 12 8 10 12 1 1 1 1 1 1 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 SPI® SPI SPI 2-Wire 2-Wire 2-Wire 4 6 8 6 7 8 SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 8 10 12 8 10 12 2 2 2 2 2 2 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 SPI SPI SPI SPI SPI SPI 6 7 8 6 7 8 MSOP MSOP MSOP TSSOP TSSOP TSSOP 8 8 8 16 16 16 8 10 12 8 10 12 8 10 12 8 10 12 4 4 4 4 4 4 4 4 4 4 4 4 ± 0.25 ± 0.5 ±1.0 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 SPI SPI SPI 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire SPI SPI SPI 6 7 8 6 7 8 6 7 8 6 7 8 MSOP MSOP MSOP MSOP MSOP MSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP 10 10 10 10 10 10 16 16 16 16 16 16 8 10 12 8 8 8 ±0.25 ±0.5 ±1.0 SPI SPI SPI 6 7 8 TSSOP TSSOP TSSOP 16 16 16 Table 10. Overview of AD53xx Parallel Devices Part No. SINGLES AD5330 AD5331 Resolution DNL VREF Pins Settling Time (μs) Additional Pin Functions BUF GAIN HBEN CLR Package Pins 8 ±0.25 1 6 ✓ 10 ±0.5 1 7 AD5340 12 ±1.0 1 8 AD5341 12 ±1.0 1 8 DUALS AD5332 8 ±0.25 2 6 AD5333 10 ±0.5 2 7 ✓ AD5342 12 ±1.0 2 8 ✓ AD5343 12 ±1.0 1 8 QUADS AD5334 8 ±0.25 2 6 AD5335 10 ±0.5 2 7 AD5336 10 ±0.5 4 7 AD5344 12 ±1.0 4 8 ✓ ✓ TSSOP 20 ✓ ✓ TSSOP 20 ✓ ✓ ✓ TSSOP 24 ✓ ✓ ✓ TSSOP 20 ✓ ✓ TSSOP 20 ✓ ✓ TSSOP 24 ✓ ✓ TSSOP 28 ✓ TSSOP 20 ✓ TSSOP 24 ✓ TSSOP 24 ✓ TSSOP 28 TSSOP 28 ✓ ✓ ✓ ✓ Rev. G | Page 22 of 24 AD5305/AD5315/AD5325 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 6 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 1.10 MAX 0.33 0.17 SEATING PLANE 0.23 0.08 8° 0° 0.80 0.60 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 41. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model AD5305ARM AD5305ARM-REEL7 AD5305ARMZ 1 AD5305ARMZ-REEL71 AD5305BRM AD5305BRM-REEL AD5305BRM-REEL7 AD5305BRMZ1 AD5305BRMZ-REEL71 AD5315ARM AD5315ARM-REEL7 AD5315ARMZ1 AD5315BRM AD5315BRM-REEL AD5315BRM-REEL7 AD5315BRMZ1 AD5315BRMZ-REEL1 AD5315BRMZ-REEL71 AD5325ARM AD5325ARM-REEL7 AD5325ARMZ1 AD5325BRM AD5325BRM-REEL AD5325BRM-REEL7 AD5325BRMZ1 AD5325BRMZ-REEL1 AD5325BRMZ-REEL71 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Z = Pb-free part; # denotes lead-free product may be top or bottom marked. Rev. G | Page 23 of 24 Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding DEA DEA D99 D99 DEB DEB DEB DEB # DEB # DFA DFA D8E DFB DFB DFB D6N D6N D6N DGA DGA D8G DGB DGB DGB D8H D8H D8H AD5305/AD5315/AD5325 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00930-0-5/06(G) Rev. G | Page 24 of 24