ON MTB9N25E High energy power fet Datasheet

MTB9N25E
Designer’s™ Data Sheet
TMOS E−FET.™
High Energy Power FET
D2PAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
The D2PAK package has the capability of housing a larger die than
any existing surface mount package which allows it to be used in
applications that require the use of surface mount components with
higher power and lower RDS(on) capabilities. This advanced TMOS
E−FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain−to−source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Short Heatsink Tab Manufactured — Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 1
1
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TMOS POWER FET
9.0 AMPERES, 250 VOLTS
RDS(on) = 0.45 W
D2PAK
CASE 418B−02
Style 2
D
®
G
S
Publication Order Number:
MTB9N25E/D
MTB9N25E
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
250
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
VDGR
250
Vdc
Gate−to−Source Voltage — Continuous
— Non−Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
ID
ID
9.0
5.7
32
Adc
PD
80
0.64
2.5
Watts
W/°C
Watts
TJ, Tstg
− 55 to 150
Rating
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 μs)
IDM
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Apk
°C
Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 3.0 mH, RG = 25 Ω)
EAS
Thermal Resistance
RθJC
RθJA
RθJA
1.56
62.5
50
°C/W
TL
260
°C
— Junction to Case
— Junction to Ambient
— Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
mJ
122
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
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MTB9N25E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
250
—
—
328
—
—
—
—
—
—
10
100
—
—
100
nAdc
2.0
—
3.0
7.0
4.0
—
Vdc
mV/°C
—
0.37
0.45
Ohm
—
—
3.5
—
5.4
4.7
gFS
3.0
5.2
—
mhos
Ciss
—
783
1100
pF
Coss
—
144
200
Crss
—
32
65
td(on)
—
10
20
tr
—
36
70
td(off)
—
27
55
tf
—
26
50
QT
—
26
40
Q1
—
4.8
—
Q2
—
12.7
—
Q3
—
9.2
—
—
—
0.9
0.81
1.5
—
trr
—
191
—
ta
—
126
—
tb
—
65
—
QRR
—
1.387
—
—
4.5
—
—
7.5
—
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 μAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
μAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 μAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 4.5 Adc)
RDS(on)
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID = 9.0 Adc)
(VGS = 10 Vdc, ID = 4.5 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 4.5 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 125 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Fall Time
Gate Charge
(See Figure 8)
(VDS = 200 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (1)
Reverse Recovery Time
(See Figure 14)
(IS = 9.0 Adc, VGS = 0 Vdc )
(IS = 9.0 Adc, VGS = 0 Vdc , TJ = 125°C)
(IS = 9.0 Adc, VGS = 0 Vdc,
dlS/dt = 100 A/μs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
μC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
(1) Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
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nH
nH
MTB9N25E
TYPICAL ELECTRICAL CHARACTERISTICS
TJ = 25°C
18
VGS = 10 V
9V
15
VDS ≥ 10 V
8V
7V
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
18
12
9
6V
6
3
0
25°C
12
100°C
9
6
3
5V
0
2
4
6
8
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
12
2
1.2
VGS = 10 V
1.0
0.8
TJ = 100°C
0.6
25°C
0.2
0
− 55°C
0
3
6
9
12
ID, DRAIN CURRENT (AMPS)
15
18
0.6
TJ = 25°C
0.5
VGS = 10 V
0.4
15 V
0.3
0
3
6
9
12
ID, DRAIN CURRENT (AMPS)
15
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
2.5
VGS = 0 V
VGS = 10 V
ID = 4.5 A
2.0
TJ = 125°C
100
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
Figure 3. On−Resistance versus Drain Current
and Temperature
1.5
1.0
0.5
0
−50
3
4
5
6
7
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 1. On−Region Characteristics
0.4
TJ = −55°C
15
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
100°C
10
25°C
1
0.1
150
Figure 5. On−Resistance Variation with
Temperature
0
50
100
150
200
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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MTB9N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to
the on−state when calculating td(off).
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate
of average input current (I G(AV) ) can be made from a
rudimentary analysis of the drive circuit so that
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
inductive; the data in the figure is taken with a resistive load,
which approximates an optimally snubbed inductive load.
Power MOSFETs may be safely operated into an inductive
load; however, snubbing reduces switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
2000
VDS = 0 V
TJ = 25°C
Ciss
1600
C, CAPACITANCE (pF)
VGS = 0 V
1200
Ciss
Crss
800
Coss
400
0
Crss
10
5
0
VGS
5
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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16
VGS
8
Q1
120
Q2
ID = 9 A
TJ = 25°C
4
60
Q3
VDS
0
6
VDD = 250 V
ID = 9 A
VGS = 10 V
TJ = 25°C
180
QT
12
18
QT, TOTAL CHARGE (nC)
0
30
24
t, TIME (ns)
12
0
1000
240
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MTB9N25E
100
tr
td(off)
10
1
tf
td(on)
1
10
1
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
I S , SOURCE CURRENT (AMPS)
9.0
7.5
VGS = 0 V
TJ = 25°C
6.0
4.5
3.0
1.5
0
0.5
0.55
0.65
0.75
0.85
0.6
0.7
0.8
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0.9
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with
an increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I DM ) nor rated voltage (V DSS ) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
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MTB9N25E
shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
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MTB9N25E
SAFE OPERATING AREA
125
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
10μs
100μs
1
1ms
10ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
ID = 9 A
100
75
50
25
0
1000
1.0
100
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
1
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
0.01
t1
SINGLE PULSE
0.01
0.00001
t2
DUTY CYCLE, D = t1/t2
0.0001
0.001
0.01
0.1
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
1.0
10
t, TIME (s)
Figure 13. Thermal Response
3
PD, POWER DISSIPATION (WATTS)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
RθJA = 50°C/W
Board material = 0.065 mil FR−4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils
2.5
2.0
1.5
1
0.5
0
IS
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
Figure 15. D2PAK Power Derating Curve
Figure 14. Diode Reverse Recovery Waveform
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MTB9N25E
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.33
8.38
0.08
2.032
0.42
10.66
0.24
6.096
0.04
1.016
0.12
3.05
0.63
17.02
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which can
defeat the purpose of using surface mount technology. For
example, a graph of RθJA versus drain pad area is shown in
Figure 16.
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RθJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet, PD can be calculated as follows:
R
JA , Thermal Resistance, Junction
to Ambient (C/W)
PD =
70
TJ(max) − TA
RθJA
Board Material = 0.0625″
G−10/FR−4, 2 oz Copper
60
TA = 25°C
2.5 Watts
° 50
θ
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a D2PAK
device, PD is calculated as follows.
5 Watts
30
20
PD = 150°C − 25°C = 2.5 Watts
50°C/W
3.5 Watts
40
0
2
4
6
8
10
A, Area (square inches)
12
14
16
Figure 16. Thermal Resistance versus Drain Pad
Area for the D2PAK Package (Typical)
The 50°C/W for the D2PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.5 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of
the drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad™. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
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MTB9N25E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,
SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 17 shows a
typical stencil for the DPAK and D2PAK packages. The
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇÇ
ÇÇÇÇÇÇ ÇÇ
ÇÇÇÇÇÇ ÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
SOLDER PASTE
OPENINGS
STENCIL
Figure 17. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* Due to shadowing and the inability to set the wave height
to incorporate other surface mount components, the D2PAK
is not recommended for wave soldering.
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MTB9N25E
TYPICAL SOLDER HEATING PROFILE
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density board.
The Vitronics SMD310 convection/infrared reflow soldering
system was used to generate this profile. The type of solder
used was 62/36/2 Tin Lead Silver with a melting point
between 177 −189°C. When this type of furnace is used for
solder reflow work, the circuit boards and solder joints tend
to heat first. The components on the board are then heated
by conduction. The circuit board, because it has a large
surface area, absorbs the thermal energy more efficiently,
then distributes this energy to the components. Because of
this effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a
figure for belt speed. Taken together, these control settings
make up a heating “profile” for that particular circuit board.
On machines controlled by a computer, the computer
remembers these profiles from one operating session to the
next. Figure 18 shows a typical heating profile for use when
soldering a surface mount device to a printed circuit board.
This profile will vary among soldering systems but it is a good
starting point. Factors that can affect the profile include the
type of soldering system in use, density and types of
components on the board, type of solder used, and the type
of board or substrate material being used. This profile shows
temperature versus time. The line on the graph shows the
STEP 1
PREHEAT
ZONE 1
RAMP"
200°C
150°C
STEP 2
STEP 3
VENT
HEATING
SOAK" ZONES 2 & 5
RAMP"
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 5
STEP 4
HEATING
HEATING
ZONES 3 & 6 ZONES 4 & 7
SPIKE"
SOAK"
170°C
160°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
Figure 18.
TMAX
Typical Solder Heating Profile
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STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER JOINT
150°C
100°C
50°C
STEP 6
VENT
MTB9N25E
PACKAGE DIMENSIONS
CASE 418B−02
ISSUE B
C
E
V
B
4
1
2
3
A
S
−T−
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
K
J
G
D 3 PL
0.13 (0.005)
H
M
T
DIM
A
B
C
D
E
G
H
J
K
S
V
INCHES
MIN
MAX
0.340
0.380
0.380
0.405
0.160
0.190
0.020
0.035
0.045
0.055
0.100 BSC
0.080
0.110
0.018
0.025
0.090
0.110
0.575
0.625
0.045
0.055
STYLE 2:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
8.64
9.65
9.65
10.29
4.06
4.83
0.51
0.89
1.14
1.40
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
14.60
15.88
1.14
1.40
GATE
DRAIN
SOURCE
DRAIN
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