Maxim MAX7367EUP+ 4-channel i2c switches/multiplexer Datasheet

19-0644; Rev 2; 2/09
4-Channel I2C Switches/Multiplexer
The MAX7367/MAX7368/MAX7369 bidirectional, fourchannel I2C switches/multiplexer expand the main I2C
bus up to four extended buses. The MAX7369 1:4
multiplexer connects the main I2C bus to one channel
at a time. The MAX7367/MAX7368 four-channel
switches connect the main I 2C bus to one or more
channels at a time.
These devices isolate bus loading by extending the I2C
bus onto different channels. The MAX7367/MAX7368/
MAX7369 allow more devices to be interconnected to a
master controller and multiple devices with the same
I2C address to communicate to a master. The channels
are selected through the main I2C bus by writing to the
internal control register of the device.
Any device connected to an I2C bus can transmit and
receive signals. The MAX7367/MAX7368/MAX7369 are
transparent to signals sent and received at each channel, allowing multiple masters. These devices are compatible with the I 2 C protocol of clock stretch,
synchronization, and arbitration in case multiple masters address the bus at the same time.
All devices are set to the default state during initial
power-up. The MAX7367/MAX7368 have a RESET input
allowing external circuitry to set the MAX7367/MAX7368
to its default state anytime after the device has powered up. The MAX7367/MAX7369 have interrupt inputs,
allowing devices on the extended bus to send an interrupt signal to the master on the main bus.
The MAX7367/MAX7369 are available in 20-pin TSSOP
packages, and the MAX7368 is available in a 16-pin
TSSOP package. All devices operate over the -40°C to
+85°C extended temperature range.
Applications
Servers
RAID
Cellular Phones
Base Stations
PCs
Multimedia Electronics
SAN/NAS
Features
o Four-Channel, Bidirectional Bus Expansion
o Voltage-Level Translation
o Low 6µA (typ) Supply Current, 0.1µA (typ)
Standby Current
o Low 16Ω (typ) On-Resistance
o Channel Selection Through I2C
o I2C-Compatible Normal or Fast Mode
o Device Address Selection
Up to Four Addresses (MAX7367)
Up to Eight Addresses (MAX7368/MAX7369)
o Bus-Loading Isolation
o Support Clock Stretch, Synchronization, and
Arbitration
o Hot Insertion
o 2.3V to 5.5V Supply Voltage Range
o 5V-Tolerant Inputs
o Interrupt from Extended Buses
(MAX7367/MAX7369)
o Hardware Reset (MAX7367/MAX7368)
Ordering Information
TEMP RANGE
PINPACKAGE
MAX7367EUP+
-40°C to +85°C
20 TSSOP
MAX7368EUE+
-40°C to +85°C
16 TSSOP
PART
MAX7369EUP+
-40°C to +85°C
20 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configurations
TOP VIEW
+
A0 1
20 VDD
A1 2
19 SDA
RESET 3
INT0 4
18 SCL
MAX7367
17 INT
SD0 5
16 SC3
SC0 6
15 SD3
INT1 7
14 INT3
SD1 8
13 SC2
SC1 9
12 SD2
GND 10
11 INT2
TSSOP
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX7367/MAX7368/MAX7369
General Description
MAX7367/MAX7368/MAX7369
4-Channel I2C Switches/Multiplexer
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +6.0V
All Other Pins to GND............................................-0.3V to +6.0V
Input Currents
VDD ...............................................................................100mA
GND ..............................................................................100mA
All Input Pins.................................................................±20mA
Output Current ....................................................................25mA
Continuous Power Dissipation (TA = +70°C)
20-Pin TSSOP (derate 11.0mW/°C
above TA = +70°C) .................................................. 879.1mW
16-Pin TSSOP (derate 9.4mW/°C
above TA = +70°C) .................................................. 754.7mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (3.3V SUPPLY)
(VDD = 2.3V to 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.6
V
0.1
1
µA
6
30
µA
1.4
2.1
V
POWER SUPPLY
Supply Voltage
VDD
2.3
Standby Current
ISTB
No load, all inputs = VDD or GND, VDD = 3.6V,
all channels disabled
Supply Current
IDD
No load, all inputs = VDD or GND,
fSCL = 100kHz, VDD = 3.6V,
all channels disabled
Power-On-Reset (POR)
Voltage
VPOR
Power-On-Reset Hysteresis
VHYST
VDD rising
0.4
V
INPUT SCL, INPUT/OUTPUT SDA
Low-Level Input Voltage
VIL
High-Level Input Voltage
VIH
Low-Level Output Current
IOL
Input Leakage Current
IL
Input Capacitance
CI
(Note 2)
-0.2
+0.3 x
VDD
V
0.7 x
VDD
5.5
V
VOL = 0.4V
3
30
VOL = 0.6V
6
50
-1
All inputs = GND
mA
+1
15
µA
pF
SELECT INPUTS A2, A1, A0, INT0–INT3, RESET
-0.2
+0.3 x
VDD
V
VIH
0.7 x
VDD
5.5
V
Input Leakage Current
IL
-1
+1
µA
Input Capacitance
CI
Low-Level Input Voltage
VIL
High-Level Input Voltage
2
(Note 2)
All inputs = GND
5
_______________________________________________________________________________________
pF
4-Channel I2C Switches/Multiplexer
MAX7367/MAX7368/MAX7369
ELECRTICAL CHARACTERISTICS (3.3V SUPPLY) (continued)
(VDD = 2.3V to 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
VDD = 3V to 3.6V, IO = 15mA, VO = 0.4V
5
16
30
VDD = 2.3V to 2.7V, IO = 10mA, VO = 0.4V
7
23
55
VI(SW) = VDD = 3.0V to 3.6V, IO = -100µA
1.6
1.9
2.8
VI(SW) = VDD = 2.3V to 2.7V, IO = -100µA
1.1
UNITS
PASS GATE
Switch On-Resistance
RON
Switch Output Voltage
VPASS
VI(SW) = VDD = 2.5V, IO = -100µA
Leakage Current
IL
Input/Output Capacitance
All inputs = GND
Low-Level Output Current
IOL
VOL = 0.4V
High-Level Output Current
IOH
2.0
V
+1
µA
1.5
-1
CIO
Ω
6
pF
INT OUTPUT
3
mA
1
µA
ELECRTICAL CHARACTERISTICS (5V SUPPLY)
(VDD = 4.5V to 5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
POWER SUPPLY
Supply Voltage
VDD
4.5
Standby Current
ISTB
No load, all inputs = VDD or GND, VDD = 5.5V,
all channels disabled
Supply Current
IDD
No load, all inputs = VDD or GND, fSCL =
100kHz, VDD = 5.5V, all channels disabled
12
50
µA
VDD rising
1.4
2.1
V
Power-On-Reset Voltage
VPOR
POR Hysteresis
VHYST
0.3
1
µA
0.4
V
INPUT SCL, INPUT/OUTPUT SDA
Low-Level Input Voltage
VIL
High-Level Input Voltage
VIH
Low-Level Output Current
IOL
Input Leakage Current
IL
Input Capacitance
CI
(Note 2)
-0.2
+0.3 x
VDD
V
0.7 x
VDD
5.5
V
VOL = 0.4V
3
30
VOL = 0.6V
6
50
-1
All inputs = GND
mA
+1
15
µA
pF
SELECT INPUTS A2, A1, A0, INT0–INT3, RESET
Low-Level Input Voltage
VIL
High-Level Input Voltage
VIH
(Note 2)
-0.2
+0.3 x
VDD
V
0.7 x
VDD
5.5
V
_______________________________________________________________________________________
3
MAX7367/MAX7368/MAX7369
4-Channel I2C Switches/Multiplexer
ELECRTICAL CHARACTERISTICS (5V SUPPLY) (continued)
(VDD = 4.5V to 5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Input Leakage Current
IL
Input Capacitance
CI
CONDITIONS
MIN
TYP
-1
All inputs = GND
MAX
UNITS
+1
µA
5
pF
PASS GATE
Switch On-Resistance
RON
Switch Output Voltage
VPASS
Leakage Current
Input/Output Capacitance
VDD = 4.5V to 5.5V, IO = 15 mA, VO = 0.4V
VI(SW) = VDD, IO = -100µA
IL
12
24
3.6
4.5
V
+1
µA
-1
CIO
All inputs = GND
Low-Level Output Current
IOL
VOL = 0.4V
High-Level Output Current
IOH
Ω
4
2.6
6
pF
INT OUTPUT
3
mA
1
µA
MAX
UNITS
0.3
ns
400
kHz
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Propagation Delay from SDA To
SD_ or SCL to SC_
tpd
SCL Clock Frequency
fSCL
Bus Free Time Between a STOP
and START Condition
tBUF
Hold Time (Repeated) START
Condition (after this period, the
first clock pulse is generated)
tHD;STA
Low Period of the SCL Clock
tLOW
High Period of the SCL Clock
tHIGH
Setup Time for a Repeated START
Condition
tSU;STA
Setup Time for STOP Condition
tSU;STO
Data Hold Time (Note 4)
tHD;DAT
Data Setup Time
tSU;DAT
Rise Time of Both SDA and SCL
Signals
4
CONDITIONS
MIN
TYP
(Note 3)
0
fSCL = 100kHz
4.7
fSCL = 400kHz
1.3
fSCL = 100kHz
4.0
fSCL = 400kHz
0.6
fSCL = 100kHz
4.7
fSCL = 400kHz
1.3
fSCL = 100kHz
4.0
fSCL = 400kHz
0.6
fSCL = 100kHz
4.7
fSCL = 400kHz
0.6
fSCL = 100kHz
4.0
fSCL = 400kHz
0.6
fSCL = 100kHz
0
3.45
fSCL = 400kHz
0
0.9
fSCL = 100kHz
250
fSCL = 400kHz
100
µs
fSCL = 100kHz
tr
µs
fSCL = 400kHz (Note 5)
µs
µs
µs
µs
µs
ns
1000
20 +
0.1Cb
_______________________________________________________________________________________
300
ns
4-Channel I2C Switches/Multiplexer
MAX7367/MAX7368/MAX7369
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Fall Time of Both SDA and SCL
Signals
CONDITIONS
MIN
TYP
fSCL = 100kHz
tf
Capacitive Load for Each Bus Line
Cb
Pulse Width of Spikes Suppressed
tSP
MAX
UNITS
300
20 +
0.1Cb
fSCL = 400kHz (Note 5)
ns
300
(Note 6)
400
pF
50
ns
µs
Data Valid Time from High to Low
tVD;DATL
(Note 7)
1
Data Valid Time from Low to High
tVD;DATH
(Note 7)
0.6
µs
Data Valid Acknowledge
tVD;ACK
1
µs
INT_ to INT Active Valid Time
tIV
4
µs
INT_ to INT Inactive Delay Time
tIR
2
µs
INT (Figure 2)
Low-Level, Pulse-Width Rejection
or INT_ Inputs
tW(REJ)L
1
µs
High-Level, Pulse-Width Rejection
or INT_ Inputs
tW(REJ)H
0.5
µs
RESET (Figure 3)
Pulse-Width Low Reset
tWL(RST)
Reset Time (SDA Clear)
tRST
500
ns
tREC;STA
0
ns
Recovery to Start
4
ns
All parameters are production tested at TA = +25°C and guaranteed by design over the specified temperature range.
Minimum value is not production tested. Guaranteed by design.
Pass gate propagation delay is calculated from 20Ω (typ) RON and the 15pF load capacitance. Not production tested.
A master device must provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL) in order to
bridge the undefined region of SCL’s falling edge.
Note 5: Cb = total capacitance of one bus line in pF.
Note 6: Guaranteed by design.
Note 7: Measurements taken with a 1kΩ pullup resistor and 50pF load.
Note 1:
Note 2:
Note 3:
Note 4:
SDA
tLOW
tf
tSU;DAT
tr
tHD;STA
tf
tSP
tBUF
tr
SCL
tHD;STA
tHD;DAT
tHIGH
tSU;STO
tSU;STA
Sr
S
P
S
Figure 1. 2-Wire Serial-Interface Timing Diagram
_______________________________________________________________________________________
5
MAX7367/MAX7368/MAX7369
4-Channel I2C Switches/Multiplexer
INT_
50%
50%
tIV
INT
tW(REJ)L
tIR
tW(REJ)H
50%
50%
Figure 2. INT Timing Diagram
SCL
SDA
tREC;STA
tRST
RESET
tWL(RST)
Figure 3. RESET Timing Diagram
6
_______________________________________________________________________________________
4-Channel I2C Switches/Multiplexer
PROPAGATION DELAY
vs. SUPPLY VOLTAGE
VPASS (V)
3.0
4
3
2.5
2.0
1.5
2
RISING EDGE
1
2.7
3.1
3.5
3.9
4.3
4.7
5.1
50
30
20
0.5
10
SCL = 100kHz AND SDA = 0V
0
2.3
5.5
SCL = 400kHz AND SDA = 0V
40
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
SUPPLY CURRENT
vs. SCL FREQUENCY
60
MAX7367 toc04
2.3
60
1.0
0
0
70
SUPPLY CURRENT (μA)
3.5
FALLING EDGE
80
MAX7367 toc03
4.0
VDD = 5V AND SDA = 0V
50
SUPPLY CURRENT (μA)
PROPAGATION DELAY (ns)
6
4.5
MAX7367 toc02
fIN = 400kHz
MAX7367 toc01
7
5
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VPASS VOLTAGE vs. SUPPLY VOLTAGE
40
30
20
10
0
100
150
200
250
300
350
400
FREQUENCY (kHz)
_______________________________________________________________________________________
7
MAX7367/MAX7368/MAX7369
Typical Operating Characteristics
(VDD = +5V, TA = +25°C, unless otherwise noted.)
4-Channel I2C Switches/Multiplexer
MAX7367/MAX7368/MAX7369
Pin Description
PIN
8
NAME
FUNCTION
MAX7367
MAX7368
MAX7369
1
1
1
A0
Device Address Bit 0 (LSB)
2
2
2
A1
Device Address Bit 1
3
3
—
RESET
4
—
4
INT0
Channel 0 Active-Low Interrupt Input. A logic-low INT0 asserts INT. If not
used, pull up INT0 through a resistor to VDD.
5
4
5
SD0
Channel 0 Serial Data
6
5
6
SC0
Channel 0 Serial Clock
Active-Low Reset Input
7
—
7
INT1
Channel 1 Active-Low Interrupt Input. A logic-low INT1 asserts INT. If not
used, pull up INT1 through a resistor to VDD.
8
6
8
SD1
Channel 1 Serial Data
9
7
9
SC1
Channel 1 Serial Clock
10
8
10
GND
Ground
11
—
11
INT2
Channel 2 Active-Low Interrupt Input. A logic-low INT2 asserts INT. If not
used, pull up INT2 through a resistor to VDD.
12
9
12
SD2
Channel 2 Serial Data
13
10
13
SC2
Channel 2 Serial Clock
14
—
14
INT3
Channel 3 Active-Low Interrupt Input. A logic-low INT3 asserts INT. If not
used, pull up INT3 through a resistor to VDD.
15
11
15
SD3
Channel 3 Serial Data
16
12
16
SC3
Channel 3 Serial Clock
—
13
3
A2
17
—
17
INT
Device Address Bit 2
Active-Low, Open-Drain Interrupt Output. Connect a pullup resistor to VDD.
18
14
18
SCL
Main Serial Clock
19
15
19
SDA
Main Serial Data
20
16
20
VDD
Power Supply. Bypass to GND with 0.1µF capacitor.
_______________________________________________________________________________________
4-Channel I2C Switches/Multiplexer
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
SWITCH CONTROL LOGIC
RESET
VDD
POWER-ON
RESET
SCL
GLITCH FILTER
SDA
INT[0–3]
MAX7367
I2C BUS
CONTROL
INTERRUPT LOGIC
A0
A1
INT
GND
_______________________________________________________________________________________
9
MAX7367/MAX7368/MAX7369
MAX7367 Functional Diagram
4-Channel I2C Switches/Multiplexer
MAX7367/MAX7368/MAX7369
MAX7368 Functional Diagram
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
SWITCH CONTROL LOGIC
RESET
VDD
POWER-ON
RESET
SCL
GLITCH FILTER
SDA
MAX7368
I2C BUS
CONTROL
A0
A1
A2
GND
10
______________________________________________________________________________________
4-Channel I2C Switches/Multiplexer
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
SWITCH CONTROL LOGIC
VDD
POWER-ON
RESET
SCL
GLITCH FILTER
SDA
INT[0–3]
MAX7369
I2C BUS
CONTROL
INTERRUPT LOGIC
A0
A1
A2
INT
GND
______________________________________________________________________________________
11
MAX7367/MAX7368/MAX7369
MAX7369 Functional Diagram
MAX7367/MAX7368/MAX7369
4-Channel I2C Switches/Multiplexer
Detailed Description
The MAX7367/MAX7368/MAX7369 bidirectional, fourchannel I2C switches/multiplexer expand the main I2C
bus up to four extended buses. The MAX7369 is a 1:4
multiplexer that connects the main I2C bus to one channel at a time. The MAX7367/MAX7368 are four-channel
switches that can connect the main I2C bus to one or
more channels at a time. These devices isolate bus
loading by separating available I2C devices into groups
on the channels. The total loading capacitance of the
main bus plus those of the connected channel must not
exceed 400pF. The extended buses are connected or
disconnected through the main I2C bus by writing to the
control register of the MAX7367/MAX7368/MAX7369.
Any device connected to an I2C bus can transmit and
receive signals. The MAX7367/MAX7368/MAX7369 are
transparent to signals sent and received at each channel,
allowing multiple masters on the buses. These devices
are compatible with the I2C protocol of clock stretch, synchronization, and arbitration in case of multiple masters
addressing the bus at the same time. The
MAX7367/MAX7368 have a RESET input that allows
external circuitry to set the MAX7367/MAX7368 to its
default state anytime after the device has powered up.
The MAX7367/MAX7369 have interrupt inputs, allowing
devices on the extended bus to send an interrupt signal
to the master on the main bus.
Device Address
The MAX7367/MAX7368/MAX7369 have selectable
device addresses through external inputs. The
MAX7367 slave address consists of 5 fixed bits
(A6–A2, set to 11100), followed by 2 pin-programmable
bits (A1 and A0), as shown in Figure 4. The MAX7368/
MAX7369 slave address consists of 4 fixed bits
(A6–A3, set to 1110), followed by 3 pin-programmable
bits (A2, A1 and A0), as shown in Figure 5. The most
significant address bit (A6) is transmitted first, followed
by the remaining bits. The addresses A2 (for MAX7368/
MAX7369), A1, and A0 can also be driven dynamically
if required, but the values must be stable when they are
expected in the address sequence.
master bus sends a byte or the master bus receives a
byte from/to the MAX7367/MAX7368/MAX7369. The last
3 bits (for the MAX7369) or 4 bits (for the MAX7367/
MAX7368) of the byte are stored in the control/interrupt
register (B0 to B2 or B0 to B3) for channel selection. If
multiple bytes are received, only the last byte received
is saved. The first four bits of the register represent the
interrupt condition (for the MAX7367/MAX7369 only).
1
1
1
0
0
FIXED
A1
A0
HARDWARE SELECTION
Figure 4. MAX7367 Slave Address
1
1
1
0
FIXED
A2
A1
A0
12
R/W
HARDWARE SELECTION
Figure 5. MAX7368/MAX7369 Slave Address
INTERRUPT BITS
(READ ONLY)
CHANNEL SELECTION BITS
(READ/WRITE)
7
6
5
4
3
2
1
0
INT3
INT2
INT1
INT0
B3
B2
B1
B0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
INT0
INT1
INT2
INT3
Control/Interrupt Register
There is a control/interrupt register inside the MAX7367/
MAX7369 (Figures 6 and 8). There is a control (only)
register inside the MAX7368 (Figure 7). Use the main
I2C bus to write or read from this register. Following the
successful acknowledgement of the slave address, the
R/W
Figure 6. MAX7367 Control/Interrupt Register
______________________________________________________________________________________
4-Channel I2C Switches/Multiplexer
7
6
5
4
3
2
1
0
X
X
X
X
B3
B2
B1
B0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
X = DON'T CARE.
After a device generates an interrupt on one of the
channels, the interrupt input is loaded into the
control/interrupt register when a read is performed. To
determine which device is generating the interrupt,
read the contents of the control/interrupt register to
determine which channel is issuing the interrupt, then
write the appropriate command to the control/interrupt
register to select the interrupted channel. Read from all
devices on the interrupted channel to determine the
exact source of the interrupt.
Table 1. MAX7367/MAX7368 Control Bits
for Channel Selection
Figure 7. MAX7368 Control Register
CONTROL BIT
INTERRUPT BITS
(READ ONLY)
COMMAND
CHANNEL SELECTION BITS
(READ/WRITE)
B0
0 = Channel 0 disabled (default)
1 = Channel 0 enabled
B1
0 = Channel 1 disabled (default)
1 = Channel 1 enabled
B2
0 = Channel 2 disabled (default)
1 = Channel 2 enabled
B3
0 = Channel 3 disabled (default)
1 = Channel 3 enabled
7
6
5
4
3
2
1
0
INT3
INT2
INT1
INT0
X
B2
B1
B0
ENABLE BIT
X = DON'T CARE.
Figure 8. MAX7369 Control/Interrupt Register
Channel Selection
Each channel selected contains an SD_ and SC_ pair.
Select a channel by writing a control byte after a successful acknowledge of the slave address. The last 4 bits of the
control byte determine which channel(s) is selected for the
MAX7367/MAX7368 as shown in Table 1. The last 3 bits of
the control byte determine which channel is selected for
the MAX7369 as shown in Table 2. The selected channels
are activated after the stop condition. When a channel is
selected, the respective SD_/SC_ pair is logic-high, ensuring no false conditions occur on the bus.
Interrupt Logic (MAX7367/MAX7369)
The MAX7367/MAX7369 have four interrupt inputs, one for
each channel, and one INT output. The INT output is an
open-drain output that requires a pullup resistor. The INT
output is asserted by a low-logic signal on any of the INT_
inputs, and it is deasserted only when all the INT_ inputs
are logic-high. Bits 4–7 of the MAX7367/MAX7369
control/interrupt register store the state of the INT_ for
each channel as shown in Table 3 and Figures 6 and 8.
The logic level of INT_ is not latched. Drive the respective
INT_ input high to remove the interrupt condition for the
channel. An interrupt can occur on any channel, regardless of whether it is selected or not selected.
Table 2. MAX7369 Control Bits for
Channel Selection
B2
B1
B0
COMMAND
0
0
0
No channel selected (default)
0
X
X
No channel selected
1
0
0
Channel 0 selected
1
0
1
Channel 1 selected
1
1
0
Channel 2 selected
1
1
1
Channel 3 selected
Table 3. MAX7367/MAX7369 Interrupt
Indicator Bits
INTERRUPT BIT
STATE
INT0
0 = No channel 0 interrupt (default)
1 = Channel 0 interrupt
INT1
0 = No channel 1 interrupt (default)
1 = Channel 1 interrupt
INT2
0 = No channel 2 interrupt (default)
1 = Channel 2 interrupt
INT3
0 = No channel 3 interrupt (default)
1 = Channel 3 interrupt
______________________________________________________________________________________
13
MAX7367/MAX7368/MAX7369
CHANNEL SELECTION BITS
(READ/WRITE)
MAX7367/MAX7368/MAX7369
4-Channel I2C Switches/Multiplexer
RESET Input (MAX7367/MAX7368)
The MAX7367/MAX7368 feature an active-low RESET
input. When RESET is driven low for more than 4ns, the
MAX7367/MAX7368 reset the internal register and I2C
state machine to their default states, allowing a master
to recover from a bus fault condition.
Power-On Reset (POR)
When power is applied to VDD, internal POR circuitry
holds the MAX7367/MAX7368/MAX7369 in a reset state
until VDD has reached the VPOR threshold. At this point,
the reset condition is released, and the MAX7367/
MAX7368/MAX7369 register and I2C state machine are
initialized to their default states (all zeroes), causing all
the channels to be deselected.
high period of the clock pulse (Figure 11). In the case
of an unsuccessful data transfer, the receiver allows
SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time.
Voltage Translation
SDA
The MAX7367/MAX7368/MAX7369 can be used as a voltage translator from the main bus to the extended buses.
The output voltage (VPASS) is limited by the supply voltage (VDD) (see the Typical Operation Characteristics).
For the MAX7367/MAX7368/MAX7369 to be used as a
voltage translator, the VPASS voltage should be lower
than or equal to the lowest bus voltage.
SCL
I2C Interface
The MAX7367/MAX7368/MAX7369 feature an I2C-compatible, 2-wire serial interface consisting of a bidirectional serial-data line (SDA) and a serial-clock line
(SCL). The master (typically a microcontroller) initiates
data transfer on the bus and generates the SCL.
Bit Transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 9).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 10).
Acknowledge Bit
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (NA).
Both the master and the MAX7367/MAX7368/MAX7369
(slave) generate acknowledge bits. To generate an
acknowledge, the receiving device must pull SDA low
before the rising edge of the acknowledge-related
clock pulse (ninth pulse) and keep it low during the
14
CHANGE OF
DATA ALLOWED
DATA STABLE
DATA VALID
Figure 9. Bit Transfer
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
Figure 10. Start and Stop Conditions
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
8
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 11. Acknowledge
______________________________________________________________________________________
9
4-Channel I2C Switches/Multiplexer
START CONDITION
S
1
1
1
Applications Information
Repeated Slave Addresses
The MAX7367/MAX7368/MAX7369 allow systems to
reuse slave addresses individually on each channel of
the extended bus. To reuse slave addresses on the
extended bus channels of the MAX7367/MAX7368,
ensure no more than one channel with a reused
address is selected at the same time.
Power-Supply Considerations
The MAX7367/MAX7368/MAX7369 operate from a
+2.3V to +5.5V power-supply voltage. Good powersupply decoupling is needed to maintain the performance of these parts. Bypass VDD to GND with a 0.1µF
surface-mount ceramic capacitor. Mount the bypass
capacitor as close as possible to the device.
ACKNOWLEDGE BIT
FROM SLAVE
(A2)
0
A1
A0
A
1
STOP CONDITION
INT3* INT2* INT1* INT0*
DEVICE ADDRESS
B3**
B2
B1
B0
NA
P
NOT ACKNOWLEDGE
BIT FROM MASTER
CONTROL BYTE
() A2 = 0 FOR MAX7367.
** DON'T CARE FOR MAX7368.
** DON'T CARE FOR MAX7369.
Figure 12. Read Command
START CONDITION
S
1
1
1
ACKNOWLEDGE BIT
FROM SLAVE
0
(A2)
DEVICE ADDRESS
() A2 = 0 FOR MAX7367.
* DON'T CARE FOR MAX7369.
X = DON'T CARE.
A1
A0
0
A
X
X
X
STOP CONDITION
X
B3*
CONTROL BYTE
B2
B1
B0
A
P
ACKNOWLEDGE
BIT FROM SLAVE
Figure 13. Write Command
______________________________________________________________________________________
15
MAX7367/MAX7368/MAX7369
Serial Addressing
A master initiates communication with a slave device
by issuing a START condition followed by a slave
address byte. The slave address byte consists of 7
address bits and a read/write bit (R/W). When idle, the
MAX7367/MAX7368/MAX7369 continuously wait for a
START condition followed by its slave address. After
recognizing a start condition followed by the correct
address, the MAX7367/MAX7368/MAX7369 are ready
to accept or send data. The least significant bit (LSB) of
the address byte (R/W) determines whether the master
is writing to or reading from the MAX7367/MAX7368/
MAX7369 (R/W = 0 selects a write command, R/W = 1
selects a read command as shown in Figures 12 and
13). After receiving the proper address, the
MAX7367/MAX7368/MAX7369 (slave) issue an ACK by
pulling SDA low for one clock cycle.
MAX7367/MAX7368/MAX7369
4-Channel I2C Switches/Multiplexer
Choosing Pullup Resistors
I2C requires pullup resistors to provide a logic-high
level to data and clock lines. There are tradeoffs
between power dissipation and speed, and a compromise must be made in choosing pullup resistor values.
Every device connected to the bus introduces some
capacitance even when the device is not in operation.
I2C specifies 300ns rise times to go from low to high
(30% to 70%) for fast mode, which is defined for a data
rate of 400kbps (refer to I2C specifications for details).
In order to meet the rise time requirement, choose the
pullup resistors such that the rise time (t R =
0.85RPULLUP x CBUS) is less than 300ns. For a bus
capacitance of 400pF, choose a pullup resistor less
than 880Ω. Often I2C devices work when the maximum
specified rise time is exceeded. However, if the rise
times become too slow, the devices on the bus do not
recognize the command signals. Optional resistors (24Ω)
in series with SDA and SCL protect the device inputs
from high-voltage spikes on the bus lines and also minimize crosstalk and undershoot of the bus signals.
Chip Information
PROCESS: BiCMOS
Pin Configurations (continued)
TOP VIEW
+
+
A0 1
20 VDD
A0 1
16 VDD
A1 2
19 SDA
A1 2
15 SDA
A2 3
18 SCL
RESET 3
14 SCL
INT0 4
13 A2
SD0 5
16 SC3
SC0 5
12 SC3
SC0 6
15 SD3
SD1 6
11 SD3
INT1 7
14 INT3
SC1 7
10 SC2
SD1 8
13 SC2
GND 8
9 SD2
SC1 9
12 SD2
GND 10
11 INT2
SD0 4
MAX7368
TSSOP
MAX7369
17 INT
TSSOP
16
______________________________________________________________________________________
4-Channel I2C Switches/Multiplexer
VCC
VDD
VDD
VDD
SDA
SDA
SD0
SCL
SCL
SC0
(INT)
(INT0)
MASTER
VDD
RESET *
MAX7367
MAX7368
MAX7369
SD1
SC1
(INT1)
VDD
SD2
SC2
(INT2)
VDD
A0
A1
SD3
A2**
SC3
GND
(INT3)
* FOR MAX7367/MAX7368.
** FOR MAX7368/MAX7369.
() FOR MAX7367/MAX7369.
______________________________________________________________________________________
17
MAX7367/MAX7368/MAX7369
Typical Operating Circuit
MAX7367/MAX7368/MAX7369
4-Channel I2C Switches/Multiplexer
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
18
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
20 TSSOP
U20-3
21-0066
16 TSSOP
U16-1
21-0066
______________________________________________________________________________________
4-Channel I2C Switches/Multiplexer
REVISION
REVISION
0
10/06
Initial release of the MAX7369
1
12/06
Initial release of the MAX7367/MAX7368
2
2/09
Changed the minimum VIL spec
DESCRIPTION
PAGES CHANGED
—
1
2–5
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX7367/MAX7368/MAX7369
Revision History