ON MC74VHC139M Dual 2−to−4 decoder/demultiplexer Datasheet

MC74VHC139
Dual 2−to−4 Decoder/
Demultiplexer
The MC74VHC139 is an advanced high speed CMOS 2−to−4
decoder/ demultiplexer fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
When the device is enabled (E = low), it can be used for gating or as
a data input for demultiplexing operations. When the enable input is
held high, all four outputs are fixed high, independent of other inputs.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
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MARKING DIAGRAMS
16
9
VHC139
AWLYYWW
SOIC−16
D SUFFIX
CASE 751B
1
8
16
High Speed: tPD = 5.0 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 100 FETs or 25 Equivalent Gates
Pb−Free Packages are Available*
9
VHC
139
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
1
8
16
74VHC139
ALYW
SOEIAJ−16
M SUFFIX
CASE 966
A
WL, L
YY, Y
WW, W
9
1
8
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2004
August, 2004 − Rev. 3
1
Ea
1
16
VCC
A0a
2
15
Eb
A1a
3
14
A0b
Y0a
4
13
A1b
Y1a
5
12
Y0b
Y2a
6
11
Y1b
Y3a
7
10
Y2b
GND
8
9
Y3b
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
MC74VHC139/D
MC74VHC139
ADDRESS
INPUTS
A0a
A1a
2
4
3
5
6
7
Ea
ADDRESS
INPUTS
A0b
A1b
Y1a
Y2a
Inputs
ACTIVE−LOW
OUTPUTS
Y3a
1
14
13
12
11
10
9
Eb
Table 1. FUNCTION TABLE
Y0a
Y0b
Y1b
Y2b
Outputs
E
A1
A0
Y0
Y1
Y2
Y3
H
X
X
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
L
ACTIVE−LOW
OUTPUTS
Y3b
15
Figure 1. Logic Diagram
En
Y0
Y1
A0
Y2
Y3
A1
Figure 2. Expanded Logic Diagram
(1/2 of Device)
INPUT
A1a
3
A0a
2
Ea
1
1
X/Y
0
2
1
EN
2
3
A1b 13
A0b 14
Eb 15
4 Y0a
5 Y1a
A1a
3
A0a
2
6 Y2a
7 Y3a
Ea
1
1
DMUX
0
0
G
3
1
2
4 Y0a
5 Y1a
6 Y2a
7 Y3a
12 Y0b
10 Y2b
A1b 13
A0b 14
10 Y2b
9 Y3b
Eb 15
9 Y3b
Figure 4. IEC Logic Diagram
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2
3
12 Y0b
11 Y1b
Figure 3. Input Equivalent Circuit
0
11 Y1b
MC74VHC139
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MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
–0.5 to +7.0
V
Vin
DC Input Voltage
–0.5 to +7.0
V
Vout
DC Output Voltage
–0.5 to VCC + 0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
–65 to +150
°C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating − SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage
2.0
5.5
V
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
TA
Operating Temperature
−55
+125
°C
tr, tf
Input Rise and Fall Time
(Figure 3)
0
0
100
20
ns/V
VCC = 3.3 V ±0.3V
VCC =5.0 V ±0.5V
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
80
TJ = 90 ° C
Time, Years
TJ = 100 ° C
Time, Hours
TJ = 110° C
Junction
Temperature (°C)
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 120° C
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
TJ = 130 ° C
NORMALIZED FAILURE RATE
The qJA of the package is equal to 1/Derating. Higher junction temperatures may affect the
expected lifetime of the device per the table and figure below.
1
1
10
100
TIME, YEARS
Figure 5. Failure Rate vs. Time
Junction Temperature
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3
1000
MC74VHC139
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DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
1.5
2.1
3.15
3.85
VIH
Minimum
High−Level Input
Voltage
2.0
3.0
4.5
5.5
VIL
Maximum
Low−Level Input
Voltage
2.0
3.0
4.5
5.5
VOH
Minimum
High−Level Output
Voltage
VIN = VIH or VIL
VOL
Maximum
Low−Level Output
Voltage
VIN = VIH or VIL
TA = ≤ 85°C
TA = 25°C
VCC
(V)
Typ
Max
Min
2.0
3.0
4.5
1.9
2.9
4.4
VIN = VIH or VIL
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
VIN = VIH or VIL
IOL = 50 mA
2.0
3.0
4.5
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
VIN = VIH or VIL
IOH = − 50 mA
TA = ≤ 125°C
Max
2.0
3.0
4.5
0.0
0.0
0.0
Max
Unit
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
V
0.5
0.9
1.35
1.65
1.9
2.9
4.4
1.9
2.9
4.4
2.48
3.80
2.34
3.66
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum
Quiescent Supply
Current
VIN = VCC or GND
5.5
4.0
40.0
40.0
mA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
tPLH,
tPHL
tPLH,
tPHL
CIN
Max
Min
Max
Min
Max
Unit
VCC = 3.3 ± 0.3 VCL = 15 pF
CL = 50 pF
7.2
9.7
11.0
14.5
1.0
1.0
13.0
16.5
1.0
1.0
13.0
16.5
ns
VCC = 5.0 ± 0.5 VCL = 15 pF
CL = 50 pF
5.0
6.5
7.2
9.2
1.0
1.0
8.5
10.5
1.0
1.0
8.5
10.5
VCC = 3.3 ± 0.3 VCL = 15 pF
CL = 50 pF
6.4
8.9
9.2
12.7
1.0
1.0
11.0
14.5
1.0
1.0
11.0
14.5
VCC = 5.0 ± 0.5 VCL = 15 pF
CL = 50 pF
4.4
5.9
6.3
8.3
1.0
1.0
7.5
9.5
1.0
1.0
7.5
9.5
4
10
Test Conditions
Maximum
Propagation Delay,
A to Y
Maximum
Propagation Delay,
E to Y
TA = − 55 to 125°C
Typ
Parameter
Min
TA = − 40 to 85°C
Maximum Input
Capacitance
10
10
ns
pF
Typical @ 25°C, VCC = 5.0 V
CPD
26
Power Dissipation Capacitance (1)
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/2 (per decoder). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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4
MC74VHC139
SWITCHING WAVEFORMS
A
VCC
50%
GND
tPHL
tPLH
Y
50% VCC
Figure 6.
TEST POINT
E
VCC
50%
tPHL
Y
tPLH
GND
OUTPUT
DEVICE
UNDER
TEST
CL*
50% VCC
*Includes all probe and jig capacitance
Figure 7.
Figure 8. Test Circuit
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5
MC74VHC139
ORDERING INFORMATION
Package
Shipping†
MC74VHC139D
SOIC−16
48 Units / Rail
MC74VHC139DR2
SOIC−16
2500 / Tape & Reel
MC74VHC139DR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC74VHC139DT
TSSOP−16
96 Units / Rail
MC74VHC139DTR2
TSSOP−16
(Pb−Free)
2500 / Tape & Reel
MC74VHC139M
SOEIAJ−16
50 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
MC74VHC139
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
M
N
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
DETAIL E
H
D
G
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7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
N−N
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
−−−
1.20
−−−
0.047
D
0.05
0.15
0.002
0.006
0.50
0.75
0.020
0.030
−W− GF
0.65 BSC
0.026 BSC
H
0.18
0.28
0.007
0.011
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0_
8_
0_
8_
MC74VHC139
PACKAGE DIMENSIONS
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE O
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
9
Q1
M_
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−−
0.031
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MC74VHC139/D
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