CY7C185 64-Kbit (8 K × 8) Static RAM Features Functional Description ■ High speed ❐ 15 ns ■ Fast tDOE ■ Low active power ❐ 715 mW ■ Low standby power ❐ 85 mW The CY7C185[1] is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and tri-state drivers. This device has an automatic power-down feature (CE1 or CE2), reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP, SOJ, or SOIC package. ■ CMOS for optimum speed/power ■ Easy memory expansion with CE1, CE2 and OE features ■ TTL-compatible inputs and outputs ■ Automatic power-down when deselected ■ Available in non Pb-free 28-pin (300-Mil) Molded SOJ, 28-pin (300-Mil) Molded SOIC and Pb-free 28-pin (300-Mil) Molded DIP An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input or output pins. The input or output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity. Logic Block Diagram I/O0 INPUT BUFFER I/O2 SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER I/O1 8K x 8 ARRAY I/O3 I/O4 I/O5 I/O6 CE1 CE2 WE COLUMN DECODER POWER DOWN I/O7 A12 A11 A10 A0 A9 OE Selection Guide Description Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) -15 15 130 15 -20 20 110 15 -35 35 100 15 Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05043 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 20, 2011 [+] Feedback CY7C185 Contents Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 3 Operating Range ............................................................... 3 Electrical Characteristics ................................................. 3 Capacitance ...................................................................... 4 Switching Characteristics ,Over the Operating Range ................................................. 5 Switching Waveforms ...................................................... 6 Typical DC and AC Characteristics ................................ 9 Truth Table ...................................................................... 10 Address Designators ..................................................... 10 Document #: 38-05043 Rev. *E Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagrams .......................................................... 11 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15 Page 2 of 15 [+] Feedback CY7C185 Pin Configuration DIP/SOJ Top View NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC WE CE2 A3 A2 A1 OE A0 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Static discharge voltage........................................... >2001 V (per MIL-STD-883, Method 3015) Storage temperature .................................. –65°C to +150°C Latch-up current ..................................................... >200 mA Ambient temperature with power applied ............................................. –55°C to +125°C Operating Range Supply voltage to ground potential ...............–0.5 V to +7.0 V Range DC voltage applied to outputs in High Z State[2] ...........................................–0.5 V to +7.0 V DC input voltage[2] ........................................–0.5 Commercial Industrial V to +7.0 V Ambient Temperature VCC 0°C to +70°C 5 V ± 10% –40°C to +85°C 5 V ± 10% Output current into outputs (LOW) .............................. 20 mA Electrical Characteristics Over the Operating Range –15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic Power-down Current Automatic Power-down Current Document #: 38-05043 Rev. *E Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min 2.4 –20 Max Min 2.4 0.4 2.2 –35 Max Min 2.4 0.4 Max Unit V 0.4 V 2.2 VCC + 0.3 V 2.2 VCC + 0.3 V V –0.5 VCC + 0.3 V 0.8 –0.5 0.8 –0.5 0.8 V GND ≤ VI ≤ VCC –5 +5 –5 +5 –5 +5 μA GND ≤ VI ≤ VCC, Output Disabled VCC = Max., IOUT = 0 mA Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL Min. Duty Cycle =100% Max. VCC, CE1 ≥ VCC – 0.3 V, or CE2 ≤ 0.3 V VIN ≥ VCC – 0.3 V or VIN ≤ 0.3 V –5 +5 –5 +5 –5 +5 μA 130 110 100 mA 40 20 20 mA 15 15 15 mA Page 3 of 15 [+] Feedback CY7C185 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max Unit 7 pF 7 pF TA = 25°C, f = 1 MHz, VCC = 5.0 V Figure 1. AC Test Loads and Waveforms R1 481 Ω 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255Ω (a) R1 481 Ω 5V OUTPUT ALL INPUT PULSES 3.0 V 5 pF INCLUDING JIGAND SCOPE R2 255Ω (b) GND 10% ≤ 5 ns Equivalent to: OUTPUT 90% 90% 10% ≤ 5 ns THÉVENIN EQUIVALENT 167Ω 1.73 V Notes 2. Minimum voltage is equal to –3.0 V for pulse durations less than 30 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05043 Rev. *E Page 4 of 15 [+] Feedback CY7C185 Switching Characteristics Over the Operating Range[4] -15 Parameter Description Min -20 Max Min -35 Max Min Max Unit Read Cycle tRC Read Cycle Time 15 20 tAA Address to Data Valid tOHA Data Hold from Address Change tACE1 CE1 LOW to Data Valid 15 20 35 ns tACE2 CE2 HIGH to Data Valid 15 20 35 ns tDOE OE LOW to Data Valid 15 ns tLZOE OE LOW to Low Z 15 3 20 5 8 3 Z[5] tHZOE OE HIGH to High tLZCE1 CE1 LOW to Low Z[6] 3 tLZCE2 CE2 HIGH to Low Z 3 tHZCE CE1 HIGH to High Z[5, 6] CE2 LOW to High Z tPU CE1 LOW to Power-up CE2 to HIGH to Power-up tPD CE1 HIGH to Power-down CE2 LOW to Power-down 35 9 8 10 0 ns 10 0 20 ns ns 3 8 15 ns 5 3 7 ns ns 3 5 0 35 5 3 7 ns ns ns 20 ns Write Cycle[7] tWC Write Cycle Time 15 20 35 ns tSCE1 CE1 LOW to Write End 12 15 20 ns tSCE2 CE2 HIGH to Write End 12 15 20 ns tAW Address Setup to Write End 12 15 25 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Setup to Write Start 0 0 0 ns tPWE WE Pulse Width 12 15 20 ns tSD Data Setup to Write End 8 10 12 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High Z[5] tLZWE WE HIGH to Low Z 0 7 3 0 7 5 ns 8 5 ns ns Notes 4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 6. At any temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device. 7. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. Document #: 38-05043 Rev. *E Page 5 of 15 [+] Feedback CY7C185 Switching Waveforms Figure 2. Read Cycle No.1[8,9] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 3. Read Cycle No.2[10,11] tRC CE1 CE2 tACE OE OE DATA OUT tDOE tLZOE HIGH IMPEDANCE tHZOE tHZCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB Notes 8. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH. 9. WE is HIGH for read cycle. 10. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL. 11. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. Document #: 38-05043 Rev. *E Page 6 of 15 [+] Feedback CY7C185 Switching Waveforms (continued) Figure 4. Write Cycle No. 1 (WE Controlled)[9,11] tWC ADDRESS tSCEI CE1 tAW tHA tSCE2 CE CE 2 tSA WE tPWE OE tSD DATA I/O tHD DATA IN VALID NOTE 12 tHZOE Figure 5. Write Cycle No. 2 (CE Controlled)[11,12,13] tWC ADDRESS tSCE1 CE1 tSA tSCE2 CE2 tAW tHA WE tSD DATA I/O tHD DATA IN VALID Notes 12. During this period, the I/Os are in the output state and input signals must not be applied. 13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05043 Rev. *E Page 7 of 15 [+] Feedback CY7C185 Switching Waveforms (continued) Figure 6. Write Cycle No. 3 (WE Controlled, OE LOW)[11,12,13,14] tWC ADDRESS CE1 tSCE1 CE2 tSCE2 tAW tHA tSA WE tSD DATA I/O NOTE 12 tHD DATA IN VALID tHZWE tLZWE Note 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05043 Rev. *E Page 8 of 15 [+] Feedback CY7C185 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 SB 1.2 I CC 0.8 0.6 0.4 4.5 5.0 0.8 0.6 0.4 V CC=5.0 V V IN=5.0 V 5.5 ISB 0.0 –55 6.0 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.6 1.4 1.3 NORMALIZED tAA NORMALIZED t AA 125 1.2 1.1 TA =25°C 1.0 1.4 1.2 1.0 VCC =5.0 V 0.8 0.9 0.8 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 0.6 –55 6.0 2.5 25.0 DELTA tAA (ns) 30.0 2.0 1.5 1.0 25 3.0 4.0 SUPPLY VOLTAGE (V) Document #: 38-05043 Rev. *E 80 VCC =5.0 V TA =25°C 60 40 20 0 0.0 5.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 VCC =5.0 V TA =25°C 80 60 40 20 0 0.0 125 20.0 15.0 10.0 0.0 1.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) 4.0 NORMALIZED I CC vs. CYCLE TIME 1.25 VCC =4.5 V TA =25°C 5.0 0.5 2.0 100 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 3.0 1.0 120 AMBIENT TEMPERATURE (°C) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 0.0 0.0 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) NORMALIZED I PO 25 OUTPUT SINK CURRENT (mA) 0.0 4.0 I CC 0.2 I SB 0.2 1.0 0 200 400 600 800 1000 CAPACITANCE (pF) NORMALIZED I CC 1.0 NORMALIZED I,CC I NORMALIZED I,CCI SB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics VCC =5.0 V TA =25°C VCC =0.5 V 1.00 0.75 0.50 10 20 30 40 CYCLE FREQUENCY (MHz) Page 9 of 15 [+] Feedback CY7C185 Address Designators Truth Table Address Name Address Function Pin Number Deselect/ Power-down A4 X3 2 A5 X4 3 High Z Deselect/ Power-down A6 X5 4 A7 X6 5 L Data Out Read A8 X7 6 L X Data In Write A9 Y1 7 H H High Z Deselect A10 Y4 8 Input/Output CE1 CE2 WE OE H X X X High Z X L X X L H H L H L H Mode A11 Y3 9 A12 Y0 10 A0 Y2 21 A1 X0 23 A2 X1 24 A3 X2 25 Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C185-15VI 51-85031 28-pin (300-Mil) Molded SOJ 20 CY7C185-20PXC 51-85014 28-pin (300-Mil) Molded DIP (Pb-free) Commercial Industrial 35 CY7C185-35SC 51-85026 28-pin (300-Mil) Molded SOIC Commercial Ordering Code Definitions CY 7 C 1 85 - XX XX X Temperature Range: X = C or I C = Commercial; I = Industrial Package Type: XX = V or PX or S V = 28-pin Molded SOJ PX = 28-pin Molded DIP (Pb-free) S = 28-pin Molded SOIC Speed: 15 ns or 20 ns or 35 ns 85 = 64 Kbit density with datawidth × 8 bits 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document #: 38-05043 Rev. *E Page 10 of 15 [+] Feedback CY7C185 Package Diagrams Figure 7. 28-pin (300-Mil) PDIP (51-85014) 51-85014 *E Figure 8. 28-pin (300-Mil) Molded SOIC (51-85026) 51-85026 *F Document #: 38-05043 Rev. *E Page 11 of 15 [+] Feedback CY7C185 Package Diagrams (continued) Figure 9. 28-pin (300-Mil) Molded SOJ (51-85031) 51-85031 *D Document #: 38-05043 Rev. *E Page 12 of 15 [+] Feedback CY7C185 Acronyms Document Conventions Acronym Description CE chip enable CMOS Complementary metal oxide semiconductor I/O Input/output OE output enable SRAM Static random access memory SOJ Small Outline J-Lead TSOP Thin Small Outline Package VFBGA Very Fine-Pitch Ball Grid Array Document #: 38-05043 Rev. *E Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes mV milli Volts mW milli Watts MHz Mega Hertz pF pico Farad °C degree Celcius W Watts Page 13 of 15 [+] Feedback CY7C185 Document History Page Document Title: CY7C185, 64-Kbit (8 K × 8) Static RAM Document Number: 38-05043 Revision ECN Submission Date Orig. of Change Description of Change ** 107145 09/10/01 SZV Change from Spec number: 38-00037 to 38-05043 *A 116470 09/16/02 CEA Add applications foot note to data sheet *B 486744 See ECN NXR Changed Low standby power from 220mW to 85mW Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the Ordering Information table *C 2263686 See ECN *D 3105329 12/09/2010 AJU *E 3235800 04/20/2011 PRAS Document #: 38-05043 Rev. *E VKN/AESA Removed 25 ns speed bin Updated the Ordering Information table as per the current product offerings Added Ordering Code Definitions. Updated Package Diagrams. Template changes. Added Acronyms and Units of Measure. Updated package diagram spec 51-85026 to *F. Page 14 of 15 [+] Feedback CY7C185 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. 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Document #: 38-05043 Rev. *E Revised April 20, 2011 Page 15 of 15 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback