TI1 DRV590DWP 1.2-a high-efficiency pwm power driver Datasheet

DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
1.2-A HIGH-EFFICIENCY PWM POWER DRIVER
FEATURES
D 1.22-A DC (82% Duty Cycle) Output Current
D
D
D
D
D
D
DESCRIPTION
The DRV590 is a high-efficiency power amplifier ideal
for driving a wide variety of thermoelectric cooler
elements in systems powered from 2.7 V to 5.5 V. PWM
operation and low output stage on-resistance
significantly decrease power dissipation in the amplifier.
(TJ ≤ 89°C)
1-A DC (100% Duty Cycle) Output Current
(TJ ≤ 89°C)
Low Supply Voltage Operation from 2.7 V
to 5.5 V
High Efficiency Generates Less Heat
Over-Temperature Protection
Short-Circuit Protection
PowerPADt SOIC and 4 × 4 mm MicroStar
Junior Packages
The DRV590 is internally protected against over
temperature conditions and current overloads due to
short circuits. The over temperature protection
activates at a junction temperature of 190°C and will
deactivate once the temperature is less than 130°C. If
the overcurrent circuitry is tripped, the amplifier will
automatically reset after 3–5 ms.
APPLICATIONS
D Thermoelectric Cooler (TEC) Driver
D Laser Diode Biasing
J5
IN– (VCOM)
The gain of the DRV590 is controlled by two input
terminals, GAIN1 and GAIN0. The amplifier may be
configured for a gain of 6, 12, 18, and 23.5 dB.
J4
IN+
C4
1 µF
R1
1 kΩ
J1
R2
1 kΩ
R3
120 kΩ
J8
VDD
R4
120 kΩ
J2
R5
120 kΩ
C3
1 µF
J3
NC
IN+
IN–
SHUTDOWN
GAIN0
GAIN1
PVDD
OUT+
NC
PGND
L1
10 µH
J7
OUT+
C5
10 µF
C6
10 µF
C9
220 pF
NC
AREF
AGND
COSC
ROSC
VDD
PVDD
OUT–
NC
PGND
R6
120 kΩ
J8
VDD
C1
1 µF
C2
1 µF
C8
10 µF
J9
GND
L2
10 µH
C7
10 µF
J6
OUT–
Typical Circuit Schematic for Driving a Thermoelectric Cooler Element
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and MicroStar Junior are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
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1
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SOIC (DWP)†
GQC‡
– 40°C to 85°C
DRV590DWP
DRV590GQCR
† The PW package is available taped and reeled. To order a taped and
reeled part, add the suffix R to the part number (e.g., DRV590PWR).
‡ The GQC package is only available taped and reeled.
MicroStar Juniort (GQC) Package
(TOP VIEW)
DWP PACKAGE
(TOP VIEW)
IN+
NC
IN+
IN–
SHUTDOWN
GAIN0
GAIN1
PVDD
OUT+
NC
PGND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
AREF
AGND
COSC
ROSC
VDD
PVDD
OUT–
NC
PGND
NC – No internal connection
IN–
SHUTDOWN
GAIN0
GAIN1
PVDD
PVDD
OUT+
A2
AGND
AREF
A6
A1
B1
A7
B7 NC
C1
C7
D1
D7
E1
F1
E7
F7
G1
G7
COSC
ROSC
VDD
PVDD
PVDD
OUT–
PGND
(SIDE VIEW)
NC – No internal connection
NOTE: The shaded terminals are used for thermal connections
to the ground plane.
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
GQC NO.
DWP NO.
AGND
A3–A5, B2–B6
C2–C6, D2–D4
18
I
Analog ground
AREF
A6
19
O
Connect capacitor to ground for AREF voltage filtering (1 µF).
COSC
B7
17
I
Connect capacitor to ground to set oscillation frequency (220 pF).
GAIN0
C1
5
I
Bit 0 of gain control (TTL logic level)
GAIN1
D1
6
I
Bit 1 of gain control (TTL logic level)
IN–
A1
3
I
Negative differential input
IN+
A2
2
I
Positive differential input
NC
A7
1, 9, 12, 20
OUT–
G7
13
O
Negative BTL output
OUT+
G1
8
O
Positive BTL output
PGND
D5–D6, E2–E6
F2–F6, G2–G6
10, 11
I
High-current grounds (2)
E1, E7, F1, F7
7, 14
I
High-current power supplies (2)
C7
16
I
Connect resistor to ground to set oscillation frequency (120 kΩ).
SHUTDOWN
B1
4
I
Places the amplifier in shutdown mode if a TTL logic low is placed on this terminal,
and normal operation if a TTL logic high is placed on this terminal.
VDD
D7
15
I
Analog power supply
PVDD
ROSC
2
Not connected
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DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VDD, PVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5.5 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
TA ≤ 25°C
2.61 W
DERATING FACTOR
GQC
20.9 mW/°C
TA = 70°C
1.67 W
TA = 85°C
1.36 W
DWP
3.66 W
29.3 mW/°C
2.34 W
1.9 W
PACKAGE
recommended operating conditions
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Supply voltage, VDD, PVDD
High-level input voltage, VIH
GAIN0, GAIN1, SHUTDOWN
Low-level input voltage, VIL
GAIN0, GAIN1, SHUTDOWN
MIN
MAX
2.7
5.5
2
Operating free-air temperature, TA
– 40
Load impedance
UNIT
V
V
0.7
V
85
°C
Ω
1
electrical characteristics at specified free-air temperature, TA = 25°C (unless otherwise noted)
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
PARAMETER
|VOS|
Output offset voltage (measured
differentially)
PSRR
Power supply rejection ratio
|IIH|
High-level input current
|IIL|
Low-level input current
IDD
IDD(SD)
Supply current, no filter
TEST CONDITIONS
VI = 0 V,
TYP
AV = any gain
mV
dB
61
1
µA
1
µA
4.5
6.5
mA
0.05
5
µA
GAIN0 = low, GAIN1 = low
5.1
6
6.5
GAIN0 = high, GAIN1 = low
11
12
12.5
GAIN0 = low, GAIN1 = high
17
18
19
GAIN0 = high, GAIN1 = high
23
23.5
24
Single ended
UNIT
77
GAIN0, GAIN1, SHUTDOWN = 0 V
Differential
MAX
25
VI = 3.3 V
VI = 0 V
Supply current, shutdown mode
Switching frequency
MIN
PVDD = 4.9 V to 5.1 V
PVDD = 3.2 V to 3.4 V
Gain
fs
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
dB
250
Rosc = 120 kΩ,
kΩ Cosc = 220 pF
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500
kHz
3
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
operating characteristics, TA = 25°C, RL = 2 Ω, gain = 6 dB (unless otherwise noted)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
TEST CONDITIONS
IO
PSRR
Maximum output current
Duty cycle = 82%
Power supply rejection ratio
f = 1 kHz,
ZI
Input impedance
VICR
Common mode input voltage range
Common-mode
PVDD = 5 V
PVDD = 3.3 V
rds(on)
Output on-resistance
on resistance
PVDD = 5 V
PVDD = 3.3 V
η
Efficiency
PVDD = 5 V
PVDD = 3.3 V
Vn
Integrated noise floor
f = 10 Hz to 5 kHz, Gain = 6 dB
MIN
TYP
MAX
1.22
C(AREF) = 1 µF
UNIT
A
70
dB
>15
kΩ
1.2
3.8
1.2
2.1
0.5
0.65
V
Ω
64%
60%
23
µV rms
functional block diagram
VDD
AGND
VDD
PVDD
Gain
Adjust
IN–
_
+
_
Deglitch
Logic
Gate
Drive
OUT–
+
_
+
Gain
Adjust
IN+
PGND
+
_
PVDD
+
_
_
+
Deglitch
Logic
Gate
Drive
OUT+
PGND
SHUTDOWN
SD
GAIN1
GAIN0
2
Gain
Biases
and
References
Ramp
Generator
COSC
ROSC
AREF
4
Start-Up
Protection
Logic
Thermal
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VDD ok
OC
Detect
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Gain and phase
vs Frequency
Efficiency
vs Load resistance
1
PSRR
Power supply rejection ratio
vs Frequency
rds(on)
Small signal drain-source
drain source on-state
on state resistance
Small-signal
IO
Maximum output current
2, 3
4
vs Supply voltage
5, 6
vs Ambient temperature
7, 8
vs Differential output voltage
9
GAIN AND PHASE
vs
FREQUENCY
100
10
72
8
Gain
44
6
16
4
2
–12
0
–40
–2
–68
–4
–6
–8
–10
10
Phase – °
Gain – dBV
Phase
–96
VI = 1.17 Vrms
VDD = 5 V
RL = 2 Ω
100
–124
–152
1k
10k
f – Frequency – Hz
–180
100k
Figure 1
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5
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
TYPICAL CHARACTERISTICS
EFFICIENCY
vs
LOAD RESISTANCE
EFFICIENCY
vs
LOAD RESISTANCE
90
90
VDD = 3.3 V
85
VDD = 5 V
PO = 2 W
85
PO = 0.25 W
80
PO = 1 W
Efficiency – %
Efficiency – %
80
75
PO = 0.5 W
70
65
PO = 0.5 W
75
70
60
65
55
50
60
2
3
4
5
6
7
8
9
2
10
3
RL – Load Resistance – Ω
4
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
PSRR – Power Supply Rejection Ratio – dB
–40
–45
–50
–55
–60
–65
–70
–75
–80
10
100
f – Frequency – Hz
1k
10k
Figure 4
6
6
7
8
9
10
Figure 3
rds(on) – Small-Signal Drain-Source On-State Resistance – Ω
Figure 2
1
5
RL – Load Resistance – Ω
SMALL-SIGNAL DRAIN-SOURCE
ON-STATE RESISTANCE
vs
SUPPLY VOLTAGE
0.8
IO = 0.5 A
0.7
0.6
rds(on) Low Side
0.5
0.4
0.3
2.7
rds(on) High Side
3.1
3.5
3.9
Figure 5
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4.3
4.7
VDD – Supply Voltage – V
5.1
5.5
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
SMALL-SIGNAL DRAIN-SOURCE
ON-STATE RESISTANCE
vs
SUPPLY VOLTAGE
0.9
IO = 1 A
0.8
0.7
0.6
rds(on) Low Side
0.5
rds(on) High Side
0.4
0.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
rds(on) – Small-Signal Drain-Source On-State Resistance – Ω
rds(on) – Small-Signal Drain-Source On-State Resistance – Ω
TYPICAL CHARACTERISTICS
SMALL-SIGNAL DRAIN-SOURCE
ON-STATE RESISTANCE
vs
AMBIENT TEMPERATURE
0.62
IO = 0.5 A
VDD = 5 V
DWP Package
0.58
rds(on) Low Side
0.54
0.50
0.46
rds(on) High Side
0.42
0.38
25
35
45
VDD – Supply Voltage – V
Figure 6
65
75
85
Figure 7
SMALL-SIGNAL DRAIN-SOURCE
ON-STATE RESISTANCE
vs
AMBIENT TEMPERATURE
MAXIMUM OUTPUT CURRENT
vs
DIFFERENTIAL OUTPUT VOLTAGE
1.4
0.62
VDD = 5 V
IO = 1 A
VDD = 3.3 V
DWP Package
0.58
rds(on) Low Side
0.54
0.50
0.46
rds(on) High Side
0.42
0.38
25
35
45
TJ = 89°C
1.2
IO – Maximum Output Current – A
rds(on) – Small-Signal Drain-Source On-State Resistance – Ω
55
TA – Ambient Temperature – °C
55
65
75
85
TA – Ambient Temperature – °C
1.0
TJ = 102°C
0.8
0.6
TJ = 124°C
0.4
0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOD – Differential Output Voltage – V
Figure 8
Figure 9
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7
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
APPLICATION INFORMATION
driving TEC elements
Below is a typical application schematic.
J5
IN– (VCOM)
J4
IN+
C4
1 µF
R1
1 kΩ
J1
R2
1 kΩ
R3
120 kΩ
J8
VDD
R4
120 kΩ
J2
R5
120 kΩ
C3
1 µF
J3
NC
IN+
IN–
SHUTDOWN
GAIN0
GAIN1
PVDD
OUT+
NC
PGND
L1
10 µH
J7
OUT+
C5
10 µF
C6
10 µF
C9
220 pF
NC
AREF
AGND
COSC
ROSC
VDD
PVDD
OUT–
NC
PGND
R6
120 kΩ
J8
VDD
C1
1 µF
C2
1 µF
C8
10 µF
J9
GND
L2
10 µH
C7
10 µF
J6
OUT–
output filter considerations
TEC element manufacturers provide electrical specifications for maximum dc current and maximum output
voltage for each particular element. The maximum ripple current, however, is typically only recommended to
be less than 10%. The maximum temperature differential across the element decreases as ripple current
increases and can be calculated using equation 1.
DT +
( 1 ) N 2)
1
(1)
DT max
∆T = actual temperature differential
∆Tmax = maximum temperature differential (specified by manufacturer)
N = ratio of ripple current to dc current
According to this relationship, a 10% ripple current reduces the maximum temperature differential by 1%. A LC
network may be used to filter the current flowing to the TEC to reduce the amount of ripple and, more importantly,
protect the rest of the system from any electromagnetic interference (EMI).
8
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DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
APPLICATION INFORMATION
driving TEC elements (continued)
filter component selection
The LC filter may be designed from a couple of different perspectives, both of which may help estimate the
overall performance of the system. The filter should be designed for the worst-case conditions during operation,
which is typically when the differential output is at 50% duty cycle. The following section serves as a starting
point for the design, and any calculations should be confirmed with a prototype circuit.
To simplify the design, half-circuit analysis may also be used. This should only be done if the TEC element is
close to the output of the filter. Any filter should always be placed as close to the DRV590 as possible to reduce
EMI.
L
OUT+
C
C
TEC
R
L
OUT+
or
OUT–
OUT–
L
2C
C
TEC
R
2
C
Figure 10. LC Output Filter
Figure 11. LC Half-Circuit Equivalent
LC filter in the frequency domain
The transfer function for the second order low-pass filter in Figure 10 and Figure 11 is shown in equation 2.
H
(jw) +
LP
(2)
1
ǒ Ǔ ) Q1 wjw0 ) 1
– ww
0
2
1
ǸL 3C
Q = quality factor
ω = DRV590 differential switching frequency
w0 +
For the DRV590, the differential output switching frequency is 500 kHz. The resonant frequency for the filter
should be chosen to be at least one order of magnitude lower than the switching frequency. Equation 2 may
then be simplified to give the following magnitude equation 3. These equations assume the use of the filter in
Figure 10, which effectively triples the capacitance.
ǒǓ
ŤHLPŤdB + –40 log
fo +
(3)
fs
fo
1
Ǹ
2p L 3C
fs = 500 kHz (DRV590 differential switching frequency)
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9
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
APPLICATION INFORMATION
LC filter in the frequency domain (continued)
If L = 10 µH and C = 10 µF, the resonant frequency is 9.2 kHz, which corresponds to –69 dB of attenuation at
the 500-kHz switching frequency. For VDD = 5 V, the amount of ripple voltage at the TEC element will be
approximately 1.7 mV.
The average TEC element has a resistance of 1.5 Ω, so the ripple current through the TEC is approximately
1.13 mA. At the 1-A maximum output current of the DRV590, this 1.13 mA corresponds to 0.113% ripple current,
causing less than 0.0001% reduction of the maximum temperature differential of the TEC element (see
equation 1).
LC filter in the time domain
The ripple current of an inductor can be calculated using equation 4.
DI +
L
ǒVDD * VTECǓDTs
(4)
L
D = duty cycle (0.5 worst case)
Ts = 1/fs = 1/500 kHz
For VDD = 5 V, VTEC = 2.5 V, and L = 10 µH, the inductor ripple current is 250 mA. To calculate how much of
that ripple current will flow through the TEC element, however, the properties of the filter capacitor must be
considered.
For relatively small capacitors (less than 10 µF) with very low equivalent series resistance (ESR, less than
10 mΩ), such as ceramic capacitors, equation 5 may be used to estimate the ripple voltage on the capacitor
due to the change in charge.
ǒǓ
f
2
DV + p (1–D) o
C
2
fs
(5)
2
V
TEC
D = duty cycle
fs = 500 kHz
1
fo +
2p ǸL 3C
For L = 10 µH and C = 10 µF, the cutoff frequency fo = 9.2 kHz. For a worst case duty cycle of 0.5 and VTEC
= 2.5, the ripple voltage on the capacitors is 2 mV. The ripple current may be simply calculated by dividing the
ripple voltage by the TEC resistance of 1.5 Ω, resulting in a ripple current through the TEC element of 1.33 mA.
Note that this is similar to the value calculated using the frequency domain approach.
For larger capacitors (greater than 10 µF) with relatively high ESR (greater than 100 mΩ), such as electrolytic
capacitors, the ESR drop dominates over the charging-discharging of the capacitor. Equation 6 can be used
to estimate the ripple voltage.
DV
C
+ DI
L
R
(6)
ESR
∆L = inductor ripple current
RESR = filter capacitor ESR
For a 100-µF electrolytic capacitor, an ESR of 0.1 Ω is common. If the 10-µH inductor is used, delivering 250 mA
of ripple current to the capacitor (as calculated above), then the ripple voltage is 25 mV. This is over ten times
that of the 10-µF ceramic capacitor, as ceramic capacitors typically have negligible ESR.
10
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DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
APPLICATION INFORMATION
LC filter in the time domain (continued)
For worst case conditions, the on-resistance of the output transistors has been ignored to give the maximum
theoretical ripple current. In reality, the voltage drop across the output transistors will decrease the maximum
VO as the output current increases. It can be shown using equation 4 that this will decrease the inductor ripple
current, and therefore the TEC ripple current.
general operation
oscillator components ROSC and COSC
The onboard ramp generator requires an external resistor and capacitor to set the oscillation frequency. For
proper operation, the resistor ROSC should be 120 kΩ with 1% tolerance. The capacitor COSC should be a
ceramic 220 pF with 10% tolerance. Both components should be grounded to AGND, which should be
connected to PGND at a single point, typically where the power and ground physically connect to the printed
circuit board.
AREF capacitor
The AREF terminal is the output of an internal mid-rail voltage regulator used for the on-board oscillator and
ramp generator. The regulator may not be used to provide power to any additional circuitry. A 1-µF ceramic
capacitor must be connected from AREF to AGND for stability (see the oscillator components ROSC and COSC
section for AGND connection information).
gain settings
The differential output voltage may be calculated using equation 7.
V
O
+V
ǒ
Ǔ
–V
–V
+ Av V
IN) IN–
OUT) OUT–
(7)
Av is the voltage gain, which may be selected by configuring GAIN0 and GAIN1 according to the table below.
The input resistance also varies with the gain setting, as shown by the typical values in Table 1. Though these
values may vary by up to 30% due to process variations, the gain settings themselves vary little, as they are
determined by resistor ratios.
Table 1. Gain Settings
GAIN0
GAIN1
AMPLIFIER GAIN
(dB, TYPICAL)
INPUT RESISTANCE
(kΩ, TYPICAL)
0
0
0
6
104
1
12
74
1
1
0
18
44
1
23.5
24
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11
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
APPLICATION INFORMATION
general operation (continued)
input configuration—differential and single-ended
If a differential input is used, it should be biased around the mid-rail of the DRV590 and must not exceed the
common-mode input range of the input stage (see the operating characteristics at the beginning of the data
sheet).
The most common configuration employs a single-ended input. The unused input should be tied to the mid-rail,
which may be simply accomplished with a resistive voltage divider. For the best performance, the resistor values
chosen should be at least an order of magnitude lower than the input resistance of the DRV590 at the selected
gain setting. This prevents the bias voltage at the unused input from shifting when the signal input is applied.
A small ceramic capacitor should also be placed from the input to ground to filter noise and keep the voltage
stable.
power supply decoupling
To reduce the effects of high-frequency transients or spikes, a small ceramic capacitor, typically 0.1 µF to 1 µF,
should be placed as close to each PVDD pin of the DRV590 as possible. For bulk decoupling, a 10-µF to 100-µF
tantalum or aluminum electrolytic capacitor should be placed relatively close to the DRV590.
SHUTDOWN operation
The DRV590 includes a shutdown mode that disables the outputs and places the device in a low supply current
state. The SHUTDOWN pin may be controlled with a TTL logic signal. When SHUTDOWN is held high, the
device operates normally. When SHUTDOWN is held low, the device is placed in shutdown. The SHUTDOWN
pin must not be left floating. If the shutdown feature is unused, the pin may simply be connected to VDD.
power dissipation and maximum ambient temperature
Though the DRV590 is much more efficient than traditional linear solutions, the IR drop across the on-resistance
of the output transistors generates some heat in the package, which may be calculated using equation 8.
P
DISS
ǒ OUTǓ
+ I
2
r
ds(on), total
(8)
For example, at the maximum output current of 1.2 A through a total on-resistance of 1 Ω, the power dissipated
in the package is 1.44 W.
The maximum ambient temperature can be calculated using equation 9.
ǒ
T +T q
A
J JA
P
Ǔ
DISS
(9)
Continuing the example above, the maximum ambient temperature driving 1.2 A without exceeding 89°C
junction temperature for a DRV590 in the DWP package (see the maximum output current vs duty cycle section)
is 39°C.
maximum output current vs duty cycle
At 100% duty cycle across the load, the reliability of the DRV590 is degraded if more than 1 A is driven through
the outputs. Furthermore, the junction temperature must not exceed 89°C at the maximum output current levels
to prevent further degradation. However, as the duty cycle across the load decreases, the maximum allowable
output current increases.
Table 2 shows the typical maximum output current, voltage across the load, and junction temperature versus
duty cycle. The dissipation and junction temperatures were calculated using equations 8 and 9. The total
on-resistance was assumed to be 1 Ω, the ambient temperature to be 25°C, and the θJA to be 34.1°C/W.
12
www.ti.com
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
APPLICATION INFORMATION
maximum output current vs duty cycle (continued)
Table 2. Typical Maximum Output Specifications vs Duty Cycle (VDD = 5 V)
DUTY CYCLE
MAX IO (A)
MAX VLOAD (V)
100%
1
4
PDISS (W)
1
TJ (°C)
67.6
95%
1.05
90%
1.11
3.69
1.11
72.2
3.38
1.24
77.6
85%
84%
1.17
3.07
1.39
83.9
1.19
3.01
1.42
85.3
83%
1.2
2.94
1.45
86.8
82%
1.22
2.88
1.49
88.3
At duty cycles less than 82%, the power dissipated from the theoretical maximum current flowing through the
on-resistance causes the junction temperature to exceed 89°C. See Figure 9 for more details.
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13
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV590GQCR
OBSOLETE
BGA
MICROSTAR
JUNIOR
GQC
48
TBD
Call TI
Call TI
-40 to 85
DRV590
DRV590ZQCR
OBSOLETE
BGA
MICROSTAR
JUNIOR
ZQC
48
TBD
Call TI
Call TI
-40 to 85
DRV590
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jun-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPLG008D – APRIL 2000 – REVISED FEBRUARY 2002
GQC (S-PBGA-N48)
PLASTIC BALL GRID ARRAY
4,10
3,90
SQ
3,00 TYP
0,50
G
F
0,50
E
D
3,00 TYP
C
B
A
1
A1 Corner
2
3
4
5
6
7
Bottom View
0,77
0,71
1,00 MAX
Seating Plane
0,35
0,25
0,25
0,05 M
0,08
0,15
4200460/E 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar Junior  BGA configuration
Falls within JEDEC MO-225
MicroStar Junior is a trademark of Texas Instruments.
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• DALLAS, TEXAS 75265
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