Infineon BTS5566G Spi power controller Datasheet

Data Sheet, Rev. 1.3, October 2007
SPOC - BTS5566G
SPI Power Controller
Automotive Power
SPI Power Controller
SPOC - BTS5566G
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
2.1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Assignment SPOC - BTS5566G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
4.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
5.1
5.2
5.3
5.4
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
13
14
15
6
6.1
6.2
6.3
6.4
6.5
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
17
18
20
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Vbb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
22
22
22
22
23
24
8
8.1
8.2
8.3
8.4
8.5
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch Bypass Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
26
26
28
29
31
9
9.1
9.2
9.3
9.4
9.5
9.6
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
32
33
33
34
36
37
10
Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11
Package Outlines SPOC - BTS5566G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data Sheet
2
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
for Advanced Light Control
1
Overview
The SPOC - BTS5566G is a five channel high-side smart power switch in
PG-DSO-36-34 package providing embedded protective functions. It is
especially designed to control standard exterior lighting in automotive
applications. It is designed to drive lamps up to 3*27W + 2*10W.
Configuration and status diagnosis is done via SPI. Additionally, there is
a current sense signal available for each channel that is routed via a
multiplexer to a single diagnosis pin.
The SPOC - BTS5566G provides a fail-safe function via limp home input
pin.
PG-DSO-36-34
Product Summary
Operating Voltage Power Switch
Logic Supply Voltage
Over Voltage Protection
Maximum Stand-By Current at 25 °C
On-State Resistance at Tj = 150 °
channel 0, 1
channel 2
channel 3,4
SPI Access Frequency
VBB
VDD
VBB(AZ,min)
IBB(OFF)
RDS(ON) max
fSCLK(max)
Package
Marking
SPOC - BTS5566G
PG-DSO-36-34
BTS5566G
3
3.8 … 5.5 V
40 V
3 µA
49 mΩ
64 mΩ
180 mΩ
Type
Data Sheet
4.5 … 28 V
2 MHz
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Overview
Basic Features
•
•
•
•
•
•
•
•
•
8 bit serial peripheral interface (daisy chain capable SPI) for control and diagnostics
CMOS compatible parallel input pins for each channel provide straightforward PWM operation
Selectable AND- / OR-combination for parallel inputs (PWM control)
Very low stand-by current
Optimized electromagnetic compatibility (EMC) for bulbs
Stable behavior at under voltage
Device ground independent from load ground
Green Product (RoHS-Compliant)
AEC Qualified
Protective Functions
•
•
•
•
•
•
•
•
Reverse battery protection with external components
Short circuit protection
Over load protection
Multi step current limitation
Thermal shutdown with latch
Over voltage protection
Loss of ground protection
Electrostatic discharge protection (ESD)
Diagnostic Functions
•
•
•
•
•
Multiplexed proportional load current sense signals (IS)
Enable function for current sense signal configurable via SPI
High accuracy of current sense signal at wide load current range
Feedback on over temperature and over load via SPI
Multiplexed switch bypass monitor provides short circuit to Vbb detection
Application Specific Functions
•
Fail-safe activation via LHI pin and configuration via input pins
Applications
•
•
•
High-side power switch for 12 V grounded loads in automotive application
Especially designed for standard exterior lighting like tail light, brake light, reverse light, parking light, license
plate lighting and turn signal indicators
Replaces electromechanical relays, fuses and discrete circuits
Data Sheet
4
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Overview
watchdog
fail safe system
limp home control
limp home control
SPOC - BTS5566G
SPOC - BTS5566G
180 mΩ 49 mΩ
49 mΩ
BL
64 mΩ
180 mΩ
RL
IND
180 mΩ 64 mΩ
LIC
SPOC
TL
RL
49 mΩ
49 mΩ
180 mΩ
BL
IND
TL
Application rear .emf
Figure 1
Application Example
Abbreviations:
BL
RL
TL
LIC
IND
Data Sheet
Brake Light (21 W, 27 W)
Reverse Light (21 W, 27 W)
Tail Light (5 W, 7 W, 10 W)
License plate lighting (5 W, 10 W)
Indicator / Flasher (21 W, 27 W)
5
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Block Diagram
2
Block Diagram
The SPOC - BTS5566G is a five channel high-side power switch in PG-DSO-36-34 package providing embedded
protective functions. An 8 bit serial peripheral interface (SPI) is used for configuration and diagnosis. The SPI can
be used in daisy chain configuration.
The device provides a current sense signal per channel that is multiplexed to the diagnosis pin IS. It can be
enabled and disabled via SPI commands. An over load and over temperature flag is provided in the SPI diagnosis
word. A multiplexed switch bypass monitor provides diagnosis at short-circuit to VBB.
The power transistors are built by N-channel vertical power MOSFETs with charge pumps. The device is
monolithically integrated in SMART SIPMOS technology.
VBB
power
supply
IN0
temperature
sensor
driver
logic
IN1
IN2
IN3
gate control
&
charge pump
load current
sense
IN4
clamp for
inductive
load
load current
limitation
channel 0
IS
LHI
ESD
protection
current sense multiplexer
switch bypass
monitor
limp home control
PWM control
OUT4
34
12
OUT3
OUT2
OUT1
OUT0
CS
SCLK
SO
SPI
SI
GND
Figure 2
Data Sheet
Block Diagram SPOC - BTS5566G
6
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Block Diagram
2.1
Terms
The following figure shows all terms used in this data sheet.
VBB
IBB
IIN 0
IIN 1
VIN 0
IIN 2
VIN 1
IIN 3
VIN 2
IIN 4
VIN 3
VIN 4
ID D
ISO
Vdd
I SI
VSO
IC S
VSI
ISC LK
VC S
VSC LK
I IS
VIS
ILH I
VBB
IN0
IN1
IN2
OUT0
I L0
VD S0
VOU T0
IN3
IN4
OUT1
I L1
VD S1
VOU T1
VDD
OUT2
SO
I L2
VD S2
VOU T2
SI
OUT3
CS
I L3
VD S3
VOU T3
SCLK
OUT4
I L4
VD S4
VOU T4
IS
LHI
VLH I
GND
IGN D
Figure 3
Terms
In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each
channel separately (e.g. VDS specification is valid for VDS0 … VDS4).
All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.CTL). In SPI register description, the
values in bold letters (e.g. 0) are default values.
Data Sheet
7
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment SPOC - BTS5566G
(top view)
VBB
GND
VDD
SO
SI
SCLK
CS
IN0
IN1
IN2
IN3
IN4
IS
LHI
n.c.
VBB
n.c.
VBB
Figure 4
Data Sheet
1
36
2
35
3
4
34
33
5
32
6
31
7
30
8
9
29
28
10
27
11
26
12
25
13
14
24
23
15
22
16
21
17
20
18
19
VBB
OUT0
OUT0
OUT0
OUT0
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
VBB
Pin Configuration PG-DSO-36-34
8
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
I/O Function
1, 16, 18, 19, 36 1)
VBB
–
Positive power supply for high-side power switch and limp home block
3
VDD
–
Logic supply (5 V)
2
GND
–
Ground connection
IN0
I
Input signal of channel 0
9
IN1
I
Input signal of channel 1
10
IN2
I
Input signal of channel 2
11
IN3
I
Input signal of channel 3
12
IN4
I
Input signal of channel 4
Power Supply Pins
Parallel Input Pins
8
Power Output Pins
32, 33, 34, 35 2)
OUT0
O
Protected high-side power output of channel 0
28, 29,30, 31
2)
OUT1
O
Protected high-side power output of channel 1
24, 25,26, 27
2)
OUT2
O
Protected high-side power output of channel 2
2)
OUT3
O
Protected high-side power output of channel 3
20, 21 2)
OUT4
O
Protected high-side power output of channel 4
7
CS
I
Chip select of SPI interface (low active)
6
SCLK
I
Serial clock of SPI interface
5
SI
I
Serial input of SPI interface
4
SO
O
Serial output of SPI interface
13
IS
O
Diagnosis output signal
LHI
I
Limp home mode activation
n.c.
–
not connected, floating
22, 23
SPI & Diagnosis Pins
Limp Home Pins
14
Other Pins
15, 17
1) All VBB pins have to be connected.
2) All output pins of each channel have to be connected.
Data Sheet
9
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Electrical Characteristics
4
Electrical Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin.
(unless otherwise specified).
Pos.
Parameter
Symbol
Limit Values
min.
Unit
Conditions
max.
Supply Voltage
4.1.1
Power supply voltage
VBB
-0.3
28
V
–
4.1.2
Logic supply voltage
VDD
-0.3
5.5
V
–
4.1.3
Reverse polarity voltage according Figure 23
-VBAT(rev)
–
16
V
TjStart = 25 °C
t ≤ 2 min 2)
4.1.4
Supply voltage for full short circuit protection (single VBB(SC)
pulse)
(Tj(0) = -40 °C … 150 °C)
0
20
V
RECU = 20mΩ
RCable=
16mΩ/m
LCable= 1µH/m
l = 0 or 5m 3)
4.1.5
Voltage at power transistor
VDS
–
54
V
–
4.1.6
Supply Voltage for Load Dump protection
VBB(LD)
–
41
V
RI = 2 Ω 4)
t = 400ms
4.1.7
Current through ground pin
IGND
-100
25
mA
t ≤ 2 min
4.1.8
Current through VDD pin
IDD
-25
12
mA
t ≤ 2 min
IL
-IL(LIM)
IL(LIM)
A
5)
IIS
-10
10
mA
t ≤ 2 min
4.1.11 Voltage at input pins
VIN
-0.3
8.0
V
–
4.1.12 Current through input pins
IIN
-0.75
-2.0
0.75
2.0
mA
–
t ≤ 2 min
4.1.13 Voltage at chip select pin
VCS
-0.3
5.7
V
–
4.1.14 Current through chip select pin
ICS
-2.0
2.0
mA
t ≤ 2 min
4.1.15 Voltage at serial input pin
VSI
-0.3
5.7
V
–
4.1.16 Current through serial input pin
ISI
-2.0
2.0
mA
t ≤ 2 min
4.1.17 Voltage at serial clock pin
VSCLK
-0.3
5.7
V
–
4.1.18 Current through serial clock pin
ISCLK
-2.0
2.0
mA
t ≤ 2 min
4.1.19 Current through serial output pin SO
ISO
-2.0
2.0
mA
t ≤ 2 min
4.1.20 Voltage at limp home input pin
VLHI
-0.3
8.0
V
–
4.1.21 Current through limp home input pin
ILHI
-0.75
-2.0
0.75
2.0
mA
–
t ≤ 2 min
Power Stages
4.1.9
Load current
Diagnosis Pin
4.1.10 Current through sense pin IS
Input Pins
SPI Pins
Limp Home Pins
Data Sheet
10
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Electrical Characteristics
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin.
(unless otherwise specified).
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
min.
max.
-40
150
°C
–
–
60
K
–
-55
150
°C
–
kV
HBM6)
–
–
Temperatures
4.1.22 Junction temperature
Tj
4.1.23 Dynamic temperature increase while switching
∆Tj
4.1.24 Storage temperature
TSTG
ESD Susceptibility
4.1.25 ESD resistivity HBM
VESD
OUT pins
other pins
-4
-2
4
2
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
3) In accordance to AEC Q100-012 and AEC Q101-006.
4) RI is the internal resistance of the load dump pulse generator.
5) Current limitation is a protection feature. Operation in current limitation is considered as “outside” normal operating range.
Protection features are not designed for continuous repetitive operation.
6) ESD resistivity, HBM according to EIA/JESD 22-A 114B (1.5kΩ, 100pF).
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
11
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Supply
5
Power Supply
The SPOC - BTS5566G is supplied by two supply voltages VBB and VDD. The VBB supply line is used by the power
switches. The VDD supply line is used by the SPI related circuitry and for driving the SO line. A capacitor between
pins VDD and GND is recommended.
There is a power-on reset function implemented for the VDD logic supply voltage. After start-up of the logic power
supply, all SPI registers are reset to their default values. The SPI interface including daisy chain function is active
as soon as VDD is provided in the specified range independent of VBB.
5.1
Power Supply Modes
The following table shows all possible power supply modes for VBB, VDD and the pin LHI.
Power Supply Modes
VBB
0V
0V
0V
0V
13.5 V
13.5 V
13.5 V
13.5 V
VDD
0V
0V
5V
5V
0V
0V
5V
5V
LHI
0V
5V
0V
5V
0V
5V
0V
5V
PROFET operating
–
–
–
–
✓
✓
✓
✓
Limp home mode
–
–
–
–
–
✓
–
✓
SPI (logic)
reset
reset
✓
✓
reset
reset
✓
reset
Stand-by current
–
–
–
–
✓
–
–
Idle current
–
–
–
–
–
–
✓
Diagnosis
–
–
–
–
–
–
✓
–
1)
–
✓ 2)
1) When all channels are in OFF-state and all SPI registers are at default values.
2) Current sense diagnosis not available in limp home mode.
To achieve stand-by mode, the limp home block must be disabled (LHI = 0 V), all channels must be switched off
and the thermal latches have to be cleared. As a result the stand-by current IBB(OFF) is valid as listed. In case of
active VDD supply, the idle mode parameters are valid only, when additionally all SPI registers are at default values
(see Section 9.6) e.g. after a reset command.
Data Sheet
12
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Supply
5.2
Reset
There are several reset trigger implemented in the device. They reset the SPI registers to their default values. The
power stages as well as the analog watchdog block are not affected by the reset signals.
The first SPI transmission after any kind of reset contains at pin SO the read information from register OUT, and
the transmission error bit TER is set.
Power-On Reset
The power-on reset is released, when VDD voltage level is higher than VDD(PO). The SPI interface can be accessed
after wake up time tWU(PO).
Reset Command
There is a reset command available to reset all register bits of the register bank and the diagnosis registers. As
soon as HWCR.RST = 1, a reset is triggered equivalent to power-on reset. The SPI interface can be accessed after
transfer delay time tCS(td).
Limp Home Mode
In limp home mode, the SPI write-registers are reset. The SPI interface is operating normally, so the limp home
register bit LHI as well as the error flags can be read.
Data Sheet
13
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Supply
5.3
Electrical Characteristics
Electrical Characteristics Power Supply
Unless otherwise specified: VBB = 9 V to 16 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °C.
typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C.
Pos.
Parameter
Symbol
5.3.1
Operating voltage
5.3.2
Stand-by current for whole device with
loads
VBB
IBB(OFF)
Limit Values
min.
typ.
max.
4.5
–
28
–
–
–
1.2
–
–
5.3.3
Logic supply voltage
5.3.4
Logic supply current
VDD
IDD
5.3.5
Logic idle current
5.3.6
Operating current for whole device
5.3.7
Power-On reset threshold voltage
5.3.8
Power-On wake up time
–
–
–
Test Conditions
V
–
µA
VDD = 0 V
VLHI = 0 V
VIN = 0 V
Tj = 25 °C
Tj ≤ 85 °C 1)
Tj = 150 °C
µA
VDD = 5 V
VLHI = 0 V
VIN = 0 V
Tj = 25 °C
Tj ≤ 85 °C 1)
Tj = 150 °C
3
3
50
Idle current for whole device with loads IBB(idle)
–
–
–
Unit
3
3
50
3.8
–
5.5
V
–
–
45
150
µA
VCS = 0 V
fSCLK = 0 Hz
IDD(idle)
–
15
35
µA
VCS = Vdd
fSCLK = 0 Hz
IGND
VDD(PO)
tWU(PO)
–
10
20
mA
fSCLK = 0 Hz
–
–
3.8
V
–
–
–
500
µs
–
1) Not subject to production test, specified by design.
Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical
values show the typical parameters expected from manufacturing at VBB = 13.5 V, VDD = 4.3 V and Tj = 25 °C.
Data Sheet
14
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Supply
5.4
Command Description
HWCR
Hardware Configuration Register
W/R
4
3
2
1
0
read
RST
0
SBM
PWM
CTL
write
RST
0
0
PWM
CTL
Field
RST
RST
Data Sheet
Bits
Type Description
4
r
Reset Command
0
Normal operation
1
Device in reset due to limp home mode
4
w
Reset Command
0
Normal operation
1
Execute reset command
15
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Stages
6
Power Stages
The high-side power stages are built by N-channel vertical power MOSFETs (DMOS) with charge pumps. There
are five channels implemented in the device. Each channel can be switched on via an input pin or via SPI register
OUT.
6.1
Output ON-State Resistance
The on-state resistance RDS(ON) depends on the supply voltage VBB as well as on the junction temperature Tj.
Figure 5 shows those dependencies. The behavior in reverse polarity mode is described in Section 7.3.
Tj = 25 °C
Vbb = 13.5 V
250
channel 0, 1 (bulb)
channel 2 (bulb)
channel 3, 4
150
100
50
0
-50 -25
channel 0, 1 (bulb)
channel 2 (bulb)
channel 3, 4
250
RDS(ON) /mΩ
RDS(ON) /mΩ
200
200
150
100
50
0
25
50 75 100 125 150
T /°C
Figure 5
Typical On-State Resistance
6.2
Input Circuit
0
5
10
15
Vbb /V
20
25
There are two ways of using the input pins in combination with the OUT SPI register by programming the
HWCR.PWM parameter.
•
•
HWCR.PWM = 0: A channel is switched on either by the according OUT register bit or the input pin.
HWCR.PWM = 1: A channel is switched on by the according OUT register bit only, when the input pin is high. In this
configuration, a PWM signal can be given to the input pin and the channel is activated by the SPI register OUT.
Figure 6 shows the complete input switch matrix.
OUT4
OUT3
OUT2
OUT1
OUT0
OR
IN0
IIN0
&
OR
IN1
IIN1
&
OR
IN2
IIN2
&
OR
IN3
IIN3
OR
IIN4
Gate Driver 1
Gate Driver 2
Gate Driver 3
&
IN4
Gate Driver 0
Gate Driver 4
&
PWM
InputMatrix.emf
Figure 6
Input Switch Matrix
The current sink to ground at the input pins ensures that the input signal is low in case of an open input pin. The
zener diode protects the input circuit against ESD pulses.
Data Sheet
16
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Stages
6.3
Power Stage Output
The power stages are built to be used in high side configuration (Figure 7).
VBB
V ON
V bb
OUT
GND
V OUT
Output.emf
Figure 7
Power Stage Output
The power DMOS switches with a dedicated slope, which is optimized in terms of EMC emission.
IN
VOUT
tON
tOFF
t
90%
70%
30%
70%
dV /
dtOFF
dV /
dtON
30%
10%
t
Figure 8
SwitchOn.emf
Switching a Load (resistive)
When switching off inductive loads with high-side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent destruction of the device, there is a
voltage clamp mechanism implemented that limits that negative output voltage to a certain level (VON(CL) (6.4.3)).
See Figure 7 for details. The maximum allowed load inductance is limited.
Data Sheet
17
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Stages
6.4
Electrical Characteristics
Electrical Characteristic Power Stages
Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C.
typical values: VBB = 13.5 V, Tj = 25 °C.
Pos. Parameter
Symbol
Limit Values
min.
typ.
Unit Test Conditions
max.
Output Characteristics
RDS(ON)
6.4.1 On-State resistance
mΩ
channel 0, 1
–
–
22.3
38
–
49
1)
channel 2
–
–
25.2
49
–
64
1)
channel 3, 4
–
–
72.9
141
–
180
1)
6.4.2 Output voltage drop limitation at
small load currents
VDS(NL)
Tj = 25 °, IL = 2.6 A
Tj = 150 °, IL = 2.6 A
Tj = 25 °C, IL = 2.6 A
Tj = 150 °C, IL = 2.6 A
Tj = 25 °C, IL = 1 A
Tj = 150 °C,IL = 1 A
mV
channel 0, 1, 2
–
35
–
IL = 35 mA
channel 3, 4
–
35
–
IL = 35 mA
40
47
54
6.4.3 Output clamp
6.4.4 Output leakage current per
channel
VON(CL)
IL(OFF)
V
IL = 20 mA
µA
VIN = 0 V
OUT.OUTn = 0
channel 0, 1
–
–
0.1
–
10
40
stand-by
not stand-by
channel 2
–
–
0.1
–
10
40
stand-by
not stand-by
channel 3, 4
–
–
0.1
–
8
40
stand-by
not stand-by
6.4.5 Inverse current capability per
channel
-IL(IC)
A
No influence on
functionality of
unaffected channels 1)
channel 0, 1, 2
–
2.5
–
–
channel 3, 4
–
1.0
–
–
RthJC
RthJA
–
–
20
K/W
1)
–
40
–
K/W
1) 2)
VIN(L)
VIN(H)
IIN(L)
IIN(H)
-0.3
–
1.0
V
–
2.6
–
5.5
V
–
3
25
75
µA
VIN = 0.4 V
10
40
75
µA
VIN = 5 V
Thermal Resistance
6.4.6 Junction to Case
6.4.7 Junction to Ambient, all channels
active
Input Characteristics
6.4.8 L-input level
6.4.9 H-input level
6.4.10 L-input current
6.4.11 H-input current
Data Sheet
18
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Stages
Electrical Characteristic Power Stages
Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C.
typical values: VBB = 13.5 V, Tj = 25 °C.
Pos. Parameter
Symbol
Limit Values
min.
typ.
Unit Test Conditions
max.
Timings
6.4.12 Turn-on time to 90% VBB
µs
tON
VBB = 13.5 V
channel 0, 1, 2
–
–
250
RL = 6.8 Ω
channel 3, 4
–
–
250
RL = 18 Ω
6.4.13 Turn-off time to 10% VBB
µs
tOFF
VBB = 13.5 V
channel 0, 1, 2
–
–
290
RL = 6.8 Ω
channel 3, 4
–
–
290
RL = 18 Ω
6.4.14 Turn-on slew rate 30% to 70% VBB dV/ dtON
V/µs VBB = 13.5 V
channel 0, 1, 2
0.1
–
0.5
channel 3, 4
0.1
–
0.5
6.4.15 Turn-off slew rate 70% to 30% VBB -dV/ dtOFF
RL = 6.8 Ω
RL = 18 Ω
V/µs VBB = 13.5 V
channel 0, 1, 2
0.1
–
0.5
RL = 6.8 Ω
channel 3, 4
0.1
–
0.5
RL = 18 Ω
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Data Sheet
19
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Stages
6.5
Command Description
OUT
Output Configuration Registers
W/R
RB
5
4
3
2
1
0
read/write
0
0
OUT4
OUT3
OUT2
OUT1
OUT0
Field
Bits
Type
Description
OUTn
n = 4 to 0
n
r/w
Set Output Mode for Channel n
0
Channel n is switched off
1
Channel n is switched on
HWCR
Hardware Configuration Register
W/R
4
3
2
1
0
read
RST
0
SBM
PWM
CTL
write
RST
0
0
PWM
CTL
Field
Bits
Type
Description
PWM
1
rw
PWM Configuration
0
Input signal OR-combined with according OUT register bit
1
Input signal AND-combined with according OUT register bit
Data Sheet
20
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Protection Functions
7
Protection Functions
The device provides embedded protective functions, which are designed to prevent IC destruction under fault
conditions described in this data sheet. Fault conditions are considered as “outside” normal operating range.
Protective functions are neither designed for continuous nor for repetitive operation.
7.1
Over Load Protection
The load current IL is limited by the device itself in case of over load or short circuit to ground. There are multiple
steps of current limitation which are selected automatically depending on the voltage VDS across the power DMOS.
Please note that the voltage at the OUT pin is VBB - VDS. Please refer to following figures for details.
IL
25
20
15
10
5
5
10
15
20
25
V DS
CurrentLimitation01.emf
Figure 9
Current Limitation Channels 0, 1 (minimum values)
IL
25
20
15
10
5
5
10
15
20
25
V DS
CurrentLimitation2.emf
Figure 10
Current Limitation Channels 2 (minimum values)
IL
12
10
8
6
4
2
5
10
15
20
25
V DS
CurrentLimitation34.emf
Figure 11
Current Limitation Channels 3, 4 (minimum values)
Current limitation to the value IL(LIM) is realized by increasing the resistance of the output channel, which leads to
rapid temperature rise inside.
Data Sheet
21
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Protection Functions
7.2
Over Temperature Protection
A temperature sensor for each channel causes an overheated channel to switch off latched to prevent destruction
( also even in case of VDD = 0V). All over temperature latches are cleared by SPI command HWCR.CTL = 1.
IN
t
IL
IL(LIM)
t
IIS
t
ERR
CTL = 1
Figure 12
Shut Down by Over Temperature
7.3
Reverse Polarity Protection
t
OverLoad.emf
In reverse polarity mode, power dissipation is caused by the intrinsic body diode of each DMOS channel as well
as each ESD diode of the logic pins. The reverse current through the channels has to be limited by the connected
loads. The current trough the ground pin, sense pin IS, the logic power supply pin VDD, the SPI pins and the
watchdog pins has to be limited as well (please refer to the maximum ratings listed on Page 10).
Note: No other protection mechanism such as temperature protection or current limitation is active during reverse
polarity.
7.4
Over Voltage Protection
In addition to the output clamp for inductive loads as described in Section 6.3, there is a clamp mechanism
available for over voltage protection. The current through the ground connection has to be limited during over
voltage. Please note that in case of over voltage the pin GND may have a high voltage offset to the module ground.
7.5
Loss of Ground
In case of complete loss of the device ground connections, but connected load ground, the SPOC - BTS5566G
securely changes to or stays in off-state.
7.6
Loss of Vbb
In case of loss of Vbb connection in on-state, all inductance of the loads has to be demagnetized through the
ground connection or through an additional path from VBB to ground. When a diode is used in the ground path for
reverse polarity reasons, the ground connection is not available for demagnetization. Then for example, a resistor
can be placed in parallel to the diode or a suppressor diode can be used between VBB and GND.
Data Sheet
22
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Protection Functions
7.7
Electrical Characteristics
Electrical Characteristics Protection Functions
Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C
typical values: VBB = 13.5 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
min.
typ.
max.
24
–
481)
–
–
1)
–
1)
–
1)
–
1)
–
Over Load Protection
IL(LIM)
7.7.1 Load current limitation
A
channel 0
channel 1
24
channel 2
24
channel 3
12
channel 4
7.7.2 Initial short circuit shut down time
12
–
–
–
48
48
27
27
µs
tOFF(SC)
channel 0, 1
–
550
VDS = 7 V
TjStart = 25 °C 1)
–
–
channel 2
–
400
–
–
channel 3, 4
–
400
–
–
150
1701)
–
°C
–
–
7
–
K
1)
mV
Tj = 150 °C
Over Temperature Protection
7.7.3 Thermal shut down temperature
Tj(SC)
7.7.4 Thermal hysteresis
∆ Tj
Reverse Battery
-VDS(rev)
7.7.5 Drain-Source diode voltage
(VOUT > Vbb)
channel 0, 1
–
600
–
IL = -2.5 A
channel 2
–
620
–
IL = -2.5 A
channel 3, 4
–
600
–
IL = -1 A
VBB(AZ)
40
47
54
V
IBB = 4 mA
IL(GND)
–
–
1
mA
1)
Over Voltage
7.7.6 Overvoltage protection
Loss of GND protection
7.7.7 Output current while GND
disconnected
1) Not subject to production test, specified by design.
Data Sheet
23
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Protection Functions
7.8
Command Description
HWCR
Hardware Configuration Register
W/R
4
3
2
1
0
read
RST
0
SBM
PWM
CTL
write
RST
0
0
PWM
CTL
Field
Bits
Type Description
CTL
0
rw
Data Sheet
Clear Thermal Latch
0
Thermal latches are untouched
1
Command: Clear all thermal latches
24
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Diagnosis
8
Diagnosis
For diagnosis purpose, the SPOC - BTS5566G provides a current sense signal and the diagnosis word at SPI.
There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled
by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery
voltage.
Please refer to Figure 13 for details.
VBB
IIS 0
latch
temperature
sensor
T
gate
control
OR
OUT4
OUT3
OUT2
load current
limitation
OUT1
OUT0
latch
load
current
sense
ERR0
channel 0
VBB
DCR.MUX
VDS (S B )
HWCR.
SBM
current sense multiplexer
IS
R IS
Diagnosis.emf
Figure 13
Block Diagram: Diagnosis
For diagnosis feedback at different operation modes, please see following table.
Table 1
Operation Modes 1)
Operation Mode
Normal Operation (OFF)
Short Circuit to GND
Input Level
OUT.OUTn
L/0
(OFF-state)
Output Level
VOUT
Current
Sense IIS
Error Flag
ERRn2)
HWCR.
SBM
GND
Z
0
1
GND
Z
0
1
Over Temperature
Z
Z
0
x
Short Circuit to VBB
VBB
Z
0
0
Z
Z
0
x
~VBB
IL / kILIS
0
0
< VBB
Z
1
x
~GND
Z
1
1
Open Load
Normal Operation (ON)
Current Limitation
Short Circuit to GND
H/1
(ON-state)
3)
Over Temperature
Z
Z
1
Short Circuit to VBB
VBB
< IL / kILIS
0
0
Open Load
VBB
Z
0
0
x
1) L = low level, H = high level, Z = high impedance, potential depends on leakage currents and external circuit x = undefined
2) The error flags are latched until they are transmitted in the standard diagnosis word via SPI
3) The over temperature flag is set latched and can be cleared by SPI command HWCR.CTL
Data Sheet
25
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Diagnosis
8.1
Diagnosis Word at SPI
The standard diagnosis at the SPI interface provides information about each channel. The error flags, an OR
combination of the over temperature flags and the over load monitoring signals are provided in the SPI standard
diagnosis bits ERRn.
The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is
transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal.
The over temperature flags, which cause an overheated channel to stay switched off, are latched directly at the
gate control block. The latches are cleared by SPI command HWCR.CTL.
Please note:
The over temperature information is latched twice. When transmitting a clear thermal latch command (HWCR.CLT),
the error flag is cleared during command transmission of the next SPI frame and ready for latching after the third
raising edge of the SCLK signal. As a result, the first standard diagnosis information after a CTL command will
indicate a failure mode at the previously affected channels although the thermal latches have been cleared
already. In case of continuous over load, the error flags are set again immediately because of the over load
monitoring signal.
In case of high duty cyle (off state of output < toff-state_min) the VDS might not be equal to VDD during the off state of
the power Mosfet. The over load monitoring signals might be set and latched in the error flags. See Application
Note “Software Strategy for Diagnosis during PWM-Operation“ for more details.
8.2
Load Current Sense Diagnosis
There is a current sense signal available at pin IS which provides a current proportional to the load current of one
selected channel. The selection is done by a multiplexer which is configured via SPI.
The current sense signal (ratio kILIS = IL / IS) is provided as long as no failure mode occurs. Usually a resistor RIS is
connected from the current sense pin to GND. It is recommended to use resistors 2.5 kΩ <RIS < 7 kΩ. A typical
value is 3.3 kΩ.
6000
dummy
Tj = 150°C
dummy
Tj = -40°C
5000
kILIS
4000
3000
2000
1000
0
Figure 14
0.5
1
1.5
2
2.5
3
3.5
IL0,1 /A
4
4.5
5
5.5
6
Current Sense Ratio kILIS Channel 0,1 1)
1) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in
Section 8.4 (Position 8.4.1).
Data Sheet
26
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Diagnosis
6000
dummy
bulb: Tj = 150°C
dummy
bulb: Tj = -40°C
5000
kILIS
4000
3000
2000
1000
0
Figure 15
0.5
1
1.5
2
IL2 /A
2.5
3
3.5
4
Current Sense Ratio kILIS Channel 2 1)
Figure 16
dummy
Tj = 150°C
dummy
Tj = -40°C
3000
kILIS
2500
2000
1500
1000
500
0
0.5
1
IL3,4 /A
1.5
2
Current Sense Ratio kILIS Channel 3, 4 1)
In case of over current as well as over temperature, the current sense signal of the affected channel is switched
off. To distinguish between over temperature and over load, the SPI diagnosis word can be used. Whereas the
over load flag is cleared every time the diagnosis is transmitted, the over temperature flag is cleared by a dedicated
SPI command (HWCR.CTL).
Details about timings between the current sense signal IIS and the output voltage VOUT and the load current IL can
be found in Figure 17.
1) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in
Section 8.4 (Position 8.4.1).
Data Sheet
27
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Diagnosis
IN
OFF
ON
OFF
tON
V OUT
tOFF
t
t
IL
ts IS (ON)
IIS
t sIS (LC)
t dIS (OFF)
t
t
SenseTiming.emf
Figure 17
Timing of Current Sense Signal
Current Sense Multiplexer
There is a current sense multiplexer implemented in the SPOC - BTS5566G that routes the sense current of the
selected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense current
also can be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, please refer
to Figure 18.
CS
DCR.MUX 111
001
000
111
ts IS (MUX )
IIS
t dIS (MUX )
t
tsIS (E N)
t
MuxTiming.emf
Figure 18
Timing of Current Sense Multiplexer
8.3
Switch Bypass Diagnosis
To detect short circuit to VDD, there is a switch bypass monitor implemented. In case of short circuit between the
output pin OUT and VBB in ON-state, the current will flow through the power transistor as well as through the short
circuit (bypass) with undefined ratio. As a result, the current sense signal will show lower values than expected by
the load current. In OFF-state, the output voltage will stay close to VBB potential which means a small VDS.
The switch bypass monitor compares the voltage VDS across the power transistor of that channel which is selected
by the current sense multiplexer (DCR.MUX) with threshold VDS(SB). The result of comparison can be read in SPI
register HWCR.SBM. The switch bypass monitor is active in ON- as well as in OFF-state.
Data Sheet
28
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Diagnosis
8.4
Electrical Characteristics
Electrical Characteristics Diagnosis
Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C
typical values: VBB = 13.5 V, Tj = 25 °C
Pos. Parameter
Symbol Limit Values
Unit Test Conditions
min.
typ.
max.
IL = 1.3 A
IL = 2.6 A
IL = 6.0 A
2400
2400
2500
3100
3000
3000
3800
3500
3500
Tj = -40 °C
–
–
IL = 1.3 A
IL = 2.6 A
IL = 6.0 A
2450
2450
2700
3030
3000
3000
3600
3350
3300
Tj = 150 °C
–
–
IL = 1.3 A
IL = 2.6 A
IL = 3.5 A
2400
2400
2500
3100
3000
3000
3800
3500
3500
Tj = -40 °C
–
–
IL = 1.3 A
IL = 2.6 A
IL = 3.5 A
2450
2450
2700
3000
3000
3000
3600
3350
3300
Tj = 150 °C
–
–
IL = 0.3 A
IL = 0.6 A
IL = 1.3 A
IL = 2.0 A
1220
1250
1280
1310
1625
1565
1520
1520
2030
1880
1760
1730
Tj = -40 °C
–
–
–
IL = 0.3 A
IL = 0.6 A
IL = 1.3 A
IL = 2.0 A
1270
1340
1360
1360
1520
1520
1520
1520
1770
1700
1680
1680
Tj = 150 °C
–
–
–
-8%
Vdd
8%
V
IIS = 1 mA
–
–
2
µA
IL = 0
DCR.MUX = 000B
–
–
1
µA
IL = IL(nom)
DCR.MUX = 111B
Load Current Sense
8.4.1 Current sense ratio
kILIS
channel 0, 1:
channel 2:
channel 3, 4:
8.4.2 Current sense voltage limitation
8.4.3 Current sense leakage / offset current
VIS(LIM)
IIS(en)
8.4.4 Current sense leakage, while diagnosis IIS(dis)
disabled
8.4.5 Current sense settling time after
channel activation
tsIS(ON)
–
–
300
µs
VBB = 13.5 V
IL = IL(nom)
RIS = 4.7 kΩ
8.4.6 Current sense desettling time after
channel deactivation
tdIS(OFF)
–
–
25
µs
VBB = 13.5 V 1)
IL = IL(nom)
RIS = 4.7 kΩ
Data Sheet
29
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Diagnosis
Electrical Characteristics Diagnosis
Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C
typical values: VBB = 13.5 V, Tj = 25 °C
Pos. Parameter
Symbol Limit Values
min.
typ.
Unit Test Conditions
max.
µs
8.4.7 Current sense settling time after change tsIS(LC)
of load current
channel 0, 1, 2
channel 3, 4
8.4.8 Current sense settling time after current tsIS(EN)
sense activation
VBB = 13.5 V 1)
RIS = 4.7 kΩ
–
–
–
–
30
30
IL = 1.3 A to 2.6 A
IL = 0.6 A to 1.3 A
–
–
25
µs
RIS = 4.7 kΩ
DCR.MUX:111B -> 000B
8.4.9 Current sense settling time after
multiplexer channel change
tsIS(MUX)
–
–
30
µs
RIS = 4.7 kΩ
DCR.MUX:000B -> 001B
8.4.10 Current sense deactivation time
tdIS(MUX)
–
–
25
µs
1)
8.4.11 Off state time during PWM operation
toff
350
–
–
µs
–
0.7
–
2.5
V
–
RIS = 4.7 kΩ
DCR.MUX: 001B -> 111B
state_min
Switch Bypass Monitor
8.4.12 Switch bypass monitor threshold
VDS(SB)
1) Not subject to production test, specified by design.
Data Sheet
30
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Diagnosis
8.5
Command Description
DCR
Diagnosis Control Registers
4
3
0
0
Field
Bits
Type Description
MUX
2:0
rw
2
1
0
MUX
Set Current Sense Multiplexer Configuration
000 current sense of channel 0 is routed to IS pin
001 current sense of channel 1 is routed to IS pin
010 current sense of channel 2 is routed to IS pin
011 current sense of channel 3 is routed to IS pin
100 current sense of channel 4 is routed to IS pin
101 IS pin is high impedance
110 IS pin is high impedance
111 IS pin is high impedance
HWCR
Hardware Configuration Register
W/R
4
3
2
1
0
read
RST
0
SBM
PWM
CTL
write
RST
0
0
PWM
CTL
Field
Bits
Type Description
SBM
2
r
Switch Bypass Monitor1)
0
VDS < VDS(SB)
1
VDS > VDS(SB)
1) Invalid in stand-by mode
Standard Diagnosis
CS
7
6
5
4
3
2
1
0
TER
0
LHI
0
ERR4
ERR3
ERR2
ERR1
ERR0
Field
Bits
Type Description
ERRn
n = 4 to 0
n
r
Data Sheet
Error flag Channel n
0
normal operation
1
failure mode occurred
31
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
9
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO,
SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS
indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on
line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter
ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain
capability.
SO
SI
CS
MSB
6
5
4
3
2
1
MSB
6
5
4
3
2
1
LSB
LSB
CS
SCLK
time
SPI.emf
Figure 19
Serial Peripheral Interface
9.1
SPI Signal Description
CS - Chip Select:
The system micro controller selects the SPOC - BTS5566G by means of the CS pin. Whenever the pin is in low
state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and
SO is forced into a high impedance state.
CS High to Low transition:
•
•
The requested information is transferred into the shift register.
SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK.
CS Low to High transition:
•
•
Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK
signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the
command is ignored.
Data from shift register is transferred into the addressed register.
SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input:
Serial input data bits are shifted-in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Section 9.5 for
further information.
SO Serial Output:
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin
goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 9.5
for further information.
Data Sheet
32
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
9.2
Daisy Chain Capability
The SPI of SPOC - BTS5566G provides daisy chain capability. In this configuration several devices are activated
by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see
Figure 20), in order to build a chain. The ends of the chain are connected with the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the
SCLK line of each device in the chain.
device 3
SO
SPI
SI
SO
SPI
SCLK
SCLK
SI
SCLK
CS
MI
MCS
MCLK
Figure 20
SO
SPI
CS
SI
MO
device 2
CS
device 1
SPI_DasyChain.emf
Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out occures at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished.
In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy
chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in
daisy chain, three times eight bits have to be shifted through the devices. After that, the MCS line must turn high
(see Figure 21).
MI
SO device 3
SO device 2
SO device 1
MO
SI device 3
SI device 2
SI device 1
MCS
MCLK
time
SPI_DasyChain2.emf
Figure 21
Data Transfer in Daisy Chain Configuration
9.3
Timing Diagrams
tCS(lead)
tCS(lag)
tCS(td)
tSCLK(P)
CS
0.7Vdd
0.2Vdd
tSCLK(H)
tSCLK(L)
0.7Vdd
0.2Vdd
SCLK
tSI(su)
tSI(h)
0.7Vdd
SI
0.2Vdd
tSO(en)
tSO(v)
tSO(dis)
0.7Vdd
SO
0.2Vdd
SPI Timing.emf
Figure 22
Data Sheet
Timing Diagram SPI Access
33
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
9.4
Electrical Characteristics
Electrical Characteristics SPI
Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 °C to +150 °C, Vdd = 3.8 V to 5.5 V
typical values: Vbb = 13.5 V, Tj = 25 °C, Vdd = 4.3 V
Pos.
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Conditions
max.
Input Characteristics (CS, SCLK, SI)
9.4.1
9.4.2
L level of pin
CS VCS(L)
SCLK VSCLK(L)
SI VSI(L)
-0.3
-0.3
-0.3
–
–
–
1.0
1.0
1.0
CS VCS(H)
SCLK VSCLK(H)
SI VSI(H)
2.6
2.6
2.6
–
–
–
5.5
5.5
5.5
H level of pin
V
VDD = 4.3 V
–
–
–
V
VDD = 4.3 V
–
–
–
9.4.3
L-input pull-up current at CS pin
ICS(L)
10
30
85
µA
VDD = 4.3 V,VCS = 0 V
9.4.4
H-input pull-up current at CS pin
ICS(H)
3
–
85
µA
VDD = 4.3 V,VCS = 2.6 V
9.4.5
L-input pull-down current at pin
SCLK ISCLK(L)
SI ISI(L)
µA
3
3
–
–
75
75
VDD = 4.3 V
VSCLK = 0.4 V
VSI = 0.4 V
H-input pull-down current at pin
SCLK ISCLK(H)
SI ISI(H)
µA
10
10
30
30
75
75
VDD = 4.3 V
VSCLK = 4.3 V
VSI = 4.3 V
9.4.6
Output Characteristics (SO)
9.4.7
L level output voltage
VSO(L)
0
–
0.5
V
ISO = -0.5 mA
9.4.8
H level output voltage
VSO(H)
VDD 0.5 V
–
VDD
V
ISO = 0.5 mA,VDD = 4.3 V
9.4.9
Output tristate leakage current
ISO(OFF)
-10
–
10
µA
VCS =VDD
0
–
2
MHz –
Timings
9.4.10 Serial clock freqency
fSCLK
9.4.11 Serial clock period
tSCLK(P)
500
–
–
ns
–
9.4.12 Serial clock high time
tSCLK(H)
250
–
–
ns
–
9.4.13 Serial clock low time
tSCLK(L)
250
–
–
ns
–
9.4.14 Enable lead time (falling CS to rising tCS(lead)
SCLK)
1
–
–
µs
–
9.4.15 Enable lag time (falling SCLK to
rising CS)
tCS(lag)
1
–
–
µs
–
9.4.16 Transfer delay time (rising CS to
falling CS)
tCS(td)
1
–
–
µs
–
9.4.17 Data setup time (required time SI to tSI(su)
falling SCLK)
100
–
–
ns
–
9.4.18 Data hold time (falling SCLK to SI)
100
–
–
ns
–
–
–
1
µs
CL = 20 pF 1)
tSI(h)
9.4.19 Output enable time (falling CS to SO tSO(en)
valid)
Data Sheet
34
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
Electrical Characteristics SPI
Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 °C to +150 °C, Vdd = 3.8 V to 5.5 V
typical values: Vbb = 13.5 V, Tj = 25 °C, Vdd = 4.3 V
Pos.
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Conditions
max.
9.4.20 Output disable time (rising CS to SO tSO(dis)
tri-state)
–
–
1
µs
CL = 20 pF 1)
9.4.21 Output data valid time with
capacitive load
–
–
250
ns
CL = 20 pF 1)
tSO(v)
1) Not subject to production test, specified by design.
Data Sheet
35
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
9.5
SPI Protocol
CS1)
7
6
5
4
3
2
1
0
Write Register
SI
1
ADDR
DATA
Read Register
SI
0
ADDR
x
x
x
x
0
x
x
x
x
x
1
X
ERR4
ERR3
ERR2
ERR1
ERR0
Read Standard Diagnosis
SI
0
x
Standard Diagnosis
SO
TER
0
LHI
Second Frame of Read Command
SO
TER
1
ADDR
DATA
1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition.
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame
the output at SPI signal SO will contain the requested information. A new command can be executed in the
second frame.
Field
Bits
Type Description
TER
CS
r
Transmission Error
0
Previous transmission was successful (modulo 8 clocks received)
1
Previous transmission failed or first transmission after reset
ADDR
6:5
rw
Address
Pointer to register for read and write command
DATA
4:0
rw
Data
Data written to or read from register selected by address ADDR
LHI
6
r
Limp Home Input Pin
0
L-input signal at pin LHI
1
H-input signal at pin LHI
ERRx
x = 4 to 0
x
r
Diagnosis of Channel x
0
No failure
1
Over temperature, over load or short circuit
Data Sheet
36
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
9.6
Register Overview
Name
W/R
Addr
OUT
W/R
HWCR
DCR
4
3
2
1
0
default1)
00B
OUT4
OUT3
OUT2
OUT1
OUT0
00H
R
10B
RST
X
SBM
PWM
CTL
00H
W
10B
RST
0
0
PWM
CTL
00H
W/R
11B
0
0
MUX
07H
1) The default values are set after reset.
Data Sheet
37
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Application Description
10
Application Description
Vbat
68nF
5V
500Ω
100nF
VDD
VBB
LHI
VCC
GPIO
8k Ω
IN0
GPIO
8k Ω
IN1
IN2
OUT0
IN3
OUT1
IN4
OUT2
IS
AD
27W
10W
OUT4
GND
10W
3.3k Ω
1nF
SPI
27W
OUT3
1k Ω
µC
27W
VDD
SPI
2k Ω
CS
2k Ω
SCLK
2kΩ
SO
2kΩ
SI
VBB
Limp
Home
LHI
8k Ω
LHI
VSS
GND
Schottky
10nF.. 100nF
Circuit .emf
Figure 23
Data Sheet
Application Circuit Example
38
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Package Outlines SPOC - BTS5566G
2.65 MAX.
0.33 ±0.08
C
0.1
2)
0.7 ±0.2
0.17 M C A-B D 36x
10.3 ±0.3
D
Bottom View
A
36
7.6 -0.2
8˚ MAX.
0.65
0.35 x 45˚
1)
0.23 +0.09
2.45 -0.2
Package Outlines SPOC - BTS5566G
0.2 -0.1
11
19
19
36
Ejector Mark
1
18
18
1
B
1)
12.8 -0.2
Index Marking
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side
GPS01089
Figure 24
PG-DSO-36-34 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our Infineon Internet Page
“Products”: http://www.infineon.com/products.
Data Sheet
39
Dimensions in mm
Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Revision History
12
Revision History
Revision
Date
Changes
1.3
07-10-30
•
Chapter 11 Package outline drawing changed
1.2
07-08-28
•
•
4.1 Conditions updated
4.1 and 6.4 : footnote change to : Specified RthJA value is according to Jedec JESD512,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was
simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2
x 35µm Cu).
1.1
07-03-05
•
•
•
•
•
•
4.1.4 Conditions updated
4.1.28 Definition change
5.2 Reset Command : tCS(td) change to : tCS(td).
8.4.1 Kilis : updated values for Channel 2-3
8.4.3 New parameter : Current sense leakage / offset current
Max Input Voltage value change to 40 Volts
•
•
•
•
•
•
•
•
Product summary Green Product (ROHS compliant) and AEC Qualified added
4.1.12 Current through input pins min value change to -0.75mA
4.1.21 Current through limp home input pin min value change to -0.75mA
Chapter 2 Test pin change to Vbb
Chapter 6 Ron definition changed
Chapter 7.2 (also even in case of Vdd = 0V) added.
Basic Feature : Green Logo added
Chapter 8.1 In case of high duty cyle ( off state of output < toff state_min) the VDS
might not be equal to VBB during the off state of the power Mosfet. The over load
monitoring signals might be set and latched in the error flags. See Application
Note “ Software Strategy for Diagnosis during PWM-Operation“ for more details
Table 8.4.10 Off stateTime during PWM operation definition
Chapter 11 68nF added between VBB and Gnd
page 18: register read value added
New template DIN A4 V1.2
•
•
•
•
Data Sheet
40
Rev. 1.3, 2007-10-30
Edition 2007-10-30
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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