INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40163B MSI 4-bit synchronous binary counter with synchronous reset Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset transition of CP advances the counter to its next state only if both CEP and CET are HIGH; otherwise no change occurs in the state of the counter. TC is HIGH when the state of the counter is 15 (O0 to O3 = HIGH) and when CET is HIGH. A LOW on SR sets all outputs (O0 to O3 and TC) LOW on the next LOW to HIGH transition of CP, independent of the state of all other synchronous mode control inputs (CEP, CET and PE). Multistage synchronous counting is possible without additional components by using a carry look-ahead counting technique; in this case, TC is used to enable successive cascaded stages. CEP, CET, PE and SR must be stable only during the set-up time before the LOW to HIGH transition of CP. DESCRIPTION The HEF40163B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset (SR)), buffered outputs from all four bit positions (O0 to O3) and a terminal count output (TC). Operation is fully synchronous and occurs on the LOW to HIGH transition of CP. When PE is LOW, the next LOW to HIGH transition of CP loads data into the counter from P0 to P3. When PE is HIGH, the next LOW to HIGH Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 HEF40163B MSI 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors 4-bit synchronous binary counter with synchronous reset January 1995 3 Product specification HEF40163B MSI Fig.2 Logic diagram. Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset HEF40163B MSI PINNING PE parallel enable input P0 to P3 parallel data inputs CEP count enable parallel input CET count enable trickle input CP clock input (LOW to HIGH, edge-triggered) SR synchronous reset input (active LOW) O0 to O3 parallel outputs TC terminal count output Fig.3 Pinning diagram. HEF40163BP(N): 16-lead DIL; plastic (SOT38-1) HEF40163BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF40163BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America SYNCHRONOUS MODE SELECTION TERMINAL COUNT GENERATION CET (O0 ⋅ O1 ⋅ O2 ⋅ O3) TC L L L no change L H L no change H L L H H H SR PE CEP CET MODE H L X X H H L X H H X L H H H H count L X X X reset preset Note 1. TC = CET ⋅ O0 ⋅ O1 ⋅ O2 ⋅ O3 Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial Fig.4 State diagram. January 1995 4 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset HEF40163B MSI AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V Dynamic power 5 TYPICAL FORMULA FOR P (µW) 1 200 fi + ∑ (foCL) × VDD2 where fi = input freq. (MHz) dissipation per 10 5 600 fi + ∑ (foCL) × package (P) 15 16 000 fi + ∑ (foCL) × VDD2 VDD2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays CP → On HIGH to LOW LOW to HIGH CP → TC HIGH to LOW LOW to HIGH CET → TC HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 5 220 ns 83 ns + (0,55 ns/pF) CL 45 90 ns 34 ns + (0,23 ns/pF) CL 15 30 60 ns 22 ns + (0,16 ns/pF) CL 5 115 230 ns 88 ns + (0,55 ns/pF) CL 10 tPHL 45 95 ns 34 ns + (0,23 ns/pF) CL 15 35 65 ns 27 ns + (0,16 ns/pF) CL 5 130 260 ns 103 ns + (0,55 ns/pF) CL 10 tPLH 55 105 ns 44 ns + (0,23 ns/pF) CL 15 35 75 ns 27 ns + (0,16 ns/pF) CL 5 140 280 ns 113 ns + (0,55 ns/pF) CL 55 115 ns 44 ns + (0,23 ns/pF) CL 10 10 tPHL tPLH 15 40 80 ns 32 ns + (0,16 ns/pF) CL 5 105 210 ns 78 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 10 tPHL 15 35 75 ns 27 ns + (0,16 ns/pF) CL 5 90 185 ns 63 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) CL 10 tPLH 15 25 50 ns 17 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 30 60 ns 10 tTHL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 15 20 40 ns 5 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 tTLH 15 January 1995 110 5 10 ns + (1,0 ns/pF) CL Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset HEF40163B MSI AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Minimum clock pulse width; LOW Set-up times Pn → CP PE → CP CEP, CET → CP SYMBOL 5 MIN. TYP. MAX. 100 50 ns 40 20 ns 15 30 15 ns 5 110 55 ns 10 10 tWCPL 40 20 ns 15 30 15 ns 5 120 60 ns 10 tsu 40 20 ns 15 25 10 ns 5 260 130 ns 10 tsu tsu 100 50 ns 15 70 35 ns 5 50 25 ns 20 10 ns 15 15 10 ns Hold times 5 20 −35 ns Pn → CP 10 10 −10 ns 15 5 −10 ns 5 15 −45 ns 5 −15 ns SR → CP PE → CP CEP, CET → CP SR → CP 10 10 tsu thold thold 15 5 −10 ns 5 25 −105 ns 15 −35 ns 15 10 −25 ns 5 15 −10 ns 5 −5 ns 5 0 ns 2,5 5 MHz 7 14 MHz 9 18 MHz 10 10 thold thold 15 Maximum clock pulse frequency 5 10 fmax 15 January 1995 6 see also waveforms Figs 5, 6, 7 and 8 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset HEF40163B MSI Conditions PE = LOW P0 to P3 = HIGH Fig.5 Waveforms showing set-up and hold times for SR input and minimum CP pulse width. Condition: PE = SR = HIGH. Fig.6 Waveforms showing set-up times and hold times for CEP and CET inputs. January 1995 7 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset HEF40163B MSI Conditions PE = LOW SR = HIGH Fig.7 Waveforms showing set-up times and hold times for Pn inputs. Condition SR = HIGH Fig.8 Waveforms showing set-up times and hold times for PE input. Note Set-up and hold times are shown as positive values but may be specified as negative values. January 1995 8 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset HEF40163B MSI Fig.9 Timing diagram. APPLICATION INFORMATION An example of an application for the HEF40163B is: • Programmable binary counter. January 1995 9 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset NOTE On the TC outputs, glitches can occur during counting. In totally synchronous mode they will not have any adverse affect. However the TC output in asynchronous mode can cause problems. Fig.10 Synchronous multi-stage counting scheme. January 1995 10 HEF40163B MSI