AD AD5405 Dual 12-bit, high bandwidth, multiplying dac with 4-quadrant resistors and parallel interface Datasheet

Dual 12-Bit, High Bandwidth, Multiplying DAC with
4-Quadrant Resistors and Parallel Interface
AD5405
FEATURES
GENERAL DESCRIPTION
On chip 4-quadrant resistors allow flexible output ranges
10 MHz multiplying bandwidth
Fast parallel interface write cycle: 58 MSPS
2.5 V to 5.5 V supply operation
±10 V reference input
Extended temperature range: −40°C to 125°C
40-lead LFCSP package
Guaranteed monotonic
4-quadrant multiplication
Power-on reset
Readback function
.5 µA typical current consumption
The AD54051 is a dual CMOS, 12-bit, current output digitalto-analog converter (DAC).This device operates from a 2.5 V to
5.5 V power supply, making it suited to battery-powered and
other applications.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external I-to-V precision
amplifier. This device also contains all the 4-quadrant resistors
necessary for bipolar operation and other configuration modes.
This DAC utilizes data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with zeros and the DAC
outputs are at zero scale.
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally-controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
As a result of manufacture with a CMOS submicron process, the
device offers excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The AD5405 has a 6 mm × 6 mm, 40-lead LFCSP package.
1
R3A
R2_3A
R3
2R
AD5405
US Patent Number 5,689,257.
VREF A R1A
R2A
R2
2R
R1
2R
RFB
2R
RFBA
VDD
DATA
INPUTS
DB0
DB11
INPUT
BUFFER
IOUT1A
12-BIT
R-2R DAC A
LATCH
IOUT2A
DAC A/B
CONTROL
LOGIC
R/W
IOUT1B
12-BIT
R-2R DAC B
LATCH
IOUT2B
LDAC
GND
POWER-ON
RESET
R3
2R
R3B
R2_3B
R1
2R
R2
2R
R2B
VREFB R1B
RFB
2R
RFB B
04463-0-001
CS
Figure 1. AD5405 Functional Block Diagram
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5405
TABLE OF CONTENTS
Specifications..................................................................................... 3
Adding Gain................................................................................ 15
Timing Characteristics..................................................................... 5
Used as a Divider or Programmable Gain Element............... 16
Absolute Maximum Ratings............................................................ 6
Reference Selection .................................................................... 16
ESD Caution.................................................................................. 6
Amplifier Selection .................................................................... 16
Pin Configuration and Function Descriptions............................. 7
Parallel Interface......................................................................... 17
Typical Performance Characteristics ............................................. 8
Microprocessor Interfacing....................................................... 17
Terminology .................................................................................... 13
PCB Layout and Power Supply Decoupling ........................... 17
General Description ....................................................................... 14
Evaluation Board for the DACs................................................ 18
DAC Section................................................................................ 14
Overview of AD54xx Devices....................................................... 22
Circuit Operation ....................................................................... 14
Outline Dimensions ....................................................................... 23
Single-Supply Applications........................................................ 15
Ordering Guide .......................................................................... 23
Positive Output Voltage ............................................................. 15
REVISION HISTORY
7/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD5405
SPECIFICATIONS1
VDD = 2.5 V to 5.5 V, VREFA = VREFB = 10 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured
with OP1177, AC performance with AD9631, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temp Coefficient2
Bipolar Zero-Code Error
Output Leakage Current
REFERENCE INPUT
Reference Input Range
VREFA, VREFB Input Resistance
VREFA to VREFB Input Resistance
Mismatch
R1, RFB Resistance
R2, R3 Resistance
R2 to R3 Resistance Mismatch
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH
Input Low Voltage, VIL
Min
Typ
Max
Unit
12
±1
−1/+2
±25
±25
±1
±10
Bits
LSB
LSB
mV
ppm FSR/°C
mV
nA
nA
±10
10
1.6
12
2.5
V
kΩ
%
DAC input resistance
Typ = 25°C, Max = 125°C
20
20
.06
24
24
.18
kΩ
kΩ
%
Typ = 25°C, Max = 125°C
0.8
0.7
1
10
V
V
V
µA
pF
VDD = 2.5 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
0.4
V
V
ISINK = 200 µA
ISOURCE = 200 µA
0.4
V
V
ISINK = 200 µA
ISOURCE = 200 µA
MHz
ns
VREF = 5 V pk-pk, DAC loaded all 1s
Measured to ±1 mV of FS. RLOAD = 100 Ω, CLOAD =15 pF.
DAC latch alternately loaded with 0s and 1s.
±5
2
8
16
16
Conditions
Guaranteed monotonic
Data = 0x0000, TA = 25°C, IOUT1
Data = 0x0000H, IOUT1
Typical resistor TC = −50 ppm/°C
2
Input Leakage Current, IIL
Input Capacitance
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
DYNAMIC PERFORMANCE
Reference Multiplying BW
Output Voltage Settling Time
1.7
VDD − 1
VDD −0.5
2
10
80
120
Digital Delay
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Output Capacitance
20
3
Digital Feedthrough
5
ns
nV-s
dB
pF
pF
nV-s
Total Harmonic Distortion
−75
−75
25
dB
dB
nV/√Hz
Output Noise Spectral Density
40
−75
2
4
Rev. 0 | Page 3 of 24
1 LSB change around major carry, VREF = 0 V
DAC latch loaded with all 0s. Reference = 10 kHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
VREF = 5 V p-p, all 1s loaded, f = 1 kHz
VREF = 5 V, sine wave generated from digital code
@ 1 kHz
AD5405
Parameter
SFDR Performance (Wideband)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50k Hz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50k Hz fOUT
Intermodulation Distortion
Clock = 10 MHz
f1 = 400 kHz, f2 = 500 kHz
f1 = 40 kHz, f2 = 50 kHz
Clock = 25 MHz
f1 = 400 kHz, f2 = 500 kHz
f1 = 40 kHz, f2 = 50 kHz
POWER REQUIREMENTS
Power Supply Range
IDD
Power Supply Sensitivity
Min
2.5
2
1
2
Typ
Max
Unit
55
63
65
dB
dB
dB
50
60
62
dB
dB
dB
73
80
87
dB
dB
dB
70
75
80
dB
dB
dB
65
72
dB
dB
51
65
dB
dB
5.5
10
0.001
V
µA
%/%
Temperature range for Y version is −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 24
Conditions
Logic inputs = 0 V or VDD
∆VDD = ±5%
AD5405
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1, 2
Write Mode
t1
t2
t3
t4
t5
t6
t7
t8
t9
Data Readback Mode
t10
t11
t12
t13
Conditions/Comments
0
0
10
10
0
6
0
5
7
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
R/W to CS setup time
R/W to CS hold time
CS low time
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
0
0
5
35
5
10
ns typ
ns typ
ns typ
ns max
ns typ
ns max
Address setup time
Address hold time
Data access time
Bus relinquish time
See Figure 2. Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital output timing measured
with load circuit in Figure 3.
R/W
t8
t2
t1
t2
t9
t3
CS
t4
t5
t 10
t 11
DACA/DACB
t6
DATA
t 12
t7
t 13
DATA VALID
DATA VALID
Figure 2. Timing Diagram
200µA
TO
OUTPUT
PIN
IOL
VOH (MIN) + VOL (MAX)
2
CL
50pF
200µA
IOH
Figure 3. Load Circuit for Data Timing Specifications
Rev. 0 | Page 5 of 24
04463-0-002
2
Unit
04463-0-003
1
Limit at TMIN, TMAX
AD5405
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VREFA, VREFB, RFBA, RFBB to GND
IOUT1, IOUT2 to GND
Logic Inputs and Output1
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
40-lead LFCSP, θJA Thermal Impedance
Lead Temperature, Soldering (10 sec.)
IR Reflow, Peak Temperature (< 20 sec.)
1
Rating
−0.3 V to +7 V
−12 V to +12 V
−0.3 V to +7 V
−0.3V to VDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
−40°C to +125°C
−65°C to +150°C
150°C
30°C/W
300°C
235°C
Over voltages at DBx, LDAC, CS, and W/R are clamped by internal diodes.
Current should be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 24
AD5405
40 RFB A
39 IOUT2A
38 IOUT1A
37 NC
36 NC
35 NC
34 NC
33 IOUT1B
32 IOUT2B
31 RFBB
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5405
TOP VIEW
30 R1B
29 R2B
28 R2_3B
27 R3B
26 VREF B
25 VDD
24 CLR
23 R/W
22 CS
21 DB0
04463-0-004
NC = NO CONNECT
PIN 1
INDICATOR
DB10 11
DB9 12
DB8 13
DB7 14
DB6 15
DB5 16
DB4 17
DB3 18
DB2 19
DB1 20
R1A 1
R2A 2
R2_3A 3
R3A 4
VREFA 5
DGND 6
LDAC 7
DAC A/B 8
NC 9
DB11 10
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1 to 4
Mnemonic
R1A to R3A
5, 26
6
7
VREFA, VREFB
DGND
LDAC
8
9, 34, 35,
36, 37
10 to 21
22
DAC A/B
NC
DB11 to DB0
CS
23
R/W
24
25
26 to 30
CLR
VDD
R3B to R1B
32
IOUT2B
33
38
39
IOUT1B
IOUT1A
IOUT2A
31, 40
RFBB, RFBA
Function
DAC A 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with
minimum of external components.
DAC Reference Voltage Input Terminals.
Digital Ground Pin.
Load DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously
updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or
synchronous update mode is selected whereby the DAC is updated on the rising edge of CS.
Selects DAC A or B. Low selects DAC A, while high selects DAC B.
Not internally connected.
Parallel Data Bits 11 through 0.
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register. Edge sensitive; when pulled high, the DAC data is latched.
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with
CS to read back contents of DAC register.
Active Low Control Input. Clears DAC output and input and DAC registers.
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC B 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with a
minimum of external components.
DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but may be biased
to achieve single-supply operation.
DAC B Current Outputs.
DAC A Current Outputs.
DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but may be biased
to achieve single-supply operation.
External Amplifier Output.
Rev. 0 | Page 7 of 24
AD5405
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
–0.40
TA = 25°C
VREF = 10V
VDD = 5V
0.8
0.6
0.4
–0.50
0.2
DNL (LSB)
INL (LSB)
TA = 25°C
VREF = 10V
VDD = 5V
–0.45
0
–0.2
–0.55
–0.60
–0.4
MIN DNL
–0.6
–0.65
–0.8
500
1000
1500
2000
2500
3000
3500
4000
CODE
–0.70
2
3
5
6
7
8
9
10
REFERENCE VOLTAGE
Figure 8. DNL vs. Reference Voltage
Figure 5. INL vs. Code (12-Bit DAC)
5
1.0
TA = 25°C
VREF = 10V
VDD = 5V
0.8
0.6
4
VDD = 5V
3
2
0.2
0
–0.2
1
0
VDD = 2.5V
–1
–2
–0.6
–3
–0.8
–4
VREF = 10V
–5
–60
–40
–1.0
0
500
1000
1500
2000
2500
3000
3500
4000
CODE
04463-0-031
–0.4
–20
0
20
40
60
80
100
120
04463-0-034
ERROR (mV)
0.4
DNL (LSB)
4
04463-0-034
0
04463-0-030
–1.0
140
TEMPERATURE (°C)
Figure 6. DNL vs. Code (12-Bit DAC)
Figure 9. Gain Error vs. Temperature
0.6
8
TA = 25°C
0.5
7
0.4
6
MAX INL
CURRENT (mA)
0.2
TA = 25°C
VREF = 10V
VDD = 5V
0.1
0
MIN INL
VDD = 5V
5
4
3
2
–0.1
VDD = 3V
1
–0.2
2
3
4
5
6
7
8
REFERENCE VOLTAGE
9
10
Figure 7. INL vs. Reference Voltage
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
INPUT VOLTAGE (V)
Figure 10. Supply Current vs. Logic Input Voltage
Rev. 0 | Page 8 of 24
5.0
04463-0-013
VDD = 2.5V
–0.3
04463-0-032
INL (LSB)
0.3
1.6
1.4
1.2
GAIN (dB)
IOUT LEAKAGE (nA)
IOUT1 VDD 5V
1.0
0.8
IOUT1 VDD 3V
0.6
0.4
0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
04463-0-036
0.2
6
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
TA = 25°C
LOADING
ZS TO FS
ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
TA = 25°C
VDD = 5V
VREF = ±3.5V
INPUT
CCOMP = 1.8pF
AD8038 AMPLIFIER
AD5405 DAC
ALL OFF
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
04463-0-014
AD5405
Figure 14. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 11. IOUT1 Leakage Current vs. Temperature
0.2
0.50
TA = 25°C
0.45
VDD = 5V
0
0.40
ALL 0s
ALL 1s
VDD = 2.5V
0.20
0.15
ALL 1s
–0.4
TA = 25°C
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AD8038 AMPLIFIER
AD5405 DAC
ALL 0s
–0.6
0.10
0.05
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
–0.8
04463-0-037
0
–60
1
3
TA = 25°C
LOADING ZS TO FS
VDD = 5V
GAIN (dB)
4
0
100
1k
10k
100k
1m
1m
10m
100m
–3
2
10
100k
TA = 25°C
VDD = 5V
AD5405
–6
VDD = 2.5V
10m
FREQUENCY (Hz)
Figure 13. Supply Current vs. Update Rate
100m
–9
10k
04463-0-038
IDD (mA)
VDD = 3V
1
10k
0
8
6
1k
Figure 15. Reference Multiplying Bandwidth–All 1s Loaded
14
10
100
FREQUENCY (Hz)
Figure 12. Supply Current vs. Temperature
12
10
VREF = ±2V, AD8038 CC 1.47pF
VREF = ±2V, AD8038 CC 1pF
VREF = ±0.15V, AD8038 CC 1pF
VREF = ±0.15V, AD8038 CC 1.47pF
VREF = ±3.51V, AD8038 CC 1.8pF
100k
1M
FREQUENCY (Hz)
10M
100M
04463-0-015
0.25
–0.2
04463-0-029
0.30
GAIN (dB)
CURRENT (µA)
0.35
Figure 16. Reference Multiplying Bandwidth vs. Frequency and Compensation
Capacitor
Rev. 0 | Page 9 of 24
AD5405
–60
0.045
7FF TO 800H
TA = 25°C
VREF = 0V
AD8038 AMPLIFIER
CCOMP = 1.8pF
0.040
VDD = 5V
–65
0.030
–70
0.025
THD + N (dB)
OUTPUT VOLTAGE (V)
0.035
TA = 25°C
VDD = 3V
VREF = 3.5V p-p
VDD = 3V
0.020
0.015
800 TO 7FFH
0.010
–80
VDD = 3V
0.005
–75
0
–85
VDD = 5V
0
20
40
60
80
100
120
140
160
180
–90
04463-0-039
–0.010
200
TIME (ns)
1
10
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 20. THD and Noise vs. Frequency
Figure 17. Midscale Transition, VREF = 0 V
100
–1.68
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
CCOMP = 1.8pF
7FF TO 800H
–1.69
VDD = 5V
–1.70
MCLK = 1MHz
80
SFDR (dB)
–1.71
–1.72
VDD = 3V
–1.73
MCLK = 200kHz
60
MCLK = 0.5MHz
40
VDD = 5V
VDD = 3V
–1.75
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
AD5405
20
–1.76
800 TO 7FFH
0
20
40
60
80
100
120
140
160
180
0
04463-0-040
–1.77
200
TIME (ns)
0
60
80
100
120
140
160
180
200
Figure 21. Wideband SFDR vs. fOUT Frequency
90
TA = 25°C
VDD = 3V
AMP = AD8038
0
40
fOUT (kHz)
Figure 18. Midscale Transition, VREF = 3.5 V
20
20
04463-0-027
–1.74
80
MCLK = 5MHz
70
MCLK = 10MHz
–20
SFDR (dB)
60
–40
FULL SCALE
–60
ZERO SCALE
50
MCLK = 25MHz
40
30
20
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
AD5405
–100
10
–120
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
0
0
100
200
300
400
500
600
700
800
900
fOUT (kHz)
Figure 19. Power Supply Rejection vs. Frequency
Figure 22. Wideband SFDR vs. fOUT Frequency
Rev. 0 | Page 10 of 24
1000
04463-0-028
–80
04463-0-026
PSRR (dB)
OUTPUT VOLTAGE (V)
100
04463-0-041
–0.005
AD5405
0
0
TA = 25°C
VDD = 5V
AMP = AD8038
AD5405
65k CODES
–10
–20
–20
–30
–40
–40
SFDR (dB)
–50
–60
–50
–60
–70
–70
–80
–80
2
0
4
6
8
FREQUENCY (MHz)
10
12
04463-0-018
–90
–90
Figure 23. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
0
–100
250
–20
350
400
450 500 550 600
FREQUENCY (MHz)
650
700
750
Figure 26. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
20
TA= 25°C
VDD = 5V
AMP = AD8038
AD5405
65k CODES
–10
300
04463-0-021
SFDR (dB)
–30
TA= 25°C
VDD = 3V
AMP = AD8038
AD5405
65k CODES
0
–20
–30
–40
SFDR (dB)
SFDR (dB)
TA= 25°C
VDD = 3V
AMP = AD8038
AD5405
65k CODES
–10
–50
–60
–70
–40
–60
–80
–80
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
4.0
4.5
5.0
–120
50
60
70
80
90
100 110 120
FREQUENCY (MHz)
0
TA = 25°C
VDD = 5V
AMP = AD8038
AD5405
65k CODES
–10
–20
140
150
Figure 27. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
Figure 24. Wideband SFDR, fOUT =500 kHz, Clock = 10 MHz
0
130
04463-0-022
–100
04463-0-019
–90
TA= 25°C
VDD = 3V
AMP = AD8038
AD5405
65k CODES
–10
–20
–30
–40
(dB)
–40
–50
–50
–60
–60
–70
–80
–80
–90
–90
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
4.0
4.5
5.0
–100
70
75
80
85
95
90
100 105
FREQUENCY (MHz)
110
115
120
04463-0-023
–70
04463-0-020
SFDR (dB)
–30
Figure 28. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
Figure 25. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
Rev. 0 | Page 11 of 24
AD5405
0
300
TA= 25°C
VDD = 5V
AMP = AD8038
AD5405
65k CODES
–20
250
MIDSCALE LOADED TO DAC
FULL SCALE LOADED TO DAC
–30
–40
(dB)
TA = 25°C
AMP = AD8038
ZERO SCALE LOADED TO DAC
OUTPUT NOISE (nV/ Hz)
–10
–50
–60
–70
–80
200
150
100
50
0
50
100
150
200
250
FREQUENCY (kHz)
300
350
400
Figure 29. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
0
100
1k
10k
FREQUENCY (Hz)
Figure 30. Output Noise Spectral Density
Rev. 0 | Page 12 of 24
100k
04463-0-025
–100
04463-0-024
–90
AD5405
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For this
DAC, ideal maximum output is VREF − 1 LSB. Gain error of the
DACs is adjustable to zero with external resistance.
Output Leakage Current
Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the IOUT1 terminal, it can
be measured by loading all 0s to the DAC and measuring the
IOUT1 current. Minimum current flows in the IOUT2 line when
the DAC is loaded with all 1s.
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For this device, it is
specified with a 100 Ω resistor to ground.
Digital to Analog Glitch lmpulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is typically
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’ s digital inputs is capacitively coupled through the
device to show up as noise on the IOUT pins and subsequently
into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal, when all 0s are
loaded to the DAC.
Digital Crosstalk
This is the glitch impulse transferred to the outputs of one
DAC in response to a full-scale code change (all 0s to all 1s,
and vice versa) in the input register of the other DAC. It is
expressed in nV-s.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s, and vice versa), while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
Channel to Channel Isolation
This refers to the proportion of input signal from one DAC’s
reference input which appears at the output of the other DAC,
and is expressed in dBs.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as the second to the fifth.
THD = 20 log
(V2 2 + V32 + V4 2 + V52 )
V1
Intermodulation Distortion
The DAC is driven by two combined sine wave references
of frequencies fa and fb. Distortion products are produced
at sum and difference frequencies of mfa ± nfb where m, n = 0,
1, 2, 3,... Intermodulation terms are those for which m or n is
not equal to zero. The second-order terms include (fa + fb)
and (fa − fb) and the third-order terms are (2fa + fb), (2fa − fb),
(f + 2fa + 2fb) and (fa − 2fb). IMD is defined as
IMD = 20 log
(rms sum of the sum and diff distortion products)
rms amplitude of the fundamental
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Rev. 0 | Page 13 of 24
AD5405
GENERAL DESCRIPTION
DAC SECTION
The AD5405 is a 12-bit, dual-channel, current-output DAC
consisting of a standard inverting R-2R ladder configuration.
Figure 31 shows a simplified diagram for a single channel of the
AD5405. The feedback resistor RFB has a value of 2R. The value
of R is typically 10 kΩ (minimum 8 kΩ and maximum 12 kΩ).
If IOUT1A and IOUT2A are kept at the same potential, a constant
current flows in each ladder leg, regardless of digital input code.
Thus, the input resistance presented at VREF is always constant.
R
VREF A
R
R
2R
2R
2R
2R
S1
S2
S3
S12
2R
With a fixed 10 V reference, the circuit shown in Figure 32 gives
a unipolar 0 V to −10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between digital code and
expected output voltage for unipolar operation.
Table 5. Unipolar Code Table
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Analog Output (V)
−VREF (4095/4096)
−VREF (2048/4096) = −VREF/2
−VREF (1/4096)
−VREF (0/4096) = 0
2R
RFB A
Bipolar Operation
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier, as shown in Figure 33.
Figure 31. Simplified Ladder Configuration
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of
each DAC, making the device extremely versatile and allowing
it to be configured in several different operating modes, such as
for unipolar output, bipolar output, or single-supply mode.
VDD
R1A
R1
2R
RFB
2R
RFBA
R2A
C1
VIN
R2
2R
R2_3A
CIRCUIT OPERATION
A1
R3A
IOUT1A
AD5405
VOUT = –VIN TO +VIN
Unipolar Mode
Using a single op amp, this DAC can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 32.
VDD
R3A
AGND
AGND
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
RFBA
When in bipolar mode, the output voltage is given by
C1
R2
2R
IOUT1A
AD5405
VOUT = VREF × D 2n −1 × VREF
A1
IOUT2A
12-Bit DAC A
R
VOUT = 0V TO –VIN
R3
2R
where D is the fractional representation of the digital word
loaded to the DAC, in the range of 0 to 4095, and n is the
number of bits. When VIN is an ac signal, the circuit performs
4-quadrant multiplication.
AGND
VREFA
GND
Figure 33. Bipolar Operation (4-Quadrant Multiplication)
RFB
2R
R2A
R2_3A
AGND
VREFA
AGND
R1A
R1
2R
A1
IOUT2A
12-Bit DAC A
R
R3
2R
04463-0-007
DAC DATA LATCHES
AND DRIVERS
04463-0-005
IOUT1A
IOUT 2A
GND
04463-0-006
AGND
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Table 6. Bipolar Code Table
Figure 32. Unipolar Operation
When an output amplifier is connected in unipolar mode, the
output voltage is given by
VOUT = − D 2n × VREF
Table 6 shows the relationship between the digital code and the
expected output voltage for bipolar operation.
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
where D is the fractional representation of the digital word
loaded to the DAC, and n is the resolution of the DAC.
D = 0 to 4095
Rev. 0 | Page 14 of 24
Analog Output (V)
+VREF (2047/2048)
0
−VREF (2047/2048)
−VREF (2048/2048)
AD5405
Stability
POSITIVE OUTPUT VOLTAGE
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open loop
response which can cause ringing or instability in the closedloop applications circuit.
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages. In order to achieve a positive
voltage output, an applied negative reference to the input of
the DAC is preferred over the output inversion through an
inverting amplifier because of the resistor’s tolerance errors. To
generate a negative reference, the reference can be level shifted
by an op amp such that the VOUT and GND pins of the reference
become the virtual ground and −2.5 V respectively, as shown in
Figure 35.
VDD = +5V
An optional compensation capacitor, C1, can be added in
parallel with RFB for stability, as shown in Figure 32 and
Figure 33. Too small a value of C1 can produce ringing at the
output, while too large a value can adversely affect the settling
time. C1 should be found empirically, but 1 pF to 2 pF is
generally adequate for the compensation.
ADR03
VOUT VIN
GND
+5V
–2.5V
VDD
R2
VDD
VREF
IOUT2
VOUT
IOUT1
IOUT2
VOUT = 0V TO +2.5V
1/2 AD8552
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
04463-0-010
Figure 34 shows these DACs operating in the voltage switching
mode. The reference voltage, VIN, is applied to the IOUT1 pin,
IOUT2 is connected to AGND, and the output voltage is available
at the VREF terminal. In this configuration, a positive reference
voltage results in a positive output voltage, making singlesupply operation possible. The output from the DAC is voltage
at a constant impedance (the DAC ladder resistance). Thus an
op amp is necessary to buffer the output voltage. The reference
input no longer sees a constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.
RFB
IOUT1
12-BIT DAC
RFB
GND
–5V
Voltage Switching Mode of Operation
VIN
VREF
1/2 AD8552
SINGLE-SUPPLY APPLICATIONS
R1
C1
VDD
Figure 35. Positive Voltage Output with Minimum Components
ADDING GAIN
In applications where the output voltage is required to be
greater than VIN, gain can be added with an additional external
amplifier or it can also be achieved in a single stage. Consider
the effect of temperature coefficients of the thin film resistors
of the DAC. Simply placing a resistor in series with the RFB
resistor causes mismatches in the temperature coefficients
resulting in larger gain temperature coefficient errors. Instead,
the circuit of Figure 36 is a recommended method of increasing
the gain of the circuit. R1, R2, and R3 should all have similar
temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended
in circuits where gains of > 1 are required.
VDD
GND
VDD
R2
VIN
VREF
12-BIT
DAC
GND
Figure 34. Single-Supply Voltage Switching Mode
RFB
IOUT1
IOUT2
VOUT
R3
R2
Note that VIN is limited to low voltages because the switches in
the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and degrades the
integral linearity of the DAC. Also, VIN must not go negative by
more than 0.3 V or an internal diode turns on, exceeding the
max ratings of the device. In this type of application, the full
range of multiplying capability of the DAC is lost.
GAIN = R2 + R3
R2
R1 = R2R3
NOTES
R2 + R3
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Rev. 0 | Page 15 of 24
Figure 36. Increasing Gain of Current Output DAC
04463-0-011
04463-0-009
C1
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
AD5405
USED AS A DIVIDER OR PROGRAMMABLE GAIN
ELEMENT
REFERENCE SELECTION
Used as a divider or programmable gain element, currentsteering DACs are very flexible and lend themselves to many
different applications. If this type of DAC is connected as the
feedback element of an op amp, and RFB is used as the input
resistor, as shown in Figure 37, then the output voltage is
inversely proportional to the digital input fraction D.
For D = 1−2n the output voltage is
VOUT = − VIN D = − VIN (1 − 2 −n )
VDD
VIN
RFB
VDD
IOUT1
VREF
IOUT2
When selecting a reference for use with the AD5405 series of
current output DACs, pay attention to the reference output
voltage temperature coefficient specification. This parameter
not only affects the full-scale error, but can also affect the
linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy
specifications. For example, an 8-bit system required to hold
its overall specification to within 1 LSB over the temperature
range 0°C to 50°C dictates that the maximum system drift with
temperature should be less than 78 ppm/°C. A 12-bit system
with the same temperature range to overall specification within
2 LSBs requires a maximum drift of 10 ppm/°C. By choosing a
precision reference with low output temperature coefficient, this
error source can be minimized. Table 7 lists some references
available from Analog Devices that are suitable for use with this
range of current output DACs.
AMPLIFIER SELECTION
GND
NOTE
ADDITIONAL PINS OMITTED FOR CLARITY
04463-0-012
VOUT
Figure 37. Current-Steering DAC Used as a Divider or
Programmable Gain Element
As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and also that the required accuracy
is met. For example, an 8-bit DAC driven with the binary code
0 × 10 (00010000), that is, 16 decimal, in the circuit of Figure 37
should cause the output voltage to be 16 × VIN. However, if the
DAC has a linearity specification of ±0.5 LSB, then D can, in
fact, have the weight anywhere in the range 15.5/256 to 16.5/256
so that the possible output voltage is in the range 15.5 VIN to
16.5 VIN—an error of 3% even though the DAC itself has a
maximum error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction D of the current into the VREF terminal
is routed to the IOUT1 terminal, the output voltage has to change
as follows:
Output Error Voltage Due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. The input offset voltage of an op amp is multiplied by
the variable gain (due to the code-dependent output resistance
of the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed upon the desired change
in output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor RFB. Most op amps have input bias currents low
enough to prevent any significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in
voltage-switching circuits, because it produces a codedependent error at the voltage output of the circuit. Most
op amps have adequate common-mode rejection for use at
12-bit resolution.
Provided the DAC switches are driven from true wide band,
low impedance sources (VIN and AGND) they settle quickly.
Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration,
minimize capacitance at the VREF node (voltage output node in
this application) of the DAC. This is done by using low input
capacitance buffer amplifiers and careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turn requires an amplifier that can handle
rail-to-rail signals. Analog Devices offers a large range of singlesupply amplifiers, as listed in Table 8.
Rev. 0 | Page 16 of 24
AD5405
Table 7. Suitable ADI Precision References Recommended for Use with AD5405 DACs
Reference
ADR01
ADR02
ADR03
ADR425
Output Voltage
10 V
5V
2.5 V
5V
Initial Tolerance
0.1%
0.1%
0.2%
0.04%
Temperature Drift
3 ppm/°C
3 ppm/°C
3 ppm/°C
3 ppm/°C
0.1 Hz to 10 Hz noise
20 µV p-p
10 µV p-p
10 µV p-p
3.4 µV p-p
Package
SC70, TSOT, SOIC
SC70, TSOT, SOIC
SC70, TSOT, SOIC
MSOP, SOIC
Table 8. Precision ADI Op Amps Suitable for Use with AD5405 DACs
Part No.
OP97
OP1177
AD8551
Max Supply Voltage V
±20
±18
+6
VOS (max) µV
25
60
5
IB (max) nA
0.1
2
0.05
GBP MHz
0.9
1.3
1.5
Slew Rate V/µs
0.2
0.7
0.4
Table 9. High Speed ADI Op Amps Suitable for Use with AD5405 DACs
Part No.
AD8065
AD8021
AD8038
Max Supply Voltage V
±12
±12
±5
VOS (max) µV
1500
1000
3000
IB (max) nA
0.01
1000
0.75
BW @ ACL MHz
145
200
350
Slew Rate V/µs
180
100
425
PARALLEL INTERFACE
MICROPROCESSOR INTERFACING
The AD5405 can be interfaced to a variety of 16-bit microcontrollers or DSP processors. Figure 38 shows the AD5405
DAC interfaced to a generic 16-bit microcontroller/DSP
processor. Microprocessor interfacing to this family of DAC is
via a data bus that uses a standard protocol compatible with
microcontrollers and DSP processors. The address decoder
selects DAC A or DAC B and also to loads parallel data to the
input latch or to read data from the DAC using an AND gate.
A0 TO AX
ADDRESS BUS
AD54xx*
MICRO/DSP*
ADDRESS
DECODER
A
A+1
WR
DAC A/B
CS
WR
DB0 TO DB11
DB0 TO DB11
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 38. AD54xx to Parallel Interface
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5405 is mounted should be designed so that the
analog and digital sections are separated, and confined to
certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
Rev. 0 | Page 17 of 24
04462-0-055
Data is loaded to the AD5405 in the format of a 12-bit parallel
word. Control lines CS and R/W allow data to be written to or
read from the DAC register. A write event takes place when CS
and R/W are brought low, data available on the data lines fills
the shift register, and the rising edge of CS latches the data and
transfers the latched data word to the DAC register. The DAC
latches are not transparent, thus a write sequence must consist
of a falling and rising edge on CS to ensure data is loaded to the
DAC register and its analog equivalent reflected on the DAC
output. A read event takes place when R/W is held high and CS
is brought low. Data is loaded from the DAC register back to the
input register and out onto the data line where it can be read
back to the controller for verification or diagnostic purposes.
The input and DAC registers of these devices are not transparent, so a falling and rising edge of CS is required to load
each data-word.
AD5405
These DACs should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR)
and effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board, and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough on the board. A microstrip
technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to the ground plane while signal traces
are placed on the soldered side.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
EVALUATION BOARD FOR THE DACS
The evaluation board consists of a DAC and a current-tovoltage amplifier, the AD8065. Included on the evaluation
board is a 10 V reference, the ADR01. An external reference
may also be applied via an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows the
user to write a code to the device.
POWER SUPPLIES FOR THE EVALUATION BOARD
The board requires ±12 V and 5 V supplies. The 12 V VDD and
VSS are used to power the output amplifier, while the 5 V is used
to power the DAC (VDD1) and transceivers (VCC).
Both supplies are decoupled to their respective ground plane
with 10 µF tantalum and 0.1 µF ceramic capacitors.
Rev. 0 | Page 18 of 24
04463-0-045
AD5405
Figure 39. Schematic of AD5405 Evaluation Board
Rev. 0 | Page 19 of 24
04463-0-046
AD5405
04463-0-047
Figure 40. Component-Side Artwork
Figure 41. Silkscreen—Component-Side View (Top Layer)
Rev. 0 | Page 20 of 24
04463-0-048
AD5405
Figure 42. Solder-Side Artwork
Rev. 0 | Page 21 of 24
AD5405
OVERVIEW OF AD54xx DEVICES
Table 10.
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
Resolution
8
8
8
8
8
10
10
10
10
10
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
No. DACs
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
INL(LSB)
±0.25
±0.25
±0.25
±0.25
±0.25
±0.5
±0.5
±0.5
±0.5
±0.25
±1
±0.5
±1
±1
±1
±1
±0.5
±1
±2
±1
±1
±1
±1
±2
±2
±2
±2
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package
RU-16, CP-20
RM-10
RU-20
RU-10
RJ-8
RM-10
RU-20, CP-20
RU-16
RU-24
RJ-8
RM-10
RM-8
RU-24
RU-20, CP-20
RU-24
RU-16
RJ-8, RM-8
RM-8
UJ-8, RM-8
RM-8
RU-28
RM-8
RU-38
RM-8
RU-28
RU-16
RU-38
Rev. 0 | Page 22 of 24
Features
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 50 MHz Serial
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 50 MHz Serial
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 58 MHz Serial
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
4 MHz BW, 50 MHz Serial Clock
4 MHz BW, 20 ns WR Pulse Width
4 MHz BW, 50 MHz Serial Clock
4 MHz BW, 20 ns WR Pulse Width
4 MHz BW, 50 MHz Serial Clock
4 MHz BW, 20 ns WR Pulse Width
4 MHz BW, 50 MHz Serial Clock
4 MHz BW, 20 ns WR Pulse Width
AD5405
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
5.75
BCS SQ
0.50
0.40
0.30
126° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
31
30
40
1
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOTTO M VIEW)
10
11
21
20
0.25 MIN
4.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 43. 40 Lead LFCSP
(CP-40)
Dimensions shown in inches and (mm)
ORDERING GUIDE
Model
AD5405YCP
AD5405YCP–REEL
AD5405YCP–REEL7
EVAL-AD5405EB
Resolution
12
12
12
INL (LSBs)
±1
±1
±1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Rev. 0 | Page 23 of 24
Package Description
LFCSP
LFCSP
LFCSP
Evaluation Kit
Package Option
CP-40
CP-40
CP-40
AD5405
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04463–0–7/04(0)
Rev. 0 | Page 24 of 24