L4956 5A LOW DROP LINEAR REGULATOR SPLITTED SUPPLY VOLTAGE FOR IMPROVED EFFICIENCY: - VPW: 3V MIN. POWER SUPPLY VOLTAGE - VSIG: 4.5V MIN. SIGNAL SUPPLY VOLTAGE 5A OUTPUT CURRENT FAST LOAD TRANSIENT RESPONSE 0.75V TYP. DROP OUT VOLTAGE AT 5A INHIBIT WITH ZEROCURRENT COMSUMPTION POWER GOOD SHORT CIRCUIT PROTECTION THERMAL SHUTDOWN HEPTAWATT PACKAGE APPLICATIONS PENTIUM AND POWER PC SUPPLIES LOW COST SOLUTION FOR 3.3V TO 1.5V CONVERSION SUITABLE FOR APPLICATIONS WITH STAND BY FEATURE MULTIPOWER BCD TECHNOLOGY HEPTAWATT ORDERING NUMBER: L4956 Designed in BCDII technology, it uses a charge pump technique to have a proper internal N-channel gate drive. The signal supply voltage input VSIG can operate from 4.5V up to an absolute of 7V and the power supply voltage input VPW can opearte from 3V min to an absolute of 7V. An RDSON of 150mV gives a voltage drop of 750mV at 5A of load current. Very fast load transients and ±1% of reference voltage precision makes this device suitable for supplying last micrprocessors generation and low voltage logics. The Heptawatt package enriches the device with auxiliary functions like power good and inhibit. DESCRIPTION The L4956 is an adjustable monolithic linear regulator designed to satisfy very heavy load transient and efficient power conversion from 3.3V to 1.26V and lower, up to 5A. TYPICAL APPLICATION VPW=3.3Vbus VPW VSIG= 5Vbus C1 C3 VSIG 1 2 INH PG 3 6 7 OUT VO R1 L4956 5 ADJ 4 C2 R2 GND D96IN374B March 1998 1/8 L4956 ABSOLUTE MAXIMUM RATINGS Symbol VPW, VSIG Parameter Value Supply Input Voltage 7 V -0.3 to 4 0 to VSIG V V 2 15 W W -40 to +150 °C ADJ pin PG and INH pins PTOT Power Dissipation @ Tamb = 50°C Power Dissipation @ Tcase = 90°C Tst, Ti Storage Temperature Unit PIN CONNECTION (Top view) 7 OUT 6 PG 5 ADJ 4 GND 3 INH 2 VSIG 1 VPW tab connected to pin 4 D96IN373 PIN FUNCTIONS No. Name 1 VPW Function 2 VSIG Unregulated signal input voltage this pin has to be by passed with a minimum capacitor of 0.1µF. 3 INH TTL-CMOS input. A logic level on this input disable the device. An internal pull-down insures insures full functionally even if the pin is open. 4 GND Ground. 5 ADJ The output is connected directly to this terminal for 1.26V operation via divider for higher voltages. 6 PG Open drain output, this pin is low when the output voltage is lower than 90%, otherwise is high. 7 OUT Unregulated power input voltage; this pin must be bypassed with a capacitor larger than 10µF. Regulated output voltage. A minimum bypass capacitor of 22µF is required to insure stability. BLOCK DIAGRAM V PW VPW 1 10µF VSIG VSIG V REF= 1.26V 2 PRE REGULATOR CURRENT LIMITATION + - CHARGE PUMP FOLDBACK BUFFER E/A POWER DMOS 150mΩ THERMAL SHUTDOWN INH 3 R1 ADJ 5 1.26V INHIBIT ACTIVE HIGH + 0.9VREF 4 6 GND 2/8 OUT 7 PG D96IN372A R2 V OUT 22µF L4956 THERMAL DATA Symbol Parameter Value Unit Rth j-pins Thermal Resistance Junction-case 2.5 °C/W Rth j-amb Thermal Resistance Junction-ambient 50 °C/W Thermal Shutdown Typ. 150 °C Thermal Hysteresis Typ. 20 °C ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise specified) Symbol Parameter VPW Power Operating Supply Voltage VSIG Signal Operating Supply Voltage VOUT Output Voltage (1) Test Condition Min. Typ. 3 4.5 Max. Unit 6.5 V 6.5 V 0 < Tj < 125°C; VPW = 3.3V 4.5V < VSIG < 6.5V; 0.1A < IO < 5A 1.240 1.260 1.280 V 3V < VPW < 5.5V; 4.5V< VSIG < 6.5V 0.1A < IO < 5A; 0 < Tj < 125°C 1.224 1.260 1.296 V 0.5 3 mV 1 5 mV 0.75 1.1 1.1 1.5 V V 6.3 7.5 A ∆VOUT Line regulation ∆VOUT Load regulation (1) VPW = 3.3V; VSIG = 5V 0.1A < IO < 5A Drop-out Voltage IO = 5A IO = 5A, Tj = 125°C Current Limiting 0 < Tj < 125°C Short Circuit Current VO = 0V, 0 < Tj < 125°C 1.8 Quiescent Current at pin VSIG 0.1A < IO < 5A 4.5V < VSIG <6.5V 1.5 3 mA Stand By Current at pin VSIG INH = HIGH VSIG = 5V 100 150 µA Inhibit Threshold 0 < Tj < 125°C 1.26 1.42 V 10 µA IO IQ (1) 3V < VPW < 5.5V; IO = 10mA 4.5V < VSIG < 6.5V Inhibit Histeresys 5.1 1.1 0.2 Inhibit Bias Sink Current 5 Power Good Threshold 0.9 x VOUT Power Good Saturation Power Good Histeresys A I6 = 4mA 0.1 0.2 V V 0.4 V V (1) Output voltage connected to ADJ. 3/8 L4956 Figure 1. DC Operating Area. Figure 2. Output Voltage Stability vs. Junction Temperature Vo ut [V ] 1 .2 8 O utput C urrent [A] 8 V pw > 3V V sig > 4.5 V T j = 1 25 ° C 7 6 P ow e r D issip a tio n L im it 1 .2 7 1 .2 6 5 4 1 .2 6 Tc = 7 0° C P dm ax=2 2 W 3 1 .2 5 5 2 1 .2 5 D C O p e ra ting A rea 1 0 V pw = 3.3V V sig = 5V I out = 1 0m A 1 .2 7 5 R d son lim it 5 Tc = 2 5° C P dm ax = 4 0 W C u rre nt Lim ita ti o n 1 .2 4 5 0 1 2 3 4 5 6 (Vpw - Vout) [V ] 7 8 5 12 0 160 [V] V p w = 3.3 V V s i g = 5V Vo u t = Va d j T j = 2 5 °C 3 2 1 0 -1 1 T j = 1 2 5 °C 0 .7 5 T j = 2 5 °C 0 .5 Minimum O utput Voltage 40 80 T j [°C ] 1 .2 5 4 -2 -3 Tj = -40 ° C 0 .2 5 P u ls e d tec n iq u e h as b e e n u s e d -4 -5 0 Figure 4. Dropout Voltage. Vpw - Vout Voltage Deviation [m Figure 3. Load Regulation. 1 .2 4 -40 P u ls ed te c hn iq u e h a s b e e n u s e d 0 1 2 3 I ou t [A ] 4 5 0 0 1 2 3 Io u t [A ] 4 5 Figure 5. Maximum Output Current vs. Junction Temperature Figure 6. Quiescent Current at pin VSIG vs. Junction Temperature. O u tp u t C u rre nt [A ] I q [m A ] 2 10 V S IG = 6 . 5 V I o u t = 1 0 m A to 5 A 3 V < V P W < 6 .5 V 1 .8 9 (V p w -Vo u t) > 2 V 8 6 1 .6 7 1 .4 6 5 1 .2 4 1 3 0 .8 2 P u ls e d te cn iq u e h a s b e e n u s e d 1 0 -4 0 -20 4/8 0 20 4 0 6 0 8 0 10 0 12 0 1 40 1 60 Tj [ºC ] 0 .6 0 .4 -40 -20 0 20 40 6 0 8 0 1 00 120 14 0 1 60 T j [ °C ] L4956 Figure 7. Quiescent Current at pin VSIG vs. Signal Input Voltage. Figure 8. Stand-By Current at pin VSIG vs. Signal Input Voltage with INH = LOGIC HIGH Iq [m A ] 3 I q [µ A ] 1 50 Io = 1 0 m A to 2 .5 5A 1 25 T j = 2 5 °C 3 V < V P W < 6 .5 V 2 1 00 1 .5 75 1 50 0 .5 25 0 0 1 2 3 4 V S I G [V ] 5 6 0 7 T j = 25 °C 3 V < V P W < 6 .5 V 4 4 .5 5 5 .5 6 V S IG [V ] 6 .5 7 Figure 9. Power Good Function V ADJ V OUT=VADJ (R1+R2)/R2 0.9 VADJ hyst = 200mV t PG Low High Low t D96IN364B Figure 10. Inhibit Function VINH Vref = 1.26V hyst = 200mV t regulator ON regulator OFF regulator ON D96IN365A t 5/8 L4956 LOAD TRANSIENT RESPONSE Figure 11. Figure 12. Vout 50mV/div CH1gnd Vout 50mV/div CH1gnd 5A 5A 0.5A CH2gnd Iout 2A/div 0.5A CH2gnd Iout 2A/div t = 5µs/div t = 5µs/div Figure 13. Test conditions: VPW = 3.3V; VSIG = 5; Vout = 1.5V; Load Transient from 0.5A to 5A; dlout = 20A/µs; Tj = 25°C dt Vout 50mV/div CH1gnd 5A 0.5A CH2gnd Iout 2A/div t = 100µs/div Figure 14. Load transient test circuit. PG VIN=3.3V VPW VSIG=5V VSIG C1,C2 470µF Panasonic HFQ 1 2 L4956 4 C16 220nF 7 6 GND 3 INH 5 OUT ADJ VOUT=1.5V R4 24Ω R5 126Ω C4 to C9 100µF/10V AVX TPS 6 each D97IN593 6/8 C10 to C15 1µF AVX X7R 6 each L4956 HEPTAWATT PACKAGE MECHANICAL DATA DIM. MIN. mm TYP. MAX. MIN. inch TYP. MAX. A 4.8 0.189 C 1.37 0.054 D 2.4 2.8 0.094 0.110 D1 1.2 1.35 0.047 0.053 E 0.35 0.55 0.014 0.022 F 0.6 0.8 0.024 0.031 F1 0.9 0.035 G 2.41 2.54 2.67 0.095 0.100 0.105 G1 4.91 5.08 5.21 0.193 0.200 0.205 G2 7.49 7.62 7.8 0.295 0.300 0.307 H2 H3 10.4 10.05 10.4 0.409 0.396 0.409 L 16.97 0.668 L1 14.92 0.587 L2 21.54 0.848 L3 22.62 0.891 L5 2.6 3 0.102 0.118 L6 15.1 15.8 0.594 0.622 L7 6 6.6 0.236 M 2.8 M1 Dia 5.08 3.65 0.260 0.110 0.200 3.85 0.144 0.152 7/8 L4956 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1998 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 8/8