TI1 LMK01801 Dual clock divider buffer evaluation board operating instruction Datasheet

SNAU118
LMK01801
Dual Clock Divider Buffer
Evaluation Board Operating Instructions
7 December 2011
LMK01801 EVAL
Texas Instruments, Inc.
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LMK01801BEVAL Evaluation Board Operating Instructions
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Table of Contents
TABLE OF CONTENTS ....................................................................................................................... 2
TABLE OF FIGURES........................................................................................................................... 3
GENERAL DESCRIPTION ................................................................................................................... 4
Block Diagram ........................................................................................................................................................... 4
Evaluation Board Kit Contents ................................................................................................................................... 5
Quick Start – Code Loader Mode ............................................................................................................................... 6
Quick Start – Pin Control Mode ................................................................................................................................. 7
Pin Control Modes...................................................................................................................................................... 8
Using CodeLoader to Program the LMK01801 ......................................................................................................... 9
Evaluation Board Inputs/Outputs ............................................................................................................................. 12
RECOMMENDED TEST EQUIPMENT ................................................................................................. 14
APPENDIX A: CODELOADER USAGE .............................................................................................. 15
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS ......................................................... 19
LMK01801 Sample Output Waveforms ................................................................................................................... 25
LMK01801 Analog Delay Sample Data................................................................................................................... 26
APPENDIX C: SCHEMATICS ............................................................................................................ 28
Power........................................................................................................................................................................ 28
Main ......................................................................................................................................................................... 29
Inputs ........................................................................................................................................................................ 30
Inputs Page 2 ............................................................................................................................................................ 31
Clock Outputs Page 1 ............................................................................................................................................... 32
Clock Outputs Page 2 ............................................................................................................................................... 33
Clock Outputs Page 3 ............................................................................................................................................... 34
APPENDIX D: BILL OF MATERIALS ................................................................................................ 35
Common Bill of Materials for Evaluation Boards .................................................................................................... 35
APPENDIX E: BALUN INFORMATION .............................................................................................. 38
Typical Balun Frequency Response ......................................................................................................................... 38
APPENDIX F: PROPERLY CONFIGURING LPT PORT ........................................................................ 39
LPT Driver Loading ................................................................................................................................................. 39
Correct LPT Port/Address ........................................................................................................................................ 39
Correct LPT Mode.................................................................................................................................................... 40
APPENDIX G: DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY ....................................... 41
APPENDIXHI: TROUBLESHOOTING INFORMATION .......................................................................... 42
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Table of Figures
Figure 1 - LMK01801 Block Diagram ........................................................................................... 4
Figure 2 - Quick Start Diagram ...................................................................................................... 6
Figure 3 - Pin Control Mode Quick Start Diagram......................................................................... 7
Figure 4 – Selecting the LMK01801 .............................................................................................. 9
Figure 6 – Setting the 122.88 MHz VCXO Default mode ........................................................... 10
Figure 5 - Loading the Device ...................................................................................................... 10
Figure 7 - Setting Divide, CLKout_TYPE, Enabled for CLKout1 on "Clock Outputs" tab. ....... 11
Figure 8 - Setting LVCMOS modes. ............................................................................................ 11
Figure 9 - Port Setup tab ............................................................................................................... 15
Figure 10 - Clock Outputs tab....................................................................................................... 16
Figure 11 - Bits/Pins tab. .............................................................................................................. 17
Figure 12 - LMK01801 Phase Noise @ 100 MHz with Output Divider = 1................................ 20
Figure 13 - LMK01801 Phase Noise @ 100 MHz with Output Divider = 4................................ 21
Figure 14 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 1........................... 22
Figure 15 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 4........................... 23
Figure 16 - Phase Noise Measurement Set-Up ............................................................................. 24
Figure 17 - Noisy vs. Clean Phase Noise...................................................................................... 24
Figure 18 - LMK01801 Sample Clock Output Waveforms.......................................................... 25
Figure 19 - CLKout12 and CLKout13 No Analog Delay............................................................. 26
Figure 20 - CLKout12 with 100 pSec of delay relative to CLKout13.......................................... 27
Figure 21 - Typical Balun Frequency Response ........................................................................... 38
Figure 22 - Successfully Opened LPT Driver............................................................................... 39
Figure 23 - Selecting the LPT Port ............................................................................................... 40
Figure 24 - Two Different Definitions .......................................................................................... 41
Figure 25 - Two Different Definitions .......................................................................................... 41
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General Description
The LMK01801 Evaluation Board simplifies evaluation of the LMK01801 Dual Clock Buffer
Divider. Configuring and controlling the board is accomplished using Texas Instrument’s
CodeLoader software, which can be downloaded from: http://www.ti.com/tool/codeloader. The
LMK01801 can also be configured to operate in a pin control mode via headers on the PCB.
Block Diagram
The block diagram in Figure 1 illustrates the functional architecture of the LMK01801 clock
divider buffer. The LMK01801 is a very low noise solution for clocking systems that require
distribution and frequency division of precision clocks. The LMK01801 features extremely low
residual noise, frequency division, digital and analog delay adjustments, and fourteen (14)
programmable differential outputs: LVPECL, LVDS and LVCMOS (2 outputs per differential
output). The LMK01801 features two independent inputs that can be driven differentially or in
single-ended mode. The first input drives output Bank A consisting of eight (8) outputs. The
second input drives output Bank B consisting of six (6) outputs.
Figure 1 - LMK01801 Block Diagram
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Evaluation Board Kit Contents
The evaluation board kit contains…
 An LMK01801 Evaluation board.
 LMK01801 Family quick start guide.
o Evaluation board instructions are downloadable from the product folder on Texas
Instument’s website, www.ti.com/.
 CodeLoader uWire cable (LPT --> uWire).
 A USB interface board can be purchased separately under NSID USB2UWIRE_IFACE.
The CodeLoader software will run on a Windows 2000 or Windows XP PC. The CodeLoader
software is used to program the internal registers of the LMK01801 device through a
MICROWIRETM interface.
Clock output configuration:
Clock
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Output Type
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
Output Connector Installed
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
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Quick Start – Code Loader Mode
1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate terminal
block.
2. Connect a reference clock from a signal generator or other source. Exact frequency
depends on programming.
3. Connect the uWire header to a computer parallel port with the CodeLoader cable. A
USB communication option is available, search at www.ti.com/ for: USB2UWIREIFACE.
4. Install jumpers on TYPE0, TYPE1, TYPE2, DivVal0, DivVal1, DivVal2 in the middle
‘uWire’ (pins 3,5) position but NOT on EN_PIN_CTRL.
5. Program the device with CodeLoader. Ctrl-L must be pressed at least once to load all
registers once after CodeLoader is started or after restoring a Mode. CodeLoader is
available for download at www.ti.com/tool/codeloader.
6. Measurements may be made at any clock output if enabled by programming.
Figure 2 - Quick Start Diagram
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Quick Start – Pin Control Mode
1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate connector.
2. Connect a reference clock from a signal generator or other source. Exact frequency
depends on programming.
3. Install a jumper on EN_PIN_CTRL header in either the High or Low position.
4. Install other jumpers on Type0, Type1, Type2, DivVal0, DivVal1, and DivVal2 headers
based on the configurations shown in Table 1 and Table 2.
Figure 3 - Pin Control Mode Quick Start Diagram
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Pin Control Modes
For the following tables, Low is defined as installing a jumper between pins 5 and 6 on the
desired header. A HIGH is defined as installing a jumper between pins 1 and 2 on the desired
header.
If EN_PIN_CTRL = LOW (jumper installed between header positions 5 and 6) then the
following table describes possible output configurations:
Header
Type0
Type1
Type2
DivVal0
DivVal1
DivVal2
Output Groups
Header = Low
Header = Middle
CLKout0 – CLKout3
LVDS
Powerdown
CLKout4 – CLKout7
LVDS
LVCMOS (Norm/Inv)
CLKout8 – CLKout13
LVDS
LVCMOS (Norm/Inv)
CLKout0-3 Divider
÷1
÷4
CLKout4-7 Divider
÷1
÷4
CLKout8-11 Divider
÷1
÷4
CLKout12-13 Divider
÷8
÷512
Table 1 - EN_PIN_CTRL = LOW Configuration
Header = High
LVPECL
LVPECL
LVPECL
÷2
÷2
÷2
÷16
If EN_PIN_CTRL = HIGH (jumper installed between header positions 1 and 2) then the
following table describes possible output configurations:
Header
Type0
Type1
Type2
DivVal0
DivVal1
DivVal2
Output Groups
Header = Low
Header = Middle
CLKout0 – CLKout3
LVDS
LVPECL
CLKout4 – CLKout7
LVCMOS (Norm/Inv)
CLKout8 – CLKout11
LVDS
LVCMOS (Norm/Inv)
CLKout12-13
LVDS
LVCMOS (Norm/Inv)
CLKout0-7 Divider
÷1
÷4
CLKout8-11 Divider
÷1
÷4
CLKout12-13 Divider
÷4
÷512
Table 2 - EN_PIN_CTRL = HIGH Configuration
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LMK01801BEVAL Evaluation Board Operating Instructions
Header = High
LVPECL
LVPECL
LVPECL
÷2
÷2
÷16
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Using CodeLoader to Program the LMK01801
The purpose of this section is to walk the user through using CodeLoader to make some
measurements with the LMK01801 device. For more information on CodeLoader refer to
Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.ti.com/tool/codeloader/.
Before proceeding, be sure to follow the Quick Start section above to ensure proper connections.
1. Start CodeLoader 4 Application
Click “Start”  “Programs”  “CodeLoader 4”  “CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
2. Select Device
Click “Select Device”  “Clock Conditioners”  “LMK01801A1”
Once started CodeLoader 4 will load the last used device. To load a new device click “Select
Device” from the menu bar, then select the subgroup and finally device to load. For this
example, the LMK01800A1 is chosen.
Selecting the device does cause the device to
be programmed. However, it is advisable to
do CTRL-L to ensure programming.
Figure 4 – Selecting the LMK01801
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3. Program/Load Device
Press “Ctrl – L”
Assuming the Port Settings are correct, it is now
possible to click “Keyboard Controls”  “Load
Device” from the menu to program the device to the
current state of the newly loaded LMK01801 file. CtrlL is the accelerator assigned to the Load Device option
and is very convenient.
Once the device has been loaded, by default
CodeLoader will automatically program changed
Figure 5 - Loading the Device
registers, so it is not necessary to load the device
again completely. It is possible to disable this functionality by ensuring there is no checkmark
by the “Options”  “AutoReload with Changes.”
Since a default mode will be restored in the next step, this step isn’t really needed but included to
emphasize the importance of pressing “Ctrl-L” to load the device at least once after starting
CodeLoader, restoring a mode, or restoring a saved setup using the File menu.
See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.ti.com/tool/codeloader for more information on port setup. Appendix H:
Troubleshooting Information contains information on troubleshooting communications.
4. Restoring a Default Mode
Click “Mode”  “122.88 MHz VCXO Default”; then
Press “Ctrl – L”
Figure 6 – Setting the 122.88 MHz VCXO Default mode
For the purposes of this walkthrough a default mode will be loaded to ensure a common starting
point. This is important because when CodeLoader is closed, it remembers the last settings used
for a particular device. By loading the default mode a common starting point is ensured.
Loading a mode does not automatically program the device so it is necessary to press
“Ctrl – L” again to program the device.
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5. Enable Clock Outputs
This CLKoutX frequency value is only valid if
the correct clock in value is specified. It may
not necessarily represent the actual frequency
unless manually entered. This is a
mathematical calculation only, not a measured
value.
To measure phase noise at the clock outputs,
1. Click on the “Bank A” tab,
2. Enable an output,
3. Then set the
a. CLKout Type,
b. divide value
Figure 7 - Setting Divide, CLKout_TYPE, Enabled for CLKout1 on "Clock Outputs" tab.
4. Connect the clock output SMAs to a spectrum analyzer or signal source analyzer.
a. For LVDS, a balun is recommended such as the ADT2-1T (for frequency range of
0.4 MHz to 450 MHz).
b. For LVPECL,
i. A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50 ohm load and
the other side can be run to the test equipment
single ended.
c. For LVCMOS,
i. One side of the LVCMOS signal can be
terminated with a 50 ohm load and the other
side can be run to the test equipment single
ended.
5. The phase noise may be measured with a spectrum analyzer
Figure 8 - Setting
or signal source analyzer.
LVCMOS modes.
See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock
outputs.
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Evaluation Board Inputs/Outputs
The following table contains descriptions of the various inputs and outputs for the evaluation
board.
Table 3. LMK01801 Evaluation Board I/O
Connector Name
CLKout0 /
CLKout0*,
CLKout2 /
CLKout2*,
CLKout4 /
CLKout4*,
CLKout6 /
CLKout6*,
CLKout8 /
CLKout8*,
CLKout9/
CLKout9*,
CLKout10 /
CLKout10*,
CLKout11/
CLKout11*,
CLKout12 /
CLKout12*,
CLKout13 /
CLKout13*
Input/Output Description
Populated connectors.
Differential clock output pairs. All outputs are configured
in LVPECL mode.
On the evaluation board, all clock outputs are AC-coupled
to allow safe testing with RF test equipment.
 All LVPECL/2VPECL clock outputs are
terminated to GND with a 240 ohm resistor, one on
each output pin of the pair.
Output
Populated connector.
Vcc
Input
DC power supply for the PCB. Removing R1, R2, or R3
allow for splitting the power to various devices on the
board.
Note: The LMK01801 Family contains internal voltage
regulators for the VCO, PLL and related circuitry. The
clock outputs do not have an internal regulator. A clean
power supply is required for best performance.
Unpopulated connector.
Vcc2
Input
Vcc input to power the output planes separately from the
Aux Plane. Refer to schematics for more information.
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Connector Name
CLKin0/CLKin0*,
CLKin1/CLKin1*
Input/Output Description
Populated connectors.
Input
The default board configuration is setup for a single-ended
reference source at CLKin0* (CLKin0 pin is AC-coupled
to ground).
If a DC-coupled clock is used to drive either of the inputs,
the high voltage level must be at least 2 volts and the low
voltage no greater than 0.4 volts.
Populated connector.
uWire
Input/Output
SYNC0,
SYNC1
Input
10-pin header programming interface for the board. Of
Most important are the CLKuWire, DATAuWire, and
LEuWire programming lines from this header. Each of
these signals, TEST, and SYNC0, and SYNC1 can be
monitored through test points on the board.
Unpopulated connector.
Access to SYNC0 or SYNC1 of device.
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Recommended Test Equipment
Power Supply
The Power Supply should be a low noise power supply.
Phase Noise / Spectrum Analyzer
For measuring phase noise an Agilent E5052A Signal Source Analyzer is recommended. An
Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the
architecture of the E5052A is superior for phase noise measurements. At frequencies less than
100 MHz the local oscillator noise of the E4445A is too high and measurements will reflect the
E4445A’s internal local oscillator performance, not the device under test.
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Appendix A: CodeLoader Usage
CodeLoader is used to program the evaluation board with either an LPT port using the included
CodeLoader cable or with a USB port using the optional USB <--> uWire cable available from
http://www.ti.com/. The part number is USB2UWIRE-IFACE.
Port Setup Tab
Figure 9 - Port Setup tab
On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that
will be used to program the device on the evaluation board. If parallel port is selected, the user
should ensure that the correct port address is entered.
The Pin Configuration field is hardware dependent and normally SHOULD NOT be changed by
the user. Figure 9 shows the default settings.
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Clock Outputs Tab
Figure 10 - Clock Outputs tab
The clock outputs tab allows the user to Enable/Disable individual clock outputs, select the clock
mode (Bypass/Divided/Delayed/Divided & Delayed – for outputs 12 and 13), set the clock
output delay value (if delay is enabled for outputs 12 and 13 only), and the clock output divider
value (2, 4, 6, …, 510 for clock outputs 12 and 13 or 1-8 for clock outputs 0 - 11).
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Bits/Pins Tab
Figure 11 - Bits/Pins tab.
The Bits/Pins tab allows the user to program bits directly. Many of which are not available on
other tabs. Refer to the datasheet for more detailed information. The bits available are:
 Common Box
o RESET - Set the reset bit. This will reset the device. In a normal application it is
not necessary to program this bit clear since it is auto-clearing. However in the
CodeLoader software, RESET must be clicked again (cleared) to not cause a reset
every time R7 is programmed.
o POWERDOWN - Place the device in powerdown mode.

Program Pins Box – These pins only have effect if the PWB headers are in the uWire
position (3-5). See Figure 2 - Quick Start Diagram for the correct configuration.
o EN_PIN_CTRL – Sets the control of the output via uWire or pins
o SYNC0 – Set high or low voltage on SYNC0 pin. Checked is high voltage.
o TRIGGER – Set high or low voltage on pin 10 of uWire header.
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Registers Tab
The registers tab shows the value of each register. This is convenient for programming the
device to the desired settings, then recording the hex values for programming in your own
application. The “Export register values in hex to text file” button will allow these register
values to be saved to a text file.
By clicking in the “bit field” it is possible to manually change the value of registers by typing ‘1’
and ‘0.’
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Appendix B: Typical Phase Noise Performance Plots
Clock Outputs
The LMK01801 Family features LVDS, LVPECL, 2VPECL, and LVCMOS types of outputs.
Include are the phase noise plots for the following outputs.
Device
LMK01801A1
LMK01801A1
LMK01801A1
LMK01801A1
LMK01801A1
LMK01801A1
LMK01801A1
LMK01801A1
CLKoutX
8
8
8
8
4
4
4
4
Output Divide
1
4
1
4
1
4
1
4
Output Type
LVPECL
LVPECL
2VPECL
2VPECL
LVDS
LVDS
LVCMOS(Norm/Inv)
LVCMOS(Norm/Inv)
Table 4 - Phase Noise Output Test Configuration
Clock Output Measurement Technique
The measurement technique for each output type varies.
LVPECL/2VPECL – Measured by using an Minicircuits ADT2-1T balun on the input and on the
output.
LVCMOS and LVDS – Measured by using an Minicircuits ADT2-1T balun on the output and
single ended input.
Parameter
Input Source
Test Case 1
Wenzel XTAL
Test Case 2
Wenzel XTAL
Test Case 3
SMHU
Input Frequency
Input Power
Output Divider
Figure
100 MHz
0 dBm
1
Figure 12
100 MHz
0 dBm
4
Figure 13
983.04 MHz
0 dBm
1
Figure 14
Table 5 - LMK01801 test conditions
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LMK01801BEVAL Evaluation Board Operating Instructions
Test Case 4
Rohde&Schwarz
SMHU
983.04 MHz
0 dBm
4
Figure 15
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LMK01801 Phase Noise, CLKin = 100 MHz, Output Divider = 1
Phase Noise with Output Divider = 1
‐80
‐90
‐100
Wenzel 100 MHz XTAL
‐110
CLKout8_2VPECL
‐120
CLKout8_LVPECL
‐130
CLKout4_LVDS
‐140
CLKout4_LVCMOS(NORM/INV)
‐150
‐160
‐170
‐180
10.0E+0
1.0E+3
100.0E+3
10.0E+6
Figure 12 - LMK01801 Phase Noise @ 100 MHz with Output Divider = 1
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LMK01801 Phase Noise, CLKin = 100 MHz, Output Divider = 4
Phase Noise with Output Divider = 4
‐80
‐90
‐100
‐110
Wenzel 100 MHz XTAL
‐120
CLKout8_2VPECL
‐130
CLKout8_LVPECL
CLKout4_LVDS
‐140
CLKout4_LVCMOS(NORM/INV)
‐150
‐160
‐170
‐180
10.0E+0 100.0E+0
1.0E+3
10.0E+3 100.0E+3
1.0E+6
Figure 13 - LMK01801 Phase Noise @ 100 MHz with Output Divider = 4
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LMK01801 Phase Noise, CLKin = 983.04 MHz, Output Divider = 1
Phase Noise with Divider = 1
‐60
‐80
‐100
LVDS /1
LVCMOS /1
‐120
2VPECL /1
LVPECL /1
‐140
SMHU
‐160
‐180
10.0E+0
100.0E+0
1.0E+3
10.0E+3
100.0E+3
1.0E+6
10.0E+6
Figure 14 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 1
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LMK01801 Phase Noise, CLKin = 983.04 MHz, Output Divider = 4
Phase Noise with Divider = 4
‐60
‐80
‐100
LVDS /4
LVCMOS /4
‐120
2VPECL /4
LVPECL /4
‐140
SMHU
‐160
‐180
10.0E+0
100.0E+0
1.0E+3
10.0E+3
100.0E+3
1.0E+6
10.0E+6
Figure 15 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 4
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Phase Noise Measurement
Power
Supply
!
Signal
Source
LMK01801
RF Output @
1 GHz, 0dBm
CLKin0 or
CLKin1
CLKoutX /
CLKoutX *
Agilent
5052A
Figure 16 - Phase Noise Measurement Set-Up
The phase noise of the signal source will impact the measured phase noise of the LMK01801.
Noisy Signal
Source!
Clean Signal
Source!
Figure 17 - Noisy vs. Clean Phase Noise
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LMK01801 Sample Output Waveforms
A
B
C
D
Figure 18 - LMK01801 Sample Clock Output Waveforms
The output waveforms shown in Figure 18 were taken at a clock in frequency of 122.88 MHz,
AC coupled. These measurements follow the VID voltage convention – See Appendix G:
Differential Voltage Measurement Terminology for more information.
The output modes are as follows:
Trace
Clock Output
A
CLKout0
B
CLKout1
C
CLKout4
D
CLKout5
Output Type
2VPECL
PECL (Low Power)
LVDS
LVCMOS (Normal/Invert)
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LMK01801 Analog Delay Sample Data
The sample analog delay data was taken at a clock in frequency of 122.88 MHz, output format of 2VPECL. Notice in Figure 19 that
with analog delay enabled there is approximately 460 ps of delay. Then in Figure 20 we added 100 ps of delay and the resulting delay
is approximately 550 ps.
Figure 19 - CLKout12 and CLKout13 No Analog Delay
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Figure 20 - CLKout12 with 100 pSec of delay relative to CLKout13
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Appendix C: Schematics
Power
1
Vcc
Vcc
2
R329
VccCLKoutPlaneA
Vcc2
TESTPOINT 1000
SMA
R332
A
J1
1
2
3
4
5
6
Direct Power
VccTP
TERMBLOCK_2
C313
1µF
C314
0.1µF
C319
10µF
C320
1µF
C321
0.1µF
C54
10µF
C55
1µF
C56
0.1µF
DNP
R330
DNP
1000
VccCLKoutPlaneA
VccCLKoutPlaneA
0
C318
0.1µF
VccCLKoutPlaneB
R333
DNP
1000
DNPC322 DNPC323 DNPC324
10µF
1µF
0.1µF
R334
1000
R335
C325
1µF
C326 DNPC327
0.1µF
0.01µF
C328
1µF
C329 DNPC330
0.1µF
0.01µF
0
1000
R336
1000
R337
0
R338
V_LM3878-ADJA
U300
4
51k
DNPC335
4.7µF
8
2
7
9
IN
SD
OUT
ADJ
NC
BYP
NC
DAP GND
5
6
C333
2200pF
1
R343
2.00k
DNPC334
10µF
VccCLKoutPlaneA
R341
DNP
1000
DNPC332
1µF
A
GND Vcc1_CLKout_CG0
CG0
DNPC357
100pF
C337
0.01µF
CG1
DNPC362
100pF
GND
Vcc8_Digital
Digital
C353
0.1µF
B
Vcc6_CLKin1
R344
DNPC336
0.1µF
LDO_OutA
TESTPOINT
R345
866
GND Vcc3_CLKout_CG1
GND
VccCLKoutPlaneB
3
LP3878SD-ADJ
0
DNPC331
0.1µF
LDO Power Options
R342
B
CLKin0
DNPC361
100pF
VccAuxPlane
R179
R339
R340
DNP
DNP
0
0
Vcc2_CLKin0
R331
DNPC315 DNPC316 DNPC317
10µF
1µF
0.1µF
SMA
VccCLKoutPlaneB
1000
1
2
C312
10µF
1000
C355
100pF
CLKin1
GND
Vcc10_CG3_p47
R346
1000
R348
DNP
1000
LP3878-ADJ 3.3 V component values:
C350 = 4.7 uF
R350= 2.00 k
C354 = 0.01 uF
R351= 866
C352 = 10 uF
R349= 51 k
C351 = 2.2 nF
VccAuxPlane
C341
1µF
LP3878SD-ADJ
V_LM3878-ADJB
4
C
R353
51k
C349
4.7µF
8
2
7
9
IN
OUT
SD
ADJ
NC
BYP
NC
DAP GND
5
6
C346
2200pF
1
R354
2.00k
C347
10µF
C339 DNPC340
0.1µF
0.01µF
Vcc13_CG0_p64
R349
1000
U301
C338
1µF
C342
1µF
C343 DNPC344
0.1µF
0.01µF
VccCLKoutPlaneB
R351
DNP
1000
C345
1µF
0
R350
0
R352
C348
0.1µF
Vcc5_CLKout_CG2
R347
0
DNPC356
100pF
CG2
GND Vcc7_CLKout_CG3
DNPC354
100pF
GND
CG3
Vcc4_Bias
DNPC360
100pF
C
Bias
3
C350
0.01µF
LP3878SD-ADJ
LDO_OutB
TESTPOINT
R355
866
GND
VccAuxPlane
LP5900SD-3.3
R356
0
C351
0.47µF
R357
51k
D
4
7
IN
LDO_LP5900
V_LM5900
U302
6
OUT
EN
NC
NC
DAP GND
1
C352
0.47µF
2
5
3
1
Designators greater than and equal to 300 are placed on bottom of PCB
D
LP5900SD-3.3
LP5900 Component values
C367 = 0.47 uF
C368 = 0.47 uF
R359 = 51 k
TESTPOINT
Populate R215 and Open R227
to use low-noise LP5900
regulator option to power CG1
and CG2 supply planes.
GND
2
National Semiconductor and/or its licensors do not warrant the accuracy or completeness of
this specification or any information contained therein. National and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit
for any particular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the design is production worthy. You should completely validate and test
your design implementation to confirm the system functionality for your application.
3
4
Designed for: Evaluation Customer
Mod. Date: 10/25/2011
Project: LMK01801 SVB
Sheet Title: Power Supplies
Sheet: 3 of 9
Size: B
Schematic: 870xxxxxx
Rev: 1.0
Assembly Variant: Version1
http://www.national.com
File: Power.SchDoc
Contact: http://www.national.com/support
© Copyright, National Semiconductor, 2009
5
28
LMK01801BEVAL Evaluation Board Operating Instructions
6
LMK01801BEVAL schematic.
Refer to BOM for differences.
SNAU118
Main
1
2
3
4
5
6
IC_SYNC1
Vcc8_Digital
Vcc7_CLKout_CG3
R310
Vcc6_CLKin1
51.0
GND
A
A
CLKin1_P
37
Vcc6_CLKin1
CLKin1_N
38
CLKin1
40
39
CLKin1*
SYNC1/CLKoutTYPE2
CLKout12_P
41
CLKout12_N
42
CLKout12
CLKout13_N
43
CLKout12*
CLKout13_P
46
47
45
CLKout13*
CLKout13
Vcc8_DIG
Vcc7_CLKout13/12
CLKout9*
CLKout2*
CLKout8*
0
CLKout3*
DAP PAD
CLKout8
CLKout3
EN_PIN_CTRL
Test/CLKoutTYPE0
Bias
SYNC0/CLKoutTYPE1
Vcc2_CLKin0
CLKout5
CLKout5_P
19
CLKout5*
18
CLKout5_N
CLKout4*
17
CLKout4_N
CLKout4
16
CLKout4_P
14
CLKin0_N
15
13
CLKin0_P
CLKin0
GND
CLKin0*
C
Vcc2_CLKin0
R318
51.0
Vcc4_Bias
CLKout11_N
34
CLKout10_N
33
CLKout10_P
B
32
Vcc5_CLKout_CG2
31
CLKout9_P
30
CLKout9_N
29
CLKout8_N
28
CLKout8_P
27
IC_EN_PIN_CTRL
26
25
DNPC358
1µF
C359
1µF
CLKout7
IC_SYNC0
CLKout2
CLKout11_P
35
GND
C
Vcc4_Bias
24
12
CLKout9
LMK01801
36
CLKout7_P
11
IC_TEST
Vcc5_CLKout8_9_10_11
Vcc1_CLKout0_1_2_3
CLKout7*
CLKout3_P 10
CLKout1
CLKout7_N 23
CLKout3_N 9
CLKout10
CLKout6*
CLKout2_N 8
CLKout1*
CLKout6
CLKout2_P 7
CLKout10*
21
6
CLKout0*
CLKout6_N 22
CLKout1_P 5
Vcc1_CLKout_CG0
CLKout11
CLKout11*
CLKout6_P
CLKout1_N 4
U1
LMK01801
CLKout0
Vcc3_CLKout4_5_6_7
CLKout0_N 3
LEuWire/CLKoutDIV2
20
CLKout0_P 2
CLKuWire/CLKoutDIV1
1
IC_uWireLE
B
DATAuWire/CLKoutDIV0
48
IC_uWireCLK
44
IC_uWireDATA
Vcc3_CLKout_CG1
D
D
Designators greater than and equal to 200 are placed on bottom of PCB
1
2
National Semiconductor and/or its licensors do not warrant the accuracy or completeness of
this specification or any information contained therein. National and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit
for any particular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the design is production worthy. You should completely validate and test
your design implementation to confirm the system functionality for your application.
3
4
Mod. Date: 10/25/2011
Designed for: Evaluation Customer
Project: LMK01801 SVB
Sheet Title: Main Sheet / IC
Sheet: 4 of 9
Size: B
Schematic: 870xxxxxx
Rev: 1.0
Assembly Variant: Version1
http://www.national.com
File: LMK01800_Core.SchDoc
Contact: http://www.national.com/support
© Copyright, National Semiconductor, 2009
5
29
LMK01801BEVAL Evaluation Board Operating Instructions
6
SNAU118
Inputs
1
2
3
4
CLKin0
V_LM5900
R301
SMA
0
C304
0.1µF
DNPC300
0.68µF
TESTPOINT
C301
0.1µF
2
3
R302
39k
R303
1000
R304
DNP
0
R305
0
VCXO_GND
R2
1000
CLKin0*
CLKin0_4_N
U2
1
Vtune Vcc
NC DNP NC
GND OUT
6
5
C302
0.1µF
C5
1µF
R4
CLKin0_3_N
DNPC3
0.1µF
C303
10µF
CLKin0_2_N
0
0
SMA
C4
100pF
R1
DNP
0
R3
3
4
2
1
VCXO_GND
PD
CLKin0_N
0
S
NC DNPSCT
P
C1
R5
R6
DNP
270
B1
CVHD-950-122.88
122.88 MHz VCXO
SD
4
DNP
SMA
CLKin0_4_P R10
0
5
6
R8
DNP
100
R11
CLKin0_3_P
R13
DNP
0
A
0.1µF DNPC2
0.1µF
R7
51.0
BALUN - ADT2-1T
CLKin0
R9
DNP
33
GND
6
VccCLKoutPlaneA
R300
DNP
0
VtuneTP
Vtune
A
5
GND
CLKin0_2_P
0
C6
R12
DNP
0
R14
DNP
270
DNP
0.1µF
R15
DNP
270
CLKin0_P
C7
0.1µF
GND
VCXO_GND
GND
B
B
CLKin1
C
C
CLKin1*
SMA
R16
CLKin1_2_N
0
CLKin1
CLKin1_N
0
R18
DNP
270
SMA
C8
R17
R21
CLKin1_2_P
0
0.1µF DNPC9
0.1µF
R19
DNP
51.0
R20
100
C10
R22
CLKin1_P
0
R23
DNP
270
R24
DNP
270
0.1µF DNPC11
0.1µF
D
D
National Semiconductor and/or its licensors do not warrant the accuracy or completeness of
this specification or any information contained therein. National and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit
for any particular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the design is production worthy. You should completely validate and test
your design implementation to confirm the system functionality for your application.
1
2
3
4
Mod. Date: 6/10/2011
Designed for: Evaluation Customer
Project: LMK01801 SVB
Sheet Title: Clock Inputs
Sheet: 6 of 9
Size: B
Schematic: 870xxxxxx
Rev: 1.0
Assembly Variant: Version1
File: InClks.SchDoc
http://www.national.com
Contact: http://www.national.com/support
© Copyright, National Semiconductor, 2009
5
30
LMK01801BEVAL Evaluation Board Operating Instructions
6
SNAU118
Inputs Page 2
1
2
3
VccCLKoutPlaneB
VccCLKoutPlaneA
LEuWire_TP
TESTPOINT
IC_SYNC1
R307
DNP
27k
A
uWire_SYNC1
TYPE2
2
4
6
R309
15k
R312
27k
5
1
3
5
SYNC1_TP
TESTPOINT
IC_uWireLE
SYNC1
VccCLKoutPlaneA
R306
DNP
27k
R308
DivVal2
1
3
5
2
4
6
HEADER_2X3
SMA
A
15k
DNP
DNPC305
33pF
HEADER_2X3
DNPC306
33pF
R311
27k
Placehold for 50 ohm resistor
cose to IC on Core Schematic
page.
uWire_CLK
or DivValue1
CLKuWire_TP
VccCLKoutPlaneA
For use with high frequency
SYNC signals.
TESTPOINT
IC_uWireCLK
SYNC0 or OutType1
VccCLKoutPlaneA
6
uWire Header and Level Translation
uWire_LE or DivValue2
SYNC1 or OutType2
VccCLKoutPlaneB
4
VccCLKoutPlaneA
uWire
R313
DNP
27k
R314
DivVal1
1
3
5
2
4
6
15k
DNPC307
33pF
HEADER_2X3
VccCLKoutPlaneA
uWire_TEST
uWire_LE
uWire_CLK
uWire_DATA
10
8
6
4
2
9
7
5
3
1
uWire_SYNC0
uWire_EN_PIN_CTRL
uWire_SYNC1
HEADER_2X5
R315
27k
IC_SYNC0
R316
DNP
27k
B
uWire_SYNC0
TYPE1
2
4
6
R317
15k
1
3
5
SYNC0_TP
TESTPOINT
uWire_DATA or DivValue0
SYNC0
VccCLKoutPlaneA
DATAuWire_TP
TESTPOINT
DNP
SMA
R320
27k
HEADER_2X3
DNPC308
33pF
Placehold for 50 ohm resistor
cose to IC on Core Schematic
page.
IC_uWireDATA
VccCLKoutPlaneA
1
3
5
2
4
6
HEADER_2X3
For use with high frequency
SYNC signals.
B
R319
DNP
27k
R321
DivVal0
15k
DNPC309
33pF
R322
27k
Test or OutType0
VccCLKoutPlaneA
VccCLKoutPlaneA
R323
DNP
27k
uWire_TEST
2
4
6
R324
15k
R325
27k
C
TEST_TP
TESTPOINT
IC_TEST
TYPE0
1
3
5
HEADER_2X3
C
DNPC310
33pF
Enable Pin Control
VccCLKoutPlaneB
VccCLKoutPlaneB
R326
DNP
27k
uWire_EN_PIN_CTRL
R327
15k
R328
27k
D
EN_PIN_CTRL_TP IC_EN_PIN_CTRL
TESTPOINT
EN_PIN_CONTROL
2
1
4
3
6
5
HEADER_2X3
D
DNPC311
33pF
National Semiconductor and/or its licensors do not warrant the accuracy or completeness of
this specification or any information contained therein. National and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit
for any particular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the design is production worthy. You should completely validate and test
your design implementation to confirm the system functionality for your application.
1
2
3
4
Mod. Date: 10/25/2011
Designed for: Evaluation Customer
Project: LMK01801 SVB
Sheet Title: Interface
Sheet: 5 of 9
Size: B
Schematic: 870xxxxxx
Rev: 1.0
Assembly Variant: Version1
http://www.national.com
File: LogicIO.SchDoc
Contact: http://www.national.com/support
© Copyright, National Semiconductor, 2009
5
31
LMK01801BEVAL Evaluation Board Operating Instructions
6
SNAU118
Clock Outputs Page 1
1
2
3
4
5
6
A
A
CLKout0
CLKout1
Default: LVPECL, AC coupled
VccCLKoutPlaneA
R25
DNP
120
VccCLKoutPlaneA
R26
DNP
82.0
R27
DNP
51.0
R28
DNP
120
CLKout0_1_P
CLKout0_P
R32
DNP
62
0.1µF
R37
DNP
62
GND
SMA
GND
R38
DNP
62
GND
CLKout0*
R43
DNP
51.0
SMA
GND
R48
DNP
82.0
R54
DNP
62
0.1µF
R59
DNP
62
R46
51.0
SMA
B
Default: LVPECL, AC coupled
R50
DNP
120
R52
51.0
R57
CLKout3*
C19
CLKout3_1_N
CLKout3_N
R55
240
SMA
R56
DNP
62
0.1µF
DNP
R58
SMA
68
C20
68
C21
DNP
DNP
R60
DNP
62
GND
0.1µF
CLKout2*
CLKout2_1_N
0.1µF
R65
DNP
51.0
SMA
VccCLKoutPlaneA
C
CLKout3
C23
CLKout3_1_P
CLKout3_P
0.1µF
R64
DNP
82.0
R51
DNP
82.0
CLKout2
C22
CLKout2_N
GND
R45
DNP
82.0
VccCLKoutPlaneA
R49
DNP
51.0
CLKout2_P
R63
DNP
120
R44
DNP
120
CLKout3
CLKout2_1_P
R61
240
CLKout1
CLKout1_1_P
DNP
0.1µF
VccCLKoutPlaneA
C18
GND
0.1µF
C17
R40
240
Default: LVPECL, AC coupled
C
SMA
CLKout1_P
VccCLKoutPlaneA
R53
240
R36
DNP
VccCLKoutPlaneA
R47
DNP
120
DNP
68
C15
0.1µF
CLKout2
0.1µF
DNP
CLKout0_1_N
B
R34
DNP
62
0.1µF
R42
DNP
82.0
CLKout1*
CLKout1_1_N
R33
240
68
C14
C16
R41
DNP
120
R30
51.0
C13
CLKout1_N
R35
CLKout0_N
R39
240
R29
DNP
82.0
CLKout0
C12
R31
240
Default: LVPECL, AC coupled
R62
240
GND
DNP
0.1µF
R66
DNP
120
R67
DNP
82.0
R68
51.0
SMA
VccCLKoutPlaneA
D
D
Notes:
National Semiconductor and/or its licensors do not warrant the accuracy or completeness of
this specification or any information contained therein. National and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit
for any particular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the design is production worthy. You should completely validate and test
your design implementation to confirm the system functionality for your application.
1. Designators greater than and equal to 300 are placed on bottom of PCB
1
2
3
4
Designed for: Evaluation Customer
Mod. Date: 6/10/2011
Project: LMK01801 SVB
Sheet Title: Clock Outputs 1/3
Sheet: 7 of 9
Size: B
Schematic: 870xxxxxx
Rev: 1.0
Assembly Variant: Version1
http://www.national.com
File: OutClks0.SchDoc
Contact: http://www.national.com/support
© Copyright, National Semiconductor, 2009
5
32
LMK01801BEVAL Evaluation Board Operating Instructions
6
SNAU118
Clock Outputs Page 2
1
2
3
CLKout4
A
4
CLKout5
Default: LVPECL, AC coupled
VccCLKoutPlaneA
R69
DNP
120
6
Default: LVPECL, AC coupled
A
VccCLKoutPlaneA
R70
DNP
82.0
C24
R71
DNP
51.0
R72
DNP
120
R73
DNP
82.0
CLKout4
CLKout4_1_P
CLKout4_P
R75
240
5
0.1µF
R78
DNP
62
R79
R74
51.0
CLKout5_1_N
R76
240
SMA
R77 0.1µF
DNP
62
68
C26
CLKout4*
GND
B
0.1µF
R86
DNP
82.0
R85
DNP
120
R87
DNP
51.0
SMA
GND
R88
DNP
120
R89
DNP
82.0
R90
51.0
CLKout7
R92
DNP
82.0
C30
R93
DNP
51.0
B
Default: LVPECL, AC coupled
R94
DNP
120
R95
DNP
82.0
CLKout6
CLKout6_1_P
0.1µF
R100
DNP
62
R101
R96
51.0
R98
240
SMA
R99 0.1µF
DNP
62
CLKout6*
CLKout6_1_N
R105
240
GND
D
R107
DNP
120
R103
DNP
62
C35
GND
0.1µF
CLKout6_N
0.1µF
R108
DNP
82.0
R109
DNP
51.0
R102
SMA
68
C33
DNP
R104
DNP
62
C34
CLKout7*
CLKout7_1_N
DNP
C31
CLKout7_N
68
C32
GND
SMA
VccCLKoutPlaneA
CLKout6_P
C
CLKout5
DNP
0.1µF
VccCLKoutPlaneA
Default: LVPECL, AC coupled
R97
240
0.1µF
CLKout5_1_P
R84
240
VccCLKoutPlaneA
R91
DNP
120
SMA
C29
CLKout5_P
VccCLKoutPlaneA
CLKout6
R80
DNP
R82
DNP
62
GND
0.1µF
CLKout4_1_N
R83
240
DNP
68
C27
DNP
R81
DNP
62
C28
GND
CLKout4_N
CLKout5*
C25
CLKout5_N
CLKout7_P
R106
240
SMA
VccCLKoutPlaneA
GND
R110
DNP
120
0.1µF
R111
DNP
82.0
DNP
C
0.1µF
CLKout7
CLKout7_1_P
DNP
R112
51.0
SMA
VccCLKoutPlaneA
Notes:
D
1. Designators greater than and equal to 300 are placed on bottom of PCB
1
2
National Semiconductor and/or its licensors do not warrant the accuracy or completeness of
this specification or any information contained therein. National and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit
for any particular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the design is production worthy. You should completely validate and test
your design implementation to confirm the system functionality for your application.
3
4
Mod. Date: 6/10/2011
Designed for: Evaluation Customer
Project: LMK01801 SVB
Sheet Title: Clock Outputs 2/3
Sheet: 8 of 9
Size: B
Schematic: 870xxxxxx
Rev: 1.0
Assembly Variant: Version1
http://www.national.com
File: OutClks1.SchDoc
Contact: http://www.national.com/support
© Copyright, National Semiconductor, 2009
5
33
LMK01801BEVAL Evaluation Board Operating Instructions
6
SNAU118
Clock Outputs Page 3
1
2
3
4
5
VccCLKoutPlaneB
CLKout8
Default: LVPECL, AC coupled
R113
DNP
120
VccCLKoutPlaneB
R114
DNP
82.0
CLKout9
R115
DNP
51.0
CLKout8_1_P
CLKout8_P
R119
240
R120 0.1µF
DNP
62
Default: LVPECL, AC coupled
R116
DNP
120
CLKout8
C36
A
6
R121
240
R1220.1µF
DNP
62
68
C38
CLKout8*
CLKout8_1_N
R127
240
0.1µF
R130
DNP
120
R126
DNP
62
C41
GND
0.1µF
C40
CLKout8_N
R131
DNP
82.0
CLKout9*
CLKout9_1_N
DNP
R124
SMA
A
68
C39
DNP
R125
DNP
62
GND
R118
51.0
CLKout9_N
SMA
R123
R117
DNP
82.0
C37
DNP
0.1µF
CLKout9
CLKout9_1_P
DNP
CLKout9_P
R128
240
SMA
R132
DNP
51.0
R129
DNP
120
0.1µF
R133
DNP
82.0
R134
51.0
SMA
VccCLKoutPlaneB
GND
VccCLKoutPlaneB
GND
VccCLKoutPlaneB
B
CLKout10
Default: LVPECL, AC coupled
R135
DNP
120
VccCLKoutPlaneB
R136
DNP
82.0
CLKout11
R137
DNP
51.0
Default: LVPECL, AC coupled
R138
DNP
120
CLKout10
C42
CLKout10_1_P
CLKout10_P
R139
DNP
82.0
C43
CLKout11_N
R141
240
R142 0.1µF
DNP
62
SMA
R143
240
R145
R1440.1µF
DNP
62
68
C44
GND
R147
DNP
62
C46
R148
DNP
62
C47
GND
0.1µF
CLKout10*
CLKout10_1_N
CLKout11_P
R149
240
0.1µF
R151
DNP
120
GND
R152
DNP
82.0
SMA
R150
240
R153
DNP
51.0
VccCLKoutPlaneB
C
R154
DNP
120
GND
Default: LVPECL, AC coupled
R157
DNP
120
0.1µF
R155
DNP
82.0
CLKout13
R159
DNP
51.0
Default: LVPECL, AC coupled
R160
DNP
120
CLKout12
C48
CLKout12_1_P
R164 0.1µF
DNP
62
R161
DNP
82.0
C49
R169
DNP
62
R165
240
R1660.1µF
DNP
62
CLKout12*
0.1µF
R174
DNP
82.0
R172
240
SMA
R175
DNP
51.0
VccCLKoutPlaneB
GND
National Semiconductor and/or its licensors do not warrant the accuracy or completeness of
this specification or any information contained therein. National and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit
for any particular purpose, or will operate in an implementation. National and/or its licensors
do not warrant that the design is production worthy. You should completely validate and test
your design implementation to confirm the system functionality for your application.
1. Designators greater than and equal to 300 are placed on bottom of PCB
2
R162
DNP
51.0
CLKout13*
R168
SMA
3
DNP
0.1µF
CLKout13
CLKout13_1_P
CLKout13_P
Notes:
1
R170
DNP
62
C53
GND
0.1µF
CLKout12_1_N
GND
D
SMA
68
C51
DNP
C52
CLKout12_N
R173
DNP
120
R156
51.0
CLKout13_1_N
SMA
R167
68
C50
R171
240
CLKout11
CLKout11_1_P
DNP
C
CLKout13_N
GND
0.1µF
VccCLKoutPlaneB
R158
DNP
82.0
CLKout12_P
R163
240
DNP
VccCLKoutPlaneB
VccCLKoutPlaneB
CLKout12
B
CLKout11*
CLKout11_1_N
DNP
SMA
R146
68
C45
DNP
CLKout10_N
R140
51.0
4
R176
DNP
120
0.1µF
R177
DNP
82.0
R178
DNP
51.0
SMA
VccCLKoutPlaneB
D
Mod. Date: 6/10/2011
Designed for: Evaluation Customer
Project: LMK01801 SVB
Sheet Title: Clock Outputs 3/3
Sheet: 9 of 9
Size: B
Schematic: 870xxxxxx
Rev: 1.0
Assembly Variant: Version1
File: OutClks2.SchDoc
http://www.national.com
Contact: http://www.national.com/support
© Copyright, National Semiconductor, 2009
5
34
LMK01801BEVAL Evaluation Board Operating Instructions
6
SNAU118
Appendix D: Bill of Materials
Common Bill of Materials for Evaluation Boards
Item
Designator
Description
RoHS
Manufacturer
PartNumber
Quantity
CAPACITORS
1
C1, C7, C8, C10, C12,
C13, C16, C17, C18,
C19, C22, C23, C24,
C25, C28, C29, C30,
C31, C35, C36, C37,
C40, C41, C42, C43,
C46, C47, C48, C49,
C52, C53, C56, C301,
C302, C304, C314,
C321
CAP, CERM, 0.1uF, 25V, +/-5%, X7R, 0603
Y
Kemet
C0603C104J3RACTU
37
2
C4
CAP, CERM, 100pF, 50V, +/-5%, C0G/NP0,
0603
Y
Kemet
C0603C101J5GACTU
1
CAP, CERM, 1uF, 10V, +/-10%, X5R, 0603
Y
Kemet
C0603C105K8PACTU
5
CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603
Y
Kemet
C0603C104K3RACTU
5
3
4
C5, C55, C313, C320,
C359
C34, C326, C329,
C339, C343
5
C54, C303, C312, C319
CAP, CERM, 10uF, 10V, +/-10%, X5R, 0805
Y
Kemet
C0805C106K8PACTU
4
6
CAP, CERM, 0.68uF, 10V, +80/20%, Y5V, 0603
Y
Kemet
C0603C684Z8VACTU
1
CAP, CERM, 0.1uF, 16V, +/-10%, X7R, 0603
Y
TDK
C1608X7R1C104K
4
8
9
10
11
C300
C318, C331, C336,
C348
C332, C341, C345
C333, C346
C334, C347
C335, C349
Y
Y
Y
Y
TDK
AVX
Kemet
Kemet
C1608X7R1C105K
06031C222JAT2A
C0805C106M8PACTU
C0603C475K8PACTU
3
2
2
2
12
C337, C350
Y
TDK
C1608C0G1E103J
2
13
14
C340, C344
C351, C352
CAP, CERM, 1uF, 16V, +/-10%, X7R, 0603
CAP, CERM, 2200pF, 100V, +/-5%, X7R, 0603
CAP, CERM, 10uF, 10V, +/-20%, X5R, 0805
CAP, CERM, 4.7uF, 10V, +/-10%, X5R, 0603
CAP, CERM, 0.01uF, 25V, +/-5%, C0G/NP0,
0603
CAP, CERM, 0.01uF, 100V, +/-10%, X7R, 0603
CAP, CERM, 0.47uF, 25V, +/-10%, X7R, 0603
Y
Y
Kemet
MuRata
C0603C103K1RACTU
GRM188R71E474KA12D
2
2
7
35
LMK01801BEVAL Evaluation Board Operating Instructions
SNAU118
Item
Designator
Description
RoHS
Manufacturer
PartNumber
Quantity
Connector, SMT, End launch SMA 50 Ohm
Y
Emerson
Network Power
142-0701-851
19
CONN TERM BLK PCB 5.08MM 2POS OR
Y
Weidmuller
1594540000
1
CONNECTORS
15
18
CLKin0*, CLKin1,
CLKin1*, CLKout0,
CLKout0*, CLKout2,
CLKout2*, CLKout4,
CLKout4*, CLKout6,
CLKout6*, CLKout8,
CLKout8*, CLKout10,
CLKout10*, CLKout12,
CLKout12*, Vcc, Vtune
J1
RESISTORS
19
R2, R179, R303, R329,
R332
FB, 1000 ohm, 600 mA, 0603
Y
Murata
BLM18HE102SN1D
5
20
R3, R5, R10, R16, R17,
R21, R22, R301, R305,
R334, R336, R346,
R349, R356
RES, 0 ohm, 5%, 0.1W, 0603
Y
Vishay-Dale
CRCW06030000Z0EA
14
21
R4, R11
RES, 0 ohm, 5%, 0.125W, 0805
Y
Vishay-Dale
CRCW08050000Z0EA
2
22
R7, R30, R46, R52,
R68, R74, R90, R96,
R112, R118, R134,
R140, R156, R159,
R175, R310, R318
RES, 51.0 ohm, 1%, 0.1W, 0603
Y
Yageo America
RC0603FR-0751RL
17
23
R20
RES, 100 ohm, 1%, 0.1W, 0603
Y
Yageo America
RC0603FR-07100RL
1
24
R31, R33, R39, R40,
R53, R55, R61, R62,
R75, R76, R83, R84,
R97, R98, R105, R106,
R119, R121, R127,
R128, R141, R143,
R149, R150, R163,
R165, R171, R172
RES, 240 ohm, 1%, 0.1W, 0603
Y
Yageo America
RC0603FR-07240RL
28
36
LMK01801BEVAL Evaluation Board Operating Instructions
SNAU118
25
26
27
28
29
30
31
32
R35, R36, R57, R58,
R79, R80, R101, R102,
R123, R124, R145,
R146, R167, R168
R302
R306, R307, R311,
R312, R313, R315,
R316, R319, R320,
R322, R323, R325,
R326, R328
R308, R309, R314,
R317, R321, R324,
R327
R331, R335, R337,
R338, R344, R347,
R350, R352
R342, R353, R357
R343, R354
R345, R355
RES, 68 ohm, 5%, 0.1W, 0603
Y
Vishay-Dale
CRCW060368R0JNEA
14
RES, 39k ohm, 5%, 0.1W, 0603
Y
Vishay-Dale
CRCW060339K0JNEA
1
RES, 27k ohm, 5%, 0.1W, 0603
Y
Vishay-Dale
CRCW060327K0JNEA
14
RES, 1.0k ohm, 5%, 0.1W, 0603
Y
Vishay-Dale
CRCW06031K00JNEA
7
FB, 120 ohm, 500 mA, 0603
Y
Murata
BLM18AG121SN1D
8
RES, 51k ohm, 5%, 0.1W, 0603
RES, 2.00k ohm, 1%, 0.1W, 0603
RES, 866 ohm, 1%, 0.1W, 0603
Y
Y
Y
Vishay-Dale
Vishay-Dale
Vishay-Dale
CRCW060351K0JNEA
CRCW06032K00FKEA
CRCW0603866RFKEA
3
2
2
INTEGRATED CIRCUITS
34
U1
35
U300, U301
36
U302
37
uWire
LMK01801
Micropower 800mA Low Noise 'Ceramic Stable'
Adjustable Voltage Regulator for 1V to 5V
Applications
Ultra Low Noise, 150mA Linear Regulator for
RF/Analog Circuits Requires No Bypass
Capacitor
Low Profile Vertical Header 2x5 0.100"
1
Y
Texas
Instruments
LP3878SD-ADJ
2
Y
Texas
Instruments
LP5900SD-3.3
1
Y
FCI
52601-G10-8LF
1
37
LMK01801BEVAL Evaluation Board Operating Instructions
SNAU118
Appendix E: Balun Information
Typical Balun Frequency Response
The following figure illustrates the typical frequency response of the Mini-circuit’s ADT2-1T
balun.
Typical Balun Insertion Loss
10
9
8
Loss (dB)
7
6
ADT2‐1T
5
4
3
2
1
0
10
100
Frequency (MHz)
Figure 21 - Typical Balun Frequency Response
38
LMK01801BEVAL Evaluation Board Operating Instructions
1000
SNAU118
Appendix F: Properly Configuring LPT Port
When trying to solve any communications issue, it is convenient to program the POWERDOWN
bit to confirm high/low current draw of the evaluation board or the PLL_MUX between “Logic
Low” and “Logic High” LD output to confirm successful communications.
LPT Driver Loading
The parallel port must be configured for proper operation. To confirm that the LPT port driver is
successfully loading click “LPT/USB”  “Check LPT Port.” If the driver properly loads then
the following message is displayed:
Figure 22 - Successfully Opened LPT Driver
Successful loading of LPT driver does not mean LPT communications in CodeLoader are setup
properly. The proper LPT port must be selected and the LPT port must not be in an improper
mode.
The PC must be rebooted after install for LPT support to work properly.
Correct LPT Port/Address
To determine the correct LPT port in Windows, open the device manager (On Windows XP,
Start  Settings  Control Panel  System  Hardware Tab  Device Manager) and check
the LPT port under the Ports (COM & LPT) node of the tree. It can be helpful to confirm that
the LPT port is mapped to the expected port address, for instance to confirm that LPT1 is really
mapped to address 0x378. This can be checked by viewing the properties of the LPT1 port and
viewing resources tab to verify that the I/O Range starts at 0x378. CodeLoader expects the a
traditional port mapping:
Port
Address
LPT1
0x378
LPT2
0x278
LPT3
0x3BC
If a non-standard address is used, use the “Other” port address in CodeLoader and type in the
port address in hexadecimal. It is possible to change the port address in the computer’s BIOS
settings. The port address is set in CodeLoader at the Port Setup tab as shown in Figure 23.
39
LMK01801BEVAL Evaluation Board Operating Instructions
SNAU118
Figure 23 - Selecting the LPT Port
Correct LPT Mode
If communications are not working, then it is possible the LPT port mode is set improperly. It is
recommended to use the simple, Output-only mode of the LPT port. This can be set in the BIOS
of the computer. Common terms for this desired parallel port mode are “Normal,” “Output,” or
“AT.” It is possible to enter BIOS setup during the initial boot up sequence of the computer.
40
LMK01801BEVAL Evaluation Board Operating Instructions
SNAU118
Appendix G: Differential Voltage Measurement Terminology
The differential voltage of a differential signal can be described by two different definitions
causing confusion when reading datasheets or communicating with other engineers. This section
will address the measurement and description of a differential signal so that the reader will be
able to understand and discern between the two different definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage
potential between the inverting and non-inverting signal. The symbol for this first measurement
is typically VID or VOD depending on if an input or output voltage is being described.
The second definition used to describe a differential signal is to measure the potential of the noninverting signal with respect to the inverting signal. The symbol for this second measurement is
VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to
ground, it only exists in reference to its differential pair. VSS can be measured directly by
oscilloscopes with floating references; otherwise this value can be calculated as twice the value
of VOD as described in the first section
Figure 24 illustrates the two different definitions side-by-side for inputs and Figure 25 illustrates
the two different definitions side-by-side for outputs. The VID and VOD definitions show VA and
VB DC levels that the non-inverting and inverting signals toggle between with respect to ground.
VSS input and output definitions show that if the inverting signal is considered the voltage
potential reference, the non-inverting signal voltage potential is now increasing and decreasing
above and below the non-inverting reference. Thus the peak-to-peak voltage of the differential
signal can be measured.
VID and VOD are often defined in volts (V) and VSS is often defined as volts peak-to-peak (VPP).
Figure 24 - Two Different Definitions
for Differential Output Signals
Figure 25 - Two Different Definitions
for Differential Input Signals
41
LMK01801BEVAL Evaluation Board Operating Instructions
SNAU118
Appendix H: Troubleshooting Information
If the evaluation board is not behaving as expected, the most likely issues are…
1) Board communication issue
2) Incorrect Programming of the device
3) Setup Error
Refer to this checklist for a practical guide on identifying/exposing possible issues.
Confirm Communications
Refer to Appendix F: Properly Configuring LPT Port to trouble shoot this item.
Remember to load device with Ctrl-L!
42
LMK01801BEVAL Evaluation Board Operating Instructions
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