Intersil ISL97671AIRZ 6-channel smbus/i2c or pwm dimming led driver with phase shift control Datasheet

6-Channel SMBus/I2C or PWM Dimming LED Driver with
Phase Shift Control
ISL97671A
Features
The ISL97671A is a 6-Channel 45V dual dimming capable LED
driver that can be used with either SMBus/I2C or PWM signal for
dimming control. The ISL97671A can drive six channels of LEDs
from input 4.5V~26.5V to output of up to 45V. It can also operate
from input as low as 3V to output of up to 26.5V in bootstrap
configuration (see Figure 40).
• 6 x 50mA Channels
• 4.5V to 26.5V Input with Max 45V Output
• 3V (see Figure 40) to 21V Input with Max 26.5V Output
• PWM Dimming with Phase Shift Control
• SMBus/I2C controlled PWM or DC Dimming
The ISL97671A features optional channel phase shift control to
minimize the input, output ripple characteristics and load
transients as well as spreading the light output to help reduce
the video and audio interference from the backlight driver
operation.
• Direct PWM Dimming
• PWM Dimming Linearity
- PWM Dimming with Adjustable Dimming Freq and Duty
Cycle Linear from 0.4% to 100% <30kHz
The device can also be configured in Direct PWM Dimming with
minimum dimming duty cycle of 0.007% at 200Hz.
- Direct PWM Dimming Duty Cycle Linear from 0.007% to
100% at 200Hz
The ISL97671A can compensate for the non-uniformity of the forward
voltage drops in the LED strings and Its headroom control circuit
monitors the highest LED forward voltage string for output regulation,
to minimize the voltage headroom and power loss in a typical
multi-string operation.
• Current Matching ±0.7%
• 600kHz/1.2MHz selectable switching frequency
• Dynamic Headroom Control
• Fault Protection
- String Open/Short Circuit, OVP, OTP, and Optional Output
Short Circuit Fault Protection
• 20 Ld 4mmx3mm QFN Package
The ISL97671A is offered in compact and thermally efficient
QFN-20 4mmx3mm package.
Applications
• Tablet PC to Notebook Displays LED Backlighting
• LCD Monitor LED Backlighting
• RGB LEDs or Field Sequential LED Backlighting
Typical Application Circuits
45V*, 6 x 50mA
VIN = 4.5~26.5V
Q1 (optional)
LX 20
2 VIN
OVP 16
4 VDC
4 VDC
PGND 19
7 SMBCLK/SCL
6 SMBDAT/SDA CH0 10
17 RSET
ISL97671A
1 FAULT
1 FAULT
2 VIN
3 EN
Q1 (optional)
ISL97671A
ISL97671A
9 AGND
COMP 18
17 RSET
*VIN > 12V
FIGURE 1A. SMBus/I2C CONTROLLED
DIMMING
8 FPWM
LX 20
OVP 16
PGND 19
6 SMBDAT/SDA
5 PWM
CH5 15
4 VDC
6 SMBDAT/SDACH0 10
3 EN
8 FPWM
2 VIN
7 SMBCLK/SCL
CH2 12
CH4 14
LX 20
OVP 16
PGND 19
7 SMBCLK/SCL
CH1 11
CH3 13
45V*, 6 x 50mA
VIN = 4.5~26.5V
Q1 (optional)
1 FAULT
5 PWM
45V*, 6 x 50mA
VIN = 4.5~26.5V
CH0 10
CH1 11
5 PWM
CH2 12
3 EN
CH3 13
17 RSET
CH4 14
8 FPWM
CH5 15
9 AGND
COMP 18
CH1 11
CH2 12
CH3 13
CH4 14
CH5 15
*VIN > 12V
FIGURE 1B. PWM DIMMING WITH
ADJUSTABLE DIMMING
9 AGND
COMP 18
*VIN > 12V
FIGURE 1C. DIRECT PWM DIMMING
FIGURE 1. ISL97671A TYPICAL APPLICATION DIAGRAMS
March 24, 2011
FN7709.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL97671A
Block Diagram
VIN = 4.5V TO 26.5V
45V*, 6 x 50mA
VIN
EN
VDC
ISL97671A
REG
S=0
IMAX
LED PWM
CONTROL
COMP
RSET
AGND
SMBCLK/SCL
SMBDAT/SDA
PWM
GM
AMP
OVP
OVP
FAULT/STATUS
REGISTER
OSC AND
RAMP
COMP
FPWM
LX
FAULT
FET
DRIVER
LOGIC
ILIMIT
REFERENCE
GENERATOR
PGND
CH0
HIGHEST VF
STRING
DETECT
OC, SC
DETECT
+
-
+
-
CH5
OC, SC
DETECT
*VIN > 12V
FAULT/STATUS
REGISTER
SMBUS/I2C
INTERFACE
AND PWM
CONTROL
LOGIC
REGISTERS
PWM BRIGHTNESS CONTROL
DEVICE CONTROL
FAULT/STATUS
IDENTIFICATION
DC BRIGHTNESS CONTROL
CONFIGURATION
+
PWM/OC/SC
DC
TEMP
SENSOR
FAULT/STATUS
REGISTER
FIGURE 2. ISL97671A BLOCK DIAGRAM
2
FN7709.1
March 24, 2011
ISL97671A
Pin Configuration
Ordering Information
PACKAGE
(Pb-free)
1. Add “-T* suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL97671A. For more information on MSL please see
techbrief TB363.
RSET
NOTES:
20
19
18
17
FAULT
1
16
OVP
VIN
2
15
CH5
EN
3
14
CH4
VDC
4
13
CH3
PWM
5
12
CH2
SMBDAT/SDA
6
11
CH1
7
8
9
10
CH0
Evaluation Board
COMP
ISL97671AIRZ-EVALZ
L20.3x4
AGND
20 Ld 3x4 QFN
PGND
671A
FPWM
ISL97671AIRZ
ISL97671A
(20 LD QFN)
TOP VIEW
PKG.
DWG. #
LX
PART
MARKING
SMBCLK/SCL
PART NUMBER
(Notes 1, 2, 3)
Pin Descriptions (I = Input, O = Output, S = Supply, X = Don’t Care)
PIN NAME
PIN #
TYPE
DESCRIPTION
FAULT
1
O
Fault Disconnect Switch Gate Control.
VIN
2
S
Input voltage for the device and LED power.
EN
3
I
The device needs 4ms for initial power-up enable. It will be disabled if it is not biased for longer than 28ms.
VDC
4
S
De-couple capacitor for internally generated supply rail.
PWM
5
I
PWM brightness control pin or DPST control input.
SMBDAT/SDA*
6
I/O
SMBus/I2C serial data input and output. When pins 6 and 7 are grounded or in logic 0’s for longer than 60ms, the
drivers will be controlled by external PWM signal.
SMBCLK/SCL*
7
I
SMBus/I2C serial clock input. When pins 6 and 7 are grounded or in logic 0’s for longer than 60ms, the drivers will
be controlled by external PWM signal.
FPWM
8
I
Set PWM dimming frequency, FPWM by connecting a resistor. When FPWM ties to VDC and SMBCLK/SMBDAT tie
to ground, the device will be in Direct PWM Dimming where the output follows the input frequency and duty cycle
without any digitization.
AGND
9
S
Analog Ground for precision circuits.
CH0, CH1
CH2, CH3
CH4, CH5
10, 11,
12, 13,
14, 15
I
Input 0, Input 1, Input 2, Input 3, Input 4, Input 5 to current source, FB, and monitoring.
OVP
16
I
Overvoltage protection input.
RSET
17
I
Resistor connection for setting LED current, (see Equation 2 for calculating the ILED(peak)).
COMP
18
O
Boost compensation pin.
PGND
19
S
Power ground
LX
20
O
Input to boost switch.
EPAD
No electrical connection but should be used to connect PGND and AGND. For example uses top plane as PGND and
bottom plane as AGND with vias on EPAD to allow heat dissipation and minimum noise coupling from PGND to
AGND operation.
3
FN7709.1
March 24, 2011
ISL97671A
Table of Contents
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
5
5
5
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . 8
Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . .
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OVP and VOUT Requirement . . . . . . . . . . . . . . . . . . . . .
Current Matching and Current Accuracy . . . . . . . . . . .
Dynamic Headroom Control . . . . . . . . . . . . . . . . . . . .
Dimming Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum DC Current Setting . . . . . . . . . . . . . . . . .
PWM DIMMING Control . . . . . . . . . . . . . . . . . . . . . .
PWM Dimming Frequency Adjustment . . . . . . . . . . .
Direct PWM Dimming . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Shift Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . .
5V Low Dropout Regulator . . . . . . . . . . . . . . . . . . . . . .
Power-Up Sequencing, Soft-Start, and
Fault Management . . . . . . . . . . . . . . . . . . . . . . . . . . .
In-rush Control and Soft-start . . . . . . . . . . . . . . . . . . .
Fault Protection and Monitoring . . . . . . . . . . . . . . . . .
Short Circuit Protection (SCP) . . . . . . . . . . . . . . . . . . .
Open Circuit Protection (OCP) . . . . . . . . . . . . . . . . . . .
Overvoltage Protection (OVP) . . . . . . . . . . . . . . . . . . . .
Undervoltage Lock-out. . . . . . . . . . . . . . . . . . . . . . . . . .
Input Overcurrent Protection . . . . . . . . . . . . . . . . . . . .
Over-Temperature Protection (OTP). . . . . . . . . . . . . . .
4
SMBus/I2C Communications. . . . . . . . . . . . . . . . . . . . . . . 18
Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Slave Device Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SMBus/I2C Register Definitions . . . . . . . . . . . . . . . . . 18
PWM Brightness Control Register (0x00). . . . . . . . . . 19
Device Control Register (0x01) . . . . . . . . . . . . . . . . . . . 20
Fault/Status Register (0x02) . . . . . . . . . . . . . . . . . . . . 21
Identification Register (0x03) . . . . . . . . . . . . . . . . . . . . 21
DC Brightness Control Register (0x07). . . . . . . . . . . . 22
Configuration Register (0x08) . . . . . . . . . . . . . . . . . . . 22
Output Channel Mask/Fault Readout
Register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Phase Shift Control Register (0x0A) . . . . . . . . . . . . . . 24
11
11
11
11
11
11
11
12
12
12
13
13
13
14
Components Selections . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Schottky Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14
14
14
14
14
15
15
15
15
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
High Current Applications . . . . . . . . . . . . . . . . . . . . . . . 25
Multiple Drivers Operation . . . . . . . . . . . . . . . . . . . . . . 25
Low Voltage Operations . . . . . . . . . . . . . . . . . . . . . . . . . 26
16-Bit Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
RGB LEDs or Field Sequenctial LED
Backlighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . 28
FN7709.1
March 24, 2011
ISL97671A
Absolute Maximum Ratings
Thermal Information
(TA = +25°C)
VIN, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 8.5V to VIN + 0.3V
VDC, COMP, RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V
SMBCLK/SCL*, SMBDAT/SDA*, FPWM, PWM . . . . . . . . . . . . -0.3V to 5.5V
EN, OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V
CH0 - CH5, LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Above voltage ratings are all with respect to AGND pin
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
Thermal Resistance (Typical)
θJA (°C/W)
20 Ld QFN Package (Notes 4, 5, 7) . . . . . .
40
Thermal Characterization (Typical)
θJC (°C/W)
2.5
PSIJT (°C/W)
20 Ld QFN Package (Note 6) . . . . . . . . . . . . . . . . . . . . .
1
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die
junction temperature can be estimated more accurately than the θJC and θJC thermal resistance ratings.
7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs.
Electrical Specifications
temperature range, -40°C to +85°C.
PARAMETER
VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted. Boldface limits apply over the operating
DESCRIPTION
CONDITION
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
26.5
V
5
µA
GENERAL
Backlight Supply Voltage
≤13 LEDs per channel (3.2V/20mA
type)
VIN Shutdown Current
TA = +25°C
IVIN
VIN Active Current
EN = 5V
VOUT
Output Voltage
4.5V < VIN ≤ 26V,
FSW = 600kHz
45
V
8.55V < VIN ≤ 26V,
FSW = 1.2MHz
45
V
VIN/0.19
V
2.6
V
VIN (Note 9)
IVIN_STBY
4.5
5
4.5V < VIN ≤ 8.55V, FSW = 1.2MHz
VUVLO
Undervoltage Lockout Threshold
VUVLO_HYS
Undervoltage Lockout Hysteresis
2.1
mA
200
mV
REGULATOR
VDC
IVDC_STBY
VLDO
LDO Output Voltage
VIN ≥ 6V
Standby Current
EN = 0V
VDC LDO Droop Voltage
VIN > 5.5V, 20mA
ENLOW
Guaranteed Range for EN Input Low Voltage
ENHI
Guaranteed Range for EN Input High Voltage
tENLow
4.55
4.8
20
5
V
5
µA
200
mV
0.5
V
1.8
EN Low Time Before Shut-down
V
30.5
ms
BOOST
SWILimit
Boost FET Current Limit
5
1.5
2.0
2.7
A
FN7709.1
March 24, 2011
ISL97671A
Electrical Specifications
VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
rDS(ON)
SS
Eff_peak
ΔIOUT/ΔVIN
DMAX
DMIN
DESCRIPTION
CONDITION
Internal Boost Switch ON-resistance
TA = +25°C
Soft-Start
100% LED Duty Cycle
Peak Efficiency
MIN
(Note 8)
Boost Minimum Duty Cycle
MAX
(Note 8)
UNIT
235
300
mΩ
7
ms
VIN = 12V, 72 LEDs, 20mA each,
L = 10µH with DCR 101mΩ,
TA = +25°C
92.9
%
VIN = 12V, 60 LEDs, 20mA each,
L = 10µH with DCR 101mΩ,
TA = +25°C
90.8
%
0.1
%
Line Regulation
Boost Maximum Duty Cycle
TYP
FSW = 1, 600kHz
90
FSW = 0, 1.2MHz
81
%
FSW = 1, 600kHz
9.5
FSW = 0, 1.2MHz
17
%
fOSC_hi
Lx Frequency High
FSW = 1, 600kHz
475
600
640
kHz
fOSC_lo
Lx Frequency Low
FSW = 0, 1.2MHz
0.97
1.14
1.31
MHz
LX Pin Leakage Current
LX = 45V, EN = 0V
10
µA
ILX_leakage
REFERENCE
FAULT DETECTION
VSC
Short Circuit Threshold Accuracy
7.5
8.2
V
Temp_shtdwn
Temperature Shutdown Threshold
150
°C
Temp_Hyst
Temperature Shutdown Hysteresis
23
°C
VOVPlo
Overvoltage Limit on OVP Pin
1.19
1.25
V
±1.0
%
+1.5
%
CURRENT SOURCES
IMATCH
IACC
VHEADROOM
VRSET
ILED(max)
DC Channel-to-Channel Current Matching
RSET = 20.1kΩ, Reg0x00 = 0xFF,
(IOUT = 20mA)
Current Accuracy
±0.7
-1.5
Dominant Channel Current Source Headroom ILED = 20mA
at CH Pin
TA = +25°C
Voltage at RSET Pin
RSET = 20.1kΩ
Maximum LED Current per Channel
VIN = 12V, VOUT = 45V, Fsw = 1.2MHz,
TA = +25°C
500
1.2
1.22
mV
1.24
V
50
mA
PWM GENERATOR
VIL
Guaranteed Range for PWM Input Low Voltage
0.8
V
VIH
Guaranteed Range for PWM Input High Voltage
1.5
VDD
V
PWM Input Frequency Range
200
30,000
Hz
FPWMI
PWMACC
tDIRECTPWM
FPWM
PWM Dimming Accuracy (Except Direct PWM
Dimming)
Direct PWM Minimum On Time
8
Direct PWM Mode
PWM Dimming Frequency Range
bits
250
350
ns
100
30,000
Hz
FAULT PIN
IFAULT
Fault Pull-down Current
VIN = 12V
VFAULT
Fault Clamp Voltage with Respect to VIN
VIN = 12, VIN - VFAULT
6
12
21
30
µA
6
7
8.3
V
FN7709.1
March 24, 2011
ISL97671A
Electrical Specifications
VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
LXstart_thres
ILXStart-up
SMBus/I2C
CONDITION
LX Start-up Threshold
TYP
0.9
LX Start-up Current
1
VIL
Guaranteed Range for Data, Clock Input Low
Voltage
VIH
Guaranteed Range for Data, Clock Input High
Voltage
VOL
SMBus/I2C Data line Logic Low Voltage
IPULLUP = 4mA
Input Leakage On SMBData/SMBClk
Measured at 4.8V
SMBus/I2C
MIN
(Note 8)
3.5
MAX
(Note 8)
UNIT
1.2
V
5
mA
0.8
V
VDD
V
0.17
V
10
µA
INTERFACE
ILEAK
tEN
DESCRIPTION
1.5
-10
TIMING SPECIFICATIONS
-SMB/I2C
Minimum Time Between EN high and
SMBus/I2C Enabled
1µF capacitor on VDC
2
0.15
ms
PWS
Pulse Width Suppression on
SMBCLK/SMBDAT
0.45
µs
fSMB
SMBus/I2C Clock Frequency
tBUF
Bus Free Time Between Stop and Start
Condition
1.3
400
kHz
µs
tHD:STA
Hold Time After (Repeated) START Condition.
After this Period, the First Clock is Generated
0.6
µs
tSU:STA
Repeated Start Condition Setup Time
0.6
µs
tSU:STO
Stop Condition Setup Time
0.6
µs
tHD:DAT
Data Hold Time
300
ns
tSU:DAT
Data Setup Time
100
ns
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
0.6
µs
tF
Clock/data Fall Time
300
ns
tR
Clock/data Rise Time
300
ns
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. At maximum VIN of 26.5V, minimum VOUT is limited 28V.
7
FN7709.1
March 24, 2011
ISL97671A
100
100
90
90
80
80
70
60
24VIN
12VIN
50
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves
5VIN
40
30
70
40
30
20
10
5
10
15
20
0
25
5VIN
50
10
0
24VIN
12VIN
60
20
0
6P10S_30mA/CHANNEL
0
5
10
15
ILED(mA)
20
25
30
35
ILED(mA)
FIGURE 3. EFFICIENCY vs up to 20mA LED CURRENT (100% LED
DUTY CYCLE) vs VIN
FIGURE 4. EFFICIENCY vs up to 30mA LED CURRENT (100% LED
DUTY CYCLE) vs VIN
100
100
90
80
70
580k
60
EFFICIENCY (%)
EFFICIENCY (%)
80
1.2MHz
50
40
30
20
60
1.2MHz
580k
40
20
10
0
0
5
10
15
20
25
0
0
30
5
10
15
VIN
FIGURE 5. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT
20mA (100% LED DUTY CYCLE)
30
0.40
CURRENT MATCHING(%)
90
80
EFFICIENCY (%)
25
FIGURE 6. EFFICIENCY vs V IN vs SWITCHING FREQUENCY AT
30mA (100% LED DUTY CYCLE)
100
70 +25°C
60
-40°C
+85°C
0°C
50
40
30
20
10
0
20
VIN
0
5
10
15
20
25
30
VIN
FIGURE 7. EFFICIENCY vs VIN vs TEMPERATURE AT 20mA (100%
LED DUTY CYCLE)
8
0.30
0.20
0.10
0.00
4.5VIN
12VIN
-0.10
-0.20
-0.30
-0.40
0
21VIN
1
2
3
4
5
6
7
CHANNEL
FIGURE 8. CHANNEL-TO-CHANNEL CURRENT MATCHING
FN7709.1
March 24, 2011
ISL97671A
Typical Performance Curves
(Continued)
1.2
0.60
-40°C
+25°C
1.0
CURRENT
VHEADROOM (V)
0.55
0.8
4.5 VIN
0.6
12 VIN
0.4
0.50
0°C
0.45
0.2
0
0
1
2
3
DC
4
5
6
FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING
DUTY CYCLE vs VIN
0.40
0
5
10
15
VIN (V)
20
25
30
FIGURE 10. VHEADROOM vs VIN AT 20mA
VIN = 6V, 6P12S
VO = 20V/DIV
VO = 50mV/DIV
2.00µs/DIV
2.00µs/DIV
I_VIN = 1A/DIV
ILED = 20mA/DIV
EN
FIGURE 11. VOUT RIPPLE VOLTAGE, VIN = 12V, 6P12S AT
20mA/CHANNEL
FIGURE 12. IN-RUSH and LED CURRENT AT VIN = 6V FOR 6P12S AT
20mA/CHANNEL
6P12S, 20mA/CH
VIN = 12V, 6P12S
VIN = 10V/DIV
VO = 20V/DIV
10.0ms/DIV
2.00µs/DIV
ILED = 20mA/DIV
I_VIN = 1A/DIV
I_VIN = 1A/DIV
ILED = 20mA/DIV
EN
EN
FIGURE 13. IN-RUSH AND LED CURRENT AT VIN = 12V FOR 6P12S
AT 20mA/CHANNEL
9
FIGURE 14. LINE REGULATION WITH VIN CHANGE FROM 6V TO 26V,
VIN = 12V, 6P12S AT 20mA/CHANNEL
FN7709.1
March 24, 2011
ISL97671A
Typical Performance Curves
(Continued)
6P12S, 20mA/CH
6P12S, 20mA/CH
VIN = 10V/DIV
VO = 1V/DIV
10.0ms/DIV
I_VIN = 1A/DIV
10.0ms/DIV
ILED = 20mA/DIV
ILED = 20mA/DIV
EN
FIGURE 15. LINE REGULATION WITH VIN CHANGE FROM 26V TO 6V
FOR 6P12S AT 20mA/CHANNEL
6P12S, 20mA/CH
FIGURE 16. LOAD REGULATION WITH ILED CHANGE FROM 0% TO
100% PWM DIMMING, VIN = 12V, 6P12S AT
20mA/CHANNEL
6P12S, 20mA/CH
VO = 10V/DIV
20.0ms/DIV
VO = 1V/DIV
10.0ms/DIV
ILED = 20mA/DIV
ILED = 20mA/DIV
I_VIN = 1A/DIV
EN
FIGURE 17. LOAD REGULATION WITH I LED CHANGE FROM 100%
TO 0% PWM DIMMING, VIN = 12V, 6P12S
AT 20mA/CHANNEL
FIGURE 18. ISL97672A SHUTS DOWN AND STOPS SWITCHING
~30ms AFTER EN GOES LOW
0.0030
ILED (mA)
0.0025
0.0020
0.0015
ILED = 20mA
FPWM = 200Hz
NO CH CAPS
0.0010
0.006 0.007 0.008 0.009 0.010 0.011 0.012 0.013 0.014
PWM DIMMING DUTY CYCLE (%)
FIGURE 19. DIRECT PWM DIMMING MINIMUM DIMMING LINEARITY
10
FN7709.1
March 24, 2011
ISL97671A
Theory of Operation
tolerance will be contributed by the current setting resistor. A 1%
tolerance resistor is therefore recommended.
PWM Boost Converter
The current mode PWM boost converter produces the minimal
voltage needed to enable the LED stack with the highest forward
voltage drop to run at the programmed current. The ISL97671A
employs current mode control boost architecture that has a fast
current sense loop and a slow voltage feedback loop. Such
architecture achieves a fast transient response that is essential
for the notebook backlight application where the power can be a
series of drained batteries or instantly change to an AC/DC
adapter without rendering a noticeably visual nuisance. The
number of LEDs that can be driven by ISL97671A depends on the
type of LED chosen in the application. The ISL97671A is capable
of boosting up to 45V and drive 6 channels of LEDs.
+
-
REF
+
-
RSET
+
-
Enable
PWM DIMMING
The EN pin is used to enable or disable the ISL97671A operation. It
is a high voltage pin that can be tied directly to VIN up to 26.5V if the
system lacks of I/O for enable signal.
OVP and VOUT Requirement
The Overvoltage Protection (OVP) pin has a function of setting the
overvoltage trip level as well as limiting the VOUT regulation
range.
The ISL97671A OVP threshold is set by RUPPER and RLOWER as
shown in Equation 1:
V OUT_OVP = 1.21V × ( R UPPER + R LOWER ) ⁄ R LOWER
(EQ. 1)
VOUT can only regulate between 64% and 100% of the VOUT_OVP
such that:
Allowable VOUT = 64% to 100% of VOUT_OVP
For example, if 10 LEDs are used with the worst case VOUT of 35V.
If R1 and R2 are chosen such that the OVP level is set at 40V,
then the VOUT is allowed to operate between 25.6V and 40V. If
the requirement is changed to a 6 LEDs 21V VOUT application,
then the OVP level must be reduced and users should follow
VOUT = (64% ~100%) OVP requirement. Otherwise, the headroom
control will be disturbed such that the channel voltage can be
much higher than expected and sometimes it can prevent the
driver from operating properly.
The ratio of the OVP capacitors should be the inverse of the OVP
resistors. For example, if RUPPER/RLOWER = 33/1, then
CUPPER/CLOWER = 1/33 with CUPPER = 100pF and CLOWER = 3.3nF.
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current
source circuit, as shown in Figure 20.
The LED peak current is set by translating the RSET current to the
output with a scaling factor of 401.8/RSET. The source terminals of
the current source MOSFETs are designed to run at 500mV to
optimize power loss versus accuracy requirements. The sources of
errors of the channel-to-channel current matching come from the
op amps offset, internal layout, reference, and current source
resistors. These parameters are optimized for current matching and
absolute current accuracy. On the other hand, the absolute accuracy is
additionally determined by the external RSET, and therefore, additional
11
DC DIMMING
FIGURE 20. SIMPLIFIED CURRENT SOURCE CIRCUIT
Dynamic Headroom Control
The ISL97671A features a proprietary Dynamic Headroom
Control circuit that detects the highest forward voltage string or
effectively the lowest voltage from any of the CH0-CH5 pins.
When this lowest channel voltage is lower than the short circuit
threshold, VSC, such voltage will be used as the feedback signal
for the boost regulator. The boost makes the output to the correct
level such that the lowest channel pin is at the target headroom
voltage. Since all LED stacks are connected to the same output
voltage, the other channel pins will have a higher voltage, but the
regulated current source circuit on each channel will ensure that
each channel has the same programmed current. The output
voltage will regulate cycle-by-cycle and is always referenced to
the highest forward voltage string in the architecture.
Dimming Controls
The ISL97671A provides SMBus/I2C controlled PWM or DC
dimming where the users need to turn the LEDs on through the
SMBus/I2C communications (see the “SMBus/I2C
Communications” on page 18). The ISL97671A also provides
PWM dimming by external PWM signal where the SMBCLK and
SMBDAT pins are grounded or pulled low and the dimming
frequency can be adjusted. The ISL97671A also allows Direct
PWM Dimming where the output duty cycle and dimming
frequency follow the input PWM signal. The three dimming mode
selection is summarized in Table 1.
TABLE 1. DIMMING MODE SELECTION
SMBCLK/SCL Pin
SIGNAL
SMBDAT/SDA
PIN SIGNAL
Low
Low
Low
Low
SMBus clock
SMBus data
I2C clock
I2C data
FPWM PIN
DIMMING MODE
SELECTION
Resistor to PWM Dimming with
ground
Adjustable Dimming
Frequency, Phase Shift
Enabled
Tie to VDC Direct PWM Dimming
Resistor to SMBus Controlled Dimming
ground
Resistor to I2C Controlled Dimming
ground
FN7709.1
March 24, 2011
ISL97671A
The ISL97671A allows two ways of controlling the LED current,
and therefore, the brightness. They are:
1. DC current adjustment
2. PWM chopping of the LED current defined in Step 1.
There are various ways to achieve DC or PWM current control,
described in the following.
MAXIMUM DC CURRENT SETTING
The initial brightness should be set by choosing an appropriate
value for RSET. This should be chosen to fix the maximum
possible LED current:
401.8
I LEDmax = --------------R SET
(EQ. 2)
Once RSET is fixed, the LED DC current can be adjusted through
Register 0x07 (BRTDC) as follows:
I LED = 1.58x ( BRTDC ⁄ R SET )
(EQ. 3)
BRTDC can be programmed from 0 to 255 in decimal and
defaults to 255 (0xFF). If left at the default value, LED current will
be fixed at ILEDmax. BRTDC can be adjusted dynamically on the fly
during operation. BRTDC = 0 disconnects all channels.
For example, if the maximum required LED current (ILED(max)) is
20mA, rearranging Equation 2 yields Equation 4:
R SET = 401.8 ⁄ 0.02 = 20.1kΩ
(EQ. 4)
To use only the SMBus/I2C controlled PWM brightness control,
users need to set Register 0x01 to 0x05.
The PWM dimming frequency is adjusted by a resistor at the
FPWM pin.
Method 2 (External Mode)
The average LED channel current can also be controlled by an
external PWM signal, as shown in Equation 8:
LILED ( ave ) = I LED × PWMI
(EQ. 8)
The PWM dimming frequency can be set or applied up to 30kHz
with duty cycles from 0.4% to 100%. The PWM dimming off time
cannot be longer than 28ms or else the driver will enter
shutdown.
To use externally applied PWM signal only for brightness control,
users need to set Register 0x01 to 0x03.
Method 3 (DPST Mode)
The average LED channel current can also be controlled by the
product of the SMBus/I2C controlled PWM and the external PWM
signals as:
I LED ( ave ) = I LED xPWM DPST
(EQ. 9)
Where:
PWM DPST = BRT ⁄ 255 × PWMI
If BRTDC is set to 200 then:
I LED = 1.58 • 200 ⁄ 20100 = 15.7mA
(EQ. 5)
The ISL97671A provides multiple PWM dimming methods, as
described in the following. Each of these methods results in PWM
chopping of the current in the LEDs for all 6 channels to provide
an average LED current. During the On periods, the LED current
will be defined by the value of RSET and BRTDC, as described in
Equations 2 and 3. The source of the PWM signal can be
described as follows:
1. Internally generated 256 step duty cycle programmed
through the SMBus/I2C.
Therefore:
(EQ. 11)
3. DPST mode. Internally generated signal with a duty cycle
defined by the product of the external PWM and SMBus/I2C
programmed PWM at the internal setting frequency.
The default PWM dimming is in DPST mode. In all of the
methods, the average LED channel current is controlled by ILED
and the PWM duty cycle in percent, as shown in Equation 6:
I LED ( ave ) = I LED × PWM
Where BRT is the value held in Register 0x00 (default setting
0xFF) controlled by SMBus/I2C and PWM is the duty cycle of the
incoming PWM signal. In this way, the users can change the
PWM current in ratiometric manner to achieve DPST compliance
backlight dimming.
To use the DPST mode, users need to set Register 0x01 to 0x01
with an external PWM signal.
The DPST mode PWM dimming frequency is adjusted by a resistor
at the FPWM pin.
2. External signal from PWM.
(EQ. 6)
SMBus/I2C
(EQ. 10)
I LED ( ave ) = I LED × BRT ⁄ 255 × PWMI
PWM DIMMING CONTROL
Method 1 (Internal Mode,
where BRT is the PWM brightness level programmed in the
Register 0x00. BRT ranges from 0 to 255 in decimal and defaults
to 255 (0xFF). BRT = 0 disconnects all channels.
For example, if the SMBus/I2C controlled PWM duty is 80%
dimming at 200Hz (see Equation 12) and the external PWM duty
cycle is 60% dimming at 1kHz, the resultant PWM duty cycle is
48% dimming at 200Hz.
PWM Dimming Frequency Adjustment
The PWM dimming frequency is set by an external resistor at the
FPWM pin as:
7
6.66 ×10
F PWM = -----------------------RFPWM
controlled PWM)
(EQ. 12)
The average LED channel current is controlled by the internally
generated PWM signal, as shown in Equation 7:
where FPWM is the desirable PWM dimming frequency and
RFPWM is the setting resistor.
I LED ( ave ) = I LED × ( BRT ⁄ 255 )
The PWM dimming frequency can be set or applied up to 30kHz
with duty cycle from 0.4% to 100%.
(EQ. 7)
12
FN7709.1
March 24, 2011
ISL97671A
Direct PWM Dimming
When Direct PWM Dimming mode is selected where FPWM is tied
to VDC and SMBCLK/SMBDAT are grounded, 6 channels of PWM
current will follow the incoming PWM signal’s frequency and duty
cycle. The change is analog fashion without any digitization that
the minimum duty cycle can be as low as 0.007% at 200Hz (or
equivalent pulse width of 350ns). To achieve this ultra low duty
cycle dimming performance, any channel capacitor, either it is
tied to VOUT or ground, cannot be used. Also in Direct PWM
Dimming mode the Phase Shift function will be disabled.
40%
ILED0
60%
40%
tD1
ILED1
tD1
ILED2
tD1
ILED3
tD1
tD1
The ISL97671A is capable of delaying the phase of each current
source to minimize load transients. By default, phase shifting is
disabled as shown in Figure 21 where the channels PWM
currents are switching uniformly. The duty cycles can be
controlled by the data in PWM Brightness Control Register via the
SMBus/I2C interface, an external PWM signal with the frequency
set by the RFPWM, or by an external PWM signal with the
frequency set by the incoming signal.
tFPWM
tON
60%
ILED4
Phase Shift Control
ILED0
PWMI
ILED5
tD2
tFPWM
ILED0
tON
tOFF
FIGURE 22. 6 EQUAL PHASE CHANNELS PHASE SHIFT
ILLUSTRATION
tPWMin
PWMI
60%
40%
tFPWM
(tPWMout)
tON
ILED1
tOFF
60%
40%
tD1
tOFF
ILED2
tD1
ILED3
ILED1
tD1
ILED4
ILED2
ILED3
ILED4
tD2
ILED1
tD1 = Fixed Delay with Integer only while the decimal value will be discarded (eg. 63.75=63)
ILED5
FIGURE 21. NO DELAY (DEFAULT PHASE SHIFT DISABLED)
When EqualPhase = 1, the phase shift evenly spreads the channels
switching across the PWM cycle, depending on how many channels
are enabled, as shown in Figures 22 and 23. Equal phase means
there are fixed delays between channels and such delay can be
calculated as Equations 13 and 14.
FIGURE 23. 4 EQUAL PHASE CHANNELS PHASE SHIFT
ILLUSTRATION
tFPWM
ILED0
tON
tOFF
tPD
ILED1
tPD
ILED2
tPD
t FPWM 255
t D1 = ------------------ x ⎛ ----------⎞
255 ⎝ N ⎠
(EQ. 13)
ILED3
tPD
ILED4
t FPWM
255
t D2 = ------------------ x ⎛ 255 – ( N – 1 ) ⎛ ----------⎞ ⎞
⎝ N ⎠⎠
255 ⎝
(EQ. 14)
where (255/N) is rounded down to the nearest integer. For
example, if N = 6, (255/N) = 42, that leads to:
tD1 = tFPWM x 42/255
tD2 = tFPWM x 45/255
where tFPWM is the sum of tON and tOFF. N is the number of LED
channels. The ISL97671A will detect the numbers of operating
channels automatically.
tPD
ILED5
FIGURE 24. PHASE SHIFT WITH 7-BIT PROGRAMMABLE DELAY
The ISL97671A allows the user to program the amount of phase
shift degree in 7-bit resolution, as shown in Figure 24. To enable
programmable phase shifting, the user must write to the Phase
Shift Control register with EqualPhase = 0 and the desirable
phase shift value of PhaseShift[6:0]. The delay between CH5 and
the repeated CH0 is the rest of the PWM cycle.
Switching Frequency
The default switching frequency is 600kHz but it can be selected
to 600kHz or 1.2MHz if the SMBus/I2C communications is used.
The switching frequency select bit is accessible in the SMBus/I2C
Configuration Register 0x08 bit 2.
13
FN7709.1
March 24, 2011
ISL97671A
5V Low Dropout Regulator
A 5V LDO regulator is present at the VDC pin to develop the
necessary low voltage supply, which is used by the chips internal
control circuitry. Because VDC is an LDO pin, it requires a bypass
capacitor of 1µF or more for the regulation. Low input voltage also
allows only lower output voltage applications only with the
maximum boost ratio defined in “Components Selections” on
page 24. The VDC pin can be used as a coarse reference with a few
mA sourcing capability.
Power-Up Sequencing, Soft-Start, and Fault
Management
The ISL97671A includes circuits to manage input current draw
during normal startup, to reduce inrush current as various bulk
capacitors charge up. The ISL97671A also detects several
external fault conditions, and acts to limit fault energy and
prevent continued startup while detected faults exist. An external
high-side PFET can optionally be fitted in series with VIN. The
ISL97671A turns this fault protection PFET off in the event of a
short fault to ground in the boost converter, avoiding damage to
the system's main power supply in such an overload condition.
In-rush Control and Soft-start
The ISL97671A has separately built in independent in-rush control
and soft-start functions. The in-rush control function is built around the
short circuit protection FET, and is only available in applications, which
include this device. At start-up, the fault protection FET is turned on
slowly due to a 30µA pull-down current output from the FAULT pin.
This discharges the fault FET's gate-source capacitance, turning on
the FET in a controlled fashion. As this happens, the output capacitor
is charged slowly through the weakly turned on FET before it becomes
fully enhanced. This results in a low in-rush current. This current can
be further reduced by adding a capacitor (in the 1nF to 5nF range)
across the gate-source terminals of the FET.
Once the boost is enabled the current in the boost power switch
is monitored and the switching is terminated in any cycle where
the current exceeds the current limit. The ISL97671A includes a
soft-start feature where this current limit starts at a low value
(285mA). This is stepped up to the final 2.0A current limit in 7
further steps of 285mA. These steps will happen over at least
8ms, and will be extended at low LED PWM frequencies if the
LED duty cycle is low. This allows the output capacitor to be
charged to the required value at a low current limit and prevents
high input current for systems that have only a low to medium
output current requirement.
For systems with no master fault protection FET, the in-rush
current will flow towards COUT when VIN is applied and it is
determined by the ramp rate of VIN and the values of COUT and L.
Fault Protection and Monitoring
The ISL97671A features extensive protection functions to cover
all the perceivable failure conditions. The failure mode of a LED
can be either open circuit or as a short. The behavior of an open
circuited LED can additionally take the form of either infinite
resistance or, for some LEDs, a zener diode, which is integrated
into the device in parallel with the now opened LED.
For basic LEDs (which do not have built-in zener diodes), an open
circuit failure of an LED will only result in the loss of one channel
14
of LEDs without affecting other channels. Similarly, a short circuit
condition on a channel that results in that channel being turned
off does not affect other channels unless a similar fault is
occurring. All LED faults are reported via the SMBus/I2C interface
to Register 0x02 (Fault/Status register). The controller is able to
determine which channels have failed via Register 0x09 (Output
Masking register). The controller can also choose to use Register
0x09 to disable faulty channels at start-up, resulting in only
further faulty channels being reported by Register 0x02.
Due to the lag in boost response to any load change at its output,
certain transient events (such as LED current steps or significant
step changes in LED duty cycle) can transiently look like LED
fault modes. The ISL97671A uses feedback from the LEDs to
determine when it is in a stable operating region and prevents
apparent faults during these transient events from allowing any
of the LED stacks to fault out. See Table 2 on page 16 for more
details.
A fault condition that results in an input current that exceeds the
devices electrical limits will result in a shutdown of all output
channels. The control device logic will remain functional such
that the Fault/Status Register can be interrogated by the system.
The root cause of the failure will be loaded to the volatile
Fault/Status Register so that the host processor can interrogate
the data for failure monitoring.
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each
channel and disables faulty channels which are detected above
the programmed short circuit threshold. The short circuit
threshold is 7.2V minimum. When an LED becomes shorted, the
action taken is described in Table 2. The default short circuit
threshold is 7.2V. The detection of this failure mode can be
disabled via Register 0x08, see Table 3B for additional
information.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can behave as
either an infinite resistance or a gradually increasing finite
resistance. The ISL97671A monitors the current in each channel
such that any string which reaches the intended output current is
considered “good”. Should the current subsequently fall below
the target, the channel will be considered an “open circuit”.
Furthermore, should the boost output of the ISL97671A reaches
the OVP limit or should the lower over-temperature threshold be
reached, all channels which are not “good” will immediately be
considered as “open circuit”. Detection of an “open circuit”
channel will result in a time-out before disabling of the affected
channel. This time-out is sped up when the device is above the
lower over-temperature threshold in an attempt to prevent the
upper over-temperature trip point from being reached.
Some users employ some special types of LEDs that have zener
diode structure in parallel with the LED for ESD enhancement, thus
enabling open circuit operation. When this type of LED goes open
circuit, the effect is as if the LED forward voltage has increased,
but no lighting. Any affected string will not be disabled, unless the
failure results in the boost OVP limit being reached, allowing all
other LEDs in the string to remain functional. Care should be taken
in this case that the boost OVP limit and SCP limit are set properly,
so as to make sure that multiple failures on one string do not
FN7709.1
March 24, 2011
ISL97671A
cause all other good channels to be faulted out. This is due to the
increased forward voltage of the faulty channel making all other
channel look as if they have LED shorts. See Table 2 for details for
responses to fault conditions.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage and keeps
the voltage at a safe level. The OVP threshold is set as:
OVP = 1.21V × ( R UPPER + R LOWER ) ⁄ R LOWER
(EQ. 15)
These resistors should be large to minimize the power loss. For
example, a 1MkΩ RUPPER and 30kΩ RLOWER sets OVP to 41.2V.
Large OVP resistors also allow COUT discharges slowly during the
PWM Off time. Parallel capacitors should also be placed across
the OVP resistors such that RUPPER/RLOWER = CLOWER/CUPPER.
Using a CUPPER value of at least 30pF is recommended. These
capacitors reduce the AC impedance of the OVP node, which is
important when using high value resistors.
Undervoltage Lock-out
If the input voltage falls below the UVLO level of 2.45V, the device
will stop switching and be reset. Operation will restart only if the
device is re-enabled through SMBus/I2C interface once the input
voltage is back in the normal VIN and operating range. In
non-SMBus/I2C applications, the part will automatically restart
once the input voltage clears the UVLO threshold with the part
already enabled.
Input Overcurrent Protection
During normal switching operation, the current through the
internal boost power FET is monitored. If the current exceeds the
current limit, the internal switch will be turned off. This
monitoring happens on a cycle by cycle basis in a self protecting
way.
15
Additionally, the ISL97671A monitors the voltage at the LX and
OVP pins. At start-up, a fixed current is injected out of the LX pins
and into the output capacitor. The device will not start up unless
the voltage at LX exceeds 1.2V. The OVP pin is also monitored
such that if it rises above and subsequently falls below 20% of
the target OVP level, the input protection FET will also be
switched off.
Over-Temperature Protection (OTP)
The ISL97671A includes two over-temperature thresholds. The lower
threshold is set to +130°C. When this threshold is reached, any
channel which is outputting current at a level significantly below the
regulation target will be treated as “open circuit” and disabled after
a time-out period. This time-out period is also reduced to 800µs
when it is above the lower threshold. The intention of the lower
threshold is to allow bad channels to be isolated and disabled before
they cause enough power dissipation (as a result of other channels
having large voltages across them) to hit the upper temperature
threshold.
The upper threshold is set to +150°C. Each time this is reached,
the boost will stop switching and the output current sources will
be switched off. Once the device has cooled to approximately
+100°C, the device will restart with the DC LED current level
reduced to 75% of the initial setting. If the dissipation problem
persists, subsequent hitting of the limit will cause identical
behavior, with the current reduced in steps to 50% and finally
25%. Hitting of the upper threshold will also set the thermal fault
bit of the Fault/Status register 0x02. Unless disabled via the EN
pin, the device stays in an active state throughout, allows the
external processor to interrogate the fault condition.
For the extensive fault protection conditions, please refer to
Figure 25 and Table 2 for details.
FN7709.1
March 24, 2011
ISL97671A
LX
VIN
VOUT
FAULT
O/P
SHORT
DRIVER
IMAX
ILIMIT
OVP
FET
DRIVER
LOGIC
CH0
VSC
CH5
VSET/2
REG
THRM
SHDN
REF
T2
TEMP
SENSOR
T1
OTP
+
VSET
Q0 VSET
PWM/OC0/SC0
SMBUS/I2C
CONTROL
LOGIC
FAULT/
STATUS
REGISTER
+
Q5
-
-
PWM/OC5/SC5
DC CURRENT
FIGURE 25. SIMPLIFIED FAULT PROTECTIONS
TABLE 2. PROTECTIONS TABLE
CASE
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION
1
CH0 Short Circuit
Upper Over-Temperature
Protection limit (OTP) not
triggered and CH0 < 7.5V
CH0 ON and burns power.
2
CH0 Short Circuit
Upper OTP triggered but
VCH0 < 7.5V
All channels go off until chip cooled Same as CH0
and then comes back on with
current reduced to 76%. Subsequent
OTP triggers will reduce IOUT further.
Highest VF of
CH1 through CH5
3
CH0 Short Circuit
Upper OTP not triggered
but CH0 > 7.5V
CH1 disabled after 6 PWM cycle
time-out.
CH1 through CH5 Normal
Highest VF of
CH1 through CH5
4
CH0 Open Circuit
with infinite
resistance
Upper OTP not triggered
and CH0 < 7.5V
VOUT will ramp to OVP. CH1 will time- CH1 through CH5 Normal
out after 6 PWM cycles and switch
off. VOUT will drop to normal level.
Highest VF of
CH1 through CH5
5
CH0 LED Open Circuit Upper OTP not triggered
and CH0 < 7.5V
but has paralleled
Zener
CH1 remains ON and has highest VF, CH1 through CH5 ON, Q1 through VF of CH0
thus VOUT increases.
Q5 burn power
6
CH0 LED Open Circuit Upper OTP triggered but
CH0 < 7.5V
but has paralleled
Zener
All channels go off until chip cooled Same as CH0
and then comes back on with
current reduced to 76%. Subsequent
OTP triggers will reduce IOUT further
7
CH0 LED Open Circuit Upper OTP not triggered
but CHx > 7.5V
but has paralleled
Zener
CH0 remains ON and has highest VF, VOUT increases, then CH-X
VF of CH0
thus VOUT increases.
switches OFF after 6 PWM cycles.
This is an unwanted shut off and
can be prevented by setting OVP
at an appropriate level.
8
Channel-to-Channel
ΔVF too high
Any channel at below the target current will fault out after 6 PWM cycles. Highest VF of
Remaining channels driven with normal current.
CH0 through CH5
Lower OTP triggered but
CHx < 7.5V
16
CH1 through CH5 Normal
VOUT REGULATED
BY
Highest VF of
CH1 through CH5
VF of CH0
FN7709.1
March 24, 2011
ISL97671A
TABLE 2. PROTECTIONS TABLE (Continued)
CASE
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION
VOUT REGULATED
BY
9
Channel-to-Channel
ΔVF too high
Upper OTP triggered but
CHx < 7.5V
All channels go off until chip cooled and then comes back on with current Highest VF of
reduced to 76%. Subsequent OTP triggers will reduce IOUT further
CH0 through CH5
10
Output LED stack
voltage too high
VOUT > VOVP
Highest VF of
Any channel that is below the target current will time-out after 6 PWM
cycles, and VOUT will return to the normal regulation voltage required for CH0 through CH5
other channels.
11
VOUT/LX shorted to
GND at start-up or
VOUT shorted in
operation
LX current and timing are The chip is permanently shutdown 31mS after power-up if VOUT/Lx is
monitored.
shorted to GND.
OVP pins monitored for
excursions below 20% of
OVP threshold.
SMBCLK
tLOW
tF
tR
VIH
VIL
tHIGH
tHD:DAT
tHD:STA
tSU:STA
tSU:DAT
tSU:STO
SMBDAT
VIH
VIL
P
tBUF
S
P
S
NOTES:
SMBus/I2C Description
S = start condition
P = stop condition
A = acknowledge
A = not acknowledge
R/W = read enable at high; write enable at low
FIGURE 26. SMBUS/I2C INTERFACE
1
7
1
1
8
1
8
1
1
S
Slave Address
W
A
Command Code
A
Data byte
A
P
Master to Slave
Slave to Master
FIGURE 27. WRITE BYTE PROTOCOL
17
FN7709.1
March 24, 2011
ISL97671A
1
7
1
1
8
1
1
8
1
1
8
1
1
S
Slave Address
W
A
Command Code
A
S
Slave Address
R
A
Data Byte
A
P
Master to Slave
Slave to Master
FIGURE 28. READ BYTE PROTOCOL
SMBus/I2C Communications
Slave Device Address
The ISL97671A can be controlled by SMBus/I2C for PWM or DC
dimming. The LEDs driving is default to off and the users will need
the SMBus/I2C interface to enable the driving and controlling of
various parameters that will be described in this section. Please
note that the ISL97671A can also be controlled by an external PWM
signal for PWM dimming without any SMBus/I2C interface. To do so,
the users need to pull the SMBCLK and SMBDAT pins to low or
ground the pins permanently if SMBus/I2C control is not used. The
switching frequency is fixed at 600kHz if SMBus/I2C is not used.
The slave address contains 7 MSB plus one LSB as R/W bit, but
these 8 bits are usually called Slave Address bytes. Figure 29 shows
the high nibble of the Slave Address byte is 0x5 or 0101b to denote
the “backlight controller class.” Bit 3 in the lower nibble of the Slave
Address byte is 1. Bit 0 is always the R/W bit, as specified by the
SMBus/I2C protocol. Note: In this document, the device address will
always be expressed as a full 8-bit address instead of the shorter
7-bit address typically used in other backlight controller
specifications to avoid confusion. Therefore, if the device is in the
write mode where bit 0 is 0, the slave address byte is 0x58 or
01011000b. If the device is in the read mode where bit 0 is 1, the
slave address byte is 0x59 or 01011001b.
Read Byte
SMBus/I2C Register Definitions
The backlight controller registers are Byte wide and accessible via the
SMBus/I2C Read/Write Byte protocols. Their bit assignments are
provided in the following sections with reserved bits containing a
default value of “0”.
MSB
0
LSB
1
0
DEVICE
IDENTIFIER
1
1
0
0
R/W
DEVICE
ADDRESS
RE
AD
/W
Figure 28 shows the four byte long Read Byte protocol starts out
with the slave address followed by the “command code” which
translates to the “register index.” Subsequently, the bus direction
turns around with the re-broadcast of the slave address with bit 0
indicating a read (“R”) cycle. The fourth byte contains the data
being returned by the backlight controller. That byte value in the
data byte reflects the value of the register being queried at the
“command code” index. Note the bus directions, which are
highlighted by the shaded label that is used on cycles during which
the slaved backlight controller “owns” or “drives” the Data line. All
other cycles are driven by the “host master.”
The backlight controller may sense the state of the pins at POR or
during normal operation - the pins will not change state while the
device is in operation.
TE
BI
T
The Write Byte protocol is only three bytes long. The first byte starts
with the slave address followed by the “command code,” which
translates to the “register index” being written. The third byte
contains the data byte that must be written into the register selected
by the “command code”. A shaded label is used on cycles during
which the slaved backlight controller “owns” or “drives” the Data
line. All other cycles are driven by the “host master.”
RI
Write Byte
FIGURE 29. SLAVE ADDRESS BYTE DEFINITION
TABLE 3A. ISL97671A REGISTER LISTING
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DEFAULT
VALUE
SMBUS/I2C
PROTOCOL
0x00
PWM Brightness
Control Register
BRT7
BRT6
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
0xFF
Read and Write
0x01
Device Control
Register
Reserved
Reserved
Reserved
Reserved
Reserved
PWM_MD
PWM_SEL
BL_CTL
0x00
Read and Write
0x02
Fault/Status
Register
Reserved
Reserved
2_CH_SD
1_CH_SD
BL_STAT
OV_CURR
THRM_SHDN
FAULT
0x00
Read Only
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FN7709.1
March 24, 2011
ISL97671A
TABLE 3A. ISL97671A REGISTER LISTING (Continued)
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DEFAULT
VALUE
SMBUS/I2C
PROTOCOL
0x03
Identification
Register
LED PANEL
MFG3
MFG2
MFG1
MFG0
REV2
REV1
REV0
0xC8
Read Only
0x07
DC Brightness
Control Register
BRTDC7
BRTDC6
BRTDC5
BRTDC4
BRTDC3
BRTDC2
BRTDC1
BRTDC0
0xFF
Read and Write
0x08
Configuration
Register
Reserved
DirectPWM
0
1
1
FSW
Reserved
VSC
0x1F
Read and Write
0x09
Output Channel
Register
Reserved
Reserved
CH5
CH4
CH3
CH2
CH1
CH0
0x3F
Read and Write
0x0A
Phase Shift Deg
Equal
Phase
Phase
Shift6
Phase
Shift5
Phase
Shift4
Phase
Shift3
Phase
Shift2
Phase
Shift1
Phase
Shift0
0x00
Read and Write
TABLE 3B. DATA BIT DESCRIPTIONS
ADDRESS
REGISTER
DATA BIT DESCRIPTIONS
0x00
PWM Brightness Control
Register
BRT[7..0] = 256 steps of DPWM duty cycle brightness control
0x01
Device Control Register
PWM_MD = PWM mode select bit (1 = absolute brightness, 0 = % change), default = 0
PWM_SEL = Brightness control select bit (1 = control by PWMI, 0 = control by SMBus/I2C), default = 0
BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0
0x02
Fault/Status Register
2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK)
1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK)
BL_STAT = BL status (1 = BL On, 0 = BL Off)
OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK)
THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK)
FAULT = Fault occurred (Logic “OR” of all of the fault conditions)
0x03
Identification Register
MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9)
REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)
0x07
DC Brightness Control Register
BRTDC[7..0] = 256 steps of DC brightness control
0x08
Configuration Register
DirectPWM = Forces the PWM input signal to directly control the current sources.
Bits 3, 4, and 5 should be 1, 1, 0
FSW = Switching frequencies selection, FSW = 0 = 1.2MHz. FSW = 1 = 600kMHz
VSC[0] = Short circuit thresholds selection, 0 = disabled, 1 = 7.2V minimum
0x09
Output Channel Mask/Fault
Readout Register
CH[5..0] = Output Channel Read and Write. In Write, 1 = Channel Enabled, 0 = Channel Disabled. In
Read, 1 = Channel OK, 0 = Channel Not OK/Channel disabled
0x0A
Phase Shift Degree
EqualPhase = Controls phase shift mode - When 1, phase shift is 360/N (where N is the number of
channels enabled). When 0, phase shift is defined by PhaseShift<6:0>.
PS[6..0] = 7-bit Phase shift setting - phase shift between each channel is
PhaseShift<6:0>/(255*PWMFreq). In direct PWM modes, phase shift between each channel is
PhaseShift<6:0>/12.8MHz.
PWM Brightness Control Register (0x00)
The Brightness control resolution has 256 steps of PWM duty cycle
adjustment. Figure 30 shows the bit assignment. All of the bits in
this Brightness Control Register can be read or write. Step 0
corresponds to the minimum step where the current is less than
10µA. Steps 1 to 255 represent the linear steps between 0.39% and
100% duty cycle with approximately 0.39% duty cycle adjustment
per step.
• An SMBus/I2C Read Byte cycle to Register 0x00 returns the
programmed PWM brightness level.
• An SMBus/I2C setting of 0xFF for Register 0x00 sets the
backlight controller to the maximum brightness.
• An SMBus/I2C setting of 0x00 for Register 0x00 sets the
backlight controller to the minimum brightness output.
• Default value for Register 0x00 is 0xFF.
• An SMBus/I2C Write Byte cycle to Register 0x00 sets the PWM
brightness level only if the backlight controller is in SMBus/I2C
mode (see Table 4) Operating Modes selected by Device
Control Register Bits 1 and 2).
19
FN7709.1
March 24, 2011
ISL97671A
REGISTER 0x00
PWM BRIGHTNESS CONTROL REGISTER
BRT7
BRT6
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
= 256 steps of PWM brightness levels
BRT[7..0]
FIGURE 30. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
REGISTER 0x01
DEVICE CONTROL REGISTER
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PWM_MD
PWM_SEL
BL_CTL
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
PWM_MD
PWM_SEL
BL_CTL
MODE
X
X
0
Backlight Off
0
0
1
SMBus/I2C and PWM dimming (DPST)
0
1
1
PWMI controlled PWM dimming
1
0
1
SMBus/I2C controlled PWM dimming
1
1
1
SMBus/I2C controlled PWM dimming
FIGURE 31. DESCRIPTIONS OF DEVICE CONTROL REGISTER
Device Control Register (0x01)
SMBus/I2C
This register has two bits that control either
controlled or external PWM controlled PWM dimming and a
single bit that controls the BL ON/OFF state. The remaining bits
are reserved. The bit assignment is shown in Figure 31. All other
bits in the Device Control Register will read as low unless
otherwise written.
• All reserved bits have no functional effect when written.
• All defined control bits return their current, latched value when
read.
A value of 1 written to BL_CTL turns on the BL in 4ms or less after
the write cycle completes. The BL is
• deemed to be on when Bit 3 BL_STAT of Register 0x02 is 1 and
Register 0x09 is not 0.
TABLE 4. OPERATING MODES SELECTED BY DEVICE CONTROL
REGISTER BITS 1 AND 2
PWM_MD
PWM_SEL
MODE
X
1
PWM Mode
1
0
SMBus/I2C Mode
0
0
SMBus/I2C and PWM Mode with DPST
The PWM_SEL bit determines whether the SMBus/I2C or PWM
input should drive the output brightness in terms of PWM
dimming. When PWM_SEL bit is 1, the PWM drives the output
brightness regardless of what the PWM_MD is.
• When SMBus/I2C mode with DPST is selected, Register 0x00
reflects the last value written to it from SMBus/I2C.
When the PWM_SEL bit is 0, the PWM_MD bit selects the
manner in which the PWM dimming is to be interpreted; when
this bit is 1, the PWM dimming is based on the SMBus/I2C
brightness setting. When this bit is 0, the PWM dimming reflects
a percentage change in the current brightness programmed in
the SMBus/I2C Register 0x00, i.e. DPST (Display Power Saving
Technology) mode as:
The default value for Register 0x01 is 0x00.
DSPT Brightness = Cbt × PWM
• A value of 0 written to BL_CTL immediately turns off the BL. The BL
is deemed to be off when Bit 3 BL_STAT of Register 0x02 is 0 and
Register 0x09 is 0.
(EQ. 16)
Where:
Cbt = Current brightness setting from SMBus/I2C Register 0x00
without influence from the PWM
20
FN7709.1
March 24, 2011
ISL97671A
PWM = is the percent duty cycle of the PWM
exception of bit 0, which can be cleared by writing to it.
For example, the Cbt = 50% duty cycle programmed in the
SMBus/I2C Register 0x00 and the PWM frequency is tuned to be
200Hz with an appropriate capacitor at the FPWM pin. On the other
hand, PWM is fed with a 1kHz 30% high PWM signal. When
PWM_SEL = 0 and PWM_MD = 0, the device is in DPST operation
where DPST brightness = 15% PWM dimming at 200Hz.
• A Read Byte cycle to Register 0x02 indicates the current BL
on/off status in BL_STAT (1 if the BL is on, 0 if the BL is off).
Fault/Status Register (0x02)
• 1_CH_SD returns a 1 if one or more channels have faulted out.
This register has 6 status bits that allow monitoring of the backlight
controller’s operating state. Bit 0 is a logical “OR” of all fault codes to
simplify error detection. Not all of the bits in this register are fault
related (Bit 3 is a simple BL status indicator). The remaining bits are
reserved and return a “0” when read and ignore the bit value when
written. All of the bits in this register are read-only, with the
• 2_CH_SD returns a 1 if two or more channels have faulted out.
REGISTER 0x02
• A Read Byte cycles to Register 0x2 also returns FAULT as the
logical OR of THRM_SHDN, OV_CURR, 2_CH_SD, and 1_CH_SD
should these events occur.
• A fault will not be reported in the event that the BL is
commanded on and then immediately off by the system.
• When FAULT is set to 1, it will remain at 1 even if the signal
which sets it goes away. FAULT will be cleared when the
FAULT/STATUS REGISTER
RESERVED
RESERVED
2_CH_SD
1_CH_SD
BL_STAT
OV_CURR
THRM_SHDN
FAULT
Bit 7 (R)
Bit 6 (R)
Bit 5 (R)
Bit 4 (R)
Bit 3 (R)
Bit 2 (R)
Bit 1 (R)
Bit 0 (R)
BIT
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
Bit 5
2_CH_SD
= Two LED output channels are shutdown (1 = shutdown, 0 = OK)
Bit 4
1_CH_SD
= One LED output channel is shutdown (1 = shutdown, 0 = OK)
Bit 3
BL_STAT
= BL Status (1 = BL On, 0 = BL Off)
Bit 2
OV_CURR
= Input Overcurrent (1 = Overcurrent condition, 0 = Current OK)
Bit 1
THRM_SHDN
= Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK)
Bit 0
FAULT
= Fault occurred (Logic “OR” of all of the fault conditions)
FIGURE 32. DESCRIPTIONS OF FAULT/STATUS REGISTER
REGISTER 0x03
ID REGISTER
LED PANEL
MFG3
MFG2
MFG1
MFG0
REV2
REV1
REV0
Bit 7 = 1
Bit 6 (R)
Bit 5 (R)
Bit 4 (R)
Bit 3 (R)
Bit 2 (R)
Bit 1 (R)
Bit 0 (R)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
MFG[3..0]
= Manufacturer ID. See “Identification Register
(0x03)” on page 21.
data 0 to 8 in decimal correspond to other vendors
data 9 in decimal represents Intersil ID
data 10 to 14 in decimal are reserved
data 15 in decimal Manufacturer ID is not
implemented
REV[2..0]
= Silicon rev (Rev 0 through Rev 7 allowed for silicon
spins)
FIGURE 33. DESCRIPTIONS OF ID REGISTER
21
FN7709.1
March 24, 2011
ISL97671A
REGISTER 0x07
DC BRIGHTNESS CONTROL REGISTER
BRTDC7
BRTDC6
BRTDC5
BRTDC4
BRTDC3
BRTDC2
BRTDC1
BRTDC0
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
BIT ASSIGNMENT
BRTDC[7..0]
BIT FIELD DEFINITIONS
= 256 steps of DC brightness levels
FIGURE 34. DESCRIPTIONS OF DC BRIGHTNESS CONTROL REGISTER
DC Brightness Control Register (0x07)
The DC Brightness Control Register 0x07 allows users to have
additional dimming flexibility by:
1. Effectively achieving 16-bits of dimming control when DC
dimming is combined with PWM dimming
2. Achieving visual or audio noise free 8-bit DC dimming over
potentially noisy PWM dimming.
The bit assignment is shown in Figure 34. All of the bits in this
Register can be read or write. Steps 0 to 255 represent the linear
steps of current adjustment in DC on-the-fly. It can also be
considered as the peak current factory calibration feature to
account for various LED production batch variations, but external
EEPROM settings storing and restoring are required.
• An SMBus/I2C Write Byte cycle to Register 0x07 sets the
brightness level in DC only.
• An SMBus/I2C Read Byte cycle to Register 0x07 returns the
current DC brightness level.
• Default value for Register 0x07 is 0xFF.
Configuration Register (0x08)
The Configuration Register provides many extra functions that
users can explore in order to optimize the driver performance at
a given application.
A DirectPWM bit allows Direct PWM where the output current
follows the same input PWM signal.The FSW bit allows users to
set the boost conversion switching frequency between 1.2MHz
and 600kHz. The VSC bits allow users to set LED string short
circuit threshold Vsc to 7.2V or disable it.
The bit assignment is shown in Figure 35. The default value for
Register 0x08 is 0x1F.
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FN7709.1
March 24, 2011
ISL97671A
Output Channel Mask/Fault Readout
Register (0x09)
This register can be read or write; the bit position corresponds to
the channel. For example, Bit 0 corresponds to Ch0 and bit
5corresponds to Ch5 and so on. Writing data to this register, it
enables the channels of interest. When reading data from this
register, any disabled channel and any faulted out channel will
read as 0. This allows the user to determine which channel is
REGISTER 0x08
faulty and optionally not enabling it in order to allow the rest of
the system to continue to function. Additionally, a faulted out
channel can be disabled and re-enabled in order to allow a retry
for any faulty channel without having to power-down the other
channels.
The bit assignment is shown in Figure 36. The default for
Register 0x09 is 0x3F.
CONFIGURATION REGISTER
RESERVED
RESERVED
BIT5
BIT4
BIT3
FSW
RESERVED
VSC
Bit 7 (R/W)
Bit 6 (R/W)
0 (W)
1(W)
1(W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
DirectPWM
Forces the PWMI signal to directly control the current sources. Note that
there is some synchronous delay between PWMI and current sources.
BITS[5-3]
FSW
These bits should always be written as 011
2 levels of Switching Frequencies (1 = 1,200kHz, 0 = 600kHz)
VSC[0]
2 levels of Short-Circuit Thresholds (0 = disabled, 1 = 7.5V minimum)
FIGURE 35. DESCRIPTIONS OF CONFIGURATION REGISTER
REGISTER 0x09
OUTPUT CHANNEL REGISTER
RESERVED
RESERVED
CH5
CH4
CH3
CH2
CH1
CH0
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
CH[5..0]
CH5 = Channel 5, CH4 = Channel 4 and so on
FIGURE 36. OUTPUT CHANNEL REGISTER
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FN7709.1
March 24, 2011
ISL97671A
REGISTER 0x0A
PHASE SHIFT CONTROL REGISTER
EQUALPHASE
PHASESHIFT6
PHASESHIFT5
PHASESHIFT4
PHASESHIFT3
PHASESHIFT2
PHASESHIFT1
PHASESHIFT0
Bit 7 (R/W)
Bit 6 (R/W)
Bit 5 (R/W)
Bit 4 (R/W)
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1 (R/W)
Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
EqualPhase
Controls phase shift mode - When 0, phase shift is defined by PhaseShift<6:0>. When 1, phase shift
is 360/N (where N is the number of channels enabled).
PhaseShift[6..0]
7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq)
In direct PWM modes, phase shift between each channel is PhaseShift<6:0>/12.8MHz
FIGURE 37. DESCRIPTIONS OF PHASE SHIFT CONTROL REGISTER
Phase Shift Control Register (0x0A)
and ΔIL at On = ΔIL at Off, therefore:
The Phase Shift Control register is used to set phase delay
between each channels. When bit 7 is set high, the phase delay
is set by the number of channels enabled and the PWM
frequency. Refer to Figures 3 and 4, the delay time is defined by
Equation 17:
( V I – 0 ) ⁄ L × D × tS = ( VO – VD – VI ) ⁄ L × ( 1 – D ) × tS
(EQ. 17)
t D1 = ( t FPWM ⁄ N )
where N is the number of channels enabled, and tFPWM is the
period of the PWM cycle. When bit 7 is set low, the phase delay is
set by bits 6 to 0 and the PWM frequency. Referencing Figure 24,
the programmable delay time is defined by Equation 18:
t PD = ( PS < 6, 0 > xt FPWM ⁄ ( 255 ) )
(EQ. 18)
where PS is an integer from 0 to 127, and tFPWM is the period of
the PWM cycle. By default, all the register bits are set low, which
sets zero delay between each channel. Note that the user should
not program the register to give more than one period of the
PWM cycle delay between the first and last enabled channels.
Components Selections
According to the inductor Voltage-Second Balance principle, the
change of inductor current during the switching regulator On
time is equal to the change of inductor current during the
switching regulator Off time. Since the voltage across an inductor
is:
V L = L × ΔI L ⁄ Δt
(EQ. 19)
24
(EQ. 20)
where D is the switching duty cycle defined by the turn-on time
over the switching period. VD is Schottky diode forward voltage
that can be neglected for approximation.
Rearranging the terms without accounting for VD gives the boost
ratio and duty cycle respectively as:
VO ⁄ VI = 1 ⁄ ( 1 – D )
(EQ. 21)
D = ( VO – VI ) ⁄ VO
(EQ. 22)
Input Capacitor
Switching regulators require input capacitors to deliver peak
charging current and to reduce the impedance of the input
supply. This reduces interaction between the regulator and input
supply, thereby improving system stability. The high switching
frequency of the loop causes almost all ripple current to flow in
the input capacitor, which must be rated accordingly.
A capacitor with low internal series resistance should be chosen
to minimize heating effects and improve system efficiency, such
as X5R or X7R ceramic capacitors, which offer small size and a
lower value of temperature and voltage coefficient compared to
other ceramic capacitors.
In Boost mode, input current flows continuously into the inductor;
AC ripple component is only proportional to the rate of the
inductor charging, thus, smaller value input capacitors may be
used. It is recommended that an input capacitor of at least 10µF
be used. Ensure the voltage rating of the input capacitor is
suitable to handle the full supply range.
FN7709.1
March 24, 2011
ISL97671A
Inductor
The selection of the inductor should be based on its maximum
current (ISAT) characteristics, power dissipation (DCR), EMI
susceptibility (shielded vs unshielded), and size. Inductor type
and value influence many key parameters, including ripple
current, current limit, efficiency, transient performance and
stability.
The inductor’s maximum current capability must be adequate
enough to handle the peak current at the worst case condition. If
an inductor core is chosen with too low a current rating,
saturation in the core will cause the effective inductor value to
fall, leading to an increase in peak to average current level, poor
efficiency and overheating in the core. The series resistance,
DCR, within the inductor causes conduction loss and heat
dissipation. A shielded inductor is usually more suitable for EMI
susceptible applications, such as LED backlighting.
The peak current can be derived from the voltage across the
inductor during the Off period, as expressed in Equation 23:
IL pk = ( V O × I O ) ⁄ ( 85% × V I ) + 1 ⁄ 2 [ V I × ( V O – V I ) ⁄ ( L × V O × f SW ) ]
(EQ. 23)
The choice of 85% is just an average term for the efficiency
approximation. The first term is the average current, which is
inversely proportional to the input voltage. The second term is
the inductor current change, which is inversely proportional to L
and fSW. As a result, for a given switching frequency and
minimum input voltage on which the system operates, the
inductor ISAT must be chosen carefully. At a given inductor size,
usually the larger the inductance, the higher the series resistance
because of the extra winding of the coil. Thus, the higher the
inductance, the lower the peak current capability. The ISL97671A
current limit should also have to be taken into account.
A larger output capacitor will also ease the driver response
during PWM dimming Off period due to the longer sample and
hold effect of the output drooping. The driver does not need to
boost harder in the next On period that minimizes transient
current. The output capacitor is also needed for compensation,
and, in general 2x4.7µF/50V ceramic capacitors are suitable for
notebook display backlight applications.
Schottky Diode
A high speed rectifier diode is necessary to prevent excessive
voltage overshoot, especially in the boost configuration. Low
forward voltage and reverse leakage current will minimize
losses, making Schottky diodes the preferred choice. Although
the Schottky diode turns on only during the boost switch Off
period, it carries the same peak current as the inductor, and
therefore, a suitable current rated Schottky diode must be used.
Applications
High Current Applications
Each channel of the ISL97671A can support up to 50mA. For
applications that need higher current, multiple channels can be
grouped to achieve the desirable current. For example, the
cathode of the last LED can be connected to CH0 to CH2, this
configuration can be treated as a single string with 150mA
current driving capability.
VOUT
CH0
CH1
Output Capacitors
The output capacitor acts to smooth the output voltage and
supplies load current directly during the conduction phase of the
power switch. Output ripple voltage consists of the discharge of
the output capacitor for ILPEAK during FET On and the voltage
drop due to flowing through the ESR of the output capacitor. The
ripple voltage can be shown as:
ΔV CO = ( I O ⁄ C O × D ⁄ fS ) + ( ( I O × ESR )
(EQ. 24)
The conservation of charge principle in Equation 24 also brings
up the fact that during the boost switch Off period, the output
capacitor is charged with the inductor ripple current minus a
relatively small output current in boost topology. As a result, the
user needs to select an output capacitor with low ESR and
enough input ripple current capability.
Output Ripple
CH2
FIGURE 38. GANGING MULTIPLE CHANNELS FOR HIGH CURRENT
APPLICATIONS
Multiple Drivers Operation
For large LCD panels where more than 6channels of LEDs are
needed, multiple ISL97671As with each driver having its own
supporting components can be controlled together with the
common SMBus/I2C. While the ISL97671A does not have extra
pins strappable slave address feature, but a separate EN signal
can be applied to each driver for asynchronous operation. A
trade-off of such scheme is that an exact faulty channel cannot
be identified since both controllers have the same I2C slave
address.
ΔVCo, can be reduced by increasing Co or fSW, or using small ESR
capacitors. In general, Ceramic capacitors are the best choice for
output capacitors in small to medium sized LCD backlight
applications due to their cost, form factor, and low ESR.
25
FN7709.1
March 24, 2011
ISL97671A
45V, 6 x 50mA*
VIN = 2.7~26.5V
Q1 (optional)
SMBCLK
ISL97671A
1 FAULT
SMBCLK
SMBDAT
SMBDAT
EN
VBIAS = 5V~12V
2 VIN
4 VDC
EN
LX 20
OVP 16
PGND 19
7 SMBCLK/SCL
6 SMBDAT/SDACH0 10
5 PWM
SMBCLK
SMBDAT
3 EN
17 RSET
EN
FIGURE 39. MULTIPLE DRIVERS OPERATION
Low Voltage Operations
The ISL97671A VIN pin can be seperately biased from the LEDs
power input to allow low voltage operation. For systems that have
only single supply, VOUT can be tied to the driver VIN pin to allow
initial start-up, (see Figure 40). The circuit works as follows; when
the input voltage is available and the device is not enable, the
VOUT follows VIN with a Schottky diode voltage drop. The VOUT
bootstrapped to VIN pin allows an initial startup once the part is
enable. Once the driver starts up with VOUT regulating to the
target, the VIN pin voltage also increases. As long as the VOUT
does not exceed 26.5V and the extra power loss on VIN is
acceptable, this configuration can be used for input voltage as
low as 3.0V. The Fault Protection FET feature cannot be used in
this configuration.
For systems that have dual supplies, VIN pin can be biased from
5V to 12V while input voltage can be as low as 2.7V, (see
Figure 41). In this configuration VB IAS is greater than or equal to
VIN for using the fault FET.
VIN = 3V~21V
26.5V, 6 x 50mA*
ISL97671A
CH1 11
CH2 12
CH3 13
CH4 14
8 FPWM
CH5 15
9 AGND
COMP 18
*VIN > 12V
FIGURE 41. DUAL SUPPLIES 2.7V OPERATION
16-Bit Dimming
The SMBus/I2C controlled PWM and DC dimmings can be
combined to effectively provide 16 bits of dimming capability,
which can be valuable for automotive and avionics display
applications.
RGB LEDs or Field Sequenctial LED
Backlighting
The ISL97671A allows users to select the six channels of PWM
dimming currents in any sequences and combinations that RGB
LEDs or Field Sequential backlighting applications can be
considered. On the other hand, the channel currents cannot be
dimmed independently at the same time.
For example, an RGB LEDs application requires channels 0 and 1
for the red LEDs at 40mA peak with 25% dimming, channels 2
and 3 for green LEDs at 20mA peak with 50% dimming, and
channels 4 and 5 for blue LEDs at 10mA peak with 100%
dimming.
1 FAULT
4 VDC
First the ILED is set at 40mA with an appropriate RSET, then the
SMBus/I2C programming sequences are shown in the followings:
LX 20
2 VIN
OVP 16
PGND 19
7 SMBCLK/SCL
Register0x01 data 0x05 “turn BL on and select SMBus dimming”
6 SMBDAT/SDACH0 10
5 PWM
3 EN
17 RSET
Register0x09 data 0x03 “select ch 0 and 1”
CH1 11
CH2 12
Register0x07 data 0xFF “set 100% of 40mA in DC”
CH3 13
Register0x00 data 0x40 “apply 25% PWM dimming”
CH4 14
8 FPWM
CH5 15
9 AGND
COMP 18
*VIN>12V
Register0x09 data 0x0C “select ch 2 and 3”
Register0x07 data 0x80 “set 50% of 40mA in DC”
FIGURE 40. SINGLE SUPPLY 3V OPERATION
Register0x00 data 0x80 “apply 50% PWM dimming”
Register0x09 data 0x30 “select ch 4 and 5”
Register0x07 data 0xFF “set 100% of 40mA in DC”
Register0x00 data 0xFF “apply 100% PWM dimming”
26
FN7709.1
March 24, 2011
ISL97671A
Compensation
The ISL97671A has two main elements in the system; the
Current Mode Boost Regulator and the op amp based
multi-channel current sources. The ISL97671A incorporates a
transconductance amplifier in its feedback path to allow the user
some levels of adjustment on the transient response and better
regulation. The ISL97671A uses current mode control
architecture, which has a fast current sense loop and a slow
voltage feedback loop. The fast current feedback loop does not
require any compensation. The slow voltage loop must be
compensated for stable operation. The compensation network is
a series Rc, Cc1 network from COMP pin to ground and an
optional Cc2 capacitor connected to the COMP pin. The Rc sets
the high frequency integrator gain for fast transient response and
the Cc1 sets the integrator zero to ensure loop stability. For most
applications, Rc is in the range of 15kΩ and Cc1 is in the range of
2.2nF. Depends on the PCB layout, a Cc2, in range of 47pF, may
be needed to create a pole to cancel the output capacitor ESR’s
zero effect for stability.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
3/24/11
FN7709.1
CHANGE
Initial Release to web.
Products
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on intersil.com: ISL97671A
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27
FN7709.1
March 24, 2011
ISL97671A
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
3.00
0.10 M C A B
0.05 M C
A
B
4
20X 0.25
16X 0.50
+0.05
-0.07
17
A
16
6
PIN 1
INDEX AREA
6
PIN 1 INDEX AREA
(C 0.40)
20
1
4.00
2.65
11
+0.10
-0.15
6
0.15 (4X)
A
10
7
VIEW "A-A"
1.65
TOP VIEW
+0.10
-0.15
20x 0.40±0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.9± 0.10
C
SEATING PLANE
0.08 C
SIDE VIEW
(16 x 0.50)
(2.65)
(3.80)
(20 x 0.25)
C
(20 x 0.60)
0.2 REF
5
0.00 MIN.
0.05 MAX.
(1.65)
(2.80)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
28
FN7709.1
March 24, 2011