A-Data ADD8608A8A Revision History Revision 1 ( Dec. 2001 ) 1.Fister release. Revision 2 ( Apr. 2002 ) 1. Changed module current specification. 2. Add Performance range. 3. Changed AC Characteristics. 4. Changed typo size on module PCB in package dimensions. Rev 2 April, 2002 1 A-Data ADD8608A8A Double Data Rate SDRAM 8M x 8 Bit x 4 Banks General Description Features The ADD8608A8A are four-bank Double Data Rate(DDR) Synchronous DRAMs organized as 8,392,608 words x 8 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Data outputs occur at both rising edges of CK and /CK. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications •2.5V for VDDQ power supply •SSTL_2 interface •MRS Cycle with address key programs -CAS Latency (2, 2.5) -Burst Length (2,4 &8) -Burst Type (sequential & Interleave) •4 banks operation •Differential clock input (CK, /CK) operation •Double data rate interface •Auto & Self refresh •8192 refresh cycle •DQM for masking •Package:66-pins 400 mil TSOP-Type II Ordering Information. Part No. Frequency Interface Package ADD8608A8A-75BA ADD8608A8A-75B 133Mhz(7.5ns/CL=2) 133Mhz(7.5ns/CL=2.5) SSTL_2 400mil 66pin TSOPII Pin Assignment VD D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 D Q0 VDD Q NC DQ1 VSSQ NC DQ2 VDD Q NC DQ3 VSSQ NC NC VD D Q NC NC VD D NC 1 NC WE CAS RAS CS NC BS0 BS1 A10/AP A0 A1 A2 A3 VDD 66-pin plastic TSOP II 400 mil Rev 2 April, 2002 2 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VS S DQ7 V S SQ NC DQ6 VDDQ NC DQ5 V S SQ NC DQ4 VDD Q NC NC VS S Q DQS NC VR E F VS S DM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VS S A-Data ADD8608A8A Pin Description PIN NAME FUNCTION CK, /CK System Clock Differential clock input. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS Chip Select Disables or Enables device operation by masking or enabling all input Address Row / Column address are multiplexed on the same pins. except CK, CKE and DQ A0~A12 Row address : A0~A12 Column address : A0~A9 BS0~BS1 Banks Select Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. DQ0~DQ7 Data Data inputs / outputs are multiplexed on the same pins. /RAS Row Address Strobe /CAS Column Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low Latches Column addresses on the positive edge of the CLK with /CAS low /WE VDD/VSS Write Enable Enables write operation and row recharge. Power Supply/Ground Power and Ground for the input buffers and the core logic. VDDQ/VSSQ Data Output Power/Ground VREF NC Power supply for output buffers. Reference Voltage Reference voltage for inputs for SSTL interface. No Connection This pin is recommended to be left No Connection on the device. Block Diagram CK CKE Clock Generator Bank3 Bank2 Mode Register Address Buffer & Refresh Counter Row Decoder Bank1 Address Bank0 /CAS /WE Rev 2 April, 2002 Column Address Buffer & Refresh Counter Data Control Circuit 3 DQM DQS Column Decoder Data Latch /RAS Control Logic /CS Command Decoder Amplifier DQ0~DQ7 A-Data ADD8608A8A Absolute Maximum Ratings Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol Value Unit VIN, Vout -0.5 ~ 3.6 V VDD, VDDQ -1.0 ~ 3.6 V TSTG -55 ~ +150 ℃ PD 1.5 W IOUT 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 ℃ Parameter Symbol Min Max Unit Note Supply voltage VDD 2.3 2.7 V Supply voltage VDDQ 2.3 2.7 Input logic high voltage VIH VREF+0.15 VDDQ+0.3 V Input logic low voltage VIL -0.3 VREF-0.15 V Differential Clock DC Input voltage VICK -0.3 VDDQ+0.3 V Input Differential CLK&/CLK voltage VID 0.7 VDDQ+0.6- V Input leakage current IIL -5 5 uA 3 Output leakage current IOL -5 5 uA 4 Reference Voltage VREF 0.49* VDDQ 0.51* VDDQ V Termination Voltage VTT VREF-0.04 VREF+0.04 1 2 5 Note : 1. VDDQ must not exceed the level of VDDQ. 2.VIL(min)=-0.9V with a pulse width ≦ 5ns . 3.Any input 0V ≦ VIN ≦ 3.6V, all other pins are not under test = 0V. 4.Dout is disabled, 0V ≦ VOUT ≦ 2.7V. 5. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed ±2% of the DC value. Rev 2 April, 2002 4 A-Data ADD8608A8A AC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 ℃ Parameter Symbol Value Unit VIH / VIL VREF+0.31/VREF-0.31 V Vtrip 1.4 V Input rise / fall time TR / tF 1 Ns Output timing measurement reference level Voutfef 1.4 V CL 50 pF AC input high / low level voltage Input timing measurement reference level voltage Output load capacitance for access time measurement Note: 1. 3.15V ≦ VDD Note 2 ≦ 3.6V is applied for VDD8608A4A5. 2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details, refer to AC/DC output load circuit. Capacitance TA=25℃, f-=1Mhz Parameter Input capacitance Pin Symbol Min Max Unit CK, /CK Cl1 2 3.0 pF A0~A12,BS0,BS1,CKE,/CS,/RAS, Cl2 2 3.0 pF CI/O 4 5 pF /CAS,/WE,DQM Data input / output capacitance DQM Output load circuit V tt =0.5*V DDQ R T=50Ω Output Z0=50Ω C LOAD =30pF V REF =0.5*V DDQ Output Load Circuit (SSTL_2) Rev 2 April, 2002 5 A-Data ADD8608A8A DC Characteristics II Speed Parameter Symbol Test condition Unit Note 110 mA 1 3 mA 40 mA 30 mA 65 mA 155 mA 1 190 mA 2 3 mA -75BA/-75B Burst length=2, One bank active Operating Current IDD1 Trc=tRC(min),IOUT=0mA Precharge standby current in power IDD2P CKE≦VIL(max), tCK=min down mode Precharge standby CKE≧VIH(min), /CS≧VIH(min), current in Non power IDD2N tCK= tCK min input signals are down mode changed one time during 2clks. Active standby current in power IDD3P CKE≦VIL(max), tCK= tCK min down mode Active standby CKE≧VIH(min), /CS≧VIH(min), current in Non power IDD3N tCK=min input signals are down mode changed one time during 2clks. tCK≧tCK(min),IOUT=0 mA Burst mode operating IDD4R current All banks active tRRC≧tRRC(min), All banks Auto refresh current IDD5 active Self refresh current IDD6 CKE≦0.2V Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC is shown at AC characteristics. Rev 2 April, 2002 6 A-Data ADD8608A8A AC Characteristics -75BA Parameter -75B Symbol Unit Min Max Min Max System clock /CAS Latency = 2.5 tCK2.5 7.5 12 7.5 12 Cycle time tCK2 7.5 12 10 12 ns Clock high pulse width tCHW 0.45 0.55 0.45 0.55 CLK Clock low pulse width tCLW 0.45 0.55 0.45 0.55 CLK Access time form CK to /CK tAC -0.75 0.75 -0.75 0.75 ns Data strobe edge to clock edge tDQSCK -0.75 0.75 -0.75 0.75 ns Clock to first rising edge of DQS delay tDQSS 0.75 1.25 0.75 1.25 CLK /RAS cycle time tRC 65 - 65 - ns /RAS to /CAS delay tRCD 20 - 20 - ns /RAS active time tRAS 45 120K 45 120K ns /RAS precharge time tRP 20 - 20 - ns /RAS to /RAS bank active delay tRRD 15 - 15 - ns /CAS to /CAS delay tCCD 1 - 1 - CLK Data-in setup time (to DQS) tDS 0.5 - 0.5 - ns Data-in hold time (to DQS) tDH 0.5 - 0.5 - ns DQS Falling Edge to CLK Setup Time tDSS 0.2 - 0.2 - CLK DQS Falling Edge Hold Time from CLK tDSH 0.2 - 0.2 - CLK Input setup time tIS 0.9 - 0.9 - ns Input hold time tIH 0.9 - 0.9 - ns DQS-in high level width tDSH 0.35 - 0.35 - CLK DQS-in low level width tDSL 0.35 - 0.35 - CLK 0 - 0 - ns 0.4 06 0.4 06 CLK 0.5 ns 1.1 CLK /CAS Latency = 2 Clock to DQS write preamble setup time tWPRES Write preamble tWPST Data strobe edge to output data edge tDQSQ Mode register set cycle time tMRD 15 DQS read preamble tRPRE 0.9 Rev 2 April, 2002 0.5 7 15 1.1 0.9 A-Data ADD8608A8A Command Truth-Table Command CKEn-1 CKEn /CS /RAS /CAS /WE DM Mode Register Set H X L L L L X No Operation H X L H H H X Bank Active H X L L H H X H X L H L H X ADDR A10/AP CA CA BS L X V Read V L V Read with Auto Precharge Write V H H X L H L L X V Write with Auto Precharge L Precharge All Bank H X L L H L X Burst Stop H X L H H L X X Auto Refresh H H L L L H X X Entry H L L L L H X H X X X Exit L H Self Refresh H H H H X X X Precharge L H H H Power down H X X X L H H X Exit H L X H X X L Entry L X H X X Enable H X X X X X L Disable H X X X X X H Data write X Rev 2 April, 2002 V H 8 X A-Data ADD8608A8A Package Information 66 34 1 33 SYMBOL A A1 A2 B c D HE E e L L1 MIN. 0.05 0.95 0.17 0.09 11.74 10.15 0.65 BSC 0.40 S θ 0° MILLIMETER NOM. 1.00 0.24 0.145 22.62 BSC 11.76 10.16 0.50 0.80 REF 0.71 REF - MAX. 1.20 0.15 1.05 0.32 0.2 11.78 10.17 MIN. 0.002 0.037 0.007 0.004 0.60 0.462 0.3996 0.026 0.016 8° 0° 400mil 66pin TSOP II Package Rev 2 April, 2002 9 INCH NOM. 0.039 0.009 0.0006 0.891 BSC 0.463 0.400 0.020 0.031 REF 0.028 REF - MAX. 0.047 0.006 0.041 0.013 0.008 0.464 0.4004 0.024 8°