ISL59442 ® Data Sheet September 21, 2005 FN7452.2 1GHz, 4 x 1 Multiplexing Amplifier Features The ISL59442 is a single-output 4:1 MUX-amp. The MUX-amp has a fixed gain of 1 and a 1GHz bandwidth. The device contains logic inputs for channel selection (S0, S1), and a three-state output control (HIZ) for individual selection of MUX amps that share a common video output line. All logic inputs have pull-downs to ground and may be left floating. • 1GHz (-3dB) Bandwidth (VOUT = 200mVP-P) • 235MHz (-3dB) Bandwidth (VOUT = 1VP-P) • Slew Rate (RL = 525Ω, VOUT = 5V) . . . . . . . . . . . . 1452V/µs • High Speed Three-state Output (HIZ) • Pb-Free Plus Anneal Available (RoHS Compliant) Applications TABLE 1. TRUTH TABLE HIZ S1 S0 OUT 0 0 0 IN0 0 0 1 IN1 0 1 0 IN2 0 1 1 IN3 • Set-top Boxes 1 X X HIZ • Security Video • HDTV/DTV Analog Inputs • Video Projectors • Computer Monitors • Broadcast Video Equipment Pinout ISL59442 (14 LD SO) TOP VIEW Functional Diagram EN0 IN0 1 14 V+ NIC 2 13 S0 S0 EN1 S1 IN1 3 GND 4 OUT IN1 DECODE 12 S1 IN0 EN2 11 HIZ IN2 IN3 EN3 IN2 5 10 OUT A=1 NIC 6 9 NIC HIZ IN3 7 8 V- Ordering Information PART NUMBER PART MARKING PACKAGE TAPE & REEL PKG. DWG. # - MDP0027 ISL59442IB 59442IB 14 Ld SO ISL59442IB-T7 59442IB 14 Ld SO 7” MDP0027 ISL59442IB-T13 59442IB 14 Ld SO 13” MDP0027 ISL59442IBZ (Note) 59442IBZ 14 Ld SO (Pb-free) - MDP0027 ISL59442IBZ-T7 (Note) 59442IBZ 14 Ld SO (Pb-free) 7” MDP0027 ISL59442IBZ-T13 59442IBZ (Note) 14 Ld SO (Pb-free) 13” MDP0027 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL59442 Absolute Maximum Ratings (TA = 25°C) Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . . . -40°C to 85°C Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, Input Video = 1VP-P & RL = 500Ω to GND, VHIZ = 0.8V, Unless Otherwise Specified DESCRIPTION CONDITIONS MIN TYP MAX UNIT No load, VHIZ = 0.8V 14.5 18 20 mA No load, VHIZ = 2.0V 12 15.5 17.5 mA GENERAL IS Supply Current (VOUT = 0V) VOUT Positive and Negative Output Swing VIN = ±3.5V, RL = 500Ω ±3.2 ±3.44 IOUT Output Current RL = 10Ω to GND ±80 ±120 ±180 mA VOS Output Offset Voltage -2 9 20 mV Ib Input Bias Current VIN = 0V -5 -2.5 -1 µA Rout Output Resistance HIZ = logic high, (DC) 1.4 MΩ HIZ = logic low, (DC) 0.2 Ω 10 MΩ RIN Input Resistance VIN = ±3.5V ACL or AV Voltage Gain VIN = ±1.5V, RL = 500Ω ITRI Output Current in Three-state VOUT = 0V V 0.999 1.001 1.003 V/V -35 6 35 µA LOGIC VH Input High Voltage (Logic Inputs) VL Input Low Voltage (Logic Inputs) IIH Input High Current (Logic Inputs) IIL Input Low Current (Logic Inputs) 2 50 V 90 0.8 V 150 µA 2 µA VOUT = 200mVP-P, CL = 1.6pF 1.0 GHz VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 235 MHz VOUT = 200mVP-P, CL = 1.6pF 100 MHz VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 35 MHz AC GENERAL -3dB BW 0.1dB BW -3dB Bandwidth 0.1dB Bandwidth dG Differential Gain Error NTC-7, RL = 150 0.01 % dP Differential Phase Error NTC-7, RL = 150 0.02 ° +SR Slew Rate 25% to 75%, VOUT = 5V, RL = 525Ω, CL = 23.6pF 1452 V/µs -SR Slew Rate 25% to 75%, VOUT = 5V, RL = 525Ω, CL = 23.6pF 1124 V/µs 2 FN7452.2 September 21, 2005 ISL59442 Electrical Specifications PARAMETER V+ = +5V, V- = -5V, GND = 0V, TA = 25°C, Input Video = 1VP-P & RL = 500Ω to GND, VHIZ = 0.8V, Unless Otherwise Specified (Continued) DESCRIPTION CONDITIONS PSRR Power Supply Rejection Ratio DC, PSRR V+ and V- combined V± = ±4.5V to ±5.5V ISO Channel Isolation f = 10MHz, Ch-Ch X-Talk and Off Isolation, CL = 1.6pF MIN TYP MAX UNIT -50 -57 dB 75 dB 2 mVP-P 135 mVP-P SWITCHING CHARACTERISTICS VGLITCH Channel-to-Channel Switching Glitch VIN = 0V, CL = 23.6pF, RS = 25Ω HIZ Switching Glitch VIN = 0V, CL = 23.6pF, RS = 25Ω tSW-L-H Channel Switching Time Low to High 1.2V logic threshold to 10% movement of analog output 30 ns tSW-H-L Channel Switching Time High to Low 1.2V logic threshold to 10% movement of analog output 28 ns VOUT = 200mVP-P, CL = 1.6pF 0.69 ns VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 1.4 ns TRANSIENT RESPONSE tr, tf Rise & Fall Time, 10% to 90% tS 0.1% Settling Time VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 6.6 ns tPLH Propagation Delay - Low to High, 10% to 10% VOUT = 200mVP-P, CL = 1.6pF 0.46 ns VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 0.92 ns Propagation Delay- High to Low, 10% to 10% VOUT = 200mVP-P, CL = 1.6pF 0.52 ns VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 0.97 ns Overshoot VOUT = 200mVP-P, CL = 1.6pF 8.3 % VOUT = 2VP-P, CL = 23.6pF, RS = 25Ω 13.3 % tPHL OS Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. 5 4 5 4 VOUT = 200mVP-P CL = 1.6pF 3 VOUT = 200mVP-P CL = 9.7pF 2 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 3 CL = 7.2pF 1 0 -1 CL = 5.5pF -2 CL = 1.6pF -3 -4 CL INCLUDES 1.6pF BOARD CAPACITANCE -5 0.001 RL = 1kΩ 2 1 RL = 500Ω 0 -1 -2 RL = 150Ω -3 RL = 75Ω -4 0.01 0.1 1 1.5 FREQUENCY (GHz) FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL 3 -5 0.001 0.01 0.1 1 1.5 FREQUENCY (MHz) FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs RL FN7452.2 September 21, 2005 ISL59442 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. 5 4 5 VOUT = 2VP-P RS = 25Ω 4 3 2 1 CL = 11.6pF CL = 16.6pF 0 -1 -2 CL = 23.6pF -3 CL INCLUDES 1.6pF BOARD CAPACITANCE -5 0.001 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 3 -4 2 1 RL = 1kΩ 0 RL = 75Ω -1 -2 RL = 500Ω -3 RL = 150Ω -4 CL = 28.6pF 0.01 VOUT = 2VP-P CL = 23.6pF RS = 25Ω -5 0.001 1 1.5 0.1 0.01 FREQUENCY (MHz) 0.5 0.2 0.1 0.3 0.0 CL = 7.2pF 0.2 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs RL CL = 9.7pF VOUT = 200mVP-P CL = 5.5pF 0.1 0 -0.1 -0.2 -0.3 -0.4 CL = 1.6pF CL INCLUDES 1.6pF BOARD CAPACITANCE -0.5 0.001 -0.1 -0.2 -0.3 RL = 1kΩ -0.4 -0.5 -0.7 0.01 0.1 RL = 500Ω -0.6 -0.8 0.001 1 1.5 0.01 1 1.5 0.1 FIGURE 6. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs RL 0.5 0.5 0.4 0.4 CL = 11.6pF CL = 16.6pF 0.2 0.1 0 -0.1 CL = 23.6pF VOUT = 2VP-P RS = 25Ω -0.3 CL INCLUDES 1.6pF BOARD CAPACITANCE -0.5 0.001 CL = 28.6pF 0.01 0.1 0.3 VOUT = 2VP-P CL = 23.6pF RS = 25Ω RL = 1kΩ RL = 500Ω 0.2 0.1 RL = 150Ω 0 RL = 75Ω -0.1 -0.2 -0.3 -0.4 1 1.5 FREQUENCY (MHz) FIGURE 7. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs CL 4 NORMALIZED GAIN (dB) 0.3 NORMALIZED GAIN (dB) RL = 75Ω FREQUENCY (MHz) FIGURE 5. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs CL -0.4 RL = 150Ω VOUT = 200mVP-P CL = 1.6pF FREQUENCY (MHz) -0.2 1 1.5 0.1 FREQUENCY (MHz) FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs CL 0.4 (Continued) -0.5 0.001 0.01 0.1 1 1.5 FREQUENCY (MHz) FIGURE 8. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs RL FN7452.2 September 21, 2005 ISL59442 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. -10 20 10 -30 -10 -40 -20 -50 -30 -60 -40 CROSSTALK -70 -50 -80 PSRR (V+) -60 -90 PSRR (V-) -70 -80 0.3 VIN = 1VP-P CL = 23.6pF RS = 25Ω -20 VIN = 200mVP-P CL = 23.6pF RS = 25Ω (dB) PSRR (dB) 0 (Continued) OFF ISOLATION -100 1 10 100 1000 FREQUENCY (MHz) -110 0.001 0.01 1 0.1 3 6 10 100 500 FREQUENCY (MHz) FIGURE 10. CROSSTALK AND OFF ISOLATION FIGURE 9. PSRR CHANNELS 100 60 INPUT VOLTAGE NOISE (nV/√Hz) OUTPUT RESISTANCE (Ω) VOUT = 100mVP-P 10 1 RF = 500Ω 50 40 30 20 10 0.1 0.1 1 10 100 0 1000 1 0.1 FREQUENCY (MHz) 100 FIGURE 12. INPUT NOISE vs FREQUENCY FIGURE 11. ROUT vs FREQUENCY S0, S1 1V/DIV 1V/DIV S0, S1 0 500mV/DIV 0 20mV/DIV 10 FREQUENCY (kHz) 0 VOUT 20ns/DIV FIGURE 13. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V, RS = 25, CL = 23.6pF 5 VOUT 0 20ns/DIV FIGURE 14. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V, RS = 25, CL = 23.6pF FN7452.2 September 21, 2005 ISL59442 Typical Performance Curves VS = ±5V, RL = 500Ω to GND, TA = 25°C, unless otherwise specified. HIZ 1V/DIV 1V/DIV HIZ 0 400mV/DIV 100mV/DIV 0 0 VOUT VOUT 0 20ns/DIV 20ns/DIV FIGURE 15. HIZ SWITCHING GLITCH VIN = 0V, RS = 25, CL = 23.6pF FIGURE 16. HIZ TRANSIENT RESPONSE VIN = 1V, RS = 25, CL = 23.6pF 160 2.4 CL = 1.6pF RL = 500Ω 120 80 2 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) (Continued) 40 0 -40 -80 1.6 1.2 0.8 0.4 0 CL = 23.6pF RS = 25Ω RL = 500Ω -0.4 -120 -160 -0.8 TIME (4ns/DIV) TIME (4ns/DIV) FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 1.136W 1.2 1 θ JA 0.8 0.6 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE SO 14 =8 8° C/ W 0.4 0.2 0.8 0.7 833mW 0.6 θ 0.5 JA = 0.4 0.3 SO 14 12 0° C/ W 0.2 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 6 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7452.2 September 21, 2005 ISL59442 Pin Descriptions PIN NUMBER PIN NAME EQUIVALENT CIRCUIT 1 IN0 Circuit 1 2, 6, 9 NIC 3 IN1 Circuit 1 Input for channel 1 4 GND Circuit 4 Ground pin 5 IN2 Circuit 1 Input for channel 2 7 IN3 Circuit 1 Input for channel 3 8 V- Circuit 4 Negative power supply 10 OUT Circuit 3 Output 11 HIZ Circuit 2 Output disable (active high); there are internal pull-down resistors, so the device will be active with no connection; "HI" puts the output in high impedance state. 12 S1 Circuit 2 Channel selection pin MSB (binary logic code) 13 S0 Circuit 2 Channel selection pin LSB (binary logic code) 14 V+ Circuit 4 Positive power supply DESCRIPTION Input for channel 0 Not Internally Connected; it is recommended this pin be tied to ground to minimize crosstalk. V+ IN V+ LOGIC PIN 33K V- + 1.2V - GND. V- CIRCUIT 1. CIRCUIT 2. V+ OUT V- CIRCUIT 3. 7 21K V+ GND CAPACITIVELY COUPLED ESD CLAMP VCIRCUIT 4. FN7452.2 September 21, 2005 ISL59442 AC Test Circuits ISL59442 ISL59442 VIN CL 2pF 50Ω or 75Ω RL 500Ω TEST EQUIPMENT RS VIN 50Ω or 75Ω CL 2pF 475Ω 50Ω or 75Ω 50Ω or 75Ω FIGURE 21B. TEST CIRCUIT FOR MEASURING WITH A 50Ω OR 75Ω FIGURE 21A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD INPUT TERMINATED EQUIPMENT ISL59442 TEST EQUIPMENT RS VIN 50Ω or 75Ω CL 2pF 50Ω or 75Ω 50Ω or 75Ω FIGURE 21C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500Ω WILL BE DEGRADED NOTE: Figure 21A illustrates the optimum output load for testing AC performance. Figure 21B illustrates the optimum output load when connecting to input terminated equipment. Figure 21C illustrates back loaded test circuit for video cable. Application Circuits *CL = CT + COUT VIN VOUT + COUT CT 1.6pF 50Ω 0pF RL = 500Ω *CL: TOTAL LOAD CAPACITANCE CT: TRACE CAPACITANCE COUT: OUTPUT CAPACITANCE FIGURE 22A. SMALL SIGNAL 200mVP-P APPLICATION CIRCUIT RS 25Ω VIN + 50Ω 1.6pF CT VOUT COUT 22pF RL = 500Ω CL = CT + COUT FIGURE 22B. LARGE SIGNAL 1VP-P APPLICATION CIRCUIT 8 FN7452.2 September 21, 2005 ISL59442 Application Information Power-Up Considerations The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dV/dT- triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/µs. Damaging currents can flow for power supply rates-of-rise in excess of 1V/µs, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. General The ISL59442 is a 4:1 mux that is ideal as a matrix element in high performance switchers and routers. The ISL59442 is optimized to drive a 2pF in parallel with a 500Ω load. The capacitance can be split between the PCB capacitance an and external load capacitance. Their low input capacitance and high input resistance provide excellent 50Ω or 75Ω terminations. Capacitance at the Output The output amplifier is optimized for capacitance to ground (CL) directly on the output pin. Increased capacitance causes higher peaking with an increase in bandwidth. The optimum range for most applications is ~1.0pF to ~6pF. The optimum value can be achieved through a combination of PC board trace capacitance (CT) and an external capacitor (COUT). A good method to maintain control over the output pin capacitance is to minimize the trace length (CT) to the next component, and include a discrete surface mount capacitor (COUT) directly at the output pin. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 23) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. For large signal applications where overshoot is important the circuit in Figure 22B should be used. The series resistor (RS) and capacitor (CL) form a low pass network that limits system bandwidth and reduces overshoot. The component values shown result in a typical pulse response shown in Figure 18. If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+. Ground Connections HIZ State For the best isolation and crosstalk rejection, the GND pin and NIC pins must connect to the GND plane. The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended this pin be tied to ground to minimize crosstalk. An internal pull-down resistor connected to the HIZ pin ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 30ns by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance 1.4MΩ. Use this state to control the logic when more than one mux shares a common output. Control Signals In the HIZ state the output is three-stated, and maintains its high Z even in the presence of high slew rates. The supply current during this state is basically the same as the active state. S0, S1, HIZ - These pins are, TTL/CMOS compatible control inputs. The S0, S1 pins select which one of the inputs connect to the output. The HIZ pin is used to three-state the output amplifiers. For control signal rise and fall times less than 10nsec the use of termination resistors close to the part will minimize transients coupled to the output. V+ SUPPLY SCHOTTKY PROTECTION LOGIC Limiting the Output Current No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required. V+ LOGIC CONTROL S0 POWER GND GND SIGNAL IN0 EXTERNAL CIRCUITS V+ V- V+ V+ V+ OUT V- DE-COUPLING CAPS IN1 VV- V- V- SUPPLY FIGURE 23. SCHOTTKY PROTECTION CIRCUIT 9 FN7452.2 September 21, 2005 ISL59442 PC Board Layout The frequency response of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. • The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip lines are used. • Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. • Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. • Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. • When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. • Minimum of 2 power supply de-coupling capacitors are recommended (1000pF, 0.01µF) as close to the devices as possible. Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. • The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk. 10 FN7452.2 September 21, 2005 ISL59442 SO Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at <http://www.intersil.com/design/packages/index.asp> All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN7452.2 September 21, 2005