AD ADR435 Current output, parallel input, 16-/14-bit multiplying dacs with four-quadrant resistor Datasheet

Current Output, Parallel Input, 16-/14-Bit
Multiplying DACs with Four-Quadrant Resistors
AD5546/AD5556
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
R1
16-bit resolution
14-bit resolution
2- or 4-quadrant multiplying DAC
±1 LSB DNL
±1 LSB INL
Operating supply voltage: 2.7 V to 5.5 V
Low noise: 12 nV/√Hz
Low power: IDD = 10 μA
0.5 μs settling time
Built-in RFB facilitates current-to-voltage conversion
Built-in 4-quadrant resistors allow 0 V to –10 V, 0 V to +10 V,
or ±10 V outputs
2 mA full-scale current ±20%, with VREF = 10 V
Automotive operating temperature: –40°C to +125°C
Compact TSSOP-28 package
RCOM
R1
REF ROFS
R2
AD5546/
AD5556
VDD
WR
RFB
DAC
RFB
IOUT
16/14
CONTROL
LOGIC
LDAC
ROFS
DAC
REGISTER
DB0 TO DB15
GND
MSB
03810-001
POR
RS
Figure 1. AD5546/AD5556 Simplified Block Diagram
GENERAL DESCRIPTION
The AD5546/AD5556 are precision 16-/14-bit, multiplying, low
power, current output, parallel input digital-to-analog converters
(DACs). They operate from a single 2.7 V to 5.5 V supply with
±10 V multiplying references for four-quadrant outputs. Builtin four-quadrant resistors facilitate the resistance matching and
temperature tracking that minimize the number of components
needed for multiquadrant applications. The feedback resistor
(RFB) simplifies the I-V conversion with an external buffer. The
AD5546/AD5556 are packaged in compact TSSOP-28 packages
with operating temperatures from –40°C to +125°C.
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
Digital waveform generation
The EVAL-AD5546SDZ is available for evaluating DAC performance. For more information, see the UG-309 evaluation board
user guide.
+
U2A
OP2177
–
+10V
C7
–10V
R1A
VREFA
RCOMA
ROFSA
RFBA
+15V
C6
R1
ROFS
VDD
C1
1µF
C2
0.1µF
U1
AD5546/AD5556
IOUT
16-/14-BIT
DATA
–
C5
0.1µF
V+
U2B
OP2177
GND
16-/14-BIT
DATA
C4
1µF
RFB
+
VOUT
V–
C8
1µF
WR LDAC RS
MSB
WR
LDAC
RS
MSB
C9
0.1µF
–15V
03810-024
+5V
R2
Figure 2. 16-/14-Bit, Four-Quadrant Multiplying DAC with a Minimum of External Components
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004-2011 Analog Devices, Inc. All rights reserved.
AD5546/AD5556
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital Section ............................................................................ 11
Applications ....................................................................................... 1
ESD Protection Circuits ............................................................ 11
Functional Block Diagram .............................................................. 1
Amplifier Selection .................................................................... 11
General Description ......................................................................... 1
Reference Selection .................................................................... 11
Revision History ............................................................................... 2
Applications Information .............................................................. 12
Specifications..................................................................................... 3
Unipolar Mode ........................................................................... 12
Electrical Characteristics ............................................................. 3
Bipolar Mode .............................................................................. 13
Timing Diagram ........................................................................... 4
AC Reference Signal Attenuator ............................................... 14
Absolute Maximum Ratings ............................................................ 5
System Calibration ..................................................................... 14
ESD Caution .................................................................................. 5
Reference Selection .................................................................... 15
Pin Configurations and Function Descriptions ........................... 6
Amplifier Selection .................................................................... 15
Typical Performance Characteristics ............................................. 8
Outline Dimensions ....................................................................... 17
Circuit Operation ........................................................................... 10
Ordering Guide .......................................................................... 17
Digital-to-Analog (DAC) Converter Section ......................... 10
REVISION HISTORY
11/11—Rev. C to Rev. D
Changes to General Description Section ...................................... 1
Changes to Ordering Guide .......................................................... 18
1/11—Rev. B to Rev. C
Changes to Figure 2 .......................................................................... 1
Changes to Figure 21 ...................................................................... 13
4/10—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 4
Moved Timing Diagram Section and Figure 5 to
Specifications Section....................................................................... 4
Moved Table 5 Through Table 7 to Digital Section Section ....... 7
Replaced Figure 15 and Figure 16 .................................................. 9
Deleted Figure 17 and Figure 18..................................................... 9
Added Reference Selection Section, Amplifier Selection Section,
and Table 11 Through Table 13 .................................................... 15
9/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Static Performance, Relative Accuracy,
Grade: AD5546C Parameter, Table 1 ............................................. 3
Changes to Ordering Guide .......................................................... 16
1/04—Revision 0: Initial Version
Rev. D | Page 2 of 20
Data Sheet
AD5546/AD5556
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, IOUT = virtual GND, GND = 0 V, VREF = –10 V to 10 V, TA = full operating temperature range, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE 1
Resolution
Symbol
Conditions
N
AD5546, 1 LSB = VREF/216 = 153 µV at
VREF = 10 V
AD5556, 1 LSB = VREF/214 = 610 µV at
VREF = 10 V
Grade: AD5556C
Grade: AD5546B
Grade: AD5546C
Monotonic
Data = zero scale, TA = 25°C
Data = zero scale, TA = TA maximum
Data = full scale
Data = full scale
Data = full scale
Relative Accuracy
INL
Differential Nonlinearity
Output Leakage Current
DNL
IOUT
Full-Scale Gain Error
Bipolar Mode Gain Error
Bipolar Mode Zero-Scale
Error
Full-Scale Tempco2
REFERENCE INPUT
VREF Range
REF Input Resistance
R1 and R2 Resistance
R1-to-R2 Mismatch
Feedback and Offset
Resistance
Input Capacitance2
ANALOG OUTPUT
Output Current
Output Capacitance2
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
GFSE
GE
GZSE
Logic Input High Voltage
Min
–18
4
4
8
CREF
IOUT
COUT
Data = full scale
Code dependent
VIL
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
IIL
CIL
Data to WR Hold Time
tDH
WR Pulse Width
tWR
LDAC Pulse Width
tLDAC
tDS
Unit
Bits
14
Bits
±1
±2
±1
±1
10
20
±4
±4
±2.5
1
VREF
REF
R1 and R2
∆(R1 to R2)
RFB, ROFS
Input Leakage Current
Input Capacitance2
INTERFACE TIMING2, 3
Data to WR Setup Time
Max
16
±1
±1
±1
TCVFS
VIH
Typ
5
5
±0.5
10
LSB
LSB
LSB
LSB
nA
nA
mV
mV
mV
ppm/°C
+18
6
6
±1.5
12
V
kΩ
kΩ
Ω
kΩ
5
pF
2
200
mA
pF
0.8
0.4
2.4
2.1
10
10
V
V
V
V
µA
pF
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
20
35
0
0
20
ns
ns
ns
ns
ns
VDD = 3 V
VDD = 5 V
VDD = 3 V
35
20
35
ns
ns
ns
Rev. D | Page 3 of 20
AD5546/AD5556
Parameter
RS Pulse Width
WR to LDAC Delay Time
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
AC CHARACTERISTICS4
Output Voltage Settling
Time
Reference Multiplying BW
DAC Glitch Impulse
Multiplying Feedthrough
Error
Digital Feedthrough
Total Harmonic Distortion
Output Noise Density
Data Sheet
Symbol
tRS
tLWD
VDD RANGE
IDD
PDISS
PSS
tS
Conditions
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Min
20
35
0
0
Typ
2.7
Logic inputs = 0 V
Logic inputs = 0 V
∆VDD = ±5%
Max
Unit
ns
ns
ns
ns
5.5
10
0.055
0.003
V
μA
mW
%/%
0.5
μs
BW
Q
VOUT/VREF
To ±0.1% of full scale, data cycles from zero
scale to full scale to zero scale
VREF = 100 mV rms, data = full scale, C6 =5.6 pF5
VREF = 0 V, midscale minus 1 to midscale
VREF = 100 mV rms, f = 10 kHz
6.8
−3
79
MHz
nV-s
dB
QD
THD
eN
WR = 1, LDAC toggles at 1 MHz
VREF = 5 V p-p, data = full-scale, f = 1 kHz
f = 1 kHz, BW = 1 Hz
7
–103
12
nV-s
dB
nV/rt Hz
1
All static performance tests (except IOUT) are performed in a closed-loop system, using an external precision OP97 I-V converter amplifier. The AD554x RFB terminal is
tied to the amplifier output. The op amp +IN is grounded, and the DAC IOUT is tied to the op amp –IN. Typical values represent average readings measured at 25°C.
2
These parameters are guaranteed by design and are not subject to production testing.
3
All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
4
All ac characteristic tests are performed in a closed-loop system using an AD8038 I-V converter amplifier except for THD where an AD8065 was used.
5
C6 is the C6 capacitor shown in Figure 20.
TIMING DIAGRAM
tWR
WR
DATA
tDS
tDH
tLWD
LDAC
tRS
03810-005
tLDAC
RS
Figure 3. AD5546/AD5556 Timing Diagram
Rev. D | Page 4 of 20
Data Sheet
AD5546/AD5556
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VDD to GND
RFB, ROFS, R1, RCOM, and REF to GND
Logic Inputs to GND
V (IOUT) to GND
Input Current to Any Pin Except Supplies
Thermal Resistance (θJA)
Maximum Junction Temperature (TJ MAX)
Operating Temperature Range
Storage Temperature Range
Lead Temperature:
Vapor Phase, 60 s
Infrared, 15 s
Package Power Dissipation
Rating
–0.3 V, +8 V
–18 V, 18 V
–0.3 V, +8 V
–0.3 V, VDD + 0.3 V
±50 mA
128°C
150°C
–40°C to +125°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
215°C
220°C
(TJ MAX – TA)/θJA
Rev. D | Page 5 of 20
AD5546/AD5556
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D7 1
28 VDD
D5 1
28
VDD
D6 2
27 D8
D4 2
27
D6
D5 3
26 D9
D3 3
26
D7
D4 4
25 D10
D2 4
25
D8
D2 6
AD5546
24 D11
D1 5
23 D12
D0 6
22 D13
TOP VIEW
D0 8 (Not to Scale) 21 D14
D1 7
RFB 10
R1 11
RCOM 12
20 D15
19 GND
18 RS
17 MSB
REF 13
16 WR
IOUT 14
15 LDAC
24
D9
23
D10
22 D11
NC 7
TOP VIEW
NC 8 (Not to Scale) 21 D12
03810-003
ROFS 9
AD5556
ROFS 9
20
D13
RFB 10
19
GND
R1 11
18
RS
RCOM 12
17
MSB
REF 13
16
WR
IOUT 14
15
LDAC
NC = NO CONNECT
Figure 4. AD5546 Pin Configuration
03810-004
D3 5
Figure 5. AD5556 Pin Configuration
Table 3. AD5546 Pin Function Descriptions
Pin No.
1 to 8
9
Mnemonic
D7 to D0
ROFS
10
11
12
RFB
R1
RCOM
13
REF
14
15
16
IOUT
LDAC
WR
17
MSB
18
RS
19
20 to 21
22 to 27
28
GND
D15 to D14
D13 to D8
VDD
Description
Digital Input Data Bits[D7: D0]. The signal level must be ≤ VDD + 0.3 V.
Bipolar Offset Resistor. Accepts up to ±18 V. In two-quadrant mode, ties to RFB. In four-quadrant mode, ties to R1
and the external reference.
Internal Matching Feedback Resistor. Connects to the output of an external op amp for I-V conversion.
Four-Quadrant Resistor R1. In two-quadrant mode, shorts to the REF pin. In four-quadrant mode, ties to ROFS.
Center Tap Point of Two Four-Quadrant Resistors, R1 and R2. In four-quadrant mode, ties to the inverting node of
the reference amplifier. In two-quadrant mode, shorts to the REF pin.
DAC Reference Input in Two-Quadrant Mode and R2 Terminal in Four-Quadrant Mode. In two-quadrant mode, this
pin is the reference input with constant input resistance vs. code. In four-quadrant mode, this pin is driven by the
external reference amplifier.
DAC Current Output. Connects to the inverting node of an external op amp for I-V conversion.
Digital Input Load DAC Control. Signal level must be ≤ VDD + 0.3 V.
Write Control Digital Input in Active Low. Transfers shift-register data to the DAC register on the rising edge. The
signal level must be ≤ VDD + 0.3 V.
Power-On Reset State. MSB = 0 resets at zero scale; MSB = 1 resets at midscale. The signal level must be
≤ VDD + 0.3 V.
Reset in Active Low. Resets to zero scale if MSB = 0, and resets to midscale if MSB = 1. The signal level must be
≤ VDD + 0.3 V.
Analog and Digital Grounds.
Digital Input Data Bits[D15:D14]. The signal level must be ≤ VDD + 0.3 V.
Digital Input Data Bits[D13:D8]. The signal level must be ≤ VDD + 0.3 V.
Positive Power Supply Input. Specified range of operation: 2.7 V to 5.5 V.
Table 4. AD5556 Pin Function Descriptions
Pin No.
1 to 6
7 to 8
9
Mnemonic
D5 to D0
NC
ROFS
10
11
12
RFB
R1
RCOM
Description
Digital Input Data Bits[D5:D0]. The signal level must be ≤ VDD+0.3 V.
No Connection. The user should not connect anything other than dummy pads on these terminals.
Bipolar Offset Resistor. Accepts up to ±18 V. In two-quadrant mode, ties to RFB. In four-quadrant mode, ties to R1
and the external reference.
Internal Matching Feedback Resistor. Connects to the output of an external op amp for I-V conversion.
Four-Quadrant Resistor R1. In two-quadrant mode, shorts to the REF pin. In four-quadrant mode, ties to ROFS.
Center Tap Point of Two Four-Quadrant Resistors, R1 and R2. In four-quadrant mode, ties to the inverting node of
the reference amplifier. In two-quadrant mode, shorts to the REF pin.
Rev. D | Page 6 of 20
Data Sheet
Pin No.
13
Mnemonic
REF
14
15
16
IOUT
LDAC
WR
17
MSB
18
RS
19
20 to 27
28
GND
D13 to D6
VDD
AD5546/AD5556
Description
DAC Reference Input in Two-Quadrant Mode and R2 Terminal in Four-Quadrant Mode. In two-quadrant mode, this
pin is the reference input with constant input resistance vs. code. In four-quadrant mode, this pin is driven by the
external reference amplifier.
DAC Current Output. Connects to the inverting node of an external op amp for I-V conversion.
Digital Input Load DAC Control. The signal level must be ≤ VDD + 0.3 V.
Write Control Digital Input in Active Low. Transfers shift-register data to the DAC register on the rising edge. The
signal level must be ≤ VDD + 0.3 V.
Power On Reset State. MSB = 0 resets at zero scale; MSB = 1 resets at midscale. The signal level must be
≤ VDD + 0.3 V.
Reset in Active Low. Resets to zero scale if MSB = 0 and resets to midscale if MSB = 1. The signal level must be
≤ VDD + 0.3 V.
Analog and Digital Grounds.
Digital Input Data Bits[D13:D6]. The signal level must be ≤ VDD + 0.3 V.
Positive Power Supply Input. Specified range of operation: 2.7 V to 5.5 V.
Rev. D | Page 7 of 20
AD5546/AD5556
Data Sheet
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
0
8192
–0.8
–1.0
16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE (Decimal)
0
8192
10,240 12,288 14,336 16,384
1.5
VREF = 2.5V
TA = 25°C
0.8
1.0
LINEARITY ERROR (LSB)
0.6
0.4
DNL (LSB)
6144
Figure 9. AD5556 Differential Nonlinearity Error
1.0
0.2
0
–0.2
–0.4
–0.6
0.5
INL
0
DNL
–0.5
–1.0
GE
03810-007
–0.8
0
8192
–1.5
16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE (Decimal)
2
4
Figure 7. AD5546 Differential Nonlinearity Error
6
8
SUPPLY VOLTAGE VDD (V)
10
Figure 10. Linearity Error vs. VDD
1.0
5
VDD = 5V
TA = 25°C
0.8
0.4
0.2
0
–0.2
–0.4
03810-008
–0.6
–0.8
–1.0
0
2048
4096
4
3
2
1
0
6144
8192 10,240 12,288 14,336 16,384
CODE (Decimal)
03810-011
SUPPLY CURRENT IDD (LSB)
0.6
INL (LSB)
4096
CODE (Decimal)
Figure 6. AD5546 Integral Nonlinearity Error
–1.0
0248
03810-010
–1.0
03810-009
DNL (LSB)
1.0
03810-006
INL (LSB)
TYPICAL PERFORMANCE CHARACTERISTICS
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOGIC INPUT VOLTAGE VIH (V)
Figure 11. Supply Current vs. Logic Input Voltage
Figure 8. AD5556 Integral Nonlinearity Error
Rev. D | Page 8 of 20
5.0
Data Sheet
AD5546/AD5556
3.0
–3.80
–3.85
–3.90
2.0
–3.95
0x5555
VOUT (V)
SUPPLY CURRENT (mA)
2.5
1.5
0x8000
–4.00
–4.05
1.0
0xFFFF
0x0000
–4.10
0.5
100k
1M
10M
–4.20
–200
100M
03810-115
03810-012
0
10k
–4.15
–100
CLOCK FREQUENCY (Hz)
0
100
200
300
400
TIME (ns)
Figure 12. AD5546 Supply Current vs. Clock Frequency
Figure 15. AD5546 Midscale Transition
2
90
VDD = 5V ± 10%
VREF = 10V
80
0
–2
70
–4
GAIN (dB)
50
40
30
–8
–10
–12
20
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
–16
–18
10k
2
VOUT
M 200ns
1M
10M
100M
Figure 16. AD5546 Unipolar Reference Multiplying Bandwidth
LDAC
CH1 5.00V CH2 2.00V
100k
FREQUENCY (Hz)
Figure 13. Power Supply Rejection Ratio vs. Frequency
1
03810-116
03810-013
–14
10
0
–6
A CH1 2.70V
B CH1 –6.20V
400.00ns
03810-014
PSRR (–dB)
60
Figure 14. Settling Time from Full Scale to Zero Scale
Rev. D | Page 9 of 20
AD5546/AD5556
Data Sheet
CIRCUIT OPERATION
variation of the AD5546/AD5556 output impedance. The
feedback resistance in parallel with the DAC ladder resistance
dominates output voltage noise. To maintain good analog
performance, it is recommended to bypass the power supply
with a 0.01 μF to 0.1 μF ceramic or chip capacitor in parallel
with a 1 μF tantalum capacitor. Also, to minimize gain error,
PCB metal traces between VREF and RFB should match.
DIGITAL-TO-ANALOG (DAC) CONVERTER SECTION
The AD5546/AD5556 are 16-/14-bit multiplying, current output, and parallel input DACs. The devices operate from a single
2.7 V to 5.5 V supply and provide both unipolar 0 V to –VREF, or
0 V to +VREF, and bipolar ±VREF output ranges from a –18 V to
+18 V reference. In addition to the precision conversion RFB
commonly found in current output DACs, there are three additional precision resistors for four-quadrant bipolar applications.
Every code change of the DAC corresponds to a step function;
gain peaking at each output step may occur if the op amp has
limited GBP and excessive parasitic capacitance present at the
op amp inverting node. A compensation capacitor, therefore,
may be needed between the I-V op amp inverting and output
nodes to smooth the step transition. Such a compensation
capacitor should be found empirically, but a 20 pF capacitor is
generally adequate for the compensation.
The AD5546/AD5556 consist of two groups of precision R-2R
ladders, which make up the 12/10 LSBs, respectively. Furthermore, the four MSBs are decoded into 15 segments of resistor
value 2R. Figure 17 shows the architecture of the 16-bit AD5546.
Each of the 16 segments in the R-2R ladder carries an equally
weighted current of one-sixteenth of full scale. The feedback
resistor, RFB, and four-quadrant resistor, ROFS, have values of 10
kΩ. Each four-quadrant resistor, R1 and R2, equals 5 kΩ. In
four-quadrant operation, R1, R2, and an external op amp work
together to invert the reference voltage and apply it to the REF
input. With ROFS and RFB connected as shown in Figure 2, the
output can swing from –VREF to +VREF.
The VDD power is used primarily by the internal logic and to
drive the DAC switches. Note that the output precision
degrades if the operating voltage falls below the specified
voltage. The user should also avoid using switching regulators
because device power supply rejection degrades at higher
frequencies.
The reference voltage inputs exhibit a constant input resistance
of 5 kΩ ±20%. The DAC output, IOUT, impedance is code dependent. External amplifier choice should take into account the
REF
2R
80kΩ
R2
5kΩ
2R
80kΩ
2R
80kΩ
R1
5kΩ
4 MSB
15 SEGMENTS
R1
R
40kΩ
R
40kΩ
R
40kΩ
R
40kΩ
R
40kΩ
R
40kΩ
R
40kΩ
R
40kΩ
2R
80kΩ
2R
80kΩ
2R
80kΩ
2R
80kΩ
2R
80kΩ
2R
80kΩ
2R
80kΩ
2R
80kΩ
2R
80kΩ
8-BIT R–2R
RA
R
R
R
R
RB
2R
80kΩ
2R
80kΩ
2R
80kΩ
2R
80kΩ
ROFS
RFB
2R
80kΩ
10kΩ
10kΩ
4-BIT R–2R
IOUT
GND
16
8
4
ADDRESS DECODER
LDAC
WR
LDAC
WR
D15
DAC REGISTER
RS
INPUT REGISTER
RS
D14
RS
D0
Figure 17. 16-Bit AD5546 Equivalent R-2R DAC Circuit with Digital Section
Rev. D | Page 10 of 20
03810-019
RCOM
2R
80kΩ
Data Sheet
AD5546/AD5556
DIGITAL SECTION
The AD5546/AD5556 have 16-/14-bit parallel inputs. The devices are double buffered with 16-/14-bit registers. The double-buffered
feature allows the update of several AD5546/AD5556 simultaneously. For the AD5546, the input register is loaded directly from a 16-bit
controller bus when the WR pin is brought low. The DAC register is updated with data from the input register when LDAC is brought
high. Updating the DAC register updates the DAC output with the new data (see Figure 17). To make both registers transparent, tie WR
low and LDAC high. The asynchronous RS pin resets the part to zero scale if the MSB pin = 0 and to midscale if the MSB pin = 1.
Table 5. AD5546 Parallel Input Data Format
MSB
B15
D15
Bit Position
Data Word
B14
D14
B13
D13
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
LSB
B0
D0
Table 6. AD5556 Parallel Input Data Format
MSB
B13
D13
Bit Position
Data Word
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
LSB
B0
D0
Table 7. Control Inputs
RS
0
1
1
1
1
WR
X1
0
1
0
LDAC
Register Operation
X
0
1
1
1
1
0
Reset output to 0, with MSB pin = 0 and to midscale with MSB pin = 1.
Load input register with data bits.
Load DAC register with the contents of the input register.
Input and DAC registers are transparent.
When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on
the falling edge of the pulse and then loaded into the DAC register on the rising edge of the pulse.
No register operation.
1
1
X = don’t care.
ESD PROTECTION CIRCUITS
are good candidates for the I-V conversion.
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and VDD, as shown in Figure 18. As
a result, the voltage level of the logic input should not be greater
than the supply voltage.
REFERENCE SELECTION
VDD
5kΩ
DGND
The voltage reference temperature coefficient (TC) and longterm drift are primary considerations. For example, a 5 V reference with a TC of 5 ppm/oC means that the output changes by
25 µV per degree Celsius. As a result, the reference that operates
at 55oC contributes an additional 750 µV full-scale error.
03810-020
DIGITAL
INPUTS
The initial accuracy and the rated output of the voltage reference determine the full span adjustment. The initial accuracy is
usually a secondary concern in precision because it can be
trimmed. Figure 23 shows an example of a trimming circuit.
The zero scale error can also be minimized by standard op amp
nulling techniques.
Figure 18. Equivalent ESD Protection Circuits
AMPLIFIER SELECTION
In addition to offset voltage, the bias current is important in op
amp selection for precision current output DACs. An input bias
current of 30 nA in the op amp contributes to 1 LSB in the
AD5546’s full-scale error. The OP1177 and AD8628 op amps
Similarly, the same 5 V reference with a ±50 ppm long-term
drift means that the output may change by ±250 µV over time.
Therefore, it is practical to calibrate a system periodically to
maintain its optimum precision.
Rev. D | Page 11 of 20
AD5546/AD5556
Data Sheet
APPLICATIONS INFORMATION
UNIPOLAR MODE
Two-Quadrant Multiplying Mode, VOUT = 0 V to +VREF
Two-Quadrant Multiplying Mode, VOUT = 0 V to –VREF
The AD5546/AD5556 DAC architecture uses a current-steering
R-2R ladder design that requires an external reference and op
amp to convert the unipolar mode of output voltage to
The AD5546/AD5556 are designed to operate with either
positive or negative reference voltages. As a result, positive
output can be achieved with an additional op amp, (see
Figure 20), and the output becomes
AD5546
AD5546
VOUT = –VREF × D/65,536
VOUT = +VREF × D/65,536
(1)
(3)
AD5556
AD5556
VOUT = –VREF × D/16,384
VOUT = +VREF × D/16,384
(2)
(4)
where D is the decimal equivalent of the input code.
Table 9 shows the positive output vs. code for the AD5546.
The output voltage polarity is opposite to the VREF polarity in
this case (see Figure 19). Table 8 shows the negative output vs.
code for the AD5546.
Table 9. AD5546 Unipolar Mode Positive Output vs. Code
D in Binary
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
Table 8. AD5546 Unipolar Mode Negative Output vs. Code
D in Binary
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
VOUT (V)
–VREF(65,535/65,536)
–VREF/2
–VREF(1/65,536)
0
VOUT (V)
+VREF(65,535/65,536)
+VREF/2
+VREF(1/65,536)
0
+5V
2
C2
0.1µF
VIN
U3
ADR03
TRIM
5
VOUT
GND
4
R1
RCOM
R1
REF
R2
ROFS
ROFS
RFB
C6
2.2pF
RFB
VDD
C3
0.1µF
IOUT
16-/14-BIT
DATA
U1
AD5546/AD5556
V+
U2
AD8628
GND
16-/14-BIT
DATA
WR LDAC RS
–
+
V–
VOUT
–2.5V TO 0V
C4
0.1µF
MSB
WR
LDAC
RS
MSB
–5V
Figure 19. Unipolar Two-Quadrant Multiplying Mode, VOUT = 0 to –VREF
Rev. D | Page 12 of 20
C5
1µF
03810-021
C1
1µF
Data Sheet
AD5546/AD5556
+
U2A
OP2177
–
+10V
C7
–10V
RCOMA
R1A
VREFA
ROFSA
RFBA
+15V
C4
1µF
C6
+5V
ROFS
R2
R1
RFB
VDD
C2
0.1µF
IOUT
16-/14-BIT
DATA
U1
–
AD5546/AD5556
C5
0.1µF
V+
U2B
VOUT
OP2177
GND
+
16-/14-BIT
DATA
V–
C8
1µF
WR LDAC RS
MSB
WR
LDAC
RS
MSB
C9
0.1µF
03810-024
C1
1µF
–15V
Figure 20. Unipolar Two-Quadrant Multiplying Mode, VOUT = 0 to +VREF
5V
2
+
VIN
U2A
OP2177
U3
ADR03
TRIM
VOUT
GND
4
–
5
C1
6
R1
REF
RCOM
R1
5V
–VREF
+VREF
ROFS
ROFS
R2
RFB
RFB
C2
VDD
IOUT
16-/14-BIT
DATA
U1
AD5546/AD5556
U2B
OP2177
16-/14-BIT
DATA
GND
WR LDAC RS
–
+
VOUT
–VREF TO +VREF
MSB
03810-002
WR
LDAC
RS
MSB
Figure 21. Four-Quadrant Multiplying Mode, VOUT = –VREF to +VREF
BIPOLAR MODE
Four-Quadrant Multiplying Mode, VOUT = –VREF to +VREF
The AD5546/AD5556 contain on-chip all the four-quadrant
resistors necessary for the precision bipolar multiplying
operation. Such a feature minimizes the number of exponent
components to only a voltage reference, dual op amp, and
compensation capacitor (see Figure 21). For example, with a
10 V reference, the circuit yields a precision, bipolar –10 V to
+10 V output.
AD5546
VOUT = (D/32768 − 1) × VREF
(5)
AD5556
VOUT = (D/16384 − 1) × VREF
Table 10 shows some of the results for the 16-bit AD5546.
Rev. D | Page 13 of 20
(6)
AD5546/AD5556
Data Sheet
ac reference signals for signal attenuation, channel equalization,
and waveform generation applications. The maximum signal
range can be up to ±18 V (see Figure 22).
Table 10. AD5546 Output vs. Code
D in Binary
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
VOUT
+VREF(32,767/32,768)
+VREF(1/32,768)
0
–VREF(1/32,768)
–VREF
SYSTEM CALIBRATION
The initial accuracy of the system can be adjusted by trimming
the voltage reference ADR0x with a digital potentiometer (see
Figure 23). The AD5170 provides an OTP (one time programmable), 8-bit adjustment that is ideal and reliable for such calibration. The Analog Devices, Inc., OTP digital potentiometer
comes with programmable software that simplifies the factory
calibration process.
AC REFERENCE SIGNAL ATTENUATOR
Besides handling digital waveforms decoded from parallel input
data, the AD5546/AD5556 handle equally well low frequency
+
U2A
OP2177
–
+10V
C7
–10V
R1A
RCOMA
ROFSA
VREFA
RFBA
+15V
C4
1F
C6
R1
+5V
R2
ROFS
RFB
VDD
C2
0.1F
IOUT
16/14-BIT
U1
–
AD5546/AD5556
C5
0.1F
V+
U2B
OP2177
GND
+
16/14 DATA
VOUT
V–
C8
1F
WR LDAC RS
MSB
WR
LDAC
RS
MSB
C9
0.1F
03810-0-024
C1
1F
–15V
Figure 22. Signal Attenuator with AC Reference
+5V
2
C2
0.1µF
+
VIN
U4
U3
ADR03
TRIM
VOUT
5
R3
470kΩ
6
GND
4
AD5170
V+
U2A
AD8628
–
10kΩ
V–
B
R7
1kΩ
–5V
+2.5V
R1A
C8
0.1µF
C9
1µF
–2.5V
C7
RCOMA
VREFA
ROFSA
RFBA
+5V
C6
R1
R2
ROFS
VDD
C3
0.1µF
U1
AD5546/AD5556
IOUT
16-/14-BIT
DATA
16-/14-BIT
DATA
–
C5
0.1µF
V+
U2B
AD8628
GND
WR LDAC RS
C4
1µF
RFB
+
V–
VOUT
0V TO +2.5V
MSB
WR
LDAC
RS
MSB
03810-025
C1
1µF
Figure 23. Full Span Calibration
Rev. D | Page 14 of 20
Data Sheet
AD5546/AD5556
REFERENCE SELECTION
When selecting a reference for use with the AD55xx series
of current output DACs, pay attention to the output voltage
temperature coefficient specification of the reference. Choosing
a precision reference with a low output temperature coefficient
minimizes error sources. Table 11 lists some of the references
available from Analog Devices that are suitable for use with this
range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed on the desired change in output
between the two codes and gives rise to a differential linearity
error, which, if large enough, can cause the DAC to be
nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output because of the bias current flowing in the
feedback resistor, RFB.
Common-mode rejection of the op amp is important in voltageswitching circuits because it produces a code-dependent error
at the voltage output of the circuit.
Provided that the DAC switches are driven from true wideband
low impedance sources, they settle quickly. Consequently, the
slew rate and settling time of a voltage-switching DAC circuit is
determined largely by the output op amp. To obtain minimum
settling time in this configuration, minimize capacitance at the
VREF node (the voltage output node in this application) of the
DAC. This is done by using low input capacitance buffer
amplifiers and careful board design.
Analog Devices offers a wide range of amplifiers for both precision
dc and ac applications, as listed in Table 12 and Table 13.
Table 11. Suitable Analog Devices Precision References
Part No.
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR420
ADR421
ADR423
ADR425
ADR431
ADR435
ADR391
ADR395
Output Voltage (V)
10
10
5.0
5.0
2.5
2.5
3.0
3.0
2.048
2.50
3.00
5.00
2.500
5.000
2.5
5.0
Initial Tolerance (%)
0.05
0.05
0.06
0.06
0.1
0.1
0.1
0.1
0.05
0.04
0.04
0.04
0.04
0.04
0.16
0.10
Maximum Temperature
Drift (ppm/°C)
3
9
3
9
3
9
3
9
3
3
3
3
3
3
9
9
Rev. D | Page 15 of 20
ISS (mA)
1
1
1
1
1
1
1
1
0.5
0.5
0.5
0.5
0.8
0.8
0.12
0.12
Output Noise (µV p-p)
20
20
10
10
6
6
10
10
1.75
1.75
2
3.4
3.5
8
5
8
Package(s)
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
TSOT-5
TSOT-5
AD5546/AD5556
Data Sheet
Table 12. Suitable Analog Devices Precision Op Amps
Part No.
OP97
OP1177
AD8675
AD8671
ADA4004-1
AD8603
AD8607
AD8605
AD8615
AD8616
Supply Voltage (V)
±2 to ±20
±2.5 to ±15
±5 to ±18
±5 to ±15
±5 to ±15
1.8 to 5
1.8 to 5
2.7 to 5
2.7 to 5
2.7 to 5
VOS Maximum
(µV)
25
60
75
75
125
50
50
65
65
65
IB Maximum
(nA)
0.1
2
2
12
90
0.001
0.001
0.001
0.001
0.001
0.1 Hz to 10 Hz
Noise (µV p-p)
0.5
0.4
0.1
0.077
0.1
2.3
2.3
2.3
2.4
2.4
Supply Current (µA)
600
500
2300
3000
2000
40
40
1000
2000
2000
Package(s)
SOIC-8 , PDIP-8
MSOP-8, SOIC-8
MSOP-8, SOIC-8
MSOP-8, SOIC-8
SOIC-8, SOT-23-5
TSOT-5
MSOP-8, SOIC-8
WLCSP-5, SOT-23-5
TSOT-23-5
MSOP-8, SOIC-8
Table 13. Suitable Analog Devices High Speed Op Amps
Part No.
AD8065
AD8066
AD8021
AD8038
ADA4899-1
AD8057
AD8058
AD8061
AD8062
AD9631
Supply Voltage (V)
5 to 24
5 to 24
5 to 24
3 to 12
5 to 12
3 to 12
3 to 12
2.7 to 8
2.7 to 8
±3 to ±6
BW @ ACL (MHz)
145
145
490
350
600
325
325
320
320
320
Slew Rate (V/µs)
180
180
120
425
310
1000
850
650
650
1300
Rev. D | Page 16 of 20
VOS (Max) (µV)
1500
1500
1000
3000
35
5000
5000
6000
6000
10,000
IB (Max) (nA)
0.006
0.006
10,500
750
100
500
500
350
350
7000
Package(s)
SOIC-8, SOT-23-5
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, SC70-5
LFCSP-8, SOIC-8
SOT-23-5, SOIC-8
SOIC-8, MSOP-8
SOT-23-5, SOIC-8
SOIC-8, MSOP-8
SOIC-8, PDIP-8
Data Sheet
AD5546/AD5556
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
0.15
0.05
COPLANARITY
0.10
0.30
0.19
1.20 MAX
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 24. 28-Lead Thin Shrink Small Outline Package [TSSOP]
RU-28
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5546BRU
AD5546BRU-REEL7
AD5546BRUZ
AD5546BRUZ-REEL7
AD5546CRUZ
AD5546CRUZ-REEL7
AD5556CRU
AD5556CRU-REEL7
AD5556CRUZ
EVAL-AD5546SDZ
1
RES
(Bit)
16
16
16
16
16
16
14
14
14
DNL
(LSB)
±1
±1
±1
±1
±1
±1
±1
±1
±1
INL
(LSB)
±2
±2
±2
±2
±1
±1
±1
±1
±1
Temperature
Range (°C)
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
Package Description
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
Evaluation Board
Z = RoHS Compliant Part.
Rev. D | Page 17 of 20
Package Option
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
Ordering Quantity
50
1,000
50
1,000
50
1,000
50
1,000
50
AD5546/AD5556
Data Sheet
NOTES
Rev. D | Page 18 of 20
Data Sheet
AD5546/AD5556
NOTES
Rev. D | Page 19 of 20
AD5546/AD5556
Data Sheet
NOTES
©2004-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03810-0-11/11(D)
Rev. D | Page 20 of 20
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