AD ADM691SQ Microprocessor supervisory circuit Datasheet

a
FEATURES
Superior Upgrade for MAX690–MAX695
Specified Over Temperature
Low Power Consumption (5 mW)
Precision Voltage Monitor
Reset Assertion Down to 1 V V CC
Low Switch On-Resistance 1.5 V Normal,
20 V in Backup
High Current Drive (100 mA)
Watchdog Timer—100 ms, 1.6 s, or Adjustable
600 nA Standby Current
Automatic Battery Backup Power Switching
Extremely Fast Gating of Chip Enable Signals (5 ns)
Voltage Monitor for Power Fail
Microprocessor
Supervisory Circuits
ADM690–ADM695
FUNCTIONAL BLOCK DIAGRAMS
VBATT
VOUT
VCC
WATCHDOG
INPUT (WDI)
The ADM690–ADM695 family of supervisory circuits offers
complete single chip solutions for power supply monitoring and
battery control functions in microprocessor systems. These
functions include µP reset, backup battery switchover, watchdog
timer, CMOS RAM write protection, and power failure warning. The complete family provides a variety of configurations to
satisfy most microprocessor system requirements.
The ADM690, ADM692 and ADM694 are available in 8-pin
DIP packages and provide:
1. Power-on reset output during power-up, power-down and
brownout conditions. The RESET output remains operational with VCC as low as 1 V.
2. Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
4. A 1.3 V threshold detector for power fail warning, low battery
detection, or to monitor a power supply other than +5 V.
The ADM691, ADM693 and ADM695 are available in 16-pin
DIP and small outline packages and provide three additional
functions.
1. Write protection of CMOS RAM or EEPROM.
2. Adjustable reset and watchdog timeout periods.
3. Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
WATCHDOG
TRANSITION DETECTOR
(1.6s)
RESET
ADM690
ADM692
ADM694
POWER FAIL
INPUT (PFI)
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
GENERAL DESCRIPTION
RESET
GENERATOR 2
4.65V 1
POWER FAIL
OUTPUT (PFO)
1.3V
1 VOLTAGE
2 RESET
DETECTOR = 4.65V (ADM690, ADM694)
4.40V (ADM692)
PULSE WIDTH = 50ms (ADM690, ADM692)
200ms (ADM694)
BATT ON
VBATT
VOUT
ADM691
ADM693
ADM695
VCC
CE IN
CE OUT
LOW LINE
4.65V 1
RESET
OSC IN
OSC SEL
WATCHDOG
INPUT (WDI)
RESET &
WATCHDOG
TIMEBASE
RESET
GENERATOR
WATCHDOG
TRANSITION DETECTOR
RESET
WATCHDOG
TIMER
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
1.3V
1VOLTAGE
WATCHDOG
OUTPUT (WDO)
DETECTOR = 4.65V (ADM691, ADM695)
4.40V (ADM693)
The ADM690–ADM695 family is fabricated using an advanced
epitaxial CMOS process combining low power consumption
(5 mW), extremely fast Chip Enable gating (5 ns) and high reliability. RESET assertion is guaranteed with VCC as low as 1 V.
In addition, the power switching circuitry is designed for minimal voltage drop thereby permitting increased output current
drive of up to 100 mA without the need for an external pass
transistor.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADM690–ADM695–SPECIFICATIONS
(VCC = Full Operating Range, VBATT = +2.8 V, TA = TMIN to
TMAX unless otherwise noted)
Parameter
Max
Units
4.75
4.5
5.5
5.5
V
V
2.0
2.0
VCC – 0.05 VCC – 0.025
VCC – 0.5
VCC – 0.25
VBATT – 0.05 VBATT – 0.02
1
0.6
4.25
4.0
V
V
V
V
V
mA
µA
–0.1
–1.0
+0.02
+0.02
BATTERY BACKUP SWITCHING
VCC Operating Voltage Range
ADM690, ADM691, ADM694, ADM695
ADM692, ADM693
VBATT Operating Voltage Range
ADM690, ADM691, ADM694, ADM695
ADM692, ADM693
VOUT Output Voltage
VOUT in Battery Backup Mode
Supply Current (Excludes IOUT)
Supply Current in Battery Backup Mode
Battery Standby Current
(+ = Discharge, – = Charge)
Min
Battery Switchover Threshold
VCC – VBATT
Battery Switchover Hysteresis
BATT ON Output Voltage
BATT ON Output Short Circuit Current
Watchdog Timeout Period, External Clock
Minimum WDI Input Pulse Width
RESET Output Voltage @ VCC = +1 V
RESET, LOW LINE Output Voltage
1.95
1
70
50
20
0.3
0.5
RESET AND WATCHDOG TIMER
Reset Voltage Threshold
ADM690, ADM691, ADM694, ADM695
ADM692, ADM693
Reset Threshold Hysteresis
Reset Timeout Delay
ADM690, ADM691, ADM692, ADM693
ADM694, ADM695
Watchdog Timeout Period, Internal Oscillator
Typ
35
1
25
4.5
4.25
4.65
4.4
40
4.73
4.48
V
V
mV
35
140
1.0
70
3840
768
50
50
200
1.6
100
70
280
2.25
140
4097
1025
4
200
0.4
ms
ms
s
ms
Cycles
Cycles
ns
mV
V
V
V
V
µA
mA
3.5
RESET, WDO Output Voltage
Output Short Circuit Source Current
Output Short Circuit Sink Current
WDI Input Threshold
Logic Low
Logic High
WDI Input Current
POWER FAIL DETECTOR
PFI Input Threshold
PFI Input Current
PFO Output Voltage
PFO Short Circuit Source Current
PFO Short Circuit Sink Current
0.4
3.5
1
3
25
25
IOUT = 1 mA
IOUT ≤ 100 mA
IOUT = 250 µA, VCC < VBATT – 0.2 V
IOUT = 100 mA
VCC = 0 V, VBATT = 2.8 V
5.5 V > VCC > VBATT + 0.2 V
TA = +25°C
Power Up
Power Down
ISINK = 3.2 mA
BATT ON = VOUT = 4.5 V Sink Current
BATT ON = 0 V Source Current
OSC SEL = HIGH, VCC = 5 V, TA = +25°C
OSC SEL = HIGH, VCC = 5 V, TA = +25°C
Long Period, VCC = 5 V, TA = +25°C
Short Period, VCC = 5 V, TA = +25°C
Long Period
Short Period
VIL = 0.4, VIH = 3.5 V
ISINK = 10 µA, VCC = 1 V
ISINK = 1.6 mA, VCC = 4.25 V
ISOURCE = 1 µA, VCC = 5 V
ISINK = 1.6 mA, VCC = 5 V
ISOURCE = 1 µA, VCC = 4.25 V
VCC = 5 V1
0.8
3.5
20
–15
50
–50
1.25
–25
1.3
± 0.01
1.35
+25
0.4
3.5
1
3
25
25
CHIP ENABLE GATING
CEIN Threshold
0.8
3.0
CEIN Pull-Up Current
CEOUT Output Voltage
3
0.4
VOUT – 1.5
VOUT – 0.05
CE Propagation Delay
µA
µA
mV
mV
mV
V
mA
µA
Test Conditions/Comments
5
9
–2–
V
V
µA
µA
V
nA
V
V
µA
mA
V
V
µA
V
V
V
ns
WDI = VOUT, TA = +25°C
WDI = 0 V, TA = +25°C
VCC = +5 V
ISINK = 3.2 mA
ISOURCE = 1 µA
PFI = Low, PFO = 0 V
PFI = High, PFO = VOUT
VIL
VIH
ISINK = 3.2 mA
ISOURCE = 3.0 mA
ISOURCE = 1 µA, VCC = 0 V
REV. A
ADM690–ADM695
Parameter
OSCILLATOR
OSC IN Input Current
OSC SEL Input Pull-Up Current
OSC IN Frequency Range
OSC IN Frequency with External Capacitor
Min
Typ
Max
±2
5
0
250
4
Units
Test Conditions/Comments
µA
µA
kHz
kHz
OSC SEL = 0 V
OSC SEL = 0 V, COSC = 47 pF
NOTE
1
WDI is a three level input which is internally biased to 38% of V CC and has an input impedance of approximately 125 kΩ.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VOUT + 0.5 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 400 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 120°C/W
Power Dissipation, Q-8 DIP . . . . . . . . . . . . . . . . . . . . 500 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 125°C/W
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
Power Dissipation, Q-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 100°C/W
Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . . 600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Model
Temperature Range
Package Option
ADM690AN
ADM690AQ
ADM690SQ
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-8
Q-8
Q-8
ADM691AN
ADM691AR
ADM691AQ
ADM691SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-16
R-16
Q-16
Q-16
ADM692AN
ADM692AQ
ADM692SQ
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-8
Q-8
Q-8
ADM693AN
ADM693AR
ADM693AQ
ADM693SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-16
R-16
Q-16
Q-16
ADM694AN
ADM694AQ
ADM694SQ
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-8
Q-8
Q-8
ADM695AN
ADM695AR
ADM695AQ
ADM695SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-16
R-16
Q-16
Q-16
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods of time may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM690–ADM695 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
ADM690–ADM695
PIN FUNCTION DESCRIPTION
Mnemonic
Function
VCC
Power Supply Input: +5 V Nominal.
VBATT
Backup Battery Input. Connect to Ground if a backup battery is not used.
VOUT
Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest potential. VOUT
can supply up to 100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBATT are not used.
GND
0 V. Ground reference for all signals.
RESET
Logic Output. RESET goes low if
1. VCC falls below the Reset Threshold
2. VCC falls below VBATT
3. The watchdog timer is not serviced within its timeout period.
The reset threshold is typically 4.65 V for the ADM690/ADM691/ADM694/ADM695 and 4.4 V for the ADM692 and
ADM693. RESET remains low for 50 ms (ADM690/ADM691/ADM692/ADM693) or 200 ms (ADM694/ADM695)
after VCC returns above the threshold. RESET also goes low for 50 (200) ms if the watchdog timer is enabled but not
serviced within its timeout period. The RESET pulse width can be adjusted on the ADM691/ADM693/ADM695 as
shown in Table I. The RESET output has an internal 3 µA pull up, and can either connect to an open collector
Reset bus or directly drive a CMOS gate without an external pull-up resistor.
WDI
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout
period, RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog
timer may be disabled if WDI is left floating or is driven to midsupply.
PFI
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V, PFO
goes low. Connect PFI to GND or VOUT when not used.
PFO
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. The
comparator is turned off and PFO goes low when VCC is below VBATT.
CEIN
Logic Input. The input to the CE gating circuit. Connect to GND or VOUT if not used.
CEOUT
Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset
threshold. If VCC is below the reset threshold, CEOUT is forced high. See Figures 5 and 6.
BATT ON
Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT
is internally switched to VCC. The output typically sinks 35 mA and can directly drive the base of an external
PNP transistor to increase the output current above the 100 mA rating of VOUT.
LOW LINE
Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises
above the reset threshold.
RESET
Logic Output. RESET is an active high output. It is the inverse of RESET.
OSC SEL
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets
the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN,
is enabled. OSC SEL has a 3 µA internal pull up, (see Table I).
OSC IN
Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external
capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period (see Table I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled
and the reset active time is fixed at 50 ms typ. (ADM691/ADM693) or 200 ms typ (ADM695). In this mode the
OSC IN pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout
period immediately after a reset is 1.6 s typical.
WDO
Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply,
the watchdog timer is disabled and WDO remains high. WDO also goes high when LOW LINE goes low.
–4–
REV. A
ADM690–ADM695
PIN CONFIGURATIONS
VBATT 1
VOUT 2
V
CC
GND
3
4
BATT ON 5
16 RESET
ADM691
ADM693
ADM695
TOP VIEW
(Not to Scale)
LOW LINE 6
OSC IN
15 RESET
14 WDO
VOUT
13 CE
V
IN
12
CE
OUT
11 WDI
7
OSC SEL 8
10
PFO
9
PFI
1
CC
2
GND
3
PFI
4
ADM690
ADM692
ADM694
TOP VIEW
(Not to Scale)
8
VBATT
7
RESET
6
WDI
5
PFO
PRODUCT SELECTION GUIDE
Part
Number
Nominal Reset
Time
Nominal VCC
Reset Threshold
Nominal Watchdog
Timeout Period
Battery Backup
Switching
Base Drive
Ext PNP
Chip Enable
Signals
ADM690
ADM691
ADM692
ADM693
ADM694
ADM695
50 ms
50 ms or ADJ
50 ms
50 ms or ADJ
200 ms
200 ms or ADJ
4.65 V
4.65 V
4.4 V
4.4 V
4.65 V
4.65 V
1.6 s
100 ms, 1.6 s, ADJ
1.6 s
100 ms, 1.6 s, ADJ
1.6 s
100 ms, 1.6 s, ADJ
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
CIRCUIT INFORMATION
Battery Switchover Section
If the continuous output current requirement at VOUT exceeds
100 mA or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM691/
ADM693/ADM695) can directly drive the base of the external
transistor.
The battery switchover circuit compares VCC to the VBATT
input, and connects VOUT to whichever is higher. Switchover
occurs when VCC is 50 mV higher than VBATT as VCC falls, and
when VCC is 70 mV greater than VBATT as VCC rises. This
20 mV of hysteresis prevents repeated rapid switching if VCC
falls very slowly or remains nearly equal to the battery voltage.
A 20 Ω MOSFET switch connects the VBATT input to VOUT
during battery backup. This MOSFET has very low input-tooutput differential (dropout voltage) at the low current levels
required for battery back up of CMOS RAM or other low
power CMOS circuitry. The supply current in battery back up
is typically 0.6 µA.
The ADM690/ADM691/ADM694/ADM695 operates with
battery voltages from 2.0 V to 4.25 V and the ADM692/ADM693
operates with battery voltages from 2.0 V to 4.0 V. High value
capacitors, either standard electrolytic or the farad size double
layer capacitors, can also be used for short-term memory back
up. A small charging current of typically 10 nA (0.1 µA max)
flows out of the VBATT terminal. This current is useful for
maintaining rechargeable batteries in a fully charged condition.
This extends the life of the back up battery by compensating
for its self discharge current. Also note that this current poses
no problem when lithium batteries are used for back up since
the maximum charging current (0.1 µA) is safe for even the
smallest lithium cells.
Figure 1. Battery Switchover Schematic
During normal operation with VCC higher than VBATT, VCC is internally switched to VOUT via an internal PMOS transistor
switch. This switch has a typical on-resistance of 1.5 Ω and can
supply up to 100 mA at the VOUT terminal. VOUT is normally
used to drive a RAM memory bank which may require instantaneous currents of greater than 100 mA. If this is the case then a
bypass capacitor should be connected to VOUT. The capacitor
will provide the peak current transients to the RAM. A capacitance value of 0.1 µF or greater may be used.
REV. A
–5–
If the battery-switchover section is not used, VBATT should be
connected to GND and VOUT should be connected to VCC.
ADM690–ADM695
POWER FAIL RESET OUTPUT
Watchdog Timer RESET
RESET is an active low output which provides a RESET signal
to the Microprocessor whenever VCC is at an invalid level. When
VCC falls below the reset threshold, the RESET output is forced
low. The nominal reset voltage threshold is 4.65 V (ADM690/
ADM691/ADM694/ADM695) or 4.4 V (ADM692/ADM693).
The watchdog timer circuit monitors the activity of the microprocessor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a RESET pulse is generated. The
nominal watchdog timeout period is preset at 1.6 seconds on the
ADM690/ADM692/ADM694. The ADM691/ADM693/ADM695
may be configured for either a fixed “short” 100 ms or a “long”
1.6 second timeout period or for an adjustable timeout period.
If the “short” period is selected, some systems may be unable to
service the watchdog timer immediately after a reset, so the
ADM691/ADM693/ADM695 automatically selects the “long”
timeout period directly after a reset is issued. The watchdog
timer is restarted at the end of reset, whether the reset was
caused by lack of activity on WDI or by VCC falling below the
reset threshold.
VCC
RESET
V2
V1
V2
t1
V1
t1
LOW LINE
t1 = RESET TIME.
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 2. Power Fail Reset Timing
On power-up RESET will remain low for 50 ms (200 ms for
ADM694 and ADM695) after VCC rises above the appropriate
reset threshold. This allows time for the power supply and microprocessor to stabilize. On power-down, the RESET output
remains low with VCC as low as 1 V. This ensures that the
microprocessor is held in a stable shutdown condition.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each “long” timeout period (1.6 s). The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI) or by connecting it to midsupply.
This RESET active time is adjustable on the ADM691/ADM693/
ADM695 by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. Refer to Table I and
Figure 4.
WDI
The guaranteed minimum and maximum thresholds of the
ADM690/ADM691/ADM694/ADM695 are 4.5 V and 4.73 V,
while the guaranteed thresholds of the ADM692/ADM693 are
4.25 V and 4.48 V. The ADM690/ADM691/ADM694/ADM695
is, therefore, compatible with 5 V supplies with a +10%, –5%
tolerance while the ADM692/ADM693 is compatible with 5 V
± 10% supplies. The reset threshold comparator has approximately 50 mV of hysteresis. The response time of the reset voltage comparator is less than 1 µs. If glitches are present on the
VCC line which could cause spurious reset pulses, then VCC
should be decoupled close to the device.
WDO
t2
t3
RESET
t1
t1
t1
t1 = RESET TIME.
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.
In addition to RESET the ADM691/ADM693/ADM695 contain an active high RESET output. This is the complement of
RESET and is intended for processors requiring an active high
RESET signal.
Figure 3. Watchdog Timeout Period and Reset Active
Time
–6–
REV. A
ADM690–ADM695
Table I. ADM691, ADM693, ADM695 Reset Pulse Width and Watchdog Timeout Selections
OSC SEL
OSC IN
Watchdog Timeout Period
Immediately
Normal
After Reset
Low
Low
Floating or High
Floating or High
External Clock Input
External Capacitor
Low
Floating or High
1024 CLKS
260 ms × C/47 pF
100 ms
1.6 s
Reset Active Period
4096 CLKS
1.04 s × C/47 pF
1.6 s
1.6 s
ADM691/ADM693
ADM695
512 CLKS
130 ms × C/47 pF
50 ms
50 ms
2048 CLKS
520 ms × C/47 pF
200 ms
200 ms
NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF).
The watchdog timeout period is fixed at 1.6 seconds, and the
reset pulse width is fixed at 50 ms on the ADM690/ADM692.
On the ADM694 the watchdog timeout period is also 1.6 seconds but the reset pulse width is fixed at 200 ms. The ADM691/
ADM693/ADM695 allow these times to be adjusted as shown
in Table I. Figure 4 shows the various oscillator configurations
which can be used to adjust the reset pulse width and watchdog
timeout period.
8
ADM691
ADM693
ADM695
7
OSC IN
COSC
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset, the timeout period is 1.6
seconds. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period becomes effective after the first transition of WDI. The software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are completed and the microprocessor is able to toggle WDI at the minimum watchdog timeout period of 70 ms.
Watchdog Output (WDO)
The Watchdog Output WDO (ADM691/ADM693/ADM695)
provides a status output which goes low if the watchdog timer
“times out” and remains low until set high by the next transition
on the Watchdog Input. WDO is also set high when VCC goes
below the reset threshold.
8
OSC SEL
Figure 4b. External Capacitor
NC
8
OSC SEL
ADM691
ADM693
ADM695
7
NC
OSC IN
Figure 4c. Internal Oscillator (1.6 Second Watchdog)
NC
8
OSC SEL
ADM691
ADM693
ADM695
OSC SEL
ADM691
ADM693
ADM695
CLOCK
0 TO 250kHz
7
OSC IN
7
OSC IN
Figure 4d. Internal Oscillator (100 ms Watchdog)
Figure 4a. External Clock Source
REV. A
–7–
ADM690–ADM695
CE Gating and RAM Write Protection (ADM691/ADM693/
ADM695)
Power Fail Warning Comparator
The ADM691/ADM693/ADM695 products include memory
protection circuitry which ensures the integrity of data in memory by preventing write operations when VCC is at an invalid
level. There are two additional pins, CEIN and CEOUT, which
may be used to control the Chip Enable or Write inputs of
CMOS RAM. When VCC is present, CEOUT is a buffered replica
of CEIN, with a 5 ns propagation delay. When VCC falls below
the reset voltage threshold or VBATT, an internal gate forces
CEOUT high, independent of CEIN.
CEOUT typically drives the CE, CS, or write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when VCC is at an invalid level. Similar protection of EEPROMs can be achieved by
using the CEOUT to drive the store or write inputs.
An additional comparator is provided for early warning of failure
in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.3 V reference. The Power
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V several milliseconds before the +5 V power supply falls below the
reset threshold. PFO is normally used to interrupt the microprocessor so that data can be stored in RAM and the shut down
procedure executed before power is lost
INPUT
POWER
R1
If the 5 ns typical propagation delay of CEOUT is excessive, connect CEIN to GND and use the resulting CEOUT to control a
high speed external logic gate.
R2
1.3V
POWER
FAIL
INPUT
PFO
POWER
FAIL
OUTPUT
ADM69x
ADM69x
CE IN
CEOUT
Figure 7. Power Fail Comparator
VCC LOW = 0
VCC OK = 1
Table II. Input and Output Status In Battery Backup Mode
Figure 5. Chip Enable Gating
VCC
RESET
V2
V1
V2
t1
V1
t1
LOW LINE
Signal
Status
VOUT
VOUT is connected to VBATT via an internal
PMOS switch.
RESET
Logic low.
RESET
Logic high. The open circuit output voltage is
equal to VOUT.
LOW LINE
Logic low.
BATT ON
Logic high. The open circuit voltage is equal to
VOUT.
WDI
WDI is ignored. It is internally disconnected
from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and VOUT. The input voltage
does not affect supply current.
WDO
Logic high. The open circuit voltage is equal
to VOUT.
PFI
The Power Fail Comparator is turned off and
has no effect on the Power Fail Output.
CEIN
CEOUT
t1 = RESET TIME.
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
PFO
Logic low.
CEIN
CEIN is ignored. It is internally disconnected
from its internal pull-up and does not source or
sink current as long as its input voltage is
between GND and VOUT. The input voltage
does not affect supply current.
CEOUT
Logic high. The open circuit voltage is equal to
VOUT.
OSC IN
OSC IN is ignored.
OSC SEL
OSC SEL is ignored.
Figure 6. Chip Enable Timing
–8–
REV. A
Typical Performance Curves–ADM690–ADM695
5.00
2.80
VCC = 5V
TA = +25°C
4.95
VCC = 0V
VBATT = +2.8V
TA = +25°C
2.79
A4
3.36 V
1V
1V
100
VOUT – V
VOUT – V
90
4.90
SLOPE = 1.5Ω
2.78
SLOPE = 20Ω
4.85
10
2.77
4.80
0%
2.76
0
20
40
60
80
100
0
200
IOUT – mA
400
600
IOUT – µA
800
1000
Figure 9. VOUT vs. IOUT Battery
Backup
Figure 8. VOUT vs. IOUT Normal
Operation
1.303
Figure 10. Reset Output Voltage vs.
Supply Voltage
4.70
53
1.302
1.301
1.300
1.299
20
RESET VOLTAGE THRESHOLD – V
RESET ACTIVE TIME – ms
VCC = +5V
PFI INPUT THRESHOLD – V
500ms
52
51
ADM690
ADM691
ADM692
ADM693
50
60
80
100
120
20
40
TEMPERATURE – °C
Figure 11. PFI Input Threshold vs.
Temperature
60
80
100
TEMPERATURE – °C
VCC = 5V
TA = +25 °C
5
Figure 12. Reset Active Time vs.
Temperature
4
3
VPFI
PFO
5
POWER-UP
4.64
POWER-DOWN
20
5
4
4
3
3
1.3V
0
0
0
1.35
1.35
1.35
1.25
1.25
1.25
PFO
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
TIME – µs
Figure 14. Power Fail Comparator
Response Time
REV. A
0
10 20
30 40 50 60
TIME – µs
70 80
90
10k
VPFI
1.3V
Figure 15. Power Fail Comparator
Response Time
–9–
+5V
1
30pF
0
0
120
VCC = 5V
TA = +25 °C
2
VPFI
1
30pF
60
80
100
TEMPERATURE – °C
6
VCC = 5V
TA = +25 °C
2
1.3V
40
Figure 13. Reset Voltage Threshold
vs. Temperature
1
2
ADM690
ADM691
ADM694
ADM695
4.66
120
6
6
4.68
4.62
49
40
VCC = +5V
0
PFO
30pF
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
TIME – µs
Figure 16. Power Fail Comparator
Response Time with Pull-Up Resistor
ADM690–ADM695
+APPLICATION INFORMATION
Increasing the Drive Current
If the continuous output current requirements at VOUT exceed
100 mA or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM691/
ADM693/ADM695) can directly drive the base of the external
transistor.
When PFO is low, resistor R3 sinks current from the summing
junction at the PFI pin. When PFO is high, the series combination of R3 and R4 source current into the PFI summing junction. This results in differing trip levels for the comparator.
7805
+7V TO +15V
INPUT
POWER
+5V
VCC
R4
R1
1.3V
PNP TRANSISTOR
+5V
INPUT
POWER
0.1µF
0.1µF
VBATT
BATTERY
BATT
ON
TO
µP NMI
PFI
ADM69x
R2
VCC
PFO
VOUT
R3
ADM691
ADM693
ADM695
5V
Figure 17. Increasing the Drive Current
PFO
Using a Rechargeable Battery for Back Up
If a capacitor or a rechargeable battery is used for back up then
the charging resistor should be connected to VOUT since this
eliminates the discharge path that would exist during power
down if the resistor is connected to VCC.
0V
(
R
)
R1 (5V – 1.3V)
R1
VL = 1.3V 1+ –––
– –––––––––––––
1.3V (R 3 + R4 )
R2
(
0.1µF
R
0.1µF
ASSUMING R 4 < < R3 THEN
R1
HYSTERESIS V H – VL = 5V –––
R2
VOUT
VCC
VBATT
RECHARGEABLE
BATTERY
VH
VIN
R1
R1
VH = 1.3V 1+ –––
+ –––
R3
R2
I = VOUT – V BATT
+5V
INPUT
POWER
VL
0V
(
)
)
Figure 19. Adding Hysteresis to the Power Fail Comparator
ADM69x
Figure 18. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is noninverting, hysteresis can be added simply by connecting a resistor between the PFO output and the PFI input as shown in Figure 19.
Monitoring the Status of the Battery
The power fail comparator can be used to monitor the status of
the backup battery instead of the power supply if desired. This
is shown in Figure 20. The PFI input samples the battery voltage and generates an active low PFO signal when the battery
voltage drops below a chosen threshold. It may be necessary to
apply a test load in order to determine the loaded battery voltage. This can be done under processor control using CEOUT.
Since CEOUT is forced high during the battery backup mode, the
test load will not be applied to the battery while it is in use, even
if the microprocessor is not powered.
–10–
REV. A
ADM690–ADM695
+5V INPUT
POWER
VBATT
CONTROL
INPUT*
VCC
PFO
PFI
D1
LOW BATTERY
SIGNAL TO
µP I/O PIN
10MΩ
BATTERY
ADM69x
OSC SEL
ADM69x
D2
OSC IN
20kΩ
OPTIONAL
TEST LOAD
CEIN
10MΩ
CE OUT
FROM µP I/O PIN
APPLIES TEST LOAD
TO BATTERY
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 21b. Programming the Watchdog Input
Figure 20. Monitoring the Battery Status
Alternate Watchdog Input Drive Circuits
Replacing the Backup Battery
The watchdog feature can be enabled and disabled under program control by driving WDI with a 3-state buffer (Figure 21a).
When three-stated, the WDI input will float thereby disabling
the watchdog timer.
When changing the backup battery with system power on, spurious resets can occur when the battery is removed. This occurs
because the leakage current flowing out of the VBATT pin will
charge up the stray capacitance. If the voltage on VBATT reaches
within 50 mV of VCC, a reset pulse is generated.
WATCHDOG
STROBE
WDI
If spurious resets during battery replacement are acceptable,
then no action is required. If not, then one of the following
solutions should be considered:
ADM69x
CONTROL
INPUT
Figure 21a. Programming the Watchdog Input
This circuit is not entirely foolproof, and it is possible that a
software fault could erroneously 3-state the buffer. This would
then prevent the ADM69x from detecting that the microprocessor is no longer operating correctly. In most cases a better
method is to extend the watchdog period rather than disabling
the watchdog. This may be done under program control using
the circuit shown in Figure 21b. When the control input is high,
the OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01 µF capacitor sets a watchdog timeout
delay of 100 seconds. When the control input is low, the OSC
SEL pin is driven high, selecting the internal oscillator. The
100 ms or the 1.6 s period is chosen, depending on which diode
in Figure 21b is used. With D1 inserted the internal timeout is
set at 100 ms, while with D2 inserted the timeout is set at 1.6 s.
1. A capacitor from VBATT to GND. This gives time while the
capacitor is charging up to replace the battery. The leakage
current will charge up the external capacitor towards the VCC
level. The time taken is related to the charging current, the
size of external capacitor and the voltage differential between
the capacitor and the charging voltage supply.
t = CEXT × VDIFF/I
The maximum leakage (charging) current is 1 µA over temperature and VDIFF = VCC–VBATT. Therefore, the capacitor
size should be chosen such that sufficient time is available to
make the battery replacement.
CEXT = TREQD (1 µA/(VCC–VBATT))
If a replacement time of 5 seconds is allowed and assuming a
VCC of 4.5 V and a VBATT of 3 V
CEXT = 3.33 µF
VBATT
BATTERY
CEXT
ADM69x
Figure 22a. Preventing Spurious RESETS During
Battery Replacement
2. A resistor from VBATT to GND. This will prevent the voltage
on VBATT from rising to within 50 mV of VCC during battery
replacement.
REV. A
–11–
ADM690–ADM695
R =(VCC – 50 mV)/1 µA
+5V
Note that the resistor will discharge the battery slightly. With a
VCC supply of 4.5 V, a suitable resistor is 4.3 MΩ. With a 3 V
battery this will draw around 700 nA. This will be negligible in
most cases.
R1
PFI
R2
VBATT
µP POWER
VCC
VOUT
ADM690
ADM692
ADM694
CMOS RAM
POWER
0.1µF
µP SYSTEM
µP RESET
RESET
BATTERY
R
+
ADM69x
VBATT
PFO
µP NMI
WDI
I/O LINE
BATTERY
GND
Figure 23a. ADM690/ADM692/ADM694 Typical Application
Circuit A
Figure 22b. Preventing Spurious RESETS During Battery
Replacement
Figure 23b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regulator. This gives an earlier warning of an impending power failure. It is useful with processors operating at low speeds or
TYPICAL APPLICATIONS
ADM690, ADM692 AND ADM694
Figure 23 shows the ADM690/ADM692/ADM694 in a typical
power monitoring, battery backup application. VOUT powers the
CMOS RAM. Under normal operating conditions with VCC
present, VOUT is internally connected to VCC. If a power failure
occurs, VCC will decay and VOUT will be switched to VBATT
thereby maintaining power for the CMOS RAM. A RESET
pulse is also generated when VCC falls below 4.65 V for the
ADM690/ADM694 or 4.4 V for the ADM692. RESET will
remain low for 50 ms (200 ms for ADM694) after VCC returns
to 5 V.
where there are a significant number of housekeeping tasks to be
completed before the power is lost.
R2
µP POWER
VCC
PFI
VOUT
ADM690
ADM692
ADM694
RESET
VBATT
GND
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is compared with a precision 1.3 V internal reference. If the input voltage drops below 1.3 V, a power fail output (PFO) signal is
generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage VT.
0.1µF
CMOS RAM
POWER
µP SYSTEM
µP RESET
PFO
µP NMI
WDI
I/O LINE
BATTERY
If the watchdog timer is not needed, the WDI input should be
left floating.
R1/R2 = (VT/1.3) – 1
0.1µF
R1
The watchdog timer input (WDI) monitors an I/O line from the
µP system. This line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line indicates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
VT = (1.3 R1/R2) + 1.3 V
+5V
7805
INPUT
POWER
V > 8V
Figure 23b. ADM690/ADM692/ADM694 Typical Application
Circuit B
ADM691, ADM693, ADM695
A typical connection for the ADM691/ADM693/ADM695 is
shown in Figure 24. CMOS RAM is powered from VOUT. When
5 V power is present this is routed to VOUT. If VCC fails then
VBATT is routed to VOUT. VOUT can supply up to 100 mA from
VCC, but if more current is required, an external PNP transistor
can be added. When VCC is higher than VBATT, the BATT ON
output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1 µF capacitor is connected to VOUT to
supply the transient currents for CMOS RAM. When VCC is
lower than VBATT, an internal 20 Ω MOSFET connects the
backup battery to VOUT.
–12–
REV. A
ADM690–ADM695
RAM Write Protection
INPUT POWER
+5V
0.1µF
0.1µF
3V
BATTERY
VCC
VBATT
R1
PFI
GND
R2
The ADM691/ADM693/ADM695 CEOUT line drives the Chip
Select inputs of the CMOS RAM. CEOUT follows CEIN as long
as VCC is above the 4.65 V (4.4 V for ADM693) reset threshold.
BATT
ON
VOUT
CMOS
RAM
CEOUT
ADM691
ADM693
ADM695
ADDRESS
DECODE
CE IN
A0–A15
Watchdog Timer
WDI
NC
OSC IN
OSC SEL
If VCC falls below the reset threshold, CEOUT goes high, independent of the logic level at CEIN. This prevents the microprocessor from writing erroneous data into RAM during power-up,
power-down, brownouts and momentary power interruptions.
I/O LINE
PFO
NMI
RESET
LOW LINE WDO
µP
RESET
RESET
0.1µF
SYSTEM STATUS
INDICATORS
Figure 24. ADM691/ADM693/ADM695 Typical Application
Reset Output
The internal voltage detector monitors VCC and generates a
RESET output to hold the microprocessor’s Reset line low
when VCC is below 4.65 V (4.4 V for ADM693). An internal
timer holds RESET low for 50 ms (200 ms for the ADM695)
after VCC rises above 4.65 V (4.4 V for ADM693). This prevents
repeated toggling of RESET even if the 5 V power drops out
and recovers with each power line cycle.
The crystal oscillator normally used to generate the clock for microprocessors can take several milliseconds to stabilize. Since
most microprocessors need several clock cycles to reset, RESET
must be held low until the microprocessor clock oscillator has
started. The power-up RESET pulse lasts 50 ms (200 ms for the
ADM695) to allow for this oscillator start-up time. If a different
reset pulse width is required, then a capacitor should be connected to OSC IN or an external clock may be used. Please refer
to Table I and Figure 4. The manual reset switch and the 0.1 µF
capacitor connected to the reset line can be omitted if a manual
reset is not needed. An inverted, active high, RESET output is
also available.
The microprocessor drives the Watchdog Input (WDI) with an
I/O line. When OSC IN and OSC SEL are unconnected, the
microprocessor must toggle the WDI pin once every 1.6 seconds to verify proper software execution. If a hardware or software failure occurs such that WDI not toggled, the ADM691/
ADM693 will issue a 50 ms (200 ms for ADM695) RESET
pulse after 1.6 seconds. This typically restarts the microprocessor’s power-up routine. A new RESET pulse is issued
every 1.6 seconds until WDI is again strobed. If a different
watchdog timeout period is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to Table I and Figure 4.
The WATCHDOG OUTPUT (WDO) goes low if the watchdog timer is not serviced within its timeout period. Once WDO
goes low, it remains low until a transition occurs at WDI. The
watchdog timer feature can be disabled by leaving WDI
unconnected.
The RESET output has an internal 3 µA pull-up, and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.
Power Fail Detector
The +5 V VCC power line is monitored via a resistive potential
divider connected to the Power Fail Input (PFI). When the
voltage at PFI falls below 1.3 V, the Power Fail Output (PFO)
drives the processor’s NMI input low. If for example a Power
Fail threshold of 4.8 V is set with resistors R1 and R2, the microprocessor will have the time when VCC falls from 4.8 V to 4.65 V
to save data into RAM. An earlier power fail warning can be
generated if the unregulated dc input to the 5 V regulator is
available for monitoring. This will allow more time for microprocessor housekeeping tasks to be completed before power is
lost.
REV. A
–13–
ADM690–ADM695
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Plastic DIP (N-8)
8
5
0.280 (7.11)
0.240 (6.10)
PIN 1
1
4
0.325 (8.25)
0.300 (7.62)
0.430 (10.92)
0.348 (8.84)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.150
(3.81)
MIN
0.160 (4.06)
0.115 (2.93)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.070 (1.77)
0.045 (1.15)
16-Lead Plastic DIP (N-16)
16
9
0.280 (7.11)
0.240 (6.10)
PIN 1
1
8
0.325 (8.25)
0.300 (7.62)
0.840 (21.33)
0.745 (18.93)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
0.150
(3.81)
0.200 (5.05)
0.125 (3.18)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.070 (1.77)
0.045 (1.15)
8-Pin Cerdip (Q-8)
5
8
0.310 (7.87)
0.220 (5.59)
PIN 1
1
4
0.420 (10.67)
MAX
0.200
(5.08)
MAX
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.320 (8.13)
0.290 (7.37)
0.015 (0.381)
0.008 (0.204)
0.100 (2.54)
BSC
0.070 (1.78)
0.30 (0.76)
–14–
REV. A
ADM690–ADM695
16-Lead Cerdip (Q-16)
9
16
0.310 (7.87)
0.220 (5.59)
PIN 1
1
8
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.150
(3.81)
MIN
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
0.320 (8.13)
0.290 (7.37)
0.015 (0.381)
0.008 (0.204)
0.070 (1.78)
0.30 (0.76)
16-Lead SOIC (R-16)
16
9
0.419
(10.65)
0.299
(7.60)
1
8
0.030
(0.75)
0.413 (10.50)
0.012
(0.3)
0.104
(2.65)
0.05 (1.27)
REF
REV. A
0.019 (0.49)
0.013
(0.32)
–15–
0.042
(1.07)
–16–
PRINTED IN U.S.A.
C1782a–2–6/96