PD - 95719 IRF3717PbF HEXFET® Power MOSFET Applications l Synchronous MOSFET for Notebook Processor Power l Synchronous Rectifier MOSFET for Isolated DC-DC Converters in Networking Systems l Lead-Free VDSS RDS(on) max 4.4m:@VGS = 10V 20V Benefits l Ultra-Low Gate Impedance l Very Low RDS(on) l Fully Characterized Avalanche Voltage and Current 1 8 S 2 7 S 3 6 4 5 S G ID 20A A A D D D D SO-8 Top View Absolute Maximum Ratings Max. Units VDS Drain-to-Source Voltage Parameter 20 V VGS Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V ± 20 ID @ TA = 25°C 20 IDM Continuous Drain Current, VGS @ 10V Pulsed Drain Current 160 ID @ TA = 70°C A 16 c PD @TA = 25°C Power Dissipation 2.5 PD @TA = 70°C Power Dissipation 1.6 TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range W 0.02 -55 to + 150 W/°C °C Thermal Resistance Parameter RθJL RθJA Junction-to-Drain Lead Junction-to-Ambient f Typ. Max. Units ––– 20 °C/W ––– 50 Notes through are on page 10 www.irf.com 1 8/10/04 IRF3717PbF Static @ TJ = 25°C (unless otherwise specified) Parameter BVDSS ∆ΒVDSS/∆TJ Min. Typ. Max. Units 20 ––– ––– Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance ––– ––– 0.014 3.7 ––– 4.4 V/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 20A Gate Threshold Voltage ––– 1.55 4.8 2.0 5.7 2.45 VGS = 4.5V, ID = 16A VDS = VGS, ID = 250µA IDSS Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current ––– ––– -5.4 ––– ––– 1.0 IGSS Gate-to-Source Forward Leakage ––– ––– ––– ––– 150 100 nA VDS = 16V, VGS = 0V, TJ = 125°C VGS = 20V Gate-to-Source Reverse Leakage Forward Transconductance ––– 57 ––– ––– -100 ––– S VGS = -20V VDS = 10V, ID = 16A Total Gate Charge Pre-Vth Gate-to-Source Charge ––– ––– 22 6.8 33 ––– Post-Vth Gate-to-Source Charge Gate-to-Drain Charge ––– ––– 2.2 7.3 ––– ––– Qgodr Qsw Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– ––– 5.7 9.5 ––– ––– Qoss td(on) Output Charge Turn-On Delay Time ––– ––– 12 12 ––– ––– tr td(off) Rise Time Turn-Off Delay Time ––– ––– 14 15 ––– ––– tf Ciss Fall Time Input Capacitance ––– ––– 6.0 2890 ––– ––– Coss Crss Output Capacitance Reverse Transfer Capacitance ––– ––– 930 430 ––– ––– RDS(on) VGS(th) ∆VGS(th)/∆TJ gfs Qg Qgs1 Qgs2 Qgd V Conditions Drain-to-Source Breakdown Voltage VGS = 0V, ID = 250µA e e V mV/°C µA VDS = 16V, VGS = 0V VDS = 10V nC VGS = 4.5V ID = 16A See Fig. 16 nC ns VDS = 10V, VGS = 0V VDD = 10V, VGS = 4.5V ID = 16A Clamped Inductive Load VGS = 0V pF VDS = 10V ƒ = 1.0MHz Avalanche Characteristics EAS IAR Parameter Single Pulse Avalanche Energy Avalanche Current c Typ. ––– ––– d Max. 32 16 Units mJ A Diode Characteristics Parameter Min. Typ. Max. Units IS Continuous Source Current ISM (Body Diode) Pulsed Source Current ––– ––– 160 VSD trr (Body Diode) Diode Forward Voltage Reverse Recovery Time ––– ––– ––– 22 1.0 32 V ns Qrr Reverse Recovery Charge ––– 13 19 nC 2 c ––– ––– 20 Conditions MOSFET symbol A showing the integral reverse D G p-n junction diode. TJ = 25°C, IS = 16A, VGS = 0V TJ = 25°C, IF = 16A, VDD = 10V di/dt = 100A/µs S e e www.irf.com IRF3717PbF 1000 VGS 10V 4.5V 3.8V 3.5V 3.3V 3.0V 2.8V 2.5V ID, Drain-to-Source Current (A) TOP 100 BOTTOM 10 1 20µs PULSE WIDTH Tj = 25°C TOP ID, Drain-to-Source Current (A) 1000 100 BOTTOM 10 2.5V 20µs PULSE WIDTH Tj = 150°C 2.5V 0.1 1 0.1 1 10 100 0.1 V DS, Drain-to-Source Voltage (V) 1 10 100 V DS, Drain-to-Source Voltage (V) Fig 2. Typical Output Characteristics Fig 1. Typical Output Characteristics 1000 1.5 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (Α) VGS 10V 4.5V 3.8V 3.5V 3.3V 3.0V 2.8V 2.5V 100 T J = 150°C 10 T J = 25°C 1 VDS = 10V 20µs PULSE WIDTH 0.1 ID = 20A VGS = 10V 1.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 5.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 T J , Junction Temperature (°C) Fig 4. Normalized On-Resistance vs. Temperature 3 IRF3717PbF 100000 6.0 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd VGS, Gate-to-Source Voltage (V) ID=16A C, Capacitance(pF) C oss = C ds + C gd 10000 Ciss Coss 1000 Crss VDS= 16V VDS= 10V 5.0 4.0 3.0 2.0 1.0 0.0 100 1 10 100 0 VDS, Drain-to-Source Voltage (V) 10 15 20 25 30 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 1000.00 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 5 100.00 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 T J = 150°C 10.00 T J = 25°C 1.00 100µsec 10 Tj = 150°C Single Pulse VGS = 0V 0.10 10msec 1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VSD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 1msec T A = 25°C 1.4 0 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRF3717PbF 2.5 VGS(th) Gate threshold Voltage (V) ID, Drain Current (A) 20 15 10 5 2.0 ID = 250µA 1.5 1.0 0 25 50 75 100 125 -75 150 -50 -25 0 25 50 75 100 125 150 T J , Temperature ( °C ) T A , Ambient Temperature (°C) Fig 9. Maximum Drain Current vs. Ambient Temperature Fig 10. Threshold Voltage vs. Temperature 100 Thermal Response ( Z thJA ) D = 0.50 10 0.20 0.10 0.05 1 0.02 0.01 τJ 0.1 R1 R1 τJ τ1 R2 R2 R3 R3 R4 R4 τC τ τ2 τ1 τ3 τ2 τ3 τ4 τ4 Ci= τi/Ri Ci= i/Ri SINGLE PULSE ( THERMAL RESPONSE ) 0.01 Ri (°C/W) τi (sec) 1.4174 0.000277 11.3607 0.103855 21.8639 1.362000 15.3721 39.60000 P DM t1 t2 Notes: 1. Duty factor D = t1/ t 2 2. Peak T J = P DM x Z thJA 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 +T A 10 100 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient www.irf.com 5 IRF3717PbF 15V DRIVER L VDS D.U.T RG + V - DD IAS 20V VGS A 0.01Ω tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS EAS , Single Pulse Avalanche Energy (mJ) 150 ID 6.5A 7.5A BOTTOM 16A TOP 100 50 0 25 tp 50 75 100 125 150 Starting T J , Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy vs. Drain Current LD VDS I AS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T VGS Current Regulator Same Type as D.U.T. Pulse Width < 1µs Duty Factor < 0.1% 50KΩ 12V .2µF Fig 14a. Switching Time Test Circuit .3µF D.U.T. + V - DS VDS 90% VGS 3mA 10% IG ID VGS Current Sampling Resistors td(on) Fig 13. Gate Charge Test Circuit 6 tr td(off) tf Fig 14b. Switching Time Waveforms www.irf.com IRF3717PbF D.U.T Driver Gate Drive + - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRF3717PbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝ 2 ⎠ This can be expanded and approximated by; Ploss = (Irms 2 × Rds(on ) ) ⎛ Qgs 2 Qgd ⎞ ⎛ ⎞ +⎜I × × Vin × f ⎟ + ⎜ I × × Vin × f ⎟ ig ig ⎝ ⎠ ⎝ ⎠ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝ 2 ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. *dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRF3717PbF SO-8 Package Outline Dimensions are shown in millimeters (inches) D 5 A 8 7 6 5 6 H 0.25 [.010] 1 2 3 A 4 MAX MIN .0532 .0688 1.35 1.75 A1 .0040 e e1 0.25 .0098 0.10 .013 .020 0.33 0.51 c .0075 .0098 0.19 0.25 D .189 .1968 4.80 5.00 E .1497 .1574 3.80 4.00 e .050 BASIC 1.27 BASIC .025 BASIC 0.635 BASIC H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 y 0° 8° 0° 8° K x 45° A C y 0.10 [.004] 8X b 0.25 [.010] MAX b e1 6X MILLIMETERS MIN A E INCHES DIM B A1 8X L 8X c 7 C A B F OOTPRINT NOT ES : 1. DIMENS IONING & TOLERANCING PER ASME Y14.5M-1994. 8X 0.72 [.028] 2. CONT ROLLING DIMENS ION: MILLIMET ER 3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS -012AA. 5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS . MOLD PROTRUS IONS NOT TO EXCEED 0.15 [.006]. 6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS . MOLD PROTRUS IONS NOT TO EXCEED 0.25 [.010]. 6.46 [.255] 7 DIMENS ION IS T HE LENGT H OF LEAD FOR SOLDERING TO A S UBST RAT E. 3X 1.27 [.050] 8X 1.78 [.070] SO-8 Part Marking EXAMPLE: T HIS IS AN IRF7101 (MOSFET ) INT ERNAT IONAL RECT IFIER LOGO XXXX F7101 DAT E CODE (YWW) P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) Y = LAS T DIGIT OF T HE YEAR WW = WEEK A = AS S EMBLY S IT E CODE LOT CODE PART NUMBER www.irf.com 9 IRF3717PbF SO-8 Tape and Reel Dimensions are shown in millimeters (inches) TERMINAL NUMBER 1 12.3 ( .484 ) 11.7 ( .461 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 330.00 (12.992) MAX. 14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 0.26mH, RG = 25Ω, IAS = 16A. Pulse width ≤ 400µs; duty cycle ≤ 2%. When mounted on 1 inch square copper board. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualifications Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.08/04 10 www.irf.com