TI1 AMC1204BDW Amc1204 20-mhz, second-order, isolated delta-sigma modulator Datasheet

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AMC1204, AMC1204B
SBAS512E – APRIL 2011 – REVISED SEPTEMBER 2015
AMC1204 20-MHz, Second-Order, Isolated Delta-Sigma Modulator
for Current-Shunt Measurement
1 Features
3 Description
•
The AMC1204 and AMC1204B are 1-bit digital
output, isolated delta-sigma (ΔΣ) modulators that can
be clocked at up to 20 MHz. The digital isolation of
the modulator output is provided by a silicon dioxide
(SiO2) barrier that is highly resistant to magnetic
interference. This barrier has been certified to provide
basic galvanic isolation of up to 4000 VPEAK
(AMC1204) and 4250 VPEAK (AMC1204B) according
to UL1577, VDE V 0884-10, and CSA standards or
specifications.
1
•
•
•
•
•
•
•
±250-mV Input Voltage Range Optimized for
Shunt Resistors
Certified Digital Isolation:
– CSA, VDE V 0884-10, and UL1577 Approved
– Isolation Voltage: 4250 VPEAK (AMC1204B)
– Working Voltage: 1200 VPEAK
– Transient Immunity: 15 kV/µs
Long Isolation Barrier Lifetime
(see Application Report SLLA197)
High Electromagnetic Field Immunity
(see Application Note SLLA181A)
Outstanding AC Performance:
– SNR: 84 dB (Minimum)
– THD: –80 dB (Maximum)
Excellent DC Precision:
– INL: ±8LSB (Maximum)
– Gain Error: ±2% (Maximum)
External Clock Input for Easier Synchronization
Fully Specified Over the Extended Industrial
Temperature Range
2 Applications
•
Shunt Resistor Based Current Sensing in:
– Motor Control
– Green Energy
– Inverter Applications
– Uninterruptible Power Supplies
The AMC1204 and AMC1204B provide a single-chip
solution for measuring the small signal of a shunt
resistor across an isolated barrier. These types of
resistors are typically used to sense currents in motor
control inverters, green energy generation systems,
and other industrial applications. The AMC1204 and
AMC1204B differential inputs easily connect to the
shunt resistor or other low-level signal sources. An
internal reference eliminates the need for external
components. When used with an appropriate external
digital filter, an effective number of bits (ENOB) of 14
is achieved at a data rate of 78 kSPS.
A 5-V analog supply (AVDD) is used by the
modulator while the isolated digital interface operates
from a 3-V, 3.3-V, or 5-V supply (DVDD). The
AMC1204 and AMC1204B are available in SOIC-16
(DW) and SOIC-8 (DWV) packages and are specified
from –40°C to 105°C.
Device Information(1)
PART NUMBER
AMC1204
PACKAGE
BODY SIZE (NOM)
SOIC (16)
10.30 mm × 7.50 mm
SOIC (8)
5.85 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
AVDD
DS
Modulator
2.5V
Ref
AGND
Isolation Barrier
VINP
VINN
DVDD
DATA
CLKIN
DGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1204, AMC1204B
SBAS512E – APRIL 2011 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configurations.................................................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
1
1
1
2
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 7
Regulatory Information.............................................. 7
IEC Safety Limiting Values ....................................... 8
IEC 61000-4-5 Ratings ............................................. 8
IEC 60664-1 Ratings............................................... 8
Isolation Characteristics .......................................... 9
Package Characteristics ........................................ 9
Typical Characteristics .......................................... 10
Detailed Description ............................................ 17
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
17
19
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2013) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed first sub-bullet of Certified Digital Isolation Feature bullet: changed IEC60747-5-5 to VDE V 0884-10................. 1
•
Changed IEC60747-5-5 to VDE V 0884-10 in first paragraph of Description section............................................................ 1
•
Changed Isolator to Package in title of Isolator Characteristics table .................................................................................... 2
•
Changed IEC60747-5-5 to VDE V 0884-10 in first row of Regulatory Information table ....................................................... 7
•
Changed Isolator to Package in title of Isolator Characteristics table .................................................................................... 9
•
Changed Isolator to Package in title of Isolator Characteristics table .................................................................................. 26
Changes from Revision C (August 2012) to Revision D
Page
•
Changed first sub-bullet of Certified Digital Isolation Feature bullet: changed IEC60747-5-2 to IEC60747-5-5.................... 1
•
Deleted chip photo.................................................................................................................................................................. 1
•
Added DWV (SSO-8) package to document .......................................................................................................................... 1
•
Changed IEC60747-5-2 to IEC60747-5-5 in first paragraph of Description section .............................................................. 1
•
Changed last paragraph of Description section ..................................................................................................................... 1
•
Added DWV pin out drawing .................................................................................................................................................. 4
•
Added DWV information to Pin Descriptions table ................................................................................................................. 4
•
Added DWV package to Thermal Information table ............................................................................................................... 5
•
Changed IEC60747-5-2 to IEC60747-5-5 in first row of Regulatory Information table .......................................................... 7
•
Added DWV package row to L(I01) and L(I02) parameters in Isolator Characteristics table................................................. 9
•
Changed first paragraph of Digital Output section: changed 78.1% to 89.06% and 21.9% to 10.94% ............................... 19
2
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SBAS512E – APRIL 2011 – REVISED SEPTEMBER 2015
Changes from Revision B (August 2011) to Revision C
Page
•
Changed Certified digital isolation, isolation voltage Feature bullet ....................................................................................... 1
•
Added AMC1204B to document ............................................................................................................................................. 1
•
Changed Description section to include AMC1204B.............................................................................................................. 1
•
Changed package name from TSSOP to SO......................................................................................................................... 4
•
Changed footnote 1 in Electrical Characteristics table........................................................................................................... 6
•
Changed Analog Inputs, VCM parameter minimum specification and unit in Electrical Characteristics table......................... 6
•
Changed Digital Output, COUT and CLOAD parameters unit specifications in Electrical Characteristics table ......................... 7
•
Added AMC1204B values to Isolation Characteristics table .................................................................................................. 9
•
Changed AMC1204 VIOTM t = 1s value in Isolation Characteristics table .............................................................................. 9
•
Changed CTI minimum specification in Isolator Characteristics table ................................................................................... 9
•
Updated Figure 51 ............................................................................................................................................................... 24
•
Updated Figure 53 ............................................................................................................................................................... 25
•
Updated Figure 54 ............................................................................................................................................................... 26
Changes from Revision A (April 2011) to Revision B
•
Page
Changed value of VIOSM parameter in IEC 61000-4-5 Ratings table...................................................................................... 8
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5 Pin Configurations
DWV Package
8-Pin SOIC
Top View
DW Package
16-Pin SOIC
Top View
AVDD
1
8
DVDD
AVDD
1
16 DGND
VINP
2
7
CLKIN
VINP
2
15 NC
VINN
3
6
DATA
VINN
3
14 DVDD
AGND
4
5
DGND
AGND
4
13 CLKIN
(1)
5
12 NC
NC
6
11 DATA
NC
7
10 NC
AGND
8
9
NC
DGND
NC = no internal connection.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
8 PINS
16 PINS
AVDD
1
1
Power
VINP
2
2
Analog input
Noninverting analog input
VINN
3
3
Analog input
Inverting analog input
AGND
4
4, 8 (1)
Power
High-side ground
DGND
5
9, 16
Power
Controller-side ground
DATA
6
11
CLKIN
7
13
Digital input
DVDD
8
14
Power
NC
—
5-7, 10,
12, 15
—
(1)
4
High-side power supply
Digital output Modulator data output
Modulator clock input
Controller-side power supply
No internal connection; can be tied to any potential or left unconnected
Both pins are connected internally via a low-impedance path; thus, only one of the pins must be tied to the ground plane.
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SBAS512E – APRIL 2011 – REVISED SEPTEMBER 2015
6 Specifications
6.1 Absolute Maximum Ratings
Over the operating ambient temperature range, unless otherwise noted.
(1)
Supply voltage, AVDD to AGND or DVDD to DGND
MIN
MAX
UNIT
–0.3
6
V
V
Analog input voltage at VINP, VINN
AGND – 0.5
AVDD + 0.5
Digital input voltage at CLKIN
DGND – 0.3
DVDD + 0.3
V
–10
10
mA
Input current to any pin except supply pins
Maximum virtual junction temperature, TJ
150
°C
Operating ambient temperature, TOA
–40
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per JEDEC standard 22, test method A114C.01 (1)
±3000
Charged-device model (CDM), per JEDEC standard 22, test method
C101 (2)
±1500
Machine model (MM), per JEDEC standard 22, test method A115A
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
TA
Operating ambient temperature
–40
105
°C
AVDD
High-side (analog) supply voltage
4.5
5
5.5
V
DVDD
Controller-side (digital) supply voltage
2.7
3.3
5.5
V
6.4 Thermal Information
AMC1204, AMC1204B
THERMAL METRIC
(1)
DW (SOIC)
DWV (SOIC)
16 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
78.5
106.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
41.3
53.6
°C/W
RθJB
Junction-to-board thermal resistance
50.2
60.3
°C/W
ψJT
Junction-to-top characterization parameter
11.5
18.5
°C/W
ψJB
Junction-to-board characterization parameter
41.2
58.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
All minimum/maximum specifications at TA = –40°C to 105°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.7 V to 5.5 V, VINP = –250
mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
16
Bits
DC ACCURACY
TA = –40°C to 85°C
–8
±2
8
LSB
TA = –40°C to 105°C
–16
±5
16
LSB
1
LSB
INL
Integral linearity error (1)
DNL
Differential nonlinearity
–1
VOS
Offset error (2)
–1
±0.1
1
TCVOS
Offset error thermal drift
–3.5
±1
3.5
GERR
Gain error (2)
–2%
±0.5%
2%
TCGERR
Gain error thermal drift
PSRR
Power-supply rejection ratio
mV
μV/°C
±30
ppm/°C
79
dB
ANALOG INPUTS
FSR
Full-scale differential voltage input range
VINP – VINN
±320
mV
Specified FSR
–250
250
mV
VCM
Operating common-mode signal (3)
–160
AVDD
mV
CI
Input capacitance to AGND
CID
Differential input capacitance
RID
Differential input resistance
IIL
Input leakage current
CMTI
Common-mode transient immunity
CMRR
Common-mode rejection ratio
VINP or VINN
7
pF
3.5
pF
12.5
kΩ
VINP – VINN = ±250 mV
–10
10
μA
VINP – VINN = ±320 mV
–50
50
μA
15
kV/μs
VIN from 0 V to 5 V at 0 Hz
108
dB
VIN from 0 V to 5 V at 100 kHz
114
dB
EXTERNAL CLOCK
tCLKIN
Clock period
fCLKIN
Input clock frequency
DutyCLKIN
Duty cycle
45.5
50
200
ns
5
20
22
MHz
5 MHz ≤ fCLKIN < 20 MHz
40%
50%
60%
20 MHz ≤ fCLKIN ≤ 22 MHz
45%
50%
55%
fIN = 1kHz, TA = –40°C to 85°C
78
87
dB
fIN = 1kHz, TA = –40°C to 105°C
70
87
dB
fIN = 1kHz, TA = –40°C to 85°C
84
88
dB
fIN = 1kHz, TA = –40°C to 105°C
83
88
AC ACCURACY
SINAD
SNR
Signal-to-noise + distortion
Signal-to-noise ratio
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range
dB
fIN = 1kHz, TA = –40°C to 85°C
–96
–80
dB
fIN = 1kHz, TA = –40°C to 105°C
–96
–70
dB
fIN = 1kHz, TA = –40°C to 85°C
82
96
dB
fIN = 1kHz, TA = –40°C to 105°C
72
96
dB
DIGITAL INPUTS (3)
IIN
Input current
CIN
Input capacitance
VIN = DVDD to DGND
–10
10
5
CMOS logic family
μA
pF
CMOS with Schmitt-trigger
VIH
High-level input voltage
DVDD = 4.5V to 5.5V
0.7DVDD
DVDD + 0.3
V
VIL
Low-level input voltage
DVDD = 4.5V to 5.5V
–0.3
0.3DVDD
V
DVDD + 0.3
V
LVCMOS logic family
VIH
(1)
(2)
(3)
6
High-level input voltage
LVCMOS
DVDD = 2.7 V to 3.6 V
2
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified 500-mV input range.
Maximum values, including temperature drift, are ensured over the full specified temperature range.
Ensured by design.
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Electrical Characteristics (continued)
All minimum/maximum specifications at TA = –40°C to 105°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.7 V to 5.5 V, VINP = –250
mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
VIL
TEST CONDITIONS
Low-level input voltage
MIN
DVDD = 2.7 V to 3.6 V
TYP
MAX
–0.3
UNIT
0.8
V
DIGITAL OUTPUTS (3)
COUT
Output capacitance
CLOAD
Load capacitance
5
CMOS logic family
High-level output voltage
DVDD = 4.5 V, IOH = –100 µA
VOL
Low-level output voltage
DVDD = 4.5 V, IOL = 100 µA
4.4
V
0.5
LVCMOS logic family
V
LVCMOS
High-level output voltage
VOL
pF
CMOS
VOH
VOH
pF
30
Low-level output voltage
IOH = 20 µA
DVDD – 0.1
V
IOH = –4 mA,
2.7 V ≤ DVDD ≤ 3.6 V
DVDD – 0.4
V
IOH = –4 mA,
4.5 V ≤ DVDD ≤ 5.5 V
DVDD – 0.8
V
IOL = 20 µA
0.1
V
IOL = 4 mA
0.4
V
V
POWER SUPPLY
AVDD
High-side supply voltage
4.5
5
5.5
DVDD
Controller-side supply voltage
2.7
3.3
5.5
V
IAVDD
High-side supply current
4.5 V ≤ AVDD ≤ 5.5 V
11
16
mA
IDVDD
Controller-side supply current
2.7 V ≤ DVDD ≤ 3.6 V
2
4
mA
PD
Power dissipation
4.5V ≤ DVDD ≤ 5.5 V
AVDD = 5.5 V, DVDD = 3.6 V
2.8
5
mA
61.6
102.4
mW
6.6 Timing Requirements
Over recommended ranges of supply voltage and operating free-air temperature, unless otherwise noted. (See Figure 1)
MIN
NOM
MAX
UNIT
45.5
50
200
ns
CLKIN clock high time
20
25
120
ns
tLOW
CLKIN clock low time
20
25
120
ns
tD
Delayed falling edge of CLKIN to DATA valid
15
ns
tCLK
CLKIN clock period
tHIGH
2
tCLK
tHIGH
CLKIN
tD
tLOW
DATA
Figure 1. Modulator Output Timing
6.7 Regulatory Information
VDE/IEC
CSA
UL
Certified according to VDE V 0884-10
Approved under CSA component
acceptance notice
Recognized under 1577 component
recognition program
Certificate number: 40016131
File number: 2350550
File number: E181974
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6.8 IEC Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A
failure of the I/O circuitry can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient
power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
The safety-limiting constraint is the operating virtual junction temperature range specified in the Absolute Maximum Ratings
table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware
determine the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of
a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and
is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then
the ambient temperature plus the power times the junction-to-air thermal resistance.
PARAMETER
IS
Safety input, output, or supply current
TC
Maximum case temperature
TEST CONDITIONS
MIN
TYP
MAX
θJA = 78.5°C/W, VI = 5.5 V,
TJ = 150°C, TA = 25°C
UNIT
10
mA
150
°C
6.9 IEC 61000-4-5 Ratings
PARAMETER
VIOSM
Surge immunity
TEST CONDITIONS
1.2/50-μs voltage surge and 8/20-μs current surge
VALUE
UNIT
±6000
V
6.10 IEC 60664-1 Ratings
PARAMETER
Basic isolation group
Installation classification
8
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TEST CONDITIONS
SPECIFICATION
Material group
II
Rated mains voltage ≤ 150VRMS
I-IV
Rated mains voltage < 300VRMS
I-IV
Rated mains voltage < 400VRMS
I-III
Rated mains voltage < 600VRMS
I-III
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6.11 Isolation Characteristics
PARAMETER
TEST CONDITIONS
VIORM
Maximum working insulation voltage
VPD(t)
Partial discharge test voltage
VIOTM
Transient overvoltage
RS
Isolation resistance
PD
Pollution degree
AMC1204
AMC1204B
UNIT
1200
1200
VPEAK
t = 1 s (100% production test),
partial discharge < 5 pC
2250
2250
VPEAK
t = 60 s (qualification test)
4000
4250
VPEAK
t = 1 s (100% production test)
4800
5100
VPEAK
VIO = 500 V at TS
> 109
> 109
Ω
2
2
Degrees
6.12 Package Characteristics
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
Minimum air gap (clearance)
Shortest terminal to terminal
distance through air
DWV package
Minimum external tracking
(creepage)
DWV package
L(I02)
Shortest terminal to terminal
distance across the package
surface
CTI
Tracking resistance
(comparative tracking index)
DIN IEC 60112/VDE 0303 part 1
> 400
V
Minimum internal gap
(internal clearance)
Distance through the insulation
0.014
mm
L(I01)
RIO
Isolation resistance
DW package
DW package
8
mm
7.9
mm
8
mm
7.9
mm
Input to output, VIO = 500 V, all pins on each side of
the barrier tied together to create a two-terminal
device, TA < 85°C
> 1012
Ω
Input to output, VIO = 500 V,
100°C ≤ TA < TA max
> 1011
Ω
CIO
Barrier capacitance input to
output
VI = 0.8 VPP at 1 MHz
1.2
pF
CI
Input capacitance to ground
VI = 0.8 VPP at 1 MHz
3
pF
(1)
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of a specific
application. Care should be taken to maintain the creepage and clearance distance of the board design to ensure that the mounting
pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal
according to the measurement techniques shown in the TI Isolation Glossary. Techniques such as inserting grooves, ribs, or both on the
PCB are used to help increase these specifications.
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6.13 Typical Characteristics
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
8
7
5
INL (LSB)
INL (LSB)
6
4
3
2
1
0
−250 −200 −150 −100 −50
0
50 100
Input Signal Amplitude (mV)
150
200
250
16
14
12
10
8
6
4
2
0
−2
−4
−6
−8
−10
−12
−14
−16
−40 −25 −10
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0
−0.2
−0.4
−0.4
−0.8
−1
−40 −25 −10
5.5
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0
−0.2
−0.4
10
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−0.4
−0.8
Figure 6. Offset Error vs Clock Frequency
95
0
−0.6
20
80
−0.2
−0.8
15
Clock Freuency (MHz)
20 35 50 65
Temperature (°C)
0.2
−0.6
10
5
Figure 5. Offset Error vs Temperature
1
Offset Error (mV)
Offset Error (mV)
Figure 4. Offset Error vs Analog Supply Voltage
1
5
110 125
−0.2
−0.6
−1
95
0
−0.8
5
AVDD (V)
80
0.2
−0.6
−1
4.5
20 35 50 65
Temperature (°C)
Figure 3. Integral Nonlinearity vs Temperature
Offset Error (mV)
Offset Error (mV)
Figure 2. Integral Nonlinearity vs Input Signal Amplitude
5
25
−1
40
45
50
Clock Duty Cycle (%)
55
60
Figure 7. Offset Error vs Clock Duty Cycle
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Typical Characteristics (continued)
2
2
1.5
1.5
1
1
Gain Error (%)
Gain Error (%)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
0.5
0
−0.5
0.5
0
−0.5
−1
−1
−1.5
−1.5
−2
4.5
5
AVDD (V)
−2
−40 −25 −10
5.5
2
1.5
1.5
1
1
0.5
0
−0.5
−1.5
15
20
Clock Frequency (MHz)
110 125
−0.5
−1.5
10
95
0
−1
5
80
0.5
−1
−2
20 35 50 65
Temperature (°C)
Figure 9. Gain Error vs Temperature
2
Gain Error (%)
Gain Error (%)
Figure 8. Gain Error vs Analog Supply Voltage
5
−2
25
40
Figure 10. Gain Error vs Clock Frequency
45
50
Clock Duty Cycle (%)
55
60
Figure 11. Gain Error vs Clock Duty Cycle
100
140
130
Unfiltered
sinc3, OSR = 256
90
CMRR (dB)
PSRR (dB)
120
80
110
100
70
90
60
0.1
1
10
100
80
0.1
Frequency (kHz)
Figure 12. Power-Supply Rejection Ratio vs Frequency
1
10
100
Input Signal Frequency (kHz)
1000
Figure 13. Common-Mode Rejection Ratio vs Input Signal
Frequency
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Typical Characteristics (continued)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
100
100
SINAD
SNR
90
SINAD and SNR (dB)
SINAD and SNR (dB)
SINAD
SNR
80
70
60
4.5
5
AVDD (V)
90
80
70
60
−40 −25 −10
5.5
Figure 14. SINAD and SNR vs Analog Supply Voltage
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 15. SINAD and SNR vs Temperature
100
100
SINAD
SNR
SINAD
SNR
90
SINAD and SNR (dB)
SINAD & SNR (dB)
80
90
80
70
70
60
50
40
30
20
10
60
0.1
1
10
Input Signal Frequency (kHz)
0
0.1
100
Figure 16. SINAD and SNR vs Input Signal Frequency
100
SINAD
SNR
90
SINADand SNR (dB)
SINAD and SNR (dB)
SINAD
SNR
80
70
5
10
15
20
Clock Frequency (MHz)
Figure 18. SINAD and SNR vs Clock Frequency
12
1000
Figure 17. SINAD and SNR vs Input Signal Amplitude
100
60
1
10
100
Input Signal Amplitude (mVpp)
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25
90
80
70
60
40
45
50
Clock Duty Cycle (%)
55
60
Figure 19. SINAD and SNR vs Clock Duty Cycle
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Typical Characteristics (continued)
−60
−60
−70
−70
−80
−80
THD (dB)
THD (dB)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
−90
−90
−100
−100
−110
−110
−120
4.5
5
AVDD (V)
−120
−40 −25 −10
5.5
Figure 20. Total Harmonic Distortion vs Analog Supply
Voltage
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 21. Total Harmonic Distortion vs Temperature
−60
0
−10
−70
−20
−30
−40
THD (dB)
THD (dB)
−80
−90
−50
−60
−70
−100
−80
−110
−100
−90
−110
−120
0.1
1
10
Input Signal Frequency (kHz)
−120
0.1
100
−60
−60
−70
−70
−80
−80
−90
−90
−100
−100
−110
−110
−120
5
10
15
20
Clock Frequency (MHz)
25
Figure 24. Total Harmonic Distortion vs Clock Frequency
1000
Figure 23. Total Harmonic Distortion vs Input Signal
Amplitude
THD (dB)
THD (dB)
Figure 22. Total Harmonic Distortion vs Input Signal
Frequency
1
10
100
Input Signal Amplitude (mVpp)
−120
40
45
50
Clock Duty Cycle (%)
55
60
Figure 25. Total Harmonic Distortion vs Clock Duty Cycle
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Typical Characteristics (continued)
120
120
110
110
100
100
SFDR (dB)
SFDR (dB)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
90
90
80
80
70
70
60
4.5
5
AVDD (V)
60
−40 −25 −10
5.5
Figure 26. Spurious-Free Dynamic Range vs Analog Supply
Voltage
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 27. Spurious-Free Dynamic Range vs Temperature
120
120
110
110
100
90
80
SFDR (dB)
SFDR (dB)
100
90
80
70
60
50
40
30
70
20
10
60
0.1
1
10
Input Signal Frequency (kHz)
0
0.1
100
120
120
110
110
100
100
90
80
70
70
5
10
15
20
Clock Frequency (MHz)
25
Figure 30. Spurious-Free Dynamic Range vs Clock
Frequency
14
90
80
60
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1000
Figure 29. Spurious-Free Dynamic Range vs Input Signal
Amplitude
SFDR (dB)
SFDR (dB)
Figure 28. Spurious-Free Dynamic Range vs Input Signal
Frequency
1
10
100
Input Signal Amplitude (mVpp)
60
40
45
50
Clock Duty Cycle (%)
55
60
Figure 31. Spurious-Free Dynamic Range vs Clock Duty
Cycle
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Typical Characteristics (continued)
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
5
10
15
20
25
30
35
40
0
5
10
15
Frequency (kHz)
16
16
14
14
12
12
10
10
8
6
2
2
5
AVDD (V)
0
−40 −25 −10
5.5
40
16
14
14
12
12
10
8
6
95
110 125
6
2
2
Figure 36. Analog Supply Current vs Clock Frequency
80
8
4
25
20 35 50 65
Temperature (°C)
10
4
15
20
Clock Frequency (MHz)
5
Figure 35. Analog Supply Current vs Temperature
16
IDVDD (mA)
IAVDD (mA)
Figure 34. Analog Supply Current vs Analog Supply Voltage
10
35
6
4
5
30
8
4
0
25
Figure 33. Frequency Spectrum (4096 Point FFT, fIN = 5 kHz,
0.56 VPP)
IAVDD (mV)
IAVDD (mA)
Figure 32. Frequency Spectrum (4096 Point FFT, fIN = 1 kHz,
0.56 VPP)
0
4.5
20
Frequency (kHz)
0
2.7
3
3.3
3.6
DVDD (V)
Figure 37. Digital Supply Current vs Digital Supply Voltage
(3 V)
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Typical Characteristics (continued)
16
16
14
14
12
12
IDVDD (mA)
IDVDD (mA)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
10
8
6
10
8
6
4
4
2
2
0
4.5
5
DVDD (V)
5.5
Figure 38. Digital Supply Current vs Digital Supply Voltage
(5 V)
DVDD = 3.3V
DVDD = 5V
0
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 39. Digital Supply Current vs Temperature
16
DVDD = 3.3V
DVDD = 5V
14
IDVDD (mA)
12
10
8
6
4
2
0
5
10
15
20
Clock Frequency (MHz)
25
Figure 40. Digital Supply Current vs Clock Frequency
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7 Detailed Description
7.1 Overview
The AMC1204 and AMC1204B are single-channel, second-order, delta-sigma (ΔΣ) modulators designed for
medium- to high-resolution analog-to-digital conversions. The isolated output of the converter (DATA) provides a
stream of digital ones and zeros accurately representing the analog input voltage over time. The time average of
this serial output is proportional to the analog input voltage.
Functional Block Diagram shows a detailed block diagram of the AMC1204 and AMC1204B. The analog input
range is tailored to directly accommodate the voltage drop across a shunt resistor used for current sensing. The
SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity as described in the
application report ISO72x Digital Isolator Magnetic-Field Immunity (SLLA181A). The external clock input
simplifies the synchronization of multiple current sense channels on system level. The extended frequency range
of up to 20 MHz supports higher performance levels compared to the other solutions available on the market.
7.2 Functional Block Diagram
Isolation Barrier
2nd-Order
DS Modulator
VINN
+
Interface Circuit
VINP
VREF
+
3-State
Output
Buffer
DATA
-
POR
+
Buffer
-
2.5V
VREF
+
VREF
CLKIN
-
Figure 41. Detailed Block Diagram
7.3 Feature Description
7.3.1 Analog Input
The differential analog input of the AMC1204 and AMC1204B is implemented with a switched-capacitor circuit.
The AMC1204 and AMC1204B measure the differential input signal VIN = (VINP – VINN) against the internal
reference of 2.5 V using internal capacitors that are continuously charged and discharged. Figure 42 shows the
simplified schematic of the AMC1204 and AMC1204B input circuitry; the right side of Figure 42 illustrates the
input circuitry with the capacitors and switches replaced by an equivalent circuit.
In Figure 42, the S1 switches close during the input sampling phase. With the S1 switches closed, CDIFF charges
to the voltage difference across VINP and VINN. For the discharge phase, both S1 switches open first and then
both S2 switches close. CDIFF discharges approximately to AGND + 0.8 V during this phase. This two-phase
sample/discharge cycle repeats with a period of tCLKIN = 1/fCLKIN. fCLKIN is the operating frequency of the
modulator. The capacitors CIP and CIN are of parasitic nature and caused by bonding wires and the internal ESD
protection structure.
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Feature Description (continued)
AVDD
AGND
AGND
CIP = 3pF
3pF
200W
VINP
S1
Equivalent
Circuit
AGND + 0.8V
S2
VINP
REFF = 12.5kW
CDIFF = 4pF
200W
S1
S2
VINN
VINN
AGND + 0.8V
3pF
CIN = 3pF
AGND
REFF =
AGND
1
fCLKIN ´ CDIFF
AGND
(fCLKIN = 20MHz)
Figure 42. Equivalent Analog Input Circuit
There are two restrictions on the analog input signals VINP and VINN. First, if the input voltage exceeds the
range AGND – 0.5 V to AVDD + 0.3 V, the input current must be limited to 10 mA because the input protection
diodes on the front end of the converter begin to turn on. In addition, the linearity and the noise performance of
the device are ensured only when the differential analog input voltage remains within ±250 mV.
7.3.2 Modulator
The modulator topology of the AMC1204 and AMC1204B is fundamentally a second-order, switched-capacitor,
ΔΣ modulator, such as the one conceptualized in Figure 43. The analog input voltage (X(t)) and the output of the
1-bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage (X2) at the input of the first
integrator or modulator stage. The output of the first integrator is further differentiated with the DAC output; the
resulting voltage (X3) feeds the input of the second integrator stage. When the value of the integrated signal (X4)
at the output of the second stage equals the comparator reference voltage, the output of the comparator
switches from high to low, or vice versa, depending on its previous state. In this case, the 1-bit DAC responds on
the next clock pulse by changing its analog output voltage (X6), causing the integrators to progress in the
opposite direction, while forcing the value of the integrator output to track the average of the input.
fCLK
X(t)
X2
Integrator 1
X3
Integrator 2
X4
DATA
fS
VREF
Comparator
X6
DAC
Figure 43. Block Diagram Of A Second-Order Modulator
The modulator shifts the quantization noise to high frequencies, as shown in Figure 44; therefore, a low-pass
digital filter should be used at the output of the device to increase the overall performance. This filter is also used
to convert from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate
(decimation). A digital signal processor (DSP), microcontroller (µC), or field programmable gate array (FPGA)
can be used to implement the filter.
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Feature Description (continued)
TI's microcontroller family TMS320F28x7x offers a suitable programmable, hardwired filter structure termed a
sigma-delta filter module (SDFM) optimized for usage with the AMC1204, AMC1304 and AMC1305 devices.
Also, the SD24_B converters on the MSP430F677x microcontrollers offer a path to directly access the integrated
sinc-filters, thus offering a system-level solution for multichannel isolated current sensing. Another option is to
use a suitable application-specific device such as the AMC1210, a four-channel digital sinc-filter.
0
Magnitude (dB)
-20
-40
-60
-80
-100
-120
-140
10
100
1k
10k
100k
1G
10G
Frequency (Hz)
Figure 44. Quantization Noise Shaping
7.3.3 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time and
low 50% of the time. A differential input of 250 mV produces a stream of ones and zeros that are high 89.06% of
the time. A differential input of –250 mV produces a stream of ones and zeros that are high 10.94% of the time.
This is also the specified linear input range of the modulator with the performance as specified in this data sheet.
The range between 250 mV and 320 mV (absolute values) is the non-linear range of the modulator. The output
of the modulator clips with a stream of only zeros with an input less than or equal to –320 mV or with a stream of
only ones with an input greater than or equal to 320 mV. The input voltage versus the output modulator signal is
shown in Figure 45.
The system clock of the AMC1204 and AMC1204B is typically 20 MHz and is provided externally at the CLKIN
pin. The data are synchronously provided at 20 MHz at the DATA output pin. The data are changing at the falling
edge of CLKIN; for more details see the Timing Requirements section.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 45. Analog Input Versus Amc1204 Modulator Output
7.4 Device Functional Modes
The AMC1204 is operational when the power supplies AVDD and DVDD are applied as specified in the
Recommended Operating Conditions section.
The AMC1204 has no additional functional modes.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Digital Filter Usage
The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort
and hardware, is a sinc3-type filter, as shown in Equation 1:
3
H(z) =
1 - z-OSR
1 - z-1
(1)
This filter provides the best output performance at the lowest hardware size (count of digital gates). For an
oversampling rate (OSR) in the range of 16 to 256, this filter is a good choice. All the characterization in this
document is also done with a sinc3 filter with OSR = 256 and an output word width of 16 bits.
In a sinc3 filter response (shown in Figure 46 and Figure 47), the location of the first notch occurs at the
frequency of output data rate fDATA = fCLK/OSR. The –3-dB point is located at half the Nyquist frequency or
fDATA/4. For some applications, it may be necessary to use another filter type with different frequency response.
Performance can be improved, for example, by using a cascaded filter structure. The first decimation stage could
be built of a sinc3 filter with a low OSR and the second stage using a high-order filter.
0
30k
fDATA = 20MHz/64 = 312.5kHz
-3dB: 81.9kHz
OSR = 64
-10
fMOD = 20MHz
OSR = 64
FSR = 32768
ENOB = 12 Bits
Settling Time =
3 ´ 1/fDATA = 9.6ms
25k
Output Code
Gain (dB)
-20
-30
-40
-50
20k
15k
10k
-60
5k
-70
0
-80
0
200
400
600
800 1000
Frequency (kHz)
1200
1400
1600
Figure 46. Frequency Response Of The Sinc3 Filter
0
5
10
15
20
25
30
Number of Output Clocks
35
40
Figure 47. Pole Response Of The Sinc3 Filter
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.
Figure 49 illustrates the ENOB of the AMC1204 and AMC1204B with different oversampling ratios. In this data
sheet, this number is calculated from SNR using Equation 2:
SNR = 1.76dB + 6.02dB ´ ENOB
(2)
An example code for an implementation of a sinc3 filter in an FPGA follows. For more information, see the
application note, Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control
Applications, (SBAA094), available for download at www.ti.com.
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Application Information (continued)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FLT is
port(RESN, MOUT, MCLK, CNR : in std_logic;
CN5 : out std_logic_vector(23 downto 0));
end FLT;
architecture RTL of FLT is
signal DN0, DN1, DN3, DN5 : std_logic_vector(23 downto 0);
signal CN1, CN2, CN3, CN4 : std_logic_vector(23 downto 0);
signal DELTA1 : std_logic_vector(23 downto 0);
begin
process(MCLK, RESn)
begin
if RESn = '0' then
DELTA1 <= (others => '0');
elsif MCLK'event and MCLK = '1' then
if MOUT = '1' then
DELTA1 <= DELTA1 + 1;
end if;
end if;
end process;
process(RESN, MCLK)
begin
if RESN = '0' then
CN1 <= (others => '0');
CN2 <= (others => '0');
elsif MCLK'event and MCLK = '1' then
CN1 <= CN1 + DELTA1;
CN2 <= CN2 + CN1;
end if;
end process;
process(RESN, CNR)
begin
if RESN = '0' then
DN0 <= (others =>
DN1 <= (others =>
DN3 <= (others =>
DN5 <= (others =>
elsif CNR'event and
DN0 <= CN2;
DN1 <= DN0;
DN3 <= CN3;
DN5 <= CN4;
end if;
end process;
'0');
'0');
'0');
'0');
CNR = '1' then
CN3 <= DN0 - DN1;
CN4 <= CN3 - DN3;
CN5 <= CN4 - DN5;
end RTL;
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8.2 Typical Application
8.2.1 Frequency Inverter Application
Because of their high AC and DC performance, isolated ΔΣ modulators are being widely used in new generation
frequency inverter designs. Frequency inverters are critical parts of industrial motor drives, photovoltaic inverters
(string and central inverters), uninterruptible power supplies (UPS), electrical and hybrid vehicles, and other
industrial applications. The input structure of the AMC1204 is optimized for use with low-impedance shunt
resistors and is therefore tailored for isolated current sensing using shunts.
DC link
Gate Driver
Gate Driver
Gate Driver
RSHUNT
RSHUNT
RSHUNT
Gate Driver
Gate Driver
Gate Driver
AMC1204
5.0 V
AMC1204
5.0 V
AMC1204
5.0 V
AMC1204
3.3 V
5.0 V
3.3 V
TMS320F2837x
AVDD
DVDD
AINP
DOUT
SD-D1
AINN
CLKIN
SD-C1
AGND
DGND
3.3 V
AVDD
DVDD
AINP
DOUT
SD-D2
AINN
CLKIN
SD-C2
AGND
DGND
3.3 V
AVDD
DVDD
AVDD
DVDD
AINP
DOUT
AINP
DOUT
SD-D3
AINN
CLKIN
AINN
CLKIN
SD-C3
AGND
DGND
AGND
DGND
SD-D4
SD-C4
Figure 48. AMC1204 in a Frequency Inverter Application
8.2.1.1 Design Requirements
Figure 48 shows a diagram of the AMC1204 in a typical frequency inverter. When the inverter stage is part of a
motor drive system, measurement of the motor phase current is done via the shunt resistors (RSHUNT).
Depending on the system design, either all three or only two phase currents are sensed.
In this example, an additional AMC1204 is used for isolated sensing of the DC link voltage. This high DC link
voltage is reduced using a high-impedance resistive divider before being sensed by the AMC1204 across a
smaller resistor. It is important to consider that the value of the resistor in the voltage divider can potentially
degrade the performance of the measurement. Such phenomenon is described in the Isolated Voltage Sensing
section.
8.2.1.2 Detailed Design Procedure
For modulator output bit-stream filtering, TI recommends a device from TI's TMS320F28x7x family of MCUs. This
family supports up to eight channels of dedicated hardwired filter structures that significantly simplify system level
design by offering two filtering paths per channel: one providing high accuracy results for the control loop and
one fast response path for overcurrent detection.
22
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AMC1204, AMC1204B
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SBAS512E – APRIL 2011 – REVISED SEPTEMBER 2015
Typical Application (continued)
8.2.1.3 Application Curves
In motor control applications, a very fast response time for overcurrent detection is required. The time for fully
settling the filter in case of a step-signal at the input of the modulator depends on its order; that is, a sinc3 filter
requires three data updates for full settling (with fDATA = fCLK / OSR). Therefore, for overcurrent protection, filter
types other than sinc3 might be better choices. An alternative is, for example, the sinc2 filter. Figure 50 compares
the settling times of different filter orders.
Sincfast is a modified sinc2 filter whose transfer function follows Equation 3.
2
H(z) =
1 - z-OSR
(1 + z-2OSR)
1 - z-1
16
(3)
16
sinc3
14
14
12
sinc2
ENOB (Bits)
ENOB (Bits)
12
sincfast
sinc3
sincfast
10
8
6
sinc
1
10
sinc2
8
6
sinc
4
4
2
2
0
1
0
1
10
100
1000
0
1
2
OSR
Figure 49. Measured Effective Number Of Bits Versus
Oversampling Ratio
3
4
5 6 7 8 9
Settling Time (ms)
10 11 12 13
Figure 50. Measured Effective Number of Bits Versus
Settling Time
In the case of a continuous signal fed into a sinc filter, the time delay for such signal corresponds to half of the
settling time shown in Figure 50.
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Typical Application (continued)
8.2.2 Example of a Resolver-Based Motor Control Analog Front End
Figure 51 shows an example of two AMC1204 and AMC1204B devices and one ADS1209 (a dual-channel, 10MHz, non-isolated modulator) connected to an AMC1210, building the entire analog front end of a resolver-based
motor control application.
For detailed information on the ADS1209 and AMC1210, visit the respective device product folders at
www.ti.com.
Resolver
Control Module
AMC1210
PWM1
Signal
Generator
PWM2
Filter Module 1
Comparator
Filter
IN1
CLK
CLK1
Sinc Filter/
Integrator
Input
Control
ADS1209
RST
Interrupt
Unit
INT
ACK
IN2
Time
Measurement
Filter
Module 2
Register
Map
CLK2
Current
Shunt
Resistor
Current
Shunt
Resistor
IN3
AMC1204,
AMC1204B
CLK3
IN4
AMC1204,
AMC1204B
CLK4
Interface
Module
Filter
Module 3
CS
ALE
RD
WR
M0
M1
AD0
AD7
Filter
Module 4
Figure 51. Example of a Resolver-Based Motor Control Analog Front End Schematic
8.2.3 Isolated Voltage Sensing
The AMC1204 is optimized for current-sensing applications using low-impedance shunts. However, the device
can also be used in isolated voltage-sensing applications if the impact of the (usually higher) impedance of the
resistor used in this case is considered. Figure 52 shows a simplified circuit typically used in high-voltage sensing
applications.
L1
R1
R2
RIN
L2
Figure 52. Voltage Measurement Application
24
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AMC1204, AMC1204B
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SBAS512E – APRIL 2011 – REVISED SEPTEMBER 2015
Typical Application (continued)
8.2.3.1
Design Requirements
In such applications, a resistor divider (R1 and R2) is used to match the relatively small input voltage range of the
AMC device. R2 and the input resistance RIN of the AMC1204 also create a resistor divider resulting in additional
gain error. With the assumption that R1 and RIN have a considerably higher value than R2, use Equation 4 to
estimate the resulting total gain error.
R
GERRTOT = GERR + 2
RIN
where
•
GERR = the gain error of AMC device.
(4)
9 Power Supply Recommendations
In a typical frequency inverter application, the high-side power supply (AVDD) for the AMC1204 and AMC1204B
is derived from the power supply of the upper gate driver. For lowest cost, a Zener diode can be used to limit the
voltage to 5 V ±10%. TI recommends a decoupling capacitor of 0.1 µF for filtering this power-supply path. This
capacitor (C1 in Figure 53) should be placed as close as possible to the AVDD pin for best performance. If better
filtering is required, an additional 1-µF to 10-µF capacitor can be used. The floating ground reference AGND is
derived from the end of the shunt resistor, which is connected to the negative input (VINN) of the AMC1204 and
AMC1204B. If a four-terminal shunt is used, the inputs of AMC1204 and AMC1204B are connected to the inner
leads, while AGND is connected to one of the outer leads of the shunt. Both digital signals, CLKIN and DATA,
can be directly connected to a digital filter.
HV+
Floating
Power Supply
Gated
Drive
Circuit
Isolation
Barrier
R1
AMC1204
AMC1204B
D1
5.1V
R3
12W
RSHUNT
To Load
Power
Supply
AVDD
DVDD
VINP
DATA
VINN
CLKIN
AGND
DGND
C1(1)
0.1mF
R2
12W
C2
330pF
C3
10pF
(optional)
C4
10pF
(optional)
Gated
Drive
Circuit
HV-
(1)
Place C1 close to the AMC1204 and AMC1204B.
Figure 53. Zener-Diode-Based High-Side Power Supply
For better performance, the differential input signal is filtered using RC filters (components R2, R3, and C2).
Optionally, C3 and C4 can be used to reduce charge dumping from the inputs. In this case, care should be taken
when choosing the quality of these capacitors: any mismatch in the capacitor values can cause a common-mode
error at the input of the modulator.
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AMC1204, AMC1204B
SBAS512E – APRIL 2011 – REVISED SEPTEMBER 2015
www.ti.com
10 Layout
10.1 Layout Guidelines
•
•
•
Place the decoupling capacitors for AVDD and DVDD as close as possible to the AMC1204.
Ensure that the traces that connect the shunt resistor to the RC filter on the VINP terminal are symmetrical to
and have the same length as the traces connecting to the VINN terminal.
The top and bottom PCB layers underneath the AMC1204 must be kept free of any conductive materials in
order to comply with the creepage and clearance distances shown in the Package Characteristics section.
10.2 Layout Example
Figure 54 shows the recommended layout and placement of the decoupling capacitors and other components
required by the AMC1204 and AMC1204B.
Top View
Clearance Area
Keep Free of Any Conductive Materials
To
Shunt
12
SMD 0603 330pF
SMD
12
0603
SMD 0603
0.1F
SMD
1206
AVDD
DGND
VINP
NC
VINN
DVDD
AGND
NC
LEGEND
CLKIN
AMC1204,
AMC1204B
0.1 F
SMD
0603
From microcontroller
or system CLK
NC
NC
DATA
NC
NC
AGND
DGND
To microcontroller
or filter IC
Top layer; copper pour and traces
High-Side Area
Controller-Side Area
Via
Figure 54. Recommended Layout
26
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AMC1204, AMC1204B
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SBAS512E – APRIL 2011 – REVISED SEPTEMBER 2015
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• ISO72x Digital Isolator Magnetic-Field Immunity, SLLA181
• Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications,
SBAA094
• Isolation Glossary, SLLA353
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
AMC1204
Click here
Click here
Click here
Click here
Click here
AMC1204B
Click here
Click here
Click here
Click here
Click here
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: AMC1204 AMC1204B
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27
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
AMC1204BDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1204B
AMC1204BDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1204B
AMC1204BDWV
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
AMC1204B
AMC1204BDWVR
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
AMC1204B
AMC1204DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1204
AMC1204DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1204
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jan-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AMC1204 :
• Automotive: AMC1204-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
AMC1204BDWR
SOIC
DW
AMC1204BDWVR
SOIC
AMC1204DWR
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
DWV
8
1000
330.0
16.4
12.05
6.15
3.3
16.0
16.0
Q1
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AMC1204BDWR
SOIC
DW
16
2000
367.0
367.0
38.0
AMC1204BDWVR
SOIC
DWV
8
1000
367.0
367.0
38.0
AMC1204DWR
SOIC
DW
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
SCALE 2.000
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
3.81
5.95
5.75
NOTE 3
4
5
0.51
0.31
0.25
C A
8X
A
7.6
7.4
NOTE 4
B
B
2.8 MAX
0.33
TYP
0.13
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0 -8
0.46
0.36
1.0
0.5
(2)
DETAIL A
TYPICAL
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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