ON MC74VHC74 Dual d−type flip−flop with set and reset Datasheet

MC74VHC74
Dual D−Type Flip−Flop
with Set and Reset
The MC74VHC74 is an advanced high speed CMOS D−type
flip−flop fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output
during the positive going transition of the Clock pulse.
Reset (RD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
VHC74G
AWLYWW
1
14
Features
•
•
•
•
•
•
•
•
•
•
•
•
High Speed: fmax = 170MHz (Typ) at VCC = 5V
Low Power Dissipation: ICC = 2mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 128 FETs or 32 Equivalent Gates
Pb−Free Packages are Available*
RD1
D1
CP1
SD1
1
RD2
5
2
6
3
Q1
Q1
4
D2
CP2
SD2
VHC
74
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
1
14
SOEIAJ−14
M SUFFIX
CASE 965
1
VHC74
ALYWG
1
A
= Assembly Location
WL, L = Wafer Lot
Y, YY = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
13
FUNCTION TABLE
12
9
11
8
Inputs
Q2
Q2
10
Figure 1. LOGIC DIAGRAM
Outputs
SD
RD
CP
D
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
L
H
Q
Q
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
*Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable
if Set and Reset go high simultaneously.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 5
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
MC74VHC74/D
MC74VHC74
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MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
RD1
1
14
VCC
Min
Max
Unit
D1
2
13
RD2
2.0
5.5
V
CP1
3
12
D2
SD1
4
11
CP2
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
Q1
5
10
SD2
Q1
6
9
Q2
GND
7
8
Q2
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
− 40
+ 85
_C
0
0
100
20
ns/V
VCC = 3.3V ±0.3V
VCC =5.0V ±0.5V
Figure 2. PIN ASSIGNMENT
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
TA = 25°C
VCC
V
Min
1.50
VCC x 0.7
VIH
Minimum High−Level
Input Voltage
2.0
3.0 to 5.5
VIL
Maximum Low−Level
Input Voltage
2.0
3.0 to 5.5
VOH
Minimum High−Level
Output Voltage
VOL
Maximum Low−Level
Output Voltage
Typ
TA = − 40 to 85°C
Max
Min
1.50
VCC x 0.7
0.50
VCC x 0.3
Vin = VIH or VIL
IOH = − 50mA
2.0
3.0
4.5
1.9
2.9
4.4
Vin = VIH or VIL
IOH = − 4mA
IOH = − 8mA
3.0
4.5
2.58
3.94
Vin = VIH or VIL
IOL = 50mA
2.0
3.0
4.5
Vin = VIH or VIL
IOL = 4mA
IOL = 8mA
Max
2.0
3.0
4.5
Unit
V
0.50
VCC x 0.3
V
V
1.9
2.9
4.4
2.48
3.80
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
V
Iin
Maximum Input
Leakage Current
Vin = 5.5V or GND
0 to 5.5
± 0.1
± 1.0
mA
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
2.0
20.0
mA
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2
MC74VHC74
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
tPLH,
tPHL
Maximum Propagation Delay,
CP to Q or Q
tPLH,
tPHL
fmax
Cin
Test Conditions
Maximum Propagation Delay,
SD or RD to Q or Q
Maximum Clock Frequency
(50% Duty Cycle)
Min
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
ns
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
6.7
9.2
11.9
15.4
1.0
1.0
14.0
17.5
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
4.6
6.1
7.3
9.3
1.0
1.0
8.5
10.5
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
7.6
10.1
12.3
15.8
1.0
1.0
14.5
18.0
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
4.8
6.3
7.7
9.7
1.0
1.0
9.0
11.0
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
80
50
125
75
70
45
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
130
90
170
115
110
75
Maximum Input Capacitance
4
ns
MHz
10
10
pF
Typical @ 25°C, VCC = 5.0V
CPD
25
Power Dissipation Capacitance (Note 1)
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 2 (per flip−flop). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
TA = 25_C
TA = − 40 to
85_C
Unit
tw
Minimum Pulse Width, CP
3.3 ± 0.3
5.0 ± 0.5
6.0
5.0
7.0
5.0
ns
tw
Minimum Pulse Width, RD or SD
3.3 ± 0.3
5.0 ± 0.5
6.0
5.0
7.0
5.0
ns
tsu
Minimum Setup Time, D to CP
3.3 ± 0.3
5.0 ± 0.5
6.0
5.0
7.0
5.0
ns
th
Minimum Hold Time, D to CP
3.3 ± 0.3
5.0 ± 0.5
0.5
0.5
0.5
0.5
ns
Minimum Recovery Time, SD or RD to CP
3.3 ± 0.3
5.0 ± 0.5
5.0
3.0
5.0
3.0
ns
trec
ORDERING INFORMATION
Package
Shipping†
MC74VHC74DR2
SOIC−14
2500 Tape & Reel
MC74VHC74DR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
MC74VHC74DT
TSSOP−14*
96 Units / Rail
MC74VHC74DTG
TSSOP−14*
96 Units / Rail
MC74VHC74DTR2
TSSOP−14*
2500 Tape & Reel
MC74VHC74DTR2G
TSSOP−14*
2500 Tape & Reel
MC74VHC74MEL
SOEIAJ−14
2000 Tape & Reel
MC74VHC74MELG
SOEIAJ−14
(Pb−Free)
2000 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
MC74VHC74
tw
SD or RD
CP
VCC
50%
GND
Q or Q
1/fmax
Q or Q
GND
tPHL
tw
tPLH
VCC
50%
50% VCC
tPLH
tPHL
Q or Q
50% VCC
50% VCC
trec
Figure 3.
VCC
50%
CP
GND
Figure 4.
Switching Waveforms
TEST POINT
VALID
D
tsu
CP
OUTPUT
VCC
50%
th
50%
DEVICE
UNDER
TEST
GND
VCC
CL*
GND
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
INPUT
Figure 7. Input Equivalent Circuit
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4
MC74VHC74
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
B
M
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
SEATING
PLANE
T B
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE A
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
G
H
DETAIL E
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5
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
MC74VHC74
PACKAGE DIMENSIONS
SOEIAJ−14
M SUFFIX
CASE 965−01
ISSUE A
14
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.10 (0.004)
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
1.42
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−−
0.056
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MC74VHC74/D
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