ON NTP85N03G Power mosfet 85 amps, 28 volts nâ channel toâ 220 and d2pak Datasheet

NTP85N03, NTB85N03
Power MOSFET
85 Amps, 28 Volts
N−Channel TO−220 and D2PAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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85 AMPERES, 28 VOLTS
RDS(on) = 6.1 mW (Typ)
Features
• Pb−Free Packages are Available
N−Channel
D
Typical Applications
•
•
•
•
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
G
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
4
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
28
Vdc
Gate−to−Source Voltage − Continuous
VGS
"20
Vdc
4
1
Drain Current
− Continuous @ TC = 25°C
− Single Pulse (tp = 10 ms)
85*
190
Adc
Apk
PD
80
0.66
W
W/°C
Operating and Storage Temperature Range
TJ, Tstg
−55 to
+150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 28 Vdc, VGS = 10 Vdc, L = 5.0 mH,
IL(pk) = 17 A, RG = 25 W)
EAS
733
mJ
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Thermal Resistance,
− Junction−to−Case
− Junction−to−Ambient (Note 1)
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
ID
IDM
1
2
2
3
D2PAK
CASE 418AA
STYLE 2
TO−220AB
CASE 221A
STYLE 5
3
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
°C/W
RqJC
RqJA
1.55
70
TL
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
*Chip current capability limited by package.
1. When surface mounted to an FR4 board using 1 in pad size, (Cu Area 1.127 in2).
NTx
85N03G
AYWW
NTx85N03G
AYWW
1
Gate
3
Source
1
Gate
2
Drain
3
Source
2
Drain
NTx85N03
x
A
Y
WW
G
= Device Code
= B or P
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 2
1
Publication Order Number:
NTP85N03/D
NTP85N03, NTB85N03
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
28
−
30.6
25
−
−
−
−
−
−
1.0
10
−
−
±100
1.0
−
1.9
−3.8
3.0
−
−
−
−
6.1
9.2
7.0
6.8
−
−
gFS
−
20
−
mhos
pF
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 28 Vdc, VGS = 0 Vdc)
(VDS = 28 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage (Note 2)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 2)
(VGS = 10 Vdc, ID = 40 Adc)
(VGS = 4.5 Vdc, ID = 40 Adc)
(VGS = 10 Vdc, ID = 10 Adc)
RDS(on)
Forward Transconductance (Note 2) (VDS = 15 Vdc, ID = 10 Adc)
Vdc
mV/°C
mW
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 24 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Transfer Capacitance
Ciss
−
2150
−
Coss
−
680
−
Crss
−
260
−
td(on)
−
10
−
tr
−
22
−
td(off)
−
32
−
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
(VDD = 15 Vdc, ID = 15 Adc,
VGS = 10 Vdc, RG = 3.3 W)
Turn−Off Delay Time
Fall Time
Gate Charge
(VDS = 24 Vdc, ID = 40 Adc,
VGS = 4.5 Vdc) (Note 2)
ns
tf
−
30
−
QT
−
29
−
Q1
−
8.0
−
Q2
−
18
−
VSD
−
−
−
0.75
1.2
0.65
1.0
−
−
Vdc
trr
−
39
−
ns
ta
−
21
−
tb
−
18
−
QRR
−
0.043
−
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 2.3 Adc, VGS = 0 Vdc)
(IS = 40 Adc, VGS = 0 Vdc) (Note 2)
(IS = 2.3 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 2.3 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms) (Note 2)
Reverse Recovery Stored Charge
mC
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
Package
Shipping †
NTP85N03
TO−220AB
50 Units / Rail
NTP85N03G
TO−220AB
(Pb−Free)
50 Units / Rail
D2PAK
50 Units / Rail
NTB85N03G
D2PAK
(Pb−Free)
50 Units / Rail
NTB85N03T4
D2PAK
800 Units / Tape & Reel
NTB85N03T4G
D2PAK
800 Units / Tape & Reel
Device
NTB85N03
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTP85N03, NTB85N03
50
80
TJ = 25°C
VGS = 10 V
8V
40
6V
3.6 V
30
5V
4.5 V
20
3.4 V
4V
10
3.2 V
3V
2.8 V
VDS ≥ 10 V
70
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
3.8 V
60
50
40
TJ = 25°C
30
TJ = 100°C
20
10
0
TJ = −55°C
0
0
1
2
3
4
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
5
2
3
4
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.07
ID = 10 A
TJ = 25°C
0.06
0.05
0.04
0.03
0.02
0.01
0
0
2
4
6
8
10
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.015
TJ = 25°C
0.01
VGS = 4.5 V
0.005
0
VGS = 10 V
5
10
15
20
30
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
0.01
VGS = 0 V
ID = 40 A
VDS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
6
0.0075
0.005
TJ = 125°C
100
TJ = 100°C
10
0.0025
0
−50
1
−25
0
25
50
75
100
125
150
4
8
12
16
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
20
NTP85N03, NTB85N03
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
5000
VGS = 0
TJ = 25°C
C, CAPACITANCE (pF)
4500
4000
3500
3000
2500
Ciss
2000
1500
1000
Coss
500
Crss
0
−15
−10
−5
0
5
10
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
Figure 7. Capacitance Variation
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4
VGS, GATE−TO−SOURCE VOLTAGE (V)
12
36
QT
10
30
VDS
8
24
VGS
6
18
Qgs
Qgd
4
12
ID = 15
TJ = 25°C
2
0
0
5
10
15
20
6
0
30
25
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
t, TIME (ns)
NTP85N03, NTB85N03
1000
VDD = 24 V
ID = 20 A
VGS = 10 V
td(off)
tf
tr
100
td(on)
10
1
1
10
100
RG, GATE RESISTANCE (W)
Qg, TOTAL GATE CHARGE (nC)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
IS, SOURCE CURRENT (AMPS)
15
VGS = 0 V
TJ = 25°C
12
9
6
3
0
0.1
0.3
0.5
0.7
0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTP85N03, NTB85N03
PACKAGE DIMENSIONS
D2PAK
CASE 418AA−01
ISSUE O
C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
V
W
−B−
4
DIM
A
B
C
D
E
F
G
J
K
M
S
V
A
1
2
S
3
−T−
SEATING
PLANE
K
W
J
G
D 3 PL
0.13 (0.005)
T B
M
STYLE 2:
PIN 1.
2.
3.
4.
M
VARIABLE
CONFIGURATION
ZONE
U
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.036
0.045 0.055
0.310
−−−
0.100 BSC
0.018 0.025
0.090 0.110
0.280
−−−
0.575 0.625
0.045 0.055
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.92
1.14
1.40
7.87
−−−
2.54 BSC
0.46
0.64
2.29
2.79
7.11
−−−
14.60 15.88
1.14
1.40
NTP85N03, NTB85N03
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
−T−
B
SEATING
PLANE
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−− 0.080
STYLE 5:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
GATE
DRAIN
SOURCE
DRAIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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NTP85N03/D
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