CY7C1366C CY7C1367C PRELIMINARY 9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 225 MHz • Available speed grades are 225, 200 and 166 MHz • Registered inputs and outputs for pipelined operation •Optimal for performance (Double-Cycle deselect) —Depth expansion without wait state •3.3V –5% and +10% core power supply (VDD) • 2.5V / 3.3V I/O operation • Fast clock-to-output times — 2.8 ns (for 225-MHz device) The CY7C1366C/CY7C1367C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). — 3.0 ns (for 200-MHz device) — 3.5 ns (for 166-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Available in Lead-Free 100 TQFP,119 BGA and 165 fBGA packages • IEEE 1149.1 JTAG-Compatible Boundary Scan Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1366C/CY7C1367C operates from a +3.3V core power supply while all outputs operate with a +3.3V or a +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. • “ZZ” Sleep Mode Option Selection Guide 225 MHz 200 MHz 166 MHz Unit Maximum Access Time 2.8 3.0 3.5 ns Maximum Operating Current 250 220 180 mA Maximum CMOS Standby Current 30 30 30 mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3 is for TQFP and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable. Cypress Semiconductor Corporation Document #: 38-05542 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised October 5, 2004 CY7C1366C CY7C1367C PRELIMINARY 1 Logic Block Diagram – CY7C1366C (256K x 36) ADDRESS REGISTER A0,A1,A 2 A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP BWD DQD,DQPD BYTE WRITE REGISTER DQD,DQPD BYTE WRITE DRIVER BWC DQc,DQPC BYTE WRITE REGISTER DQc,DQPC BYTE WRITE DRIVER DQB,DQPB BYTE WRITE REGISTER DQB,DQPB BYTE WRITE DRIVER BWB GW CE1 CE2 CE3 OE ENABLE REGISTER SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQPA DQPB DQPC DQPD E DQA,DQPA BYTE WRITE DRIVER DQA,DQPA BYTE WRITE REGISTER BWA BWE MEMORY ARRAY INPUT REGISTERS PIPELINED ENABLE SLEEP ZZ CONTROL 2 Logic Block Diagram – CY7C1367C (512K x 18) A0, A1, A ADDRESS REGISTER 2 MODE ADV CLK A[1:0] Q1 BURST COUNTER AND LOGIC CLR Q0 ADSC ADSP BWB BWA BWE GW CE1 CE2 CE3 DQB , DQPB BYTE WRITE DRIVER DQB, DQPB BYTE WRITE REGISTER DQA, DQPA BYTE WRITE DRIVER DQA , DQPA BYTE WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs, DQPA DQPB E INPUT REGISTERS OE ZZ SLEEP CONTROL Document #: 38-05542 Rev. *A Page 2 of 27 CY7C1366C CY7C1367C PRELIMINARY Pin Configurations NC NC NC CY7C1367C (512K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC / 72M NC / 36M VSS VDD NC / 18M A A A A A A A A DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CY7C1366C (256K X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC / 72M NC / 36M VSS VDD NC / 18M A A A A A A A A DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-pin TQFP Pinout (3 Chip Enables) Document #: 38-05542 Rev. *A A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC Page 3 of 27 CY7C1366C CY7C1367C PRELIMINARY Pin Configurations (continued) 119-ball BGA (2 Chip Enable with JTAG) 1 CY7C1366C (256K x 36) 3 4 5 A A ADSP A VDDQ 2 A B C NC NC CE2 A A A ADSC VDD A A A A NC NC D E DQC DQC DQPC DQC VSS VSS NC CE1 VSS VSS DQPB DQB DQB DQB F VDDQ DQC VSS OE VSS DQB VDDQ G H J K DQC DQC VDDQ DQD DQC DQC VDD DQD BWC VSS NC VSS ADV BWB VSS NC VSS DQB DQB VDD DQA DQB DQB VDDQ DQA BWA VSS DQA DQA DQA VDDQ VSS DQA DQA GW VDD CLK NC 6 A 7 VDDQ L DQD DQD M VDDQ DQD BWD VSS N DQD DQD VSS BWE A1 P DQD DQPD VSS A0 VSS DQPA DQA R NC A MODE VDD NC A NC T U NC VDDQ NC TMS A TDI A TCK A TDO NC NC ZZ VDDQ CY7C1367C (512K x 18) 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC CE2 A A NC NC A A ADSC VDD A C A A NC D DQB NC VSS NC VSS DQPA NC E NC DQB VSS CE1 VSS NC DQA OE ADV VSS DQA VDDQ GW VDD VSS VSS NC NC DQA VDD DQA NC VDDQ CLK VSS NC DQA NC BWA VSS DQA NC NC VDDQ F VDDQ NC VSS G H J NC DQB VDDQ DQB NC VDD BWB VSS NC K NC DQB VSS L M DQB VDDQ NC DQB VSS VSS N DQB NC VSS BWE A1 VSS DQA NC P NC DQPB VSS A0 VSS NC DQA R T U NC NC VDDQ A A TMS MODE A TDI VDD NC TCK NC A TDO A A NC NC ZZ VDDQ Document #: 38-05542 Rev. *A Page 4 of 27 CY7C1366C CY7C1367C PRELIMINARY Pin Configurations (continued) 165-ball fBGA (3 Chip Enable) CY7C1366C (256K x 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC / 288M A CE1 BWC BWB CE3 BWE ADSC ADV A NC R NC A CE2 BWD BWA CLK GW A NC / 144M NC DQC VDDQ VSS VSS VSS VSS VSS VSS VDDQ VDDQ VSS VDD OE VSS VDD ADSP DQPC DQC VDDQ NC DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD DQB DQB DQC NC DQD DQC VSS DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS NC / 18M VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC / 72M A A TDI A1 TDO A A A A MODE NC / 36M A A TMS A0 TCK A A A A 7 8 9 10 11 A CY7C1367C (512K x 18) 1 2 A B C D E F G H J K L M N P NC / 288M A 3 4 5 6 NC CE3 A CE1 CE2 BWB NC NC BWA NC NC NC DQB VDDQ VSS VDD VSS VDDQ NC DQB VDDQ NC DQB VDDQ NC NC DQB DQB VSS NC VDDQ NC VDDQ DQB NC DQB DQB DQPB R CLK BWE GW ADSC OE ADV ADSP A VSS VSS VSS VSS VSS VDD VDDQ VSS VDDQ NC NC VDD VSS VSS VSS VDD VDDQ NC DQA VDD VSS VSS VSS VDD VDDQ NC DQA VDD VDD VDD VSS VSS ‘VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQA DQA ZZ NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC NC NC VDDQ VDDQ VDD VSS VSS NC VSS NC / 18M VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC NC NC / 72M A A TDI A1 TDO A A A A MODE NC / 36M A A TMS A0 TCK A A A A Document #: 38-05542 Rev. *A A NC / 144M DQPA DQA Page 5 of 27 PRELIMINARY CY7C1366C CY7C1367C Pin Definitions Name A0, A1, A I/O InputSynchronous Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2]are sampled active. A1: A0 are fed to the two-bit counter. BWA,BWB InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. BWC,BWD GW BWE CLK CE1 CE2 CE3[2] OE ADV ADSP ADSC ZZ DQs, DQPs VDD VSS VSSQ VDDQ MODE TDO InputSynchronous InputSynchronous InputClock InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction Synchronous with CE1 and CE3[2] to select/deselect the device.CE2 is sampled only when a new external address is loaded. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction Synchronous with CE1 and CE2 to select/deselect the device.Not connected for BGA. Where referenced, CE3[2] is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it Synchronous automatically increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. InputAddress Strobe from Controller, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a three-state condition. Power Supply Power supply inputs to the core of the device. Ground Ground for the core of the device. I/O Ground Ground for the I/O circuitry. I/O Power Supply Power supply for the I/O circuitry. InputSelects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static Static during device operation. Mode Pin has an internal pull-up. JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG Synchronous feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages. Document #: 38-05542 Rev. *A Page 6 of 27 PRELIMINARY CY7C1366C CY7C1367C Pin Definitions (continued) Name TDI TMS TCK NC I/O Description JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAGClock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be Clock connected to VSS. This pin is not available on TQFP packages. – No Connects. Not internally connected to the die. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1366C/CY7C1367C supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Selects CE1, CE2, CE3[2] and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tco if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. The CY7C1366C/CY7C1367C is a double-cycle deselect part. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately after the next clock rise. Document #: 38-05542 Rev. *A Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the write operation is controlled by BWE and BWX signals. The CY7C1366C/CY7C1367C provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1366C/CY7C1367C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQ are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1366C/CY7C1367C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so will three-state the output drivers. As a safety precaution, DQX are Page 7 of 27 CY7C1366C CY7C1367C PRELIMINARY automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1366C/CY7C1367C provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel® Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Both read and write burst operations are supported. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10 Partial Truth Table for Read/Write[5, 10] Function (CY7C1366C) Read Read Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write Bytes B, A Write Byte C – (DQC and DQPC) Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D – (DQD and DQPD) Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes Truth Table for Read/Write[5, 10] Function (CY7C1367C) Read Read Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write All Bytes Write All Bytes Document #: 38-05542 Rev. *A GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X GW BWE BWB BWA H H H H H L H L L L L X X H H L L X X H L H L X Page 8 of 27 CY7C1366C CY7C1367C PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) Test MODE SELECT (TMS) The CY7C1366C/CY7C1367C incorporates a serial boundary scan test access port (TAP)in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The CY7C1366C/CY7C1367C contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure . TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Disabling the JTAG Feature Test Data-Out (TDO) It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) TAP Controller Block Diagram 0 TAP Controller State Diagram 1 Bypass Register 2 1 0 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE TDI 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 Selection Circuitry TDO Identification Register CAPTURE-IR x . . . . . 2 1 0 Boundary Scan Register SHIFT-IR 1 Instruction Register 31 30 29 . . . 2 1 0 0 SHIFT-DR 0 1 EXIT1-DR 1 EXIT1-IR 0 1 0 PAUSE-IR 1 TCK TMS 0 PAUSE-DR TAP CONTROLLER 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 1 0 1 0 0 Selection Circuitry 0 UPDATE-IR 1 0 Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Document #: 38-05542 Rev. *A TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Page 9 of 27 PRELIMINARY Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register CY7C1366C CY7C1367C Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. Boundary Scan Register IDCODE The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Document #: 38-05542 Rev. *A The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE / PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE / PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE / PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Page 10 of 27 CY7C1366C CY7C1367C PRELIMINARY register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass TAP Timing 1 2 Test Clock (TCK) 3 t TH t TMSS t TMSH t TDIS t TDIH t TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the operating Range[3, 4] Parameter Symbol Min 50 Max Unit 20 MHz Clock TCK Clock Cycle Time tTCYC TCK Clock Frequency tTF TCK Clock HIGH time tTH 25 ns TCK Clock LOW time tTL 25 ns ns Output Times TCK Clock LOW to TDO Valid tTDOV TCK Clock LOW to TDO Invalid tTDOX 0 ns TMS Set-Up to TCK Clock Rise tTMSS 5 ns TDI Set-Up to TCK Clock Rise tTDIS 5 ns tCS 5 TMS hold after TCK Clock Rise tTMSH 5 ns TDI Hold after Clock Rise tTDIH 5 ns tCH 5 ns 5 ns Setup Times Capture Set-Up to TCK Rise Hold Times Capture Hold after Clock Rise Document #: 38-05542 Rev. *A Page 11 of 27 CY7C1366C CY7C1367C PRELIMINARY TAP AC Switching Characteristics Over the operating Range[3, 4] Parameter Symbol Min Max Unit Notes: 3. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 4. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document #: 38-05542 Rev. *A Page 12 of 27 CY7C1366C CY7C1367C PRELIMINARY 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ....... ........................................VSS to 3.3V Input pulse levels ........................................ VSS to 2.5V Input rise and fall times ...................... ..............................1ns Input rise and fall time ......................................................1ns Input timing reference levels ...........................................1.5V Input timing reference levels................... ......................1.25V Output reference levels...................................................1.5V Output reference levels .................. ..............................1.25V Test load termination supply voltage...............................1.5V Test load termination supply voltage .................... ........1.25V 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Output Load Equivalent 1.5V 1.25V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[5] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Conditions Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Max. Unit IOH = –4.0 mA 2.4 V IOH = –1.0 mA VDDQ = 2.5V 2.0 V IOH = –100 µA VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 V IOL = 8.0 mA VDDQ = 3.3V 0.4 V IOL = 8.0 mA VDDQ = 2.5V 0.4 V IOL = 100 µA VDDQ = 3.3V 0.2 V VDDQ = 2.5V 0.2 V Input HIGH Voltage Input LOW Voltage Input Load Current Min. VDDQ = 3.3V VDDQ = 3.3V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.5 0.7 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA GND < VIN < VDDQ Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24)[6] CY7C1366C (256K x36) CY7C1367C (512K x18) 000 000 01011 01011 Description Describes the version number. Reserved for Internal Use Device Width (23:18) 000110 000110 Defines memory type and architecture Cypress Device ID (17:12) 100110 010110 Defines width and density 00000110100 00000110100 1 1 Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Note: 5. All voltages referenced to VSS (GND). 6. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device. Document #: 38-05542 Rev. *A Page 13 of 27 CY7C1366C CY7C1367C PRELIMINARY Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 71 71 Boundary Scan Order (165-ball fBGA package) 71 71 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 119-Ball BGA Boundary Scan Order CY7C1366C (256K x 36) BALL ID Signal Name BIT# K4 H4 CLK 2 GW 3 M4 4 F4 5 6 CY7C1367C (512K x 18) BALL ID Signal Name BIT# BALL ID Signal Name BIT# BALL ID Signal Name 37 P4 A0 1 38 N4 A1 2 K4 H4 CLK GW 37 P4 A0 38 N4 A1 BWE 39 R6 A OE 40 T5 A 3 M4 4 F4 BWE 39 R6 A OE 40 T5 A B4 ADSC 41 T3 A A4 ADSP 42 R2 A 5 6 B4 ADSC 41 T3 A A4 ADSP 42 R2 A 7 G4 ADV 43 R3 8 C3 A 44 P2 MODE DQPD 7 G4 ADV 43 R3 MODE 8 C3 A 44 Internal Internal 9 B3 A 45 P1 DQD 9 B3 A 45 Internal Internal 10 D6 DQPB 46 L2 DQD 10 T2 A 46 Internal Internal 11 H7 DQB 47 K1 DQD 11 Internal Internal 47 Internal Internal 12 G6 DQB 48 N2 DQD 12 Internal Internal 48 P2 DQPB 13 E6 DQB 49 N1 DQD 13 Internal Internal 49 N1 DQB 14 D7 DQB 50 M2 DQD 14 D6 DQPA 50 M2 DQB 15 E7 DQB 51 L1 DQD 15 E7 DQA 51 L1 DQB 16 F6 DQB 52 K2 DQD 16 F6 DQA 52 K2 DQB 17 G7 DQB 53 Internal Internal 17 G7 DQA 53 Internal Internal 18 H6 DQB 54 H1 DQC 18 H6 DQA 54 H1 DQB BIT# 1 Document #: 38-05542 Rev. *A Page 14 of 27 CY7C1366C CY7C1367C PRELIMINARY 119-Ball BGA Boundary Scan Order (continued) CY7C1366C (256K x 36) BIT# BALL ID Signal Name BIT# 19 T7 ZZ 20 K7 21 CY7C1367C (512K x 18) BALL ID Signal Name BIT# BALL ID Signal Name BIT# BALL ID Signal Name 55 G2 DQC 19 T7 ZZ 55 G2 DQB DQA 56 E2 DQC 20 K7 DQA 56 E2 DQB L6 DQA 57 D1 DQC 21 L6 DQA 57 D1 DQB 22 N6 DQA 58 H2 DQC 22 N6 DQA 58 Internal Internal 23 P7 DQA 59 G1 DQC 23 P7 DQA 59 Internal Internal 24 N7 DQA 60 F2 DQC 24 Internal Internal 60 Internal Internal 25 M6 DQA 61 E1 DQC 25 Internal Internal 61 Internal Internal 26 L7 DQA 62 D2 DQPC 26 Internal Internal 62 Internal Internal 27 K6 DQA 63 C2 A 27 Internal Internal 63 C2 A 28 P6 DQPA 64 A2 A 28 Internal Internal 64 A2 A 29 T4 A 65 E4 CE1 29 T6 A 65 E4 CE1 30 A3 A 66 B2 CE2 30 A3 A 66 B2 CE2 31 C5 A 67 L3 BWD 31 C5 A 67 Internal Internal 32 B5 A 68 G3 BWC 32 B5 A 68 Internal Internal 33 A5 A 69 G5 BWB 33 A5 A 69 G3 BWB 34 C6 A 70 L5 BWA 34 C6 A 70 L5 BWA 71 Internal Internal 35 A6 A 71 Internal Internal 36 B6 A 35 A6 A 36 B6 A 165-Ball fBGA Boundary Scan Order CY7C1366C (256K x 36) CY7C1367C (512K x 18) BIT# BALL ID Signal Name BIT# BALL ID Signal Name BIT# BALL ID Signal Name BIT# BALL ID Signal Name 1 B6 CLK 37 R6 A0 1 B6 CLK 37 R6 A0 2 B7 GW 38 P6 A1 2 B7 GW 38 P6 A1 3 A7 BWE 39 R4 A 3 A7 BWE 39 R4 A 4 B8 OE 40 P4 A 4 B8 OE 40 P4 A 5 A8 ADSC 41 R3 A 5 A8 ADSC 41 R3 A 6 B9 ADSP 42 P3 A 6 B9 ADSP 42 P3 A 7 A9 ADV 43 R1 MODE 7 A9 ADV 43 R1 MODE 8 B10 A 44 N1 DQPD 8 B10 A 44 Internal Internal 9 A10 A 45 L2 DQD 9 A10 A 45 Internal Internal 10 C11 DQPB 46 K2 DQD 10 A11 A 46 Internal Internal 11 E10 DQB 47 J2 DQD 11 Internal Internal 47 Internal Internal 12 F10 DQB 48 M2 DQD 12 Internal Internal 48 N1 DQPB 13 G10 DQB 49 M1 DQD 13 Internal Internal 49 M1 DQB 14 D10 DQB 50 L1 DQD 14 C11 DQPA 50 L1 DQB 15 D11 DQB 51 K1 DQD 15 D11 DQA 51 K1 DQB 16 E11 DQB 52 J1 DQD 16 E11 DQA 52 J1 DQB 17 F11 DQB 53 Internal Internal 17 F11 DQA 53 Internal Internal Document #: 38-05542 Rev. *A Page 15 of 27 CY7C1366C CY7C1367C PRELIMINARY 165-Ball fBGA Boundary Scan Order (continued) CY7C1366C (256K x 36) BIT# BALL ID Signal Name 18 G11 19 H11 20 21 22 23 24 25 26 27 28 N11 DQPA 64 29 R11 A 65 30 R10 A 66 31 P10 A 67 32 R9 A 33 P9 A 34 R8 35 P8 36 P11 A CY7C1367C (512K x 18) Signal Name BIT# BALL ID Signal Name Signal Name BIT# BALL ID DQB 54 G2 DQC 18 G11 ZZ 55 F2 DQC 19 H11 J10 DQA 56 E2 DQC 20 K10 DQA 57 D2 DQC 21 L10 DQA 58 G1 DQC 22 M10 DQA 59 F1 DQC 23 J11 DQA 60 E1 DQC 24 K11 DQA 61 D1 DQC 25 L11 DQA 62 C1 DQPC 26 Internal M11 DQA 63 B2 A 27 Internal A2 A 28 Internal A3 CE1 29 R11 B3 CE2 30 R10 A 66 B3 CE2 B4 BWD 31 P10 A 67 Internal Internal 68 A4 BWC 32 R9 A 68 Internal Internal 69 A5 BWB 33 P9 A 69 A4 BWB A 70 B5 BWA 34 R8 A 70 B5 BWA A 71 A6 CE3 35 P8 A 71 A6 CE3 36 P11 A Document #: 38-05542 Rev. *A BIT# BALL ID DQA 54 G2 DQB ZZ 55 F2 DQB J10 DQA 56 E2 DQB K10 DQA 57 D2 DQB L10 DQA 58 Internal Internal M10 DQA 59 Internal Internal Internal Internal 60 Internal Internal Internal Internal 61 Internal Internal Internal 62 Internal Internal Internal 63 B2 A Internal 64 A2 A A 65 A3 CE1 Page 16 of 27 CY7C1366C CY7C1367C PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current..................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V DC Voltage Applied to Outputs in three-state ....................................... –0.5V to VDDQ + 0.5V Parameter Description Ambient Temperature Commercial 0°C to +70°C Industrial DC Input Voltage....................................–0.5V to VDD + 0.5V Electrical Characteristics Over the Operating Range Range Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage[7] VIL Input LOW Voltage[7] IX Input Load Current except ZZ and MODE GND ≤ VI ≤ VDDQ Min. Unit 3.135 3.6 V 3.135 VDD V VDDQ = 2.5V 2.375 2.625 VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 VDDQ = 2.5V, VDD = Min., IOH= –1.0 mA 2.0 VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA V V V 0.4 V 0.4 V 2.0 VDD + 0.3V V VDDQ = 2.5V 1.7 VDD + 0.3V V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA VDDQ = 3.3V µA –30 Input Current of MODE Input = VSS Input = VDD 5 Input = VSS µA µA –5 30 µA 5 µA 4.4-ns cycle, 225 MHz 250 mA 5-ns cycle, 200 MHz 220 mA 6-ns cycle, 166 MHz 180 mA All speeds 50 mA All speeds 30 mA Automatic CE VDD = Max, Device Deselected, or All speeds Power-down VIN ≤ 0.3V or VIN > VDDQ – 0.3V Current—CMOS Inputs f = fMAX = 1/tCYC VDD = Max, Device Deselected, Automatic CE All Speeds Power-down VIN ≥ VIH or VIN ≤ VIL, f = 0 Current—TTL Inputs 50 mA 40 mA Input = VDD IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB1 Automatic CE Power-down Current—TTL Inputs VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC ISB2 Automatic CE VDD = Max, Device Deselected, Power-down VIN ≤ 0.3V or VIN > VDDQ – 0.3V, Current—CMOS Inputs f = 0 ISB3 ISB4 Max. VDDQ = 3.3V VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA Input Current of ZZ VDDQ [7, 8] Test Conditions VDD VDD 3.3V – 5%/+10% 2.5V – 5% to VDD –40°C to +85°C –5 Shaded areas contain advance information. Notes: 7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 8. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD\ Document #: 38-05542 Rev. *A Page 17 of 27 CY7C1366C CY7C1367C PRELIMINARY Thermal Resistance[9] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package BGA Package fBGA Package Unit 25 25 27 °C/W 9 6 6 °C/W fBGA Package Unit Capacitance[9] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 2.5V TQFP Package BGA Package 5 5 5 pF 5 5 5 pF 5 7 7 pF AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R = 351Ω VT = 1.5V 2.5V I/O Test Load INCLUDING JIG AND SCOPE (a) OUTPUT RL = 50Ω Z0 = 50Ω INCLUDING JIG AND SCOPE ≤ 1ns ≤ 1ns (c) ALL INPUT PULSES VDDQ GND 5 pF 90% 10% 90% (b) R =1538Ω VT = 1.25V (a) 10% R = 1667Ω 2.5V OUTPUT ALL INPUT PULSES VDDQ (b) 10% 90% 10% 90% ≤ 1ns ≤ 1ns (c) Note: 9. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05542 Rev. *A Page 18 of 27 CY7C1366C CY7C1367C PRELIMINARY Switching Characteristics Over the Operating Range[14, 15] 225 MHz Parameter tPOWER Description VDD(Typical) to the first Access[10] Min. Max 200 MHz Min. Max 166 MHz Min. Max Unit 1 1 1 ms Clock tCYC Clock Cycle Time 4.4 5.0 6.0 ns tCH Clock HIGH 1.8 2.0 2.4 ns tCL Clock LOW 1.8 2.0 2.4 ns Output Times tCO Data Output Valid After CLK Rise 2.8 3.0 3.5 ns tDOH Data Output Hold After CLK Rise 1.25 1.25 1.25 ns tCLZ Clock to Low-Z[11, 12, 13] 1.25 1.25 1.25 ns tCHZ High-Z[11, 12, 13] 1.25 tOEV tOELZ tOEHZ Clock to OE LOW to Output Valid OE LOW to Output Low-Z[11, 12, 13] 2.8 1.25 2.8 0 [11, 12, 13] 1.25 3.0 0 2.8 OE HIGH to Output High-Z 3.0 3.5 ns 3.5 ns 3.5 ns 0 3.0 ns Set-up Times tAS Address Set-up Before CLK Rise 1.4 1.5 1.5 ns tADS ADSC, ADSP Set-up Before CLK Rise 1.4 1.5 1.5 ns 1.5 1.5 ns tWES ADV Set-up Before CLK Rise GW, BWE, BWX Set-up Before CLK Rise 1.4 1.4 1.5 1.5 ns tDS Data Input Set-up Before CLK Rise 1.4 1.5 1.5 ns tCES Chip Enable Set-Up Before CLK Rise 1.4 1.5 1.5 ns Address Hold After CLK Rise 0.4 0.5 0.5 ns 0.5 0.5 ns 0.4 0.5 0.5 ns tWEH ADSP , ADSC Hold After CLK Rise ADV Hold After CLK Rise GW,BWE, BWX Hold After CLK Rise 0.4 0.4 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.4 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.4 0.5 0.5 ns tADVS Hold Times tAH tADH tADVH Shaded areas contain advance information. Notes: 10. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 11. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 12. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions 13. This parameter is sampled and not 100% tested. 14. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 15. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05542 Rev. *A Page 19 of 27 CY7C1366C CY7C1367C PRELIMINARY Switching Waveforms Read Cycle Timing[16] tCYC CLK tCH tADS tCL tADH ADSP tADS tADH ADSC tAS ADDRESS tAH A1 A2 tWES A3 Burst continued with new base address tWEH GW, BWE,BW X Deselect cycle tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t Data Out (DQ) High-Z CLZ t OEHZ Q(A1) tOEV tCO t OELZ tDOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) t CO Single READ BURST READ DON’T CARE Burst wraps around to its initial state UNDEFINED Notes: 16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05542 Rev. *A Page 20 of 27 CY7C1366C CY7C1367C PRELIMINARY Switching Waveforms (continued) Write Cycle Timing[16, 17] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BWX tWES tWEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t DS Data in (D) High-Z t OEHZ t DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Note: 17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document #: 38-05542 Rev. *A Page 21 of 27 CY7C1366C CY7C1367C PRELIMINARY Switching Waveforms (continued) Read/Write Cycle Timing[16, 18, 19] tCYC CLK tCL tCH tADS tADH tAS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) tWES tWEH BWE, BWX tCES tCEH CE ADV OE tDS tCO Data In (D) tOELZ High-Z tCLZ Data Out (Q) tDH High-Z Q(A1) Back-to-Back READs tOEHZ D(A3) Q(A2) Q(A4) Q(A4+2) BURST READ Single WRITE DON’T CARE Q(A4+1) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes: 18. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 19. GW is HIGH. Document #: 38-05542 Rev. *A Page 22 of 27 CY7C1366C CY7C1367C PRELIMINARY Switching Waveforms (continued) ZZ Mode Timing [20, 21] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) 225 Ordering Code CY7C1366C-225AXC Package Name 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Commercial A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Industrial CY7C1367C-225AXI CY7C1366C-225BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Commercial JTAG BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Industrial JTAG CY7C1367C-225BGC CY7C1366C-225BGI CY7C1367C-225BGI CY7C1366C-225BZC BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial 3 Chip Enables with JTAG BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Industrial 3 Chip Enables with JTAG CY7C1367C-225BZC CY7C1366C-225BZI CY7C1367C-225BZI 200 CY7C1366C-200AXC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Commercial A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Industrial CY7C1367C-200AXC CY7C1366C-200AXI CY7C1367C-200AXI CY7C1366C-200BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Commercial JTAG BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Industrial JTAG CY7C1367C-200BGC CY7C1366C-200BGI CY7C1367C-200BGI CY7C1366C-200BZC BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial 3 Chip Enables with JTAG BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Industrial 3 Chip Enables with JTAG CY7C1367C-200BZC CY7C1366C-200BZI CY7C1367C-200BZI Operating Range A101 CY7C1367C-225AXC CY7C1366C-225AXI Part and Package Type Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05542 Rev. *A Page 23 of 27 CY7C1366C CY7C1367C PRELIMINARY Ordering Information (continued) Speed (MHz) Package Name Ordering Code 166 CY7C1366C-166AXC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Commercial A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Industrial CY7C1367C-166AXC CY7C1366C-166AXI CY7C1367C-166AXI CY7C1366C-166BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with JTAG Commercial BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with JTAG Industrial BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables with JTAG Commercial BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables with JTAG Industrial CY7C1367C-166BGC CY7C1366C-166BGI CY7C1367C-166BGI CY7C1366C-166BZC CY7C1367C-166BGC CY7C1366C-166BZI Operating Range Part and Package Type CY7C1367C-166BGI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.Lead-free BG and BZ packages (Ordering code:BGX,BZX) will be available in 2005. Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 1.40±0.05 14.00±0.10 81 100 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 SEE DETAIL 50 0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 GAUGE PLANE 0.10 0° MIN. 0°-7° A 51 31 R 0.08 MIN. 0.20 MAX. 12°±1° (8X) SEATING PLANE R 0.08 MIN. 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05542 Rev. *A A 51-85050-*A Page 24 of 27 PRELIMINARY CY7C1366C CY7C1367C Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Document #: 38-05542 Rev. *A Page 25 of 27 CY7C1366C CY7C1367C PRELIMINARY Package Diagrams (continued) 165 FBGA 13 x 15 x 1.40 MM BB165D 51-85180-** i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05542 Rev. *A Page 26 of 27 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1366C CY7C1367C PRELIMINARY Document History Page Document Title: CY7C1366C/CY7C1367C 9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM (Preliminary) Document Number: 38-05542 REV. ECN NO. Issue Date Orig. of Change ** 241690 See ECN RKF New data sheet *A 278969 See ECN RKF Changed Boundary Scan order to match the B rev of these devices. Document #: 38-05542 Rev. *A Description of Change Page 27 of 27