DATASHEET Radiation Hardened 30V 32-Channel Analog Multiplexer ISL71841SEH Features The ISL71841SEH is a radiation hardened, 32-channel high ESD protected multiplexer that is fabricated using Intersil’s proprietary P6SOI (Silicon On Insulator) process technology to mitigate single event effects. It operates with a dual supply voltage ranging from ±10.8V to ±16.5V. It has a 5-bit address plus an enable pin that can be driven with adjustable logic thresholds to conveniently select 1 of 32 available channels. An inactive channel is separated from an active channel by a high impedance, which inhibits any interaction between them. • DLA SMD# 5962-15220 The ISL71841SEH’s low rON allows for improved signal integrity and reduced power losses. The ISL71841SEH is also designed for cold sparing making it excellent for high reliability applications that have redundancy requirements. It is designed to provide a high impedance to the analog source in a powered off condition, making it easy to add additional backup devices without loading signal sources. The ISL71841SEH also incorporates input analog overvoltage protection, which will disable the switch to protect downstream devices. • Flexible split rail operation - Positive supply above GND (V+) . . . . . . . +10.8V to +16.5V - Negative supply below GND (V-) . . . . . . . . -10.8V to -16.5V The ISL71841SEH is available in a 48 Ld CQFP, 44 Ld CLCC, or die form and operates across the extended temperature range of -55°C to +125°C. • Break-before-make switching There is also a 16-channel version available offered in a 28 Ld CDFP, please refer to the ISL71840SEH datasheet for more information. For a list of differences please refer to Table 1 on page 3. Related Literature • UG037, “ISL71841SEHEV1Z Evaluation Board User Guide” • TR007, “Single Event Effects (SEE) Testing of the ISL71841SEH 32:1 30V Multiplexer” • Fabricated using P6SOI process technology - Provides latch-up immunity • ESD protection 8kV (HBM) • Rail-to-rail operation • Overvoltage protection • Low rON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <500Ω (typical) • Adjustable logic threshold control with VREF pin • Cold sparing capable (from ground). . . . . . . . . . . . . . . . .±25V • Analog overvoltage range (from ground) . . . . . . . . . . . . .±35V • Off switch leakage . . . . . . . . . . . . . . . . . . . 100nA (maximum) • Transition times (tR, tF) . . . . . . . . . . . . . . . . . . . 500ns (typical) • Grounded metal lid (internally connected) • Operating temperature range. . . . . . . . . . . .-55°C to +125°C • Radiation tolerance - High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si) - Low dose rate (0.01rad(Si)/s) . . . . 100krad(Si) (see Note) - SEB LETTH . . . . . . . . . . . . . . . . . . . . . . . . . 86.4MeV•cm2/mg NOTE: Product capability established by initial characterization. All subsequent lots are assurance tested to 50krad (0.01rad(Si)/s) wafer-by-wafer. • TR011, “Total Dose Testing of the ISL71841SEH 32-channel Analog Multiplexer” ISL71841SEH 600 500 IN01 IN03 . . . OUT ADC IN32 rDS(ON) (Ω) IN02 400 +125°C +25°C 300 200 100 -55°C 5 0 ADDRESS EN FIGURE 1. TYPICAL APPLICATION June 3, 2016 FN8735.4 1 -20 -15 -10 -5.0 0 5.0 10 SWITCH INPUT VOLTAGE (V) 15 20 FIGURE 2. rDS(ON) vs POWER SUPPLY ACROSS SWITCH INPUT COMMON-MODE VOLTAGE AT +25°C CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015, 2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL71841SEH Table of Contents Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications (±15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications (±12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Post High Dose Rate Radiation Characteristics (V± = ±15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Post High Dose Rate Radiation Characteristics (V± = ±12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Post Low Dose Rate Radiation Characteristics (V± = ±15V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Post Low Dose Rate Radiation Characteristics (V± = ±12V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VREF and Logic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 24 24 ISL71841SEH vs ISL71840SEH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Interface Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Assembly Related Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Weight of Packaged Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lid Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 25 Metalization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 R48.A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Ceramic Leadless Chip Carrier Packages (CLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Submit Document Feedback 2 FN8735.4 June 3, 2016 ISL71841SEH Ordering Information ORDERING NUMBER (Note 3) TEMP RANGE (°C) PART NUMBER PKG. DWG. # PACKAGE 5962R1522001VXC ISL71841SEHVF (Note 1) -55 to +125 48 LD CQFP (RoHS Compliant) R48.A N/A ISL71841SEHF/PROTO (Note 1) -55 to +125 48 LD CQFP (RoHS Compliant) R48.A 5962R1522001VYA ISL71841SEHVL (Note 2) -55 to +125 44 LD CLCC J44.A N/A ISL71841SEHL/PROTO (Note 2) -55 to +125 44 LD CLCC J44.A 5962R1522001V9A ISL71841SEHVX -55 to +125 DIE (RoHS Compliant) N/A ISL71841SEHX/SAMPLE -55 to +125 DIE (RoHS Compliant) N/A ISL71841SEHEV1Z Evaluation Board NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. These Intersil Hermetic Packaged products are intended for SnPb soldering and may be shipped with terminations precoated with SnPb solder compatible with SnPb soldering operations only. 3. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be used when ordering. TABLE 1. TABLE OF DIFFERENCES SPECIFICATION ISL71840SEH ISL71841SEH Number of Channels 16 32 Supply Current (I+/I-) 350µA (Maximum) 400µA (Maximum) 60nA (Maximum) 120nA (Maximum) Output Leakage (+125°C) Submit Document Feedback 3 FN8735.4 June 3, 2016 ISL71841SEH Pin Configurations 39 38 37 10 11 12 13 14 15 16 17 36 35 34 33 32 31 18 19 20 21 22 23 24 25 26 27 28 29 30 IN28 IN27 IN26 IN25 IN24 IN23 IN22 IN21 IN20 IN19 IN18 IN17 IN29 1 IN28 2 IN31 3 IN30 4 OUT IN14 5 IN15 IN13 6 IN16 IN12 IN13 IN14 IN15 IN16 NC OUT NC NC IN32 IN31 IN30 IN29 IN12 IN11 IN10 IN9 IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 6 5 4 3 2 1 48 47 46 45 44 43 42 7 41 8 40 9 IN32 ISL71841SEH (44 LD CLCC) TOP VIEW ISL71841SEH (48 LD CQFP) TOP VIEW 44 43 42 41 40 IN11 7 39 IN27 IN10 8 38 IN26 IN9 9 37 IN25 IN8 10 36 IN24 IN7 11 35 IN23 IN6 12 34 IN22 IN5 13 33 IN21 IN4 14 32 IN20 IN3 15 31 IN19 IN2 16 30 IN18 IN1 17 29 IN17 V- NC GND EN A4 A3 A2 A1 A0 V+ VREF V- EN GND NC A4 NC A3 A1 A2 A0 V+ VREF 18 19 20 21 22 23 24 25 26 27 28 Pin Descriptions PIN NAME PIN NUMBER 48 LD CQFP PIN NUMBER 44 LD CLCC NC 2, 26, 27, 47, 48 NA OUT 1 1 Output for multiplexer V+ 19 18 Positive power supply V- 30 27 Negative power supply INx DESCRIPTION Not connected, no internal connection 3, 4, 5, 6, 7, 8, 9, 10, 11, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, Inputs for multiplexer 13, 14, 15, 16, 17, 12, 13, 14, 15, 16, 17, 18, 31, 32, 33, 34, 35, 36, 37, 29, 30, 31, 32, 33, 34, 35, 36, 38, 39, 40, 41, 42, 43, 44, 37, 38, 39, 40, 41, 42, 43, 44 45, 46 Ax 21, 22, 23, 24, 25 20, 21, 22, 23, 24, EN 28 25 Enable control for multiplexer (active low) VREF 20 19 Reference voltage used to set logic thresholds GND 29 26 Ground LID NA NA Package Lid is internally connected to GND (Pin 29 on CQFP, Pin 26 on CLCC) Submit Document Feedback 4 Address lines for multiplexer FN8735.4 June 3, 2016 ISL71841SEH Absolute Maximum Ratings Thermal Information (V+) Positive Supply Voltage above GND (Note 6). . . . . . . . . . . . . . . . . +20V Negative Supply Voltage below GND (V-) (Note 6) . . . . . . . . . . . . . . . . .-20V Maximum Supply Voltage Differential (V+ to V-) (Note 6) . . . . . . . . . . . 40V Analog Input Voltage (INx) From GND (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35V Digital Input Voltage Range (EN, Ax) . . . . . . . . . . . . . . . . . . . . . . . . GND to V+ VREF to GND (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16.5V ESD Tolerance Human Body Model (Tested per MIL-STD-883 TM 3015) . . . . . . . . . 8kV Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 250V Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 250V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 48 Ld CQFP (Notes 4, 5) . . . . . . . . . . . . . . . 50 2 44 Ld CLCC (Notes 4, 5). . . . . . . . . . . . . . . . 31 3 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Recommended Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C Positive Supply Voltage Above GND (V+) . . . . . . . . . . . . . +10.8V to +16.5V Negative Supply Voltage Below GND (V-) . . . . . . . . . . . . . . .-10.8V to -16.5V Supply Voltage Differential (V+ to V-) . . . . . . . . . . . . . . . . . . . . 21.6V to 33V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is the center of the package underside. 6. Tested in a heavy ion environment at LET = 86.3MeV•cm2/mg at +125°C. Electrical Specifications (±15V) V+ = 15V, V- = -15V, VAH = 4.0V, VAL = 0.8V, VREF = VEN = 5.0V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C or across a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300krad(Si)/s or a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. SYMBOL VS Analog Input Signal Range rON Channel ON-Resistance ΔrON RFLAT(ON) IS(OFF) rON Match Between Channels MIN (Note 7) TYP MAX (Note 7) V- - V+ V V± = ±15.0V, ±16.5V IOUT = -1mA, VIN = +5V, -5V - - 500 Ω V± = ±15.0V, ±16.5V IOUT = -1mA, VIN = V+, V- - - 700 Ω VIN = +5V, -5V; IOUT = -1mA - 10 20 Ω PARAMETER TEST CONDITIONS UNIT ON-Resistance Flatness VIN = +5V, -5V - - 25 Ω Switch Off Leakage VIN = V+ - 5V, V± = ±16.5V All unused inputs are tied to V- + 5V -10 - 10 nA Post radiation -100 - 100 nA V- + 5V, V± = ±16.5V VIN = All other inputs = V+ - 5V TA = +25°C, -55°C -10 - 10 nA TA = +125°C -20 - 20 nA Post radiation -100 - 100 nA VIN = +25V, V± = VEN = VA = VREF = 0V TA = +25°C, V± = 0V -10 - 10 nA TA = -55°C, +125°C -10 - 80 nA Post radiation -100 - 100 nA VIN = -25V, V± = VEN = VA = VREF = 0V TA = +25°C, V± = 0V -10 - 10 nA TA = -55°C, +125°C -80 - 10 nA Post radiation -100 - 100 nA IS(OFF) POWER OFF Switch Off Leakage with Device Powered Off Submit Document Feedback 5 FN8735.4 June 3, 2016 ISL71841SEH Electrical Specifications (±15V) V+ = 15V, V- = -15V, VAH = 4.0V, VAL = 0.8V, VREF = VEN = 5.0V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C or across a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300krad(Si)/s or a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) SYMBOL IS(OFF) POWER OFF Switch Off Leakage with Device Powered Off IS(ON) OVERVOLT IS(OFF) OVERVOLT ID(OFF) MIN (Note 7) TYP MAX (Note 7) UNIT VIN = +25V, VEN/VA/VREF = 0V V± = OPEN, TA = +25°C -10 - 10 nA TA = -55°C, +125°C -10 - 80 nA Post radiation -100 - 100 nA VIN = -25V, VEN/VA/VREF = 0V V± = OPEN, TA = +25°C -10 - 10 nA TA = -55°C, +125°C -80 - 10 nA Post radiation -100 - 100 nA VIN = +35V, VOUT = 0V, TA = +25°C, -55°C All unused switch inputs = GND, V± = ±16.5V -10 - 10 nA TA = +125°C -80 - 80 nA Post radiation -500 - 500 nA VIN = -35V, VOUT = 0V, TA = +25°C, -55°C All unused switch inputs = GND, V± = ±16.5V -10 - 10 nA PARAMETER Switch On Leakage Current Into the Source (overvoltage) Switch Off Leakage Current Into the Source (overvoltage) Switch Off Leakage TEST CONDITIONS TA = +125°C -20 - 20 nA Post radiation -500 - 500 nA VIN = +35V, VOUT = 0V, TA = +25°C, -55°C All unused switch inputs = GND, V± = ±16.5V -10 - 10 nA TA = +125°C -80 - 80 nA Post radiation -750 - 750 nA VIN = -35V, VOUT = 0V, TA = +25°C, -55°C All unused switch inputs = GND, V± = ±16.5V -10 - 10 nA TA = +125°C -20 - 20 nA Post radiation -750 - 750 nA VOUT = V+ - 5V, all inputs = V- + 5V V± = ±16.5V, TA = +25°C, -55°C -10 - 10 nA 0 - 120 nA -80 - 80 nA -10 - 10 nA TA = +125°C -120 - 0 nA Post radiation -80 - 80 nA VOUT = 0V, VIN = +35V, V± = ±16.5V All unused inputs are tied to GND -10 - 10 nA Post radiation -500 - 500 nA VOUT = 0V, VIN = -35V, V± = ±16.5V All unused inputs are tied to GND -10 - 10 nA Post radiation -500 - 500 nA TA = +125°C Post radiation V- V+ - VOUT = + 5V, all inputs = 5V V± = ±16.5V, TA = +25°C, -55°C ID(OFF) OVERVOLT Switch Off Leakage Current Into the Drain (overvoltage) Submit Document Feedback 6 FN8735.4 June 3, 2016 ISL71841SEH Electrical Specifications (±15V) V+ = 15V, V- = -15V, VAH = 4.0V, VAL = 0.8V, VREF = VEN = 5.0V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C or across a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300krad(Si)/s or a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) SYMBOL PARAMETER ID(ON) Switch On Leakage Current Into the Source/Drain MIN (Note 7) TYP MAX (Note 7) UNIT -10 - 10 nA TA = +125°C 0 - 120 nA Post radiation -100 - 100 nA -10 - 10 nA TA = +125°C -120 - 0 nA TEST CONDITIONS VIN = VOUT = V+ - 5V, TA = +25°C, -55°C All unused inputs = V- + 5V, V± = ±16.5V V- VIN = VOUT = + 5V, TA = +25°C, -55°C All unused inputs = V- + 5V, V± = ±16.5V Post radiation -100 - 100 nA Logic Input High/Low Voltage VREF = 5.0V 1.2 - 1.6 V IAH, IENH Input Current with VAH, VENH VA = VEN = 4.0V V+= 16.5V, V- = -16.5V -100 - 100 nA IAL, IENL Input Current with VAL, VENL VA = VEN = 0.8V V+ = 16.5V, V- = -16.5V -100 - 100 nA I+ Quiescent Supply Current VIN = VA = VEN = 0.8V, V± = ±15.0V, ±16.5V - - 400 µA I- Quiescent Supply Current VIN = VA = VEN = 0.8V, V± = ±15.0V, ±16.5V -400 - - µA I+ Standby Supply Current VIN = VA = VEN = 4.0V, V± = ±15.0V, ±16.5V - - 400 µA I- Standby Supply Current VIN = VA = VEN = 4.0V, V± = ±15.0V, ±16.5V -400 - - µA IREF Supply Current into VREF VREF = 5.5V, VIN = VA = VEN = 0.8V, V± = ±15.0V, ±16.5V 10 - 35 µA tALH Transition Time Figures 4, 5 - 0.5 800 ns tAHL Transition Time Figures 4, 5 - 0.5 800 ns tBBM Break-Before-Make Delay Figures 8, 9 TA = -55°C, +25°C, +125°C 5 50 200 ns Post radiation 5 - 400 ns Figures 6, 7 TA = -55°C, +25°C, +125°C - 0.5 600 ns Post radiation - - 800 ns Figures 6, 7 TA = -55°C, +25°C, +125°C - 0.5 600 ns Post radiation - - 800 ns - 2 5 pC VAH/L, VENH/L DYNAMIC tENABLE tDISABLE Enable Turn-On Time Disable Turn-Off Time VCTE Charge Injection CL = 100pF, VIN = 0V, (Figure 6) VISO Off Isolation VEN = 4V, RL = 1kΩ, f = 200kHz, CL = 7pF, VRMS = 3V 75 - - dB VCT Crosstalk VEN = 0.8V, RL = 1kΩ, f = 200kHz, CL = 7pF, VRMS = 3V 47 - - dB CA Digital Input Capacitance f = 1MHz, V+ = V- = 0V - - 7 pF f = 1MHz, V+ f = 1MHz, V+ CIN(OFF) COUT(OFF) Input Capacitance Output Capacitance Submit Document Feedback 7 = V- = 0V - - 5 pF = V- = 0V - - 50 pF FN8735.4 June 3, 2016 ISL71841SEH Electrical Specifications (±12V) V+ = 12V, V- = -12V, VAH = 4.0V, VAL = 0.8V, VREF = VEN = 5.0V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C or across a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300krad(Si)/s or a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. SYMBOL PARAMETER VS Analog Input Signal Range rON Channel ON-Resistance ΔrON RFLAT(ON) TEST CONDITIONS MIN (Note 7) TYP V- MAX (Note 7) UNIT V+ V V± = ±10.8V, ±13.2V IOUT = -1mA, VIN = +5V, -5V - - 500 Ω V± = ±10.8V, ±13.2V IOUT = -1mA, VIN = V+, V- - - 700 Ω rON Match Between Channels VIN = +5V, -5V; IOUT = -1mA - 10 20 Ω ON-Resistance Flatness VIN = +5V, -5V, V± = ±13.2V - - 25 Ω VIN = +5V, -5V, V± = ±10.8V, TA = +25°C, -55°C, +125°C - - 30 Ω VIN = +5V, -5V, V± = ±10.8V, post radiation, TA = +25°C - - 40 Ω I+ Quiescent Supply Current VIN = VA = VEN = 0.8V, V± = ±10.8V, ±13.2V - - 400 µA I- Quiescent Supply Current VIN = VA = VEN = 0.8V, V± = ±10.8V, ±13.2V -400 - - µA I+ Standby Supply Current VIN = VA = VEN = 4.0V, V± = ±10.8V, ±13.2V - - 400 µA I- Standby Supply Current VIN = VA = VEN = 4.0V, V± = ±10.8V, ±13.2V -400 - - µA IREF Supply Current Into VREF VREF = 5.5V, VIN = VA = VEN = 0.8V, V± = ±10.8V, ±13.2V - - 35 µA tALH Transition Time Figures 4, 5 - 0.5 800 ns tAHL Transition Time Figures 4, 5 - 0.5 800 ns tBBM Break-Before-Make Delay Figures 8, 9 TA = -55°C, +25°C, +125°C 5 50 200 ns Post radiation 5 - 400 ns Figures 6, 7 TA = -55°C, +25°C, +125°C - 0.5 600 ns Post radiation - - 800 ns Figures 6, 7 TA = -55°C, +25°C, +125°C - 0.5 600 ns Post radiation - - 800 ns DYNAMIC tENABLE tDISABLE Enable Turn-On Time Disable Turn-Off Time NOTE: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Submit Document Feedback 8 FN8735.4 June 3, 2016 ISL71841SEH TABLE 2. TRUTH TABLE A4 A3 A2 A1 A0 EN “ON”-CHANNEL X X X X X 1 None 0 0 0 0 0 0 1 0 0 0 0 1 0 2 0 0 0 1 0 0 3 0 0 0 1 1 0 4 0 0 1 0 0 0 5 0 0 1 0 1 0 6 0 0 1 1 0 0 7 0 0 1 1 1 0 8 0 1 0 0 0 0 9 0 1 0 0 1 0 10 0 1 0 1 0 0 11 0 1 0 1 1 0 12 0 1 1 0 0 0 13 0 1 1 0 1 0 14 0 1 1 1 0 0 15 0 1 1 1 1 0 16 1 0 0 0 0 0 17 1 0 0 0 1 0 18 1 0 0 1 0 0 19 1 0 0 1 1 0 20 1 0 1 0 0 0 21 1 0 1 0 1 0 22 1 0 1 1 0 0 23 1 0 1 1 1 0 24 1 1 0 0 0 0 25 1 1 0 0 1 0 26 1 1 0 1 0 0 27 1 1 0 1 1 0 28 1 1 1 0 0 0 29 1 1 1 0 1 0 30 1 1 1 1 0 0 31 1 1 1 1 1 0 32 NOTE: X = Don’t care, “1” = Logic High, “0” = Logic Low Submit Document Feedback 9 FN8735.4 June 3, 2016 ISL71841SEH Block Diagram V+ A0 IN1 1 OUT A1 A2 A3 A4 IN32 32 EN V‐ ADDRESS INPUT BUFFER AND LEVEL SHIFTER DECODERS MULTIPLEX SWITCHES FIGURE 3. BLOCK DIAGRAM Submit Document Feedback 10 FN8735.4 June 3, 2016 ISL71841SEH Timing Diagrams ISL71841SEH +4.0V +0.8V A4 A3 A2 A1 A0 50Ω 4V IN01 +15V, 0V “11111” ADDRESS IN02-IN31 50% 0V, +15V IN32 50% “00000” 0.8V 15V +0.8V tAHL OUT EN 10kΩ 50pF 50% 50% 0V FIGURE 4. ADDRESS TIME TO OUTPUT TEST CIRCUIT FIGURE 5. ADDRESS TIME TO OUTPUT DIAGRAM ISL71841SEH A4 A3 A2 A1 A0 tALH OUTPUT 4V IN01 +10V IN02-IN32 ENABLE 50% 50% 0.8V 10V EN +4.0V OUT 1kΩ 50Ω +0.8V tDISABLE tENABLE 50pF OUTPUT 50% 50% 0V FIGURE 7. TIME TO ENABLE/DISABLE OUTPUT DIAGRAM FIGURE 6. TIME TO ENABLE/DISABLE OUTPUT TEST CIRCUIT ISL71841SEH +4.0V A4 A3 A2 A1 A0 50Ω +0.8V IN01 4V +5V IN02-IN31 ADDRESS IN32 0.8V +0.8V OUT EN VOUT 5V 50% 1kΩ 50pF OUT 0V FIGURE 9. BREAK-BEFORE-MAKE DIAGRAM FIGURE 8. BREAK-BEFORE-MAKE TEST CIRCUIT 4V ISL71841SEH +4.0V +0.8V 50Ω A4 A3 A2 A1 A0 tBBM IN01 0V ADDRESS IN02-IN31 IN32 0.8V 15V +0.8V EN OUT Q = 100pF * ΔVOUT VOUT OUT 100pF ΔVOUT 0V FIGURE 10. CHARGE INJECTION TEST CIRCUIT Submit Document Feedback 11 FIGURE 11. CHARGE INJECTION DIAGRAM FN8735.4 June 3, 2016 ISL71841SEH Typical Performance Curves 600 600 500 500 +125°C +25°C 300 +125°C +25°C 400 rDS(ON) (Ω) 400 rDS(ON) (Ω) V± = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. 300 200 200 100 100 -55°C -55°C 0 -20 -15 -10 -5 0 5 10 15 0 -20 20 -15 -10 SWITCH INPUT VOLTAGE (V) 600 700 500 600 +125°C 200 0 -20 20 400 300 -15 -10 -5 0 5 10 15 -55°C 0 -15 20 -10 SWITCH INPUT VOLTAGE (V) -5 0 5 10 15 10 15 SWITCH INPUT VOLTAGE (V) FIGURE 14. rDS(ON) vs VCM (V± = 16.5V) FIGURE 15. rDS(ON) vs VCM (V± = 10.8V) 600 600 500 500 +125°C +25°C 400 rDS(ON) (Ω) rDS(ON) (Ω) 15 +25°C 100 -55°C 300 200 0 -15 10 200 100 100 5 +125°C 500 300 400 0 FIGURE 13. rDS(ON) vs VCM (V± = 15.0V) rDS(ON) (Ω) rDS(ON) (Ω) FIGURE 12. rDS(ON) vs VCM (V± = 14.5V) 400 +25°C -5 SWITCH INPUT VOLTAGE (V) +125°C +25°C 300 200 100 -55°C -10 -5 0 5 SWITCH INPUT VOLTAGE (V) FIGURE 16. rDS(ON) vs VCM (V± = 12.0V) Submit Document Feedback 12 10 15 0 -15 -55°C -10 -5 0 5 SWITCH INPUT VOLTAGE (V) FIGURE 17. rDS(ON) vs VCM (V± = 13.2V) FN8735.4 June 3, 2016 ISL71841SEH Typical Performance Curves V± = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 700 600 t ADDHL (ns) 500 5V/DIV +125°C 400 +25°C -55°C 300 200 2V/DIV 100 tADDLH = 211.199ns tADDHL = 561.469ns 0 10 11 12 500ns/DIV 13 14 15 16 17 SPLIT SUPPLY RAILS (±V) FIGURE 18. TYPICAL ADDRESS TO OUTPUT DELAY (V± = ±15V, +25°C) FIGURE 19. ADDRESS TO OUTPUT DELAY (HIGH TO LOW) 300 250 t ADDLH (ns) 5V/DIV 200 -55°C +125°C 150 1V/DIV +25°C 100 50 0 10 11 12 13 14 15 16 17 tDISABLE = 202.207ns tENABLE = 352.379ns 500ns/DIV SPLIT SUPPLY RAILS (±V) FIGURE 21. TYPICAL ENABLE TO OUTPUT DELAY (V± = ±15V, +25°C) FIGURE 20. ADDRESS TO OUTPUT DELAY (LOW TO HIGH) 400 600 350 500 300 t DISABLE (ns) t ENABLE (ns) 300 400 +125°C 200 +25°C -55°C 250 200 150 100 100 0 10 -55°C +25°C +125°C 50 11 12 13 14 15 16 SPLIT SUPPLY RAILS (±V) FIGURE 22. ENABLE TO OUTPUT DELAY (LOW TO HIGH) Submit Document Feedback 13 17 0 10 11 12 13 14 15 16 17 SPLIT SUPPLY RAILS (±V) FIGURE 23. DISABLE TO OUTPUT DELAY (LOW TO HIGH) FN8735.4 June 3, 2016 ISL71841SEH Typical Performance Curves V± = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 120 100 +125°C 2V/DIV tBBM (ns) 80 60 +25°C 40 1V/DIV -55°C 20 tBBM = 73.425ns 0 10 11 12 13 14 15 16 200ns/DIV SPLIT SUPPLY RAILS (±V) FIGURE 24. TYPICAL BREAK-BEFORE-MAKE DELAY (V± = 15V, +25°C) FIGURE 25. BREAK-BEFORE-MAKE DELAY 160 120 100 120 OFF ISOLATION (dB) OFF ISOLATION (dB) 140 100 80 60 40 80 60 40 20 20 0 100 1k 10k 100k 0 10 10M 1M 100 FREQUENCY (Hz) FIGURE 26. OFF ISOLATION (V± = ±15V, RL = 1kΩ, +25°C) 140 120 120 100 100 80 60 40 1M 80 60 40 20 20 0 1k 10k 100k FREQUENCY (Hz) FIGURE 27. OFF ISOLATION (V± = ±15V, RL = OPEN, +25°C) CROSSTALK (dB) CROSSTALK (dB) 17 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 28. CROSSTALK (V± = ±15V, RL = 1kΩ, +25°C) Submit Document Feedback 14 10M 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 29. CROSSTALK (V± = ±15V, RL = OPEN, +25°C) FN8735.4 June 3, 2016 ISL71841SEH Typical Performance Curves VIN: 5V/div VOUT: 5V/div V± = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) V+ = +12V V- = -12V 100µs/DIV FIGURE 30. OVERVOLTAGE/UNDERVOLTAGE PROTECTION (+25°C) Submit Document Feedback 15 FN8735.4 June 3, 2016 ISL71841SEH Post High Dose Rate Radiation Characteristics (V± = ±15V) Unless otherwise specified, V± = ±15V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a high dose rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. 0 SUPPLY CURRENT SHIFT (µA) SUPPLY CURRENT SHIFT (µA) 7 6 BIASED 5 4 3 GROUNDED 2 1 0 0 20 40 60 80 100 120 140 -1 GROUNDED -2 -3 -4 -6 -7 160 BIASED -5 0 20 1.6 80 100 120 140 160 60 1.4 50 BIASED 1.2 rDS(ON) SHIFT (Ω) SUPPLY CURRENT SHIFT (µA) 60 FIGURE 32. IEE SUPPLY CURRENT SHIFT vs HDR RADIATION FIGURE 31. ICC SUPPLY CURRENT SHIFT vs HDR RADIATION 1.0 0.8 GROUNDED 0.6 0.4 BIASED 40 30 GROUNDED 20 10 0.2 0 0 40 HIGH DOSE RATE RADIATION (krad(Si)) HIGH DOSE RATE RADIATION (krad(Si)) 20 40 60 80 100 120 140 0 160 0 20 40 60 80 100 120 140 160 HIGH DOSE RATE RADIATION (krad(Si)) HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 34. rDS(ON) SHIFT (VIN = V+) vs HDR RADIATION FIGURE 33. IREF SUPPLY CURRENT SHIFT vs HDR RADIATION 25 20 18 16 rDS(ON) SHIFT (Ω) rDS(ON) SHIFT (Ω) 20 BIASED 15 10 5 0 0 40 60 80 100 120 140 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 35. rDS(ON) SHIFT (VIN = +5V) vs HDR RADIATION Submit Document Feedback 16 12 10 8 6 GROUNDED 4 GROUNDED 20 BIASED 14 2 160 0 0 20 40 60 80 100 120 140 160 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 36. rDS(ON) SHIFT (VIN = -5V) vs HDR RADIATION FN8735.4 June 3, 2016 ISL71841SEH Post High Dose Rate Radiation Characteristics (V± = ±15V) Unless otherwise specified, V± = ±15V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a high dose rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. (Continued) 8 250 7 BIASED 200 5 tADDLH SHIFT (ns) rDS(ON) SHIFT (Ω) 6 BIASED 4 3 2 GROUNDED 1 0 150 100 GROUNDED 50 -1 -2 0 20 40 60 80 100 120 140 0 160 0 20 HIGH DOSE RATE RADIATION (krad(Si)) 40 60 80 100 120 140 160 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 37. rDS(ON) SHIFT (VIN = V-) vs HDR RADIATION FIGURE 38. tADD SHIFT (LOW TO HIGH) vs HDR RADIATION 35 60 30 50 BIASED BIASED 20 tBBM SHIFT (ns) tADDHL SHIFT (ns) 25 15 10 5 GROUNDED 40 30 20 GROUNDED 0 10 -5 -10 0 20 40 60 80 100 120 140 0 0 160 20 HIGH DOSE RATE RADIATION (krad(Si)) 40 60 80 100 120 140 160 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 39. tADD SHIFT (HIGH TO LOW) vs HDR RADIATION FIGURE 40. tBBM SHIFT vs HDR RADIATION 50 200 180 160 tDISABLE SHIFT (ns) tENABLE SHIFT (ns) 40 BIASED 30 20 10 GROUNDED 140 BIASED 120 GROUNDED 100 80 60 40 0 20 -10 0 20 40 60 80 100 120 140 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 41. tENABLE SHIFT vs HDR RADIATION Submit Document Feedback 17 160 0 0 20 40 60 80 100 120 140 160 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 42. tDISABLE SHIFT vs HDR RADIATION FN8735.4 June 3, 2016 ISL71841SEH Post High Dose Rate Radiation Characteristics (V± = ±12V) Unless otherwise specified, V± = ±12V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a high dose rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. 0 SUPPLY CURRENT SHIFT (µA) SUPPLY CURRENT SHIFT (µA) 7 6 BIASED 5 4 3 2 GROUNDED 1 0 0 20 40 60 80 100 120 140 -1 GROUNDED -2 -3 -4 -5 BIASED -6 -7 0 160 20 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 43. ICC SUPPLY CURRENT SHIFT vs HDR RADIATION rDS(ON) SHIFT (Ω) SUPPLY CURRENT SHIFT (µA) 50 BIASED 1.2 100 120 140 160 1.0 0.8 GROUNDED 0.6 0.4 BIASED 40 30 20 10 0.2 0 20 40 60 80 100 120 140 0 160 GROUNDED 0 20 HIGH DOSE RATE RADIATION (krad(Si)) 25 25 rDS(ON) SHIFT (Ω) 30 BIASED 15 10 GROUNDED 5 0 20 40 60 80 100 120 140 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 47. rDS(ON) SHIFT (VIN = +5V) vs HDR RADIATION Submit Document Feedback 18 60 80 100 120 140 160 FIGURE 46. rDS(ON) SHIFT (VIN = V+) vs HDR RADIATION 30 20 40 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 45. IREF SUPPLY CURRENT SHIFT vs HDR RADIATION rDS(ON) SHIFT (Ω) 80 60 1.4 0 60 FIGURE 44. IEE SUPPLY CURRENT SHIFT vs HDR RADIATION 1.6 0 40 HIGH DOSE RATE RADIATION (krad(Si)) 20 BIASED 15 10 GROUNDED 5 160 0 0 20 40 60 80 100 120 140 160 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 48. rDS(ON) SHIFT (VIN = -5V) vs HDR RADIATION FN8735.4 June 3, 2016 ISL71841SEH Post High Dose Rate Radiation Characteristics (V± = ±12V) 10 300 8 250 tADDLH SHIFT (ns) rDS(ON) SHIFT (Ω) Unless otherwise specified, V± = ±12V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a high dose rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed. (Continued) 6 BIASED 4 2 0 -2 20 40 60 80 BIASED 150 100 50 GROUNDED 0 200 100 120 140 0 160 GROUNDED 0 20 HIGH DOSE RATE RADIATION (krad(Si)) 60 40 BIASED 50 30 BIASED tBBM SHIFT (ns) tADDHL SHIFT (ns) 35 25 20 15 10 0 20 40 60 80 100 40 30 20 GROUNDED GROUNDED 10 5 120 140 0 160 0 20 HIGH DOSE RATE RADIATION (krad(Si)) 60 80 100 120 140 160 FIGURE 52. tBBM SHIFT vs HDR RADIATION 200 50 180 45 BIASED 160 tDISABLE SHIFT (ns) 40 tENABLE SHIFT (ns) 40 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 51. tADD SHIFT (HIGH TO LOW) vs HDR RADIATION 35 30 25 20 15 GROUNDED 10 BIASED 140 120 GROUNDED 100 80 60 40 20 5 0 160 FIGURE 50. tADD SHIFT (LOW TO HIGH) vs HDR RADIATION FIGURE 49. rDS(ON) SHIFT (VIN = V-) vs HDR RADIATION 0 40 60 80 100 120 140 HIGH DOSE RATE RADIATION (krad(Si)) 0 20 40 60 80 100 120 140 HIGH DOSE RATE RADIATION (krad(Si)) FIGURE 53. tENABLE SHIFT vs HDR RADIATION Submit Document Feedback 19 160 0 0 20 40 60 80 100 120 140 HIGH DOSE RATE RADIATION (krad(Si)) 160 FIGURE 54. tDISABLE SHIFT vs HDR RADIATION FN8735.4 June 3, 2016 ISL71841SEH Post Low Dose Rate Radiation Characteristics (V± = ±15V) Unless otherwise specified, V± = ±15V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. 0 1.0 SUPPLY CURRENT SHIFT (µA) SUPPLY CURRENT SHIFT (µA) 1.2 GROUNDED 0.8 0.6 BIASED 0.4 0.2 0 0 10 20 30 40 50 -0.2 BIASED -0.4 -0.6 -0.8 -1.0 GROUNDED -1.2 -1.4 60 0 FIGURE 55. ICC SUPPLY CURRENT SHIFT vs LDR RADIATION 30 40 50 60 10 8 GROUNDED 2.0 rDS(ON) SHIFT (Ω) SUPPLY CURRENT SHIFT (µA) 20 FIGURE 56. IEE SUPPLY CURRENT SHIFT vs LDR RADIATION 2.5 1.5 BIASED 1.0 BIASED 6 4 2 0 GROUNDED 0.5 0 10 LOW DOSE RATE RADIATION (krad(Si)) LOW DOSE RATE RADIATION (krad(Si)) -2 0 10 20 30 40 50 -4 60 0 LOW DOSE RATE RADIATION (krad(Si)) 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 57. IREF SUPPLY CURRENT SHIFT vs LDR RADIATION FIGURE 58. rDS(ON) SHIFT (VIN = +5V) vs LDR RADIATION 25 6 5 20 BIASED 3 rDS(ON) SHIFT (Ω) rDS(ON) SHIFT (Ω) 4 2 GROUNDED 1 0 -1 -2 15 BIASED 10 5 0 GROUNDED -3 -4 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 59. rDS(ON) SHIFT (VIN = -5V) vs LDR RADIATION Submit Document Feedback 20 60 -5 0 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 60. rDS(ON) SHIFT (VIN = V+) vs LDR RADIATION FN8735.4 June 3, 2016 ISL71841SEH Post Low Dose Rate Radiation Characteristics (V± = ±15V) Unless otherwise specified, V± = ±15V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued) 250 0 BIASED -1 200 -2 rDS(ON) SHIFT (Ω) tADDLH SHIFT (ns) GROUNDED -3 -4 -5 -6 -7 100 50 -8 BIASED -9 -10 0 10 20 30 40 50 0 0 60 LOW DOSE RATE RADIATION (krad(Si)) 60 FIGURE 62. tADD SHIFT (LOW TO HIGH) vs LDR RADIATION 0 14 -40 tBBM SHIFT (ns) -30 BIASED -50 -60 -70 -80 -90 -100 0 GROUNDED 12 -20 tADDHL SHIFT (ns) 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 61. rDS(ON) SHIFT (VIN = V-) vs LDR RADIATION -10 20 30 40 50 8 BIASED 6 4 2 GROUNDED 10 10 0 60 0 LOW DOSE RATE RADIATION (krad(Si)) 300 15 250 tDISABLE SHIFT (ns) BIASED 10 5 GROUNDED 30 40 50 60 BIASED 200 GROUNDED 150 100 50 -5 -10 0 20 FIGURE 64. tBBM SHIFT vs LDR RADIATION 20 0 10 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 63. tADD SHIFT (HIGH TO LOW) vs LDR RADIATION tENABLE SHIFT (ns) GROUNDED 150 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 65. tENABLE SHIFT vs LDR RADIATION Submit Document Feedback 21 60 0 0 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 66. tDISABLE SHIFT vs LDR RADIATION FN8735.4 June 3, 2016 ISL71841SEH Post Low Dose Rate Radiation Characteristics (V± = ±12V) Unless otherwise specified, V± = ±12V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. 0 1.0 SUPPLY CURRENT SHIFT (µA) SUPPLY CURRENT SHIFT (µA) 1.2 GROUNDED 0.8 0.6 BIASED 0.4 0.2 0 0 10 20 30 40 50 -0.2 BIASED -0.4 -0.6 -0.8 -1.0 GROUNDED -1.2 -1.4 60 0 LOW DOSE RATE RADIATION (krad(Si)) 30 60 30 rDS(ON) SHIFT (Ω) GROUNDED 1.5 1.0 BIASED 0.5 25 BIASED 20 15 10 5 0 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) -5 60 GROUNDED 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 60 FIGURE 70. rDS(ON) SHIFT (VIN = V+) vs LDR RADIATION FIGURE 69. IREF SUPPLY CURRENT SHIFT vs LDR RADIATION 8 12 10 6 8 rDS(ON) SHIFT (Ω) BIASED 6 4 2 0 GROUNDED 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 71. rDS(ON) SHIFT (VIN = +5V) vs LDR RADIATION Submit Document Feedback 22 GROUNDED 4 2 BIASED 0 -2 -2 -4 50 35 2.0 0 40 FIGURE 68. IEE SUPPLY CURRENT SHIFT vs LDR RADIATION 2.5 SUPPLY CURRENT SHIFT (µA) 20 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 67. ICC SUPPLY CURRENT SHIFT vs LDR RADIATION rDS(ON) SHIFT (Ω) 10 60 -4 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 60 FIGURE 72. rDS(ON) SHIFT (VIN = -5V) vs LDR RADIATION FN8735.4 June 3, 2016 ISL71841SEH Post Low Dose Rate Radiation Characteristics (V± = ±12V) Unless otherwise specified, V± = ±12V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued) 2 350 0 300 tADDLH SHIFT (ns) rDS(ON) SHIFT (Ω) -2 GROUNDED -4 -6 -8 -10 -12 250 200 100 50 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 0 60 20 16 15 14 10 12 BIASED 5 0 -5 10 8 BIASED 6 2 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 0 60 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 60 FIGURE 76. tBBM SHIFT vs LDR RADIATION 25 300 20 250 tDISABLE SHIFT (ns) BIASED tENABLE SHIFT (ns) 60 GROUNDED FIGURE 75. tADD SHIFT (HIGH TO LOW) vs LDR RADIATION 15 10 5 GROUNDED 0 200 BIASED 150 100 GROUNDED 50 -5 -10 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) 4 GROUNDED -15 -20 0 FIGURE 74. tADD SHIFT (LOW TO HIGH) vs LDR RADIATION tBBM SHIFT (ns) tADDHL SHIFT (ns) FIGURE 73. rDS(ON) SHIFT (VIN = V-) vs LDR RADIATION -10 GROUNDED 150 BIASED 0 BIASED 0 10 20 30 40 50 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 77. tENABLE SHIFT vs LDR RADIATION Submit Document Feedback 23 60 0 0 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 78. tDISABLE SHIFT vs LDR RADIATION FN8735.4 June 3, 2016 ISL71841SEH Applications Information ISL71841SEH vs ISL71840SEH Power-Up Considerations There is a 16-channel version of the ISL71841SEH available in a 28 Ld CDFP. In terms of performance specs, the parts are very similar in behavior. Apart from the apparent increase in channel density, the ISL71841SEH does have slightly higher output leakage compared to the ISL71840SEH due to having more channels connected to the output. The supply current for the ISL71841SEH is also a bit higher compared to the ISL71840SEH. (See Table 1 on page 3.) The circuit is designed to be insensitive to any given power-up sequence between V+, V- and VREF, however, it is recommended that all supplies power-up relatively close to each other. Overvoltage Protection The ISL71841SEH has overvoltage protection on both the input as well as the output. On the output, the voltage is limited to a diode past the rails. Each of the inputs has independent overvoltage protection that works regardless of the switch being selected. If a switch experiences an overvoltage condition (3V to 4V past the rail), the switch is turned off. As soon as the voltage returns within the rails, the switch returns to normal operation. VREF and Logic Functionality The VREF pin sets the logic threshold for the ISL71841SEH. The range for VREF is between 4.5V and 5.5V with a nominal voltage of 5V. The address pins and enable are compared against roughly 30% of VREF voltage (refer to Figure 79). With 5.0V on VREF, the switching point is set to around 1.4V. This switching point allows for both 5V and 3.3V logic control. ISL71841SEH A/EN 400kΩ VREF TO DECODER 200kΩ FIGURE 79. SIMPLIFIED VREF CIRCUITRY Submit Document Feedback 24 FN8735.4 June 3, 2016 ISL71841SEH Die Characteristics Assembly Related Information Die Dimensions SUBSTRATE POTENTIAL Floating 5000µm x 4080µm (197 mils x 161 mils) Thickness: 483µm ±25µm (19 mils ±1 mil) Additional Information Interface Materials WORST CASE CURRENT DENSITY GLASSIVATION 1.6 x 105 A/cm2 Type: 12kÅ Silicon Nitride on 3kÅ Oxide TRANSISTOR COUNT TOP METALLIZATION 10752 Type: 300Å TiN on 2.8µm AlCu In Bondpads, TiN has been removed. Weight of Packaged Device 48 Ld CQFP: 1.54 grams (typical) 44 Ld CLCC: 2.02 grams (typical) BACKSIDE FINISH Silicon Lid Characteristics PROCESS Finish: Gold Potential: Grounded, tied to package GND pin In 48 Ld CQFP: pin 29 In 44 Ld CLCC: pin 26 P6SOI Metalization Mask Layout IN12 IN13 IN14 IN15 IN16 OUT IN32 IN31 IN30 IN29 IN28 IN11 IN27 IN10 IN26 IN9 IN25 IN8 IN24 IN7 IN23 IN6 IN22 IN5 IN21 IN4 IN20 IN3 IN19 IN2 IN18 IN1 Submit Document Feedback V+ VREF 25 A0 A1 A2 A3 A4 EN BAR GND V‐ IN17 FN8735.4 June 3, 2016 ISL71841SEH TABLE 3. ISL71840SEH DIE LAYOUT X-Y COORDINATES PAD NUMBER PAD NAME PACKAGING PIN ΔX (µm) ΔY (µm) X (µm) Y (µm) 1 IN28 P42 122 122 2232.2 1776.05 2 IN29 P43 122 122 1956.5 1772.2 3 IN30 P44 122 122 1529.15 1772.2 4 IN31 P45 122 122 1171.85 1772.2 5 IN32 P46 122 122 816.35 1772.2 9 OUT P1 122 122 7.2 1773.25 11 IN16 P3 122 122.05 -829.525 1772.2 12 IN15 P4 122 122 -1192.2 1772.2 13 IN14 P5 122 122 -1553.65 1772.2 14 IN13 P6 122 122 -1965.35 1772.2 15 IN12 P7 122 122 -2232.2 1775.55 16 IN11 P8 122 122 -2232.2 1343.55 17 IN10 P9 122 122 -2232.2 944.5 18 IN9 P10 122 122 -2232.2 626.15 19 IN8 P11 122 122 -2232.2 354.4 20 IN7 P12 122 122.05 -2232.2 108.275 21 IN6 P13 122 122 -2232.2 -138.75 22 IN5 P14 122 122 -2232.2 -391.8 23 IN4 P15 122 122 -2232.2 -622.95 24 IN3 P16 122 122 -2232.2 -948.55 25 IN2 P17 122 122 -2232.2 -1379.95 26 IN1 P18 122 122 -2232.2 -1775.95 27 V+ P19 122 122 -1970.75 -1789.2 28 VREF P20 122 122 -1558.65 -1789.2 29 A0 P21 122 122 -1196.8 -1789.2 30 A1 P22 122 122 -835.6 -1789.2 31 A2 P23 122 122 -533 -1789.2 32 A3 P24 122 122 -109.45 -1789.2 33 A4 P25 122 122 313.95 -1789.2 37 EN_B P28 122 122 1171.9 -1789.2 38 GND P29, P29 320 122 1525.85 -1789.1 39 V- P30 122 122 1955.7 -1789.2 40 IN17 P31 122 122 2232.2 -1774.95 41 IN18 P32 122 122 2232.2 -1380.25 42 IN19 P33 122 122 2232.2 -947.45 43 IN20 P34 122 122 2232.2 -624.75 44 IN21 P35 122 122 2232.2 -391.95 45 IN22 P36 122 122 2232.2 -139.05 46 IN23 P37 122 122.05 2232.2 107.525 47 IN24 P38 122 122 2232.2 353.6 48 IN25 P39 122 122 2232.2 626.9 49 IN26 P40 122 122 2232.2 943.9 50 IN27 P41 122 122 2232.2 1342.7 NOTE: Origin of coordinates is the center of the die. Submit Document Feedback 26 FN8735.4 June 3, 2016 ISL71841SEH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE June 3, 2016 FN8735.4 Updated Ordering information table on page 3 by updating first column and updating Note 3. Updated bolding in Electrical Specification table and added test conditions to the Break-Before-Make Delay, Enable Turn-On Time and Disable Turn-Off Time specifications. Changed from “VS” to “V±” in the titles of the Typical Performance, Post High and Post Low Dose Rate Radiation Characteristics curve tables. Changed units from mA to µA for Figures 31, 32, 33, 43, 44, 45, 55, 56, 57, 67, 68, 69 April 15, 2016 FN8735.3 Added ISL71841SEHVL and ISL71841SEHL/PROTO details to the Ordering Information table on page 3 and added the applicable packaging information throughout datasheet. Updated the heading for the Low Dose Rate Radiation Characteristics (Vs = ±15V) table on page 20 in third sentence changed from “high” to “low”. Updated the heading for the Low Dose Rate Radiation Characteristics (Vs = ±12V) table on page 22 in third sentence changed from “high” to “low”. December 11, 2015 FN8735.2 Updated Y-axis labels on Figures 31 through 78. Updated crosstalk and off Isolation MIN in Electrical Spec table on page 7 from -75 to 75 (off isolation) and -47 to 47 (crosstalk). Changed all instances of VDD to V+ and VSS to V-. September 29, 2015 FN8735.1 Updated Related Literature on page 1. Updated testing information for ESD tolerances, HBM, CDM and MM in “Absolute Maximum Ratings” on page 5 From: Human Body Model (Tested per MIL-PRF-883 3015.7) Charged Device Model (Tested per MIL-PRF-883 3015.7) Machine Model (Tested per MIL-PRF-883 3015.7) To: Human Body Model (Tested per MIL-STD-883 TM 3015) Charged Device Model (Tested per JESD22-C101D) Machine Model (Tested per JESD22-A115-A) Updated crosstalk and off Isolation MIN in Electrical Spec table on page 7 from -90 to -75 (off isolation) and -47 (crosstalk) Added Figures 26, 28 and 30 and updated figure titles for Figures 27 and 29 on page 14. Updated top metalization thickness and composition in “Die Characteristics” on page 25. Added Table 3 on page 26. June 11, 2015 FN8735.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 27 FN8735.4 June 3, 2016 ISL71841SEH Package Outline Drawing R48.A 48 CERAMIC QUAD FLATPACK PACKAGE (CQFP) Rev 3, 10/12 1.118 (28.40) 1.080 (27.43) 0.572 (14.53) 0.555 (14.10) #1 #48 0.287 (7.29) 0.253 (6.43) 0.040 (1.02) BSC PIN 1 INDEX AREA 0.572 (14.53) 0.555 (14.10) 1.118 (28.40) 1.080 (27.43) 0.007 (0.18) MIN 0.015 (0.38) 0.008 (0.20) 0.015 (0.38) MIN TOP VIEW 0.099 (2.51) 0.076 (1.93) 0.016 (0.41) 0.009 (0.23) SIDE VIEW NOTE: 1. All dimensions are in inches (millimeters). Submit Document Feedback 28 FN8735.4 June 3, 2016 ISL71841SEH Ceramic Leadless Chip Carrier Packages (CLCC) J44.A MIL-STD-1835 CQCC1-N44 (C-5) 44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE 0.010 S E H S D INCHES D3 SYMBOL j x 45o E3 B E h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1 -E- B1 e L -H- L3 MILLIMETERS MAX MAX NOTES 6, 7 A 0.064 0.120 1.63 3.05 0.054 0.088 1.37 2.24 - B 0.033 0.039 0.84 0.99 4 B1 0.022 0.028 0.56 0.71 2, 4 B2 0.072 REF 1.83 REF - B3 0.006 0.022 0.15 0.56 - D 0.640 0.662 16.26 16.81 - D1 0.500 BSC 12.70 BSC - D2 0.250 BSC 6.35 BSC - D3 - 0.662 E 0.640 0.662 16.26 16.81 2 16.81 - E1 0.500 BSC 12.70 BSC - E2 0.250 BSC 6.35 BSC - E3 e - 0.662 0.050 BSC 0.015 - - 16.81 2 1.27 BSC 0.38 - 2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.90 2.41 - L3 0.003 0.015 0.08 0.38 ND 11 - 11 3 NE 11 11 3 N 44 44 3 -F- Rev. 0 5/18/94 B3 E1 E2 MIN A1 e1 0.007 M E F S H S MIN 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. L2 B2 L1 D2 e1 D1 NOTES: 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. Submit Document Feedback 29 FN8735.4 June 3, 2016