Cypress MB91F592BPMC-GSE1 Fr family fr81s 32-bit microcontroller Datasheet

The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
How to Check the Ordering Part Number
1. Go to www.cypress.com/pcn.
2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click
Apply.
3. Click the corresponding title from the search results.
4. Download the Affected Parts List file, which has details of all changes
For More Information
Please contact your local sales office for additional information about Cypress products and
solutions.
About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB91590 Series
FR Family FR81S 32-Bit Microcontroller
This series is Cypress 32-bit microcontroller designed for automotive and industrial control applications. It contains the FR81S CPU
that is compatible with the FR family. The FR81S has a high level performance among the Cypress FR family by enhancing CPU
instruction pipeline and load store processing, and improving internal bus transfer.
It is best suited for application control for automotive.
Features
FR81S CPU Core
Peripheral Functions
 32-bit RISC, load/store architecture, pipeline 5-stage
 Clock generation (equipped with SSCG function)
structure
 Main
oscillation (4MHz)
oscillation (32kHz) or none sub oscillation
 PLL multiplication rate : 1 to 32 times
 Sub
 Maximum operating frequency:
128 MHz (Source oscillation = 4.0 MHz and 32 multiplied
(PLL clock multiplication system))
It shows maximum CPU frequency of series. The
specification of each part number can be referred in
“Product Lineup” and “Electrical Characteristics.”
 General-purpose register : 32 bits ×16 sets
 Built-in Program flash memory capacity 2048 + 64KB (series
maximum)
 Built-in Data flash memory capacity(WorkFlash) 64KB
 Built-in RAM capacity
 Main
RAM
RAM (on AHB)
 Backup RAM
 Sub
 16-bit fixed length instructions (basic instruction),
1 instruction per cycle
 Instructions appropriate to embedded applications
transfer instruction
 Bit processing instruction
 Barrel shift instruction etc.
 General-purpose ports (5V Pin) : 63
(dual clock products : 61)
2
 Included I C pseudo open drain support ports : 4
 Memory-to-memory
 General-purpose ports (3V Pin) : 93
 Included
48 combined external bus interface (For GDC
external memory I/F)
 High-level language support instructions
 Function
entry/exit instructions
 Register content multi-load and store instructions
 External bus interface
 GDC
external memory for I/F use
address, 16-bit data
 Power supply voltage fixed to 3.3V
 Bit search instructions
 25-bit
 Logical
1 detection, 0 detection, and change-point
detection
 DMA Controller
 Branch instructions with delay slot
 Reduced
 Up
overhead during branch process
2
 Register interlock function
 Easy
 8/10-bit
 The support at the built-in / instruction level of the multiplier
 Signed
32-bit multiplication : 5 cycles
16-bit multiplication : 3 cycles
32 channels
3μs
 External interrupt input: 16 channels
 Level
("H" / "L"), or edge detection (rising or falling)
enabled
cycles (16 priority levels)
 The Harvard architecture allows simultaneous execution of
 LIN-UART
program and data access.
6
channels, ch.2 to ch.7
synchronous mode, LIN-UART mode is selectable.
 LIN protocol Revision 2.1 is supported
 SPI (Serial Peripheral Interface) supported (synchronous
mode)
 Full-duplex double buffering system
 LIN synch break detection (linked to the input capture)
 Built-in dedicated baud rate generator
 DMA transfer support
 UART,
 Instruction compatibility with the FR Family
 Built-in memory protection function (MPU)
 Eight
protection areas can be specified commonly for
instructions and the data.
 Control access privilege in both privilege mode and user
mode.
 Built-in FPU (floating point arithmetic)
 IEEE754
resolution :
time :
 Conversion
 Interrupt (PC/PS saving)
6
to 16 channels can be started simultaneously.
transfer factors (Internal peripheral request and software)
 A/D converter (successive approximation type)
assembler writing
 Signed
192KB (Series maximum)
64KB (Series maximum)
8KB
compliant
register 32-bit × 16 sets
 Floating-point
Cypress Semiconductor Corporation
Document Number: 002-04727 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 1, 2017
MB91590 Series
 Multi-function serial communication (built-in
transmission/reception FIFO memory) :
 2 channels for MB91F591/2/4/6/7/9
 6 channels for MB91F59A/B
< UART (Asynchronous serial interface) >
• Full-duplex double buffering system, 16-byte
transmission FIFO memory, 16-byte reception FIFO
memory
• Parity or no parity is selectable.
• Built-in dedicated baud rate generator
• An external clock can be used as the transfer clock
• Parity, frame, and overrun error detect functions provided
• DMA transfer support
 Free-run timer :
 32-bit
× 2 channels (Can select each channel for input
capture, output compare) for MB91F591/2/4/6/7/9
 32-bit × 2 channels (LSYN (LIN synch field detection) for
exclusive input capture) for MB91F591/2/4/6/7/9
 32-bit × 8 channels (Can select ch.0, 1, 2, and 3 for input
capture, output compare) for MB91F59A/B
 Input capture :
 32-bit
× 6 channels (linked to the free-run timer) for
MB91F591/2/4/6/7/9
 32-bit × 2 channels (linked to the free-run timer) LSYN (LIN
synch field detected) Exclusive for MB91F591/2/4/6/7/9
 32-bit × 12 channels (linked to the free-run timer) LSYN
(LIN synch field detected) for MB91F59A/B
<CSIO (Synchronous serial interface) >
• Full-duplex double buffering system, 16-byte
transmission FIFO memory, 16-byte reception FIFO
memory
• SPI supported; master and slave systems supported; 5 to
9-bit data length can be set.
• Built-in dedicated baud rate generator (Master operation)
• An external clock can be entered. (Slave operation)
• Overrun error detect function is provided
• DMA transfer support
 Output compare : 32-bit × 4 channels (linked to the free-run
<LIN-UART (Asynchronous Serial Interface for LIN) >
• Full-duplex double buffering system, 16-byte
transmission FIFO memory, 16-byte reception FIFO
memory
• LIN protocol Revision 2.1 supported
• Master and slave systems supported
• Framing error and overrun error detection
• LIN synch break generation and detection; LIN synch
delimiter generation
• Built-in dedicated baud rate generator
• An external clock can be adjusted by the reload counter
• DMA transfer support
 Real-time clock (RTC) (for day, hours, minutes, seconds)
< I 2C >
• ch.0 and ch.1 only supported
• Full-duplex double buffering system, 16-byte
transmission FIFO memory, 16-byte reception FIFO
memory
• Standard mode (Max. 100kbps) / high-speed mode (Max.
400kbps) supported
• DMA transfer supported (for transmission only)
 CAN Controller (C-CAN) : 3 channels
 Transfer
speed : Up to 1Mbps
message buffering : 1 channel,
32-transmission/reception message buffering : 2 channels
 64-transmission/reception
timer)
 Sound generator : 5 channels
 Frequency
and amplitude sequencers provided
 Stepping motor controller : 6 channels
 8/10-bit
PWM
current output supported (4 lines × 6 channels)
 Can refer back electromotive force using pin-shared A/D
converter
 High
 Main/sub
oscillation frequency can be selected for the
operation clock (dual product only)
 Calibration: The hardware watchdog for CR oscillation drive
and real-time clock (RTC) for sub clock drive (dual product
only)
 The CR oscillation frequency can be trimmed
 The main clock to sub clock (dual product only) ratio can
be corrected by setting the real-time clock prescaler
 Clock Supervisor
 Monitoring
abnormality (damage of crystal etc.) of sub
oscillation (32kHz) (two system clock kinds) of the outside
and main oscillation (4 MHz)
 When abnormality is detected, it switches to the CR clock.
 Base timer : 2 channels
 16-bit
timer
of four PWM/PPG/PWC/reload timer functions can be
selected and used
 As for the functions of PWC and reload timer, 2 channels of
cascade mode can be used as 32-bit timer.
 Any
 CRC generation
 Watchdog timer
 Hardware
 Software
watchdog
watchdog
 Up/down counter: 16-bit × 3 channels for MB91F59A/B
 NMI
 PPG : 16-bit × 24 channels
 Interrupt controller
 Reload timer :
 Interrupt request batch read
 16-bit
× 4 channels for MB91F591/2/4/6/7/9
 16-bit × 8 channels for MB91F59A/B
Document Number: 002-04727 Rev. *B
 Multiple
interrupts from peripherals can be read by a series
of registers.
Page 2 of 174
MB91590 Series
 I/O relocation
 Peripheral
function pins can be reassigned.
 Low-power consumption mode
 Sleep
/ Stop / Watch / Sub RUN mode
(power shutdown) / Watch (power shutdown) mode
 GDC part self-support power supply
 Stop
 Power on reset
 Low-voltage detection reset(external low-voltage detection)
 Low-voltage detection reset(internal low-voltage detection)
 GDC
 Internal/memory
frequency : 81MHz
resolution of the display which can support : 800 × 480
at the maximum
Screen overlay of five simultaneous layers at the maximum
(window)
Size of the resolution which can be supported varies
depending on color format.
 Analog video input (NTSC)
 Digital video input (RGB666/555)
 YUV input (BT.656)
 Video image expansion/reduction /invert function is
supported
 RGB Digital output (6-bit × 3)
 Built-in 2D rendering engine
The line drawing is supported.
The Bitblt function is supported.
Display list operation is supported
8bpp indirect color
ARGB-1555 direct color
Alpha blending, anti-aliasing
 The
Document Number: 002-04727 Rev. *B
 Built-in
Sprite engine
Equipped with automatic display function when booted
Maximum of 512 sprites are supported
32 special sprites capable of automatic animation are
supported.
The command list execution is supported.
1bpp, 2bpp, 4bpp, 8bpp indirect color
ARGB-1555, RGB-565, ARGB-8888 direct color
The color format for each sprite can be set.
Horizontal invert, Vertical invert
Alpha blending
 Built-in memory
• 800KB(MB91F591/2/4/6/7/9)
• 1792KB(MB91F59A/B)
 HS-SPI(MB91F59A/B)
 Device Package : LQFP-208, HQFP-208*, BGA320,
TEQFP-208*
 CMOS 90nm Technology
 Power supplies
 5V/3.3V
Power supply
internal 1.2V is generated from 5V/3.3V with the
voltage step-down circuit.
 I/O of an external bus and GDC, 3.3V power supply used.
 For other I/O, 5V power supply used.
 If 2 power supplies are used, they must turn on in the
specified sequence (5V →3.3V).
 The
*: Under consideration. For detailed information about mount
conditions, contact your sales representative.
Page 3 of 174
MB91590 Series
Contents
1. Product Lineup .................................................................................................................................................................. 5
2. Pin Assignment ............................................................................................................................................................... 11
2.1
Pin Assignment (MB91F591/2/4/6/7/9 Single Clock Product)...................................................................................... 11
2.2
Pin Assignment (MB91F591/2/4/6/7/9 dual Clock Product) ......................................................................................... 12
2.3
Pin Assignment (MB91F59A/B Single Clock Product) ................................................................................................. 13
2.4
Pin Assignment (MB91F59A/B dual Clock Product) .................................................................................................... 14
2.5
Pin Assignment (BGA Product) ................................................................................................................................... 15
3. Pin Description ................................................................................................................................................................ 16
3.1
Pin Description of LQFP-208/TEQFP-208 ................................................................................................................... 16
3.2
MB91F59A/B (BGA320) .............................................................................................................................................. 30
4. I/O Circuit Type ............................................................................................................................................................... 45
5. Handling Precautions ..................................................................................................................................................... 50
5.1
Precautions for Product Design ................................................................................................................................... 50
5.2
Precautions for Package Mounting .............................................................................................................................. 51
5.3
Precautions for Use Environment ................................................................................................................................ 52
6. Handling Devices ............................................................................................................................................................ 53
7. Block Diagram ................................................................................................................................................................. 56
8. Memory Map .................................................................................................................................................................... 58
9. I/O Map ............................................................................................................................................................................. 68
10. Interrupt Vector Table ................................................................................................................................................... 106
11. Electrical Characteristics ............................................................................................................................................. 109
11.1 Absolute Maximum Ratings ....................................................................................................................................... 109
11.2 Recommended Operating Conditions ....................................................................................................................... 111
11.3 DC Characteristics .................................................................................................................................................... 112
11.4 AC Characteristics ..................................................................................................................................................... 119
11.4.1 Main Clock Timing...................................................................................................................................................... 119
11.5 A/D Converter ............................................................................................................................................................ 163
11.5.1 Electrical Characteristics ............................................................................................................................................ 163
11.5.2 Definition of A/D Converter Terms ............................................................................................................................. 164
11.5.3 Notes on Using A/D Converter ................................................................................................................................... 166
11.6 Flash Memory ............................................................................................................................................................ 167
11.6.1 Electrical Characteristics ............................................................................................................................................ 167
11.6.2 Notes .......................................................................................................................................................................... 167
12. Ordering Information .................................................................................................................................................... 168
13. Package Dimensions .................................................................................................................................................... 169
14. Major Changes .............................................................................................................................................................. 172
Document History ............................................................................................................................................................... 173
Sales, Solutions, and Legal Information........................................................................................................................... 174
Products .............................................................................................................................................................................. 174
PSoC® Solutions ................................................................................................................................................................. 174
Cypress Developer Community......................................................................................................................................... 174
Technical Support .............................................................................................................................................................. 174
Document Number: 002-04727 Rev. *B
Page 4 of 174
MB91590 Series
1. Product Lineup
Product
Item
CPU core
Technology
Package
Sub clock
Maximum CPU operating frequency
Maximum GDC operating frequency
Built-in CR oscillator
System clock
Main
Flash
Work
Main
RAM
Backup
VRAM
Watchdog timer
Clock supervisor
Low-voltage detection reset
(External low-voltage detection)
Low-voltage detection reset
(Internal low-voltage detection)
NMI function
DMA Controller
CAN
LIN-UART
Multi-function Serial Interface
A/D converter (8bit/10bit)
Reload timer(16bit)
Base timer(16bit)
Free-run timer(32bit)
Input capture(32bit)
Output compare(32bit)
PPG timer(16bit)
Sound generator
Real-time clock
External interrupt
CR/SUB compensation function
CRC generation
Stepping motor control
Stop mode (including power shut-off)
Power supply voltage
Operating temperature
Allowable power [mW]
Others
On chip debugger
Document Number: 002-04727 Rev. *B
MB91F591B/BS
FR81S
90nm
LQFP208
Yes (Non-S series)
No (S series)
80MHz
81MHz
100kHz
On chip PLL
576KB
64KB
40KB
8KB
260KB
1ch Hardware
1ch Software
Initial value "ON"
MB91F591BH/BHS
Initial value "OFF"
Yes
Yes
Yes
16ch
1ch (64msg)
2ch (32msg)
6ch
2ch
1unit/32ch
4ch
2ch
2ch
6ch
4ch
24ch
5ch
Yes
16ch
Yes
Yes
6ch
Supported
MICOM : 4.5V to 5.5V
GDC : 3.0V to 3.6V
-40°C to +105°C
1250
Flash product
Yes
Page 5 of 174
MB91590 Series
Product
Item
CPU core
Technology
Package
Sub clock
Maximum CPU operating
frequency
Maximum GDC operating
frequency
Built-in CR oscillator
System clock
Main
Flash
Work
Main
RAM
Backup
VRAM
Watchdog timer
Clock supervisor
Low-voltage detection reset
(External low-voltage detection)
Low-voltage detection reset
(Internal low-voltage detection)
NMI function
DMA Controller
MB91F592B
/BS
FR81S
90nm
LQFP208
Yes (Non-S series)
No (S series)
MB91F592BH
/BHS
MB91F594B
/BS
MB91F594BH
/BHS
80MHz
81MHz
100kHz
On chip PLL
576KB
64KB
40KB
8KB
800KB
1ch Hardware
1ch Software
Initial value
"ON"
1088KB
64KB
Initial value
"OFF"
Initial value
"ON"
Initial value
"OFF"
Yes
Yes
Yes
16ch
1ch (64msg)
CAN
2ch (32msg)
LIN-UART
6ch
Multi-function Serial Interface
2ch
A/D converter (8bit/10bit)
1unit/32ch
Reload timer(16bit)
4ch
Base timer(16bit)
2ch
Free-run timer(32bit)
2ch
Input capture(32bit)
6ch
Output compare(32bit)
4ch
PPG timer(16bit)
24ch
Sound generator
5ch
Real-time clock
Yes
External interrupt
16ch
CR/SUB compensation function Yes
CRC generation
Yes
Stepping motor control
6ch
Stop mode (including power
Supported
shut-off)
MICOM:4.5V to 5.5V
Power supply voltage
GDC:3.0V to 3.6V
Operating temperature
-40°C to +105°C
Allowable power [mW]
1250
Others
Flash product
On chip debugger
Yes
Document Number: 002-04727 Rev. *B
Page 6 of 174
MB91590 Series
Product
Item
CPU core
Technology
Package
Sub clock
Maximum CPU operating
frequency
Maximum GDC operating
frequency
Built-in CR oscillator
System clock
Main
Flash
Work
Main
RAM
Backup
VRAM
Watchdog timer
Clock supervisor
Low-voltage detection reset
(External low-voltage
detection)
Low-voltage detection reset
(Internal low-voltage
detection)
NMI function
DMA Controller
CAN
LIN-UART
Multi-function Serial
Interface
A/D converter (8bit/10bit)
Reload timer(16bit)
Base timer(16bit)
Free-run timer(32bit)
Input capture(32bit)
Output compare(32bit)
PPG timer(16bit)
Sound generator
Real-time clock
External interrupt
CR/SUB compensation
function
CRC generation
Stepping motor control
Stop mode
(including power shut-off)
Power supply voltage
Operating temperature
Allowable power [mW]
Others
On chip debugger
MB91F596B
/BS*
FR81S
90nm
HQFP208
Yes (Non-S series)
No (S series)
MB91F596BH
/BHS*
MB91F597B
/BS*
MB91F597BH
/BHS*
128MHz
81MHz
100kHz
On chip PLL
576KB
64KB
40KB
8KB
260KB
1ch Hardware
1ch Software
Initial value
"ON"
800KB
Initial value
"OFF"
Initial value
"ON"
Initial value
"OFF"
Yes
Yes
Yes
16ch
1ch (64msg)
2ch (32msg)
6ch
2ch
1unit/32ch
4ch
2ch
2ch
6ch
4ch
24ch
5ch
Yes
16ch
Yes
Yes
6ch
Supported
MICOM:4.5V to 5.5V
GDC:3.0V to 3.6V
-40°C to +105°C
2500
Flash product
Yes
*: Under consideration. For detailed information about mount conditions, contact your sales representative.
Document Number: 002-04727 Rev. *B
Page 7 of 174
MB91590 Series
Product
Item
CPU core
Technology
Package
Sub clock
Maximum CPU operating frequency
Maximum GDC operating frequency
Built-in CR oscillator
System clock
Main
Flash
Work
Main
RAM
Backup
VRAM
Watchdog timer
Clock supervisor
Low-voltage detection reset
(External low-voltage detection)
Low-voltage detection reset
(Internal low-voltage detection)
NMI function
DMA Controller
CAN
LIN-UART
Multi-function Serial Interface
A/D Converter (8bit/10bit)
Reload timer(16bit)
Base timer(16bit)
Free-run timer(32bit)
Input capture(32bit)
Output compare(32bit)
PPG timer(16bit)
Sound generator
Real-time clock
External interrupt
CR/SUB compensation function
CRC generation
Stepping motor control
Stop mode (including power shut-off)
Power supply voltage
Operating temperature
Allowable power [mW]
Others
On chip debugger
MB91F599B/BS*
FR81S
90nm
HQFP208
Yes (Non-S series)
No (S series)
128MHz
81MHz
100kHz
On chip PLL
1088KB
64KB
64KB
8KB
800KB
1ch Hardware
1ch Software
Initial value "ON"
MB91F599BH/BHS*
Initial value "OFF"
Yes
Yes
Yes
16ch
1ch (64msg)
2ch (32msg)
6ch
2ch
1unit/32ch
4ch
2ch
2ch
6ch
4ch
24ch
5ch
Yes
16ch
Yes
Yes
6ch
Supported
MICOM:4.5V to 5.5V
GDC:3.0V to 3.6V
-40°C to +105°C
2500
Flash product
Yes
*: Under consideration. For detailed information about mount conditions, contact your sales representative.
Document Number: 002-04727 Rev. *B
Page 8 of 174
MB91590 Series
Product
Item
CPU core
Technology
Package
Sub clock
Maximum CPU operating
frequency
Maximum GDC operating
frequency
Built-in CR oscillator
System clock
Main
Flash
Work*2
Main
Sub on
RAM
AHB
Backup
VRAM
Watchdog timer
Clock supervisor
Low-voltage detection reset
(External low-voltage detection)
Low-voltage detection reset
(Internal low-voltage detection)
NMI function
DMA Controller
MB91F59AC
/F59ACS
MB91F59ACH
/F59ACHS
MB91F59BC
/F59BCS
MB91F59BCH
/F59BCHS
FR81S
90nm
BGA320/TEQFP-208*1
Yes (Non-S series)
No (S series)
128MHz
81MHz
100kHz
On chip PLL
1600KB
64KB
192KB
2112KB
64KB
8KB
1792KB
1ch Hardware
1ch Software
Initial value
"ON"
Initial value
"OFF"
Initial value
"ON"
Initial value
"OFF"
Yes
Yes
Yes
16ch
1ch (64msg)
CAN
2ch (32msg)
LIN-UART
6ch
Multi-function Serial Interface
6ch*3
High Speed SPI (GDC)
Yes
A/D converter (8bit/10bit)
1unit/32ch
Up/down counter(16bit)
3ch
Reload timer(16bit)
8ch
Base timer(16bit)
2ch
Free-run timer(32bit)
8ch
Input capture(32bit)
12ch
Output compare(32bit)
4ch
PPG timer(16bit)
24ch
Sound generator
5ch
Real-time clock
Yes
External interrupt
16ch
CR/SUB compensation function Yes
CRC generation
Yes
Stepping motor control
6ch
Stop mode (including power
Supported
shut-off)
MICOM:4.5V to 5.5V
Power supply voltage
GDC:3.0V to 3.6V
Operating temperature
-40°C to +105°C
Allowable power [mW]
2500
Others
Flash product
Yes
JTAG Boundary Scan Test
(Only support BGA package products)
On chip debugger
Yes
Document Number: 002-04727 Rev. *B
Page 9 of 174
MB91590 Series
*1
:Under consideration.
*2
: Start address of Work Flash memory is different between MB91F591/2/4/6/7/9 and MB91F59A/B.
*3
: I2C is supported with ch.0 and ch.1 only.
Main difference of functionality between MB91F594 and MB91F59B
Part
MCU part
GDC part
Item
FLASH (main)
RAM (Main)
RAM (Sub on AHB)
Multi-function Serial Interface
Free-run timer
Input Capture
Reload timer
Up/down counter
Package
1088KB
64KB
2ch
2ch
6ch
4ch
LQFP208
MB91F594
JTAG Boundary Scan Test
-
VRAM
High Speed SPI
800KB
-
MB91F59B
2112KB
192KB
64KB
6ch
8ch
12ch
8ch
3ch
BGA320/TEQPF-208*
Yes
(Only support BGA package
products)
1792KB
Yes
*: Under consideration.
Document Number: 002-04727 Rev. *B
Page 10 of 174
MB91590 Series
2. Pin Assignment
2.1
Pin Assignment (MB91F591/2/4/6/7/9 Single Clock Product)
PPG0_1
PPG9_1
PPG4_2
PPG3_2
PPG7_2
ICU5_1
ICU4_1
ICU1_1
TOT2
TOT1
TOT0
TIN3
TIN2
TIN1
TIN0
-
PPG6_2
PPG5_2
-
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VSS
AVCC3
AVSS3
VIN
REFOUT
AVR3
AVSS3
AVCC3
PG0
PG3
PG2
PG1
PH3
PC7
PC6
PC5
PC4
PC3
PC2
VCC3
VSS
PB7
PB6
PB5
PB4
PB3
PB2
PA7
PA6
PA5
PA4
PA3
PA2
VCC3
VSS
VCC5
P136
P137
VSS
MD2
P122
P121
P120
P117
P116
P115
P114
P097
P094
P113
P112
P090
DCKIN CMDTRG CSOUT HSIN
VSIN
CCLK BIN7
BIN6
BIN5
BIN4
BIN3
BIN2
GIN7
GIN6
GIN5
GIN4
GIN3
VIN7
GIN2
VIN6
RIN7
VIN5
RIN6
VIN4
RIN5
VIN3
RIN4
VIN2
RIN3
VIN1
RIN2
VIN0
(Single clock product)
(Single clock product)
OCU0 SCK5
TOT3
FRCK0 SOT5
INT7
FRCK1 SIN5
INT6
SGO3 SCK4
TRG4
SGA3 SOT4
SGO2 SIN4
SGA2 SCK3
TRG3
WOT
SOT3
INT8
SGO1 SIN3
INT15
RX2
INT11
TX2
ADTG
PPG0_2
-
-
(TOP VIEW)
●
-
-
-
-
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
-
TIN0_2
TIN1_2
TIN2_2
TIN3_2
TOT0_2
TOT1_2
TOT2_2
TOT3_2
-
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
- GOUT2
- GOUT3
- GOUT4
- GOUT5
- GOUT6
- GOUT7
BOUT2
BOUT3
BOUT4
BOUT5
BOUT6
BOUT7
- DCKOUT
- VSYNC
- HSYNC
- DEOUT
SIN2_1
D0
SOT2_1
D1
SCK2_1
D2
SIN3_1
D3
SOT3_1
D4
SCK3_1
D5
D6
D7
D8
ROUT0
D9
ROUT1
D10
GOUT0
D11
GOUT1
D12
BOUT0
D13
BOUT1
D14
D15
WEX
CS0X
CS1X
REX
A00
-
VCC3
PD2
PD3
PD4
PD5
PD6
PD7
PE2
PE3
PE4
PE5
PE6
PE7
PF2
PF3
PF4
PF5
VCC3
VSS
C_3
PF6
PF7
PG4
PG5
PG6
PG7
P000
P001
P002
P003
P004
P005
P006
P007
P010
VSS
VCC3
P011
P012
P013
P014
P015
P016
P017
P020
P021
P022
P023
P024
P025
P026
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
FR+GDC
TOP VIEW
LQFP-208 / HQFP-208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
DVCC
DVSS
P087
PWM2M5
P086
PWM2P5
P085
PWM1M5
P084
PWM1P5
P083
PWM2M4
P082
PWM2P4
P081
PWM1M4
P080
PWM1P4
DVCC
DVSS
P077
PWM2M3
P076
PWM2P3
P075
PWM1M3
P074
PWM1P3
P073
PWM2M2
P072
PWM2P2
P071
PWM1M2
P070
PWM1P2
DVCC
DVSS
P067
PWM2M1
P066
PWM2P1
P065
PWM1M1
P064
PWM1P1
P063
PWM2M0
P062
PWM2P0
P061
PWM1M0
P060
PWM1P0
DVCC
DVSS
C_1
VSS
VCC5
P107
SGO4_1
P106
SGA4_1
P105
SCK5_1
P104
SOT5_1
P103
SIN5_1
P102
SCK4_1
P101
SOT4_1
P100
SIN4_1
AVSS5/AVRL5 AVRH5
AVCC5
P125
OCU3
P124
OCU2
P123
OCU1
P096
RX0
P095
TX0
VCC5
-
AN31
AN30
AN29
AN28
AN27
AN26
AN25
AN24
AN23
AN22
AN21
AN20
AN19
AN18
AN17
AN16
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
-
ICU4_2
ICU3_2
ICU2_2
ICU1_2
ICU0_2
SCK6
SOT6
SIN6
SCK7_1
SOT7_1
SIN7_1
TOT1_1
TOT0_1
TIN3_1
TIN2_1
TIN1_1
TIN0_1
INT9
-
PPG23
PPG22
PPG21
PPG20
PPG19
PPG18
PPG17
PPG16
PPG15_1
PPG14_1
PPG13_1
PPG12_1
ICU0
ICU5_2
-
-
PPG5_1
PPG4_1
PPG3_1
PPG2_1
PPG1_1
PPG10
PPG9
PPG8
PPG10_2
PPG9_2
PPG8_2
PPG10_1
-
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VSS
DEBUGIF
P111
P110
P093
P092
P091
NMIX
P134
P133
P132
P131
P130
P127
P126
VCC5
VSS
RSTX
MD0
MD1
X0
X1
VSS
P057
P056
P055
P054
P053
P052
P051
P050
C_2
VSS
VCC3
P047
P046
P045
P044
P043
P042
P041
P040
P037
P036
P035
P034
P033
P032
P031
P030
P027
VCC3
RX1
TX1
SGA1
SGO0
SGA0
TRG2
TRG5
TRG1
TRG0
RDY
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
SOT2
SCK2
SIN2
PPG1_3
PPG11_1
SCK0
SOT0
SIN0
SPI_XCS
SPI_SCK
SPI_DI
SPI_DO
INT10
INT14
INT13
INT12
SCK1
SOT1
SIN1
ICU3_1
TOT3_1 ICU0_1
TOT2_1 ICU2_1
INT5
ICU5
INT3
ICU4
INT2
ICU3
INT4
ICU2
INT0
ICU1
INT1
PPG2_2
PPG1_2
PPG8_1
PPG7_1
PPG6_1
TIOB1
TIOB0
TIOA1
TIOA0
-
-
-
Document Number: 002-04727 Rev. *B
Page 11 of 174
MB91590 Series
2.2
Pin Assignment (MB91F591/2/4/6/7/9 dual Clock Product)
PPG0_1
PPG9_1
PPG4_2
PPG3_2
PPG6_2
PPG5_2
PPG7_2
ICU5_1
ICU4_1
ICU1_1
VSS
MD2
P122
P121
P120
P117
P116
P115
P114
P097
P094
P113
P112
P090
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VSS
AVCC3
AVSS3
VIN
REFOUT
AVR3
AVSS3
AVCC3
PG0
PG3
PG2
PG1
PH3
PC7
PC6
PC5
PC4
PC3
PC2
VCC3
VSS
PB7
PB6
PB5
PB4
PB3
PB2
PA7
PA6
PA5
PA4
PA3
PA2
VCC3
VSS
VCC5
DCKIN
CSOUT
HSIN
VSIN
CCLK
BIN7
BIN6
BIN5
BIN4
BIN3
BIN2
GIN7
GIN6
GIN5
GIN4
GIN3
GIN2
RIN7
RIN6
RIN5
RIN4
RIN3
RIN2
(X1A)
(X0A)
OCU0
FRCK0
FRCK1
SGO3
SGA3
SGO2
SGA2
WOT
SGO1
RX2
TX2
-
CMDTRG VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0
(Dual clock product)
(Dual clock product)
SCK5
TOT3
SOT5
INT7
TOT2
SIN5
INT6
TOT1
SCK4
TRG4
TOT0
SOT4
TIN3
SIN4
TIN2
SCK3
TRG3
TIN1
SOT3
INT8
TIN0
SIN3
INT15
INT11
ADTG
PPG0_2 -
-
-
(TOP VIEW)
●
-
-
-
-
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
-
TIN0_2
TIN1_2
TIN2_2
TIN3_2
TOT0_2
TOT1_2
TOT2_2
TOT3_2
-
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
- GOUT2
- GOUT3
- GOUT4
- GOUT5
- GOUT6
- GOUT7
BOUT2
BOUT3
BOUT4
BOUT5
BOUT6
BOUT7
- DCKOUT
- VSYNC
- HSYNC
- DEOUT
SIN2_1
D0
SOT2_1
D1
SCK2_1
D2
SIN3_1
D3
SOT3_1
D4
SCK3_1
D5
D6
D7
D8
ROUT0
D9
ROUT1
D10
GOUT0
D11
GOUT1
D12
BOUT0
D13
BOUT1
D14
D15
WEX
CS0X
CS1X
REX
A00
-
VCC3
PD2
PD3
PD4
PD5
PD6
PD7
PE2
PE3
PE4
PE5
PE6
PE7
PF2
PF3
PF4
PF5
VCC3
VSS
C_3
PF6
PF7
PG4
PG5
PG6
PG7
P000
P001
P002
P003
P004
P005
P006
P007
P010
VSS
VCC3
P011
P012
P013
P014
P015
P016
P017
P020
P021
P022
P023
P024
P025
P026
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
FR+GDC
TOP VIEW
LQFP-208 / HQFP-208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
DVCC
DVSS
P087
PWM2M5
P086
PWM2P5
P085
PWM1M5
P084
PWM1P5
P083
PWM2M4
P082
PWM2P4
P081
PWM1M4
P080
PWM1P4
DVCC
DVSS
P077
PWM2M3
P076
PWM2P3
P075
PWM1M3
P074
PWM1P3
P073
PWM2M2
P072
PWM2P2
P071
PWM1M2
P070
PWM1P2
DVCC
DVSS
P067
PWM2M1
P066
PWM2P1
P065
PWM1M1
P064
PWM1P1
P063
PWM2M0
P062
PWM2P0
P061
PWM1M0
P060
PWM1P0
DVCC
DVSS
C_1
VSS
VCC5
P107
SGO4_1
P106
SGA4_1
P105
SCK5_1
P104
SOT5_1
P103
SIN5_1
P102
SCK4_1
P101
SOT4_1
P100
SIN4_1
AVSS5/AVRL5 AVRH5
AVCC5
P125
OCU3
P124
OCU2
P123
OCU1
P096
RX0
P095
TX0
VCC5
-
AN31
AN30
AN29
AN28
AN27
AN26
AN25
AN24
AN23
AN22
AN21
AN20
AN19
AN18
AN17
AN16
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
-
ICU4_2
ICU3_2
ICU2_2
ICU1_2
ICU0_2
SCK6
SOT6
SIN6
SCK7_1
SOT7_1
SIN7_1
TOT1_1
TOT0_1
TIN3_1
TIN2_1
TIN1_1
TIN0_1
INT9
-
PPG23
PPG22
PPG21
PPG20
PPG19
PPG18
PPG17
PPG16
PPG15_1
PPG14_1
PPG13_1
PPG12_1
ICU0
ICU5_2
-
-
PPG5_1
PPG4_1
PPG3_1
PPG2_1
PPG1_1
PPG10
PPG9
PPG8
PPG10_2
PPG9_2
PPG8_2
PPG10_1
-
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VSS
DEBUGIF
P111
P110
P093
P092
P091
NMIX
P134
P133
P132
P131
P130
P127
P126
VCC5
VSS
RSTX
MD0
MD1
X0
X1
VSS
P057
P056
P055
P054
P053
P052
P051
P050
C_2
VSS
VCC3
P047
P046
P045
P044
P043
P042
P041
P040
P037
P036
P035
P034
P033
P032
P031
P030
P027
VCC3
RX1
TX1
SGA1
SGO0
SGA0
TRG2
TRG5
TRG1
TRG0
RDY
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
SOT2
SCK2
SIN2
PPG1_3
PPG11_1
SCK0
SOT0
SIN0
SPI_XCS
SPI_SCK
SPI_DI
SPI_DO
INT10
INT14
INT13
INT12
SCK1
SOT1
SIN1
ICU3_1
TOT3_1 ICU0_1
TOT2_1 ICU2_1
INT5
ICU5
INT3
ICU4
INT2
ICU3
INT4
ICU2
INT0
ICU1
INT1
PPG2_2
PPG1_2
PPG8_1
PPG7_1
PPG6_1
TIOB1
TIOB0
TIOA1
TIOA0
-
-
-
Document Number: 002-04727 Rev. *B
Page 12 of 174
MB91590 Series
2.3
Pin Assignment (MB91F59A/B Single Clock Product)
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VSS
AVCC3
AVSS3
VIN
REFOUT
AVR3
AVSS3
AVCC3
PG0/DCKIN/CMDTRG
PG3/CSOUT
PG2/HSIN
PG1/VSIN
PH3/CCLK
PC7/BIN7
PC6/BIN6
PC5/BIN5
PC4/BIN4
PC3/BIN3
PC2/BIN2
VCC3
VSS
PB7/GIN7
PB6/GIN6
PB5/GIN5
PB4/GIN4
PB3/GIN3/VIN7
PB2/GIN2/VIN6
PA7/RIN7/VIN5
PA6/RIN6/VIN4
PA5/RIN5/VIN3
PA4/RIN4/VIN2
PA3/RIN3/VIN1
PA2/RIN2/VIN0
VCC3
VSS
VCC5
P136
P137
VSS
MD2
P122/OCU0/SCK5/TOT3/PPG7_2
P121/FRCK0/SOT5/INT7/TOT2/PPG6_2
P120/FRCK1/SIN5/INT6/TOT1/PPG5_2
P117/SGO3/SCK4/TRG4/TOT0/FRCK2
P116/SGA3/SOT4/TIN3/FRCK3
P115/SGO2/SIN4/TIN2/FRCK4
P114/SGA2/SCK3/TRG3/TIN1/ICU5_1/FRCK7
P097/WOT/SOT3/INT8/TIN0/ICU4_1/PPG0_1
P094/SGO1/SIN3/INT15/ICU1_1/PPG9_1/TIN9_1
P113/RX2/INT11/PPG4_2/TIN7
P112/TX2/PPG3_2/TOT10_1
P090/ADTG/PPG0_2/TIN7_1
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
○
FR+GDC
TOP VIEW
LQFP-208 / TEQFP-208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
DVCC
DVSS
P087/PWM2M5/AN31/ICU4_2/PPG23
P086/PWM2P5/AN30/ICU3_2/PPG22
P085/PWM1M5/AN29/ICU2_2/PPG21/UDCAIN2
P084/PWM1P5/AN28/ICU1_2/PPG20/UDCBIN2
P083/PWM2M4/AN27/ICU0_2/PPG19/UDCZIN2
P082/PWM2P4/AN26/SCK6/PPG18/UDCZIN0_1
P081/PWM1M4/AN25/SOT6/PPG17/UDCBIN0_1
P080/PWM1P4/AN24/SIN6/PPG16/UDCAIN0_1
DVCC
DVSS
P077/PWM2M3/AN23/SCK7_1/PPG15_1/ICU6
P076/PWM2P3/AN22/SOT7_1/PPG14_1/ICU7
P075/PWM1M3/AN21/SIN7_1/PPG13_1/ICU8
P074/PWM1P3/AN20/PPG12_1/SCK8/ICU9
P073/PWM2M2/AN19/SOT8/ICU10
P072/PWM2P2/AN18/SIN8/ICU11
P071/PWM1M2/AN17/SCK9
P070/PWM1P2/AN16/SOT9
DVCC
DVSS
P067/PWM2M1/AN15/UDCAIN0/SIN9
P066/PWM2P1/AN14/UDCBIN0
P065/PWM1M1/AN13/UDCZIN0
P064/PWM1P1/AN12/UDCAIN1
P063/PWM2M0/AN11/UDCBIN1
P062/PWM2P0/AN10/UDCZIN1/SCK10
P061/PWM1M0/AN9/SOT10
P060/PWM1P0/AN8/SIN10
DVCC
DVSS
C_1
VSS
VCC5
P107/SGO4_1/AN7/PPG5_1/TOT7_1/ICU11_1
P106/SGA4_1/AN6/PPG4_1/TIN10_1/ICU10_1
P105/SCK5_1/AN5/TOT1_1/PPG3_1/ICU9_1
P104/SOT5_1/AN4/TOT0_1/PPG2_1/ICU8_1
P103/SIN5_1/AN3/TIN3_1/PPG1_1/ICU7_1
P102/SCK4_1/AN2/TIN2_1/PPG10/ICU6_1
P101/SOT4_1/AN1/TIN1_1/PPG9
P100/SIN4_1/AN0/TIN0_1/PPG8
AVSS5/AVRL5
AVRH5
AVCC5
P125/OCU3/ICU0/PPG10_2/TIN10/SCK11
P124/OCU2/ICU5_2/PPG9_2/TIN9/SOT11
P123/OCU1/PPG8_2/TIN8/SIN11
P096/RX0/INT9
P095/TX0/PPG10_1
VCC5
VCC3
P027/A01
P030/A02
P031/A03
P032/A04
P033/A05
P034/A06
P035/A07
P036/A08
P037/A09/QSPI_SIO0
P040/A10/QSPI_SIO1
P041/A11/QSPI_SIO2
P042/A12/QSPI_SIO3
P043/A13/QSPI_CS0
P044/A14/QSPI_CS1
P045/A15/QSPI_CS2
P046/A16/QSPI_CS3
P047/A17/QSPI_CLK
VCC3
VSS
C_2
P050/A18
P051/A19
P052/A20
P053/A21/SPI_DO
P054/A22/SPI_DI
P055/A23/SPI_SCK
P056/A24/SPI_XCS
P057/RDY
VSS
X1
X0
MD1
MD0
RSTX
VSS
VCC5
P126/TRG0/SIN0/INT1
P127/SOT0
P130/SCK0/INT0/ICU1/TIOA0
P131/TRG1/SIN1/INT4/ICU2/TIOA1/TOT7
P132/SOT1/INT2/ICU3/TIOB0/TOT8
P133/TRG5/PPG11_1/SCK1/INT3/ICU4/TIOB1/TOT9
P134/TRG2/PPG1_3/INT5/ICU5/TOT10
NMIX
P091/SGA0/SIN2/INT12/TOT2_1/ICU2_1/PPG6_1
P092/SGO0/SCK2/INT13/TOT3_1/ICU0_1/PPG7_1
P093/SGA1/SOT2/INT14/ICU3_1/PPG8_1/TIN8_1
P110/TX1/PPG1_2/FRCK5/TOT8_1
P111/RX1/INT10/PPG2_2/FRCK6/TOT9_1
DEBUGIF
VSS
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
VCC3
PD2/ROUT2
PD3/ROUT3
PD4/ROUT4
PD5/ROUT5
PD6/ROUT6
PD7/ROUT7
PE2/GOUT2
PE3/GOUT3
PE4/GOUT4
PE5/GOUT5
PE6/GOUT6
PE7/GOUT7
PF2/BOUT2
PF3/BOUT3
PF4/BOUT4
PF5/BOUT5
VCC3
VSS
C_3
PF6/BOUT6
PF7/BOUT7
PG4/DCKOUT
PG5/VSYNC
PG6/HSYNC
PG7/DEOUT
P000/D0/SIN2_1/TIN0_2/PPG0
P001/D1/SOT2_1/TIN1_2/PPG1
P002/D2/SCK2_1/TIN2_2/PPG2
P003/D3/SIN3_1/TIN3_2/PPG3
P004/D4/SOT3_1/TOT0_2/PPG4
P005/D5/SCK3_1/TOT1_2/PPG5
P006/D6/TOT2_2/PPG6
P007/D7/TOT3_2/PPG7
P010/D8
VSS
VCC3
P011/D9/ROUT0
P012/D10/ROUT1
P013/D11/GOUT0
P014/D12/GOUT1
P015/D13/BOUT0
P016/D14/BOUT1
P017/D15
P020/WEX
P021/CS0X
P022/CS1X
P023/REX
P024
P025
P026/A00
VSS
Document Number: 002-04727 Rev. *B
Page 13 of 174
MB91590 Series
2.4
Pin Assignment (MB91F59A/B dual Clock Product)
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VSS
AVCC3
AVSS3
VIN
REFOUT
AVR3
AVSS3
AVCC3
PG0/DCKIN/CMDTRG
PG3/CSOUT
PG2/HSIN
PG1/VSIN
PH3/CCLK
PC7/BIN7
PC6/BIN6
PC5/BIN5
PC4/BIN4
PC3/BIN3
PC2/BIN2
VCC3
VSS
PB7/GIN7
PB6/GIN6
PB5/GIN5
PB4/GIN4
PB3/GIN3/VIN7
PB2/GIN2/VIN6
PA7/RIN7/VIN5
PA6/RIN6/VIN4
PA5/RIN5/VIN3
PA4/RIN4/VIN2
PA3/RIN3/VIN1
PA2/RIN2/VIN0
VCC3
VSS
VCC5
X1A
X0A
VSS
MD2
P122/OCU0/SCK5/TOT3/PPG7_2
P121/FRCK0/SOT5/INT7/TOT2/PPG6_2
P120/FRCK1/SIN5/INT6/TOT1/PPG5_2
P117/SGO3/SCK4/TRG4/TOT0/FRCK2
P116/SGA3/SOT4/TIN3/FRCK3
P115/SGO2/SIN4/TIN2/FRCK4
P114/SGA2/SCK3/TRG3/TIN1/ICU5_1/FRCK7
P097/WOT/SOT3/INT8/TIN0/ICU4_1/PPG0_1
P094/SGO1/SIN3/INT15/ICU1_1/PPG9_1/TIN9_1
P113/RX2/INT11/PPG4_2/TIN7
P112/TX2/PPG3_2/TOT10_1
P090/ADTG/PPG0_2/TIN7_1
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
○
FR+GDC
TOP VIEW
LQFP-208 / TEQFP-208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
DVCC
DVSS
P087/PWM2M5/AN31/ICU4_2/PPG23
P086/PWM2P5/AN30/ICU3_2/PPG22
P085/PWM1M5/AN29/ICU2_2/PPG21/UDCAIN2
P084/PWM1P5/AN28/ICU1_2/PPG20/UDCBIN2
P083/PWM2M4/AN27/ICU0_2/PPG19/UDCZIN2
P082/PWM2P4/AN26/SCK6/PPG18/UDCZIN0_1
P081/PWM1M4/AN25/SOT6/PPG17/UDCBIN0_1
P080/PWM1P4/AN24/SIN6/PPG16/UDCAIN0_1
DVCC
DVSS
P077/PWM2M3/AN23/SCK7_1/PPG15_1/ICU6
P076/PWM2P3/AN22/SOT7_1/PPG14_1/ICU7
P075/PWM1M3/AN21/SIN7_1/PPG13_1/ICU8
P074/PWM1P3/AN20/PPG12_1/SCK8/ICU9
P073/PWM2M2/AN19/SOT8/ICU10
P072/PWM2P2/AN18/SIN8/ICU11
P071/PWM1M2/AN17/SCK9
P070/PWM1P2/AN16/SOT9
DVCC
DVSS
P067/PWM2M1/AN15/UDCAIN0/SIN9
P066/PWM2P1/AN14/UDCBIN0
P065/PWM1M1/AN13/UDCZIN0
P064/PWM1P1/AN12/UDCAIN1
P063/PWM2M0/AN11/UDCBIN1
P062/PWM2P0/AN10/UDCZIN1/SCK10
P061/PWM1M0/AN9/SOT10
P060/PWM1P0/AN8/SIN10
DVCC
DVSS
C_1
VSS
VCC5
P107/SGO4_1/AN7/PPG5_1/TOT7_1/ICU11_1
P106/SGA4_1/AN6/PPG4_1/TIN10_1/ICU10_1
P105/SCK5_1/AN5/TOT1_1/PPG3_1/ICU9_1
P104/SOT5_1/AN4/TOT0_1/PPG2_1/ICU8_1
P103/SIN5_1/AN3/TIN3_1/PPG1_1/ICU7_1
P102/SCK4_1/AN2/TIN2_1/PPG10/ICU6_1
P101/SOT4_1/AN1/TIN1_1/PPG9
P100/SIN4_1/AN0/TIN0_1/PPG8
AVSS5/AVRL5
AVRH5
AVCC5
P125/OCU3/ICU0/PPG10_2/TIN10/SCK11
P124/OCU2/ICU5_2/PPG9_2/TIN9/SOT11
P123/OCU1/PPG8_2/TIN8/SIN11
P096/RX0/INT9
P095/TX0/PPG10_1
VCC5
VCC3
P027/A01
P030/A02
P031/A03
P032/A04
P033/A05
P034/A06
P035/A07
P036/A08
P037/A09/QSPI_SIO0
P040/A10/QSPI_SIO1
P041/A11/QSPI_SIO2
P042/A12/QSPI_SIO3
P043/A13/QSPI_CS0
P044/A14/QSPI_CS1
P045/A15/QSPI_CS2
P046/A16/QSPI_CS3
P047/A17/QSPI_CLK
VCC3
VSS
C_2
P050/A18
P051/A19
P052/A20
P053/A21/SPI_DO
P054/A22/SPI_DI
P055/A23/SPI_SCK
P056/A24/SPI_XCS
P057/RDY
VSS
X1
X0
MD1
MD0
RSTX
VSS
VCC5
P126/TRG0/SIN0/INT1
P127/SOT0
P130/SCK0/INT0/ICU1/TIOA0
P131/TRG1/SIN1/INT4/ICU2/TIOA1/TOT7
P132/SOT1/INT2/ICU3/TIOB0/TOT8
P133/TRG5/PPG11_1/SCK1/INT3/ICU4/TIOB1/TOT9
P134/TRG2/PPG1_3/INT5/ICU5/TOT10
NMIX
P091/SGA0/SIN2/INT12/TOT2_1/ICU2_1/PPG6_1
P092/SGO0/SCK2/INT13/TOT3_1/ICU0_1/PPG7_1
P093/SGA1/SOT2/INT14/ICU3_1/PPG8_1/TIN8_1
P110/TX1/PPG1_2/FRCK5/TOT8_1
P111/RX1/INT10/PPG2_2/FRCK6/TOT9_1
DEBUGIF
VSS
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
VCC3
PD2/ROUT2
PD3/ROUT3
PD4/ROUT4
PD5/ROUT5
PD6/ROUT6
PD7/ROUT7
PE2/GOUT2
PE3/GOUT3
PE4/GOUT4
PE5/GOUT5
PE6/GOUT6
PE7/GOUT7
PF2/BOUT2
PF3/BOUT3
PF4/BOUT4
PF5/BOUT5
VCC3
VSS
C_3
PF6/BOUT6
PF7/BOUT7
PG4/DCKOUT
PG5/VSYNC
PG6/HSYNC
PG7/DEOUT
P000/D0/SIN2_1/TIN0_2/PPG0
P001/D1/SOT2_1/TIN1_2/PPG1
P002/D2/SCK2_1/TIN2_2/PPG2
P003/D3/SIN3_1/TIN3_2/PPG3
P004/D4/SOT3_1/TOT0_2/PPG4
P005/D5/SCK3_1/TOT1_2/PPG5
P006/D6/TOT2_2/PPG6
P007/D7/TOT3_2/PPG7
P010/D8
VSS
VCC3
P011/D9/ROUT0
P012/D10/ROUT1
P013/D11/GOUT0
P014/D12/GOUT1
P015/D13/BOUT0
P016/D14/BOUT1
P017/D15
P020/WEX
P021/CS0X
P022/CS1X
P023/REX
P024
P025
P026/A00
VSS
Document Number: 002-04727 Rev. *B
Page 14 of 174
MB91590 Series
2.5
Pin Assignment (BGA Product)
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
21
B
C
75 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 95
22
C
D
74 143 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 161 96
23
D
E
73 142 203 256
219 162 97
24
E
F
72 141 202 255
220 163 98
25
F
G
71 140 201 254
257 258 259 260 261 262 263 264
221 164 99
26
G
H
70 139 200 253
284 285 286 287 288 289 290 265
222 165 100 27
H
J
69 138 199 252
283 304 305 306 307 308 291 266
223 166 101 28
J
K
68 137 198 251
282 303 316 317 318 309 292 267
224 167 102 29
K
L
67 136 197 250
281 302 315 320 319 310 293 268
225 168 103 30
L
M
66 135 196 249
280 301 314 313 312 311 294 269
226 169 104 31
M
N
65 134 195 248
279 300 299 298 297 296 295 270
227 170 105 32
N
P
64 133 194 247
278 277 276 275 274 273 272 271
228 171 106 33
P
R
63 132 193 246
229 172 107 34
R
T
62 131 192 245
230 173 108 35
T
U
61 130 191 244 243 242 241 240 239 238 237 236 235 234 233 232 231 174 109 36
U
V
60 129 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 110 37
V
W
59 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111
38
W
Y
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Document Number: 002-04727 Rev. *B
Page 15 of 174
MB91590 Series
3. Pin Description
3.1
Pin Description of LQFP-208/TEQFP-208
Pin No.
84
83
171
(dual clock
product)
172
(dual clock
product)
171
(single clock
product)
172
(single clock
product)
97
87
86
85
169
27
28
29
30
31
Pin Name
Polarity
I/O Circuit
Types*1
Function*2
X0
X1
–
–
L
L
Main clock oscillation input pin
Main clock oscillation output pin
X0A
–
N
Sub clock oscillation input pin
X1A
–
N
Sub clock oscillation output pin
P137
–
A
General-purpose I/O port
P136
–
A
General-purpose I/O port
NMIX
RSTX
MD0
MD1
MD2
P000
D0
SIN2_1
TIN0_2
PPG0
P001
D1
SOT2_1
TIN1_2
PPG1
P002
D2
SCK2_1
TIN2_2
PPG2
P003
D3
SIN3_1
TIN3_2
PPG3
P004
D4
SOT3_1
TOT0_2
PPG4
N
N
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
F1
F1
P
P
F2
Non-masking interrupt input pin
External reset input pin
Mode pin 0
Mode pin 1
Mode pin 2
General-purpose I/O port (3V pin)
External bus · Data bit0 I/O pin
LIN-UART ch.2 serial data input pin (1)
Reload timer ch.0 event input pin (2)
PPG ch.0 output pin
General-purpose I/O port (3V pin)
External bus · Data bit1 I/O pin
LIN-UART ch.2 serial data output pin (1)
Reload timer ch.1 event input pin (2)
PPG ch.1 output pin
General-purpose I/O port (3V pin)
External bus · Data bit2 I/O pin
LIN-UART ch.2 clock I/O pin (1)
Reload timer ch.2 event input pin (2)
PPG ch.2 output pin
General-purpose I/O port (3V pin)
External bus · Data bit3 I/O pin
LIN-UART ch.3 serial data input pin (1)
Reload timer ch.3 event input pin (2)
PPG ch.3 output pin
General-purpose I/O port (3V pin)
External bus · Data bit4 I/O pin
LIN-UART ch.3 serial data output pin (1)
Reload timer ch.0 output pin (2)
PPG ch.4 output pin
Document Number: 002-04727 Rev. *B
O
O
O
O
O
Page 16 of 174
MB91590 Series
Pin No.
32
33
34
35
38
39
40
41
42
43
44
45
46
47
48
49
50
51
54
Pin Name
P005
D5
SCK3_1
TOT1_2
PPG5
P006
D6
TOT2_2
PPG6
P007
D7
TOT3_2
PPG7
P010
D8
P011
D9
ROUT0
P012
D10
ROUT1
P013
D11
GOUT0
P014
D12
GOUT1
P015
D13
BOUT0
P016
D14
BOUT1
P017
D15
P020
WEX
P021
CS0X
P022
CS1X
P023
REX
P024
P025
P026
A00
P027
A01
Polarity
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Types*1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Function*2
General-purpose I/O port (3V pin)
External bus · Data bit5 I/O pin
LIN-UART ch.3 clock I/O pin (1)
Reload timer ch.1 output pin (2)
PPG ch.5 output pin
General-purpose I/O port (3V pin)
External bus · Data bit6 I/O pin
Reload timer ch.2 output pin (2)
PPG ch.6 output pin
General-purpose I/O port (3V pin)
External bus · Data bit7 I/O pin
Reload timer ch.3 output pin (2)
PPG ch.7 output pin
General-purpose I/O port (3V pin)
External bus · Data bit8 I/O pin
General-purpose I/O port (3V pin)
External bus · Data bit9 I/O pin
Display digital R0 output pin
General-purpose I/O port (3V pin)
External bus · Data bit10 I/O pin
Display digital R1 output pin
General-purpose I/O port (3V pin)
External bus · Data bit11 I/O pin
Display digital G0 output pin
General-purpose I/O port (3V pin)
External bus · Data bit12 I/O pin
Display digital G1 output pin
General-purpose I/O port (3V pin)
External bus · Data bit13 I/O pin
Display digital B0 output pin
General-purpose I/O port (3V pin)
External bus · Data bit14 I/O pin
Display digital B1 output pin
General-purpose I/O port (3V pin)
External bus · Data bit15 I/O pin
General-purpose I/O port (3V pin)
External bus · Write enable output pin
General-purpose I/O port (3V pin)
External bus · Chip select 0 output pin
General-purpose I/O port (3V pin)
External bus · Chip select 1 output pin
General-purpose I/O port (3V pin)
External bus · Read enable output pin
General-purpose I/O port (3V pin)
General-purpose I/O port (3V pin)
General-purpose I/O port (3V pin)
External bus · Address bit0 output pin
General-purpose I/O port (3V pin)
External bus · Address bit1 output pin
Page 17 of 174
MB91590 Series
Pin No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
74
75
76
Pin Name
P030
A02
P031
A03
P032
A04
P033
A05
P034
A06
P035
A07
P036
A08
P037
A09
QSPI_SIO0
P040
A10
QSPI_SIO1
P041
A11
QSPI_SIO2
P042
A12
QSPI_SIO3
P043
A13
QSPI_CS0
P044
A14
QSPI_CS1
P045
A15
QSPI_CS2
P046
A16
QSPI_CS3
P047
A17
QSPI_CLK
P050
A18
P051
A19
P052
A20
Polarity
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Types*1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Function*2
General-purpose I/O port (3V pin)
External bus · Address bit2 output pin
General-purpose I/O port (3V pin)
External bus · Address bit3 output pin
General-purpose I/O port (3V pin)
External bus · Address bit4 output pin
General-purpose I/O port (3V pin)
External bus · Address bit5 output pin
General-purpose I/O port (3V pin)
External bus · Address bit6 output pin
General-purpose I/O port (3V pin)
External bus · Address bit7 output pin
General-purpose I/O port (3V pin)
External bus · Address bit8 output pin
General-purpose I/O port (3V pin)
External bus · Address bit9 output pin
HS_SPI SDATA0 I/O pin(MB91F59A/B only)
General-purpose I/O port (3V pin)
External bus · Address bit10 output pin
HS_SPI SDATA1 I/O pin(MB91F59A/B only)
General-purpose I/O port (3V pin)
External bus · Address bit11 output pin
HS_SPI SDATA2 I/O pin(MB91F59A/B only)
General-purpose I/O port (3V pin)
External bus · Address bit12 output pin
HS_SPI SDATA3 I/O pin(MB91F59A/B only)
General-purpose I/O port (3V pin)
External bus · Address bit13 output pin
HS_SPI SSEL0 Output pin(MB91F59A/B only)
General-purpose I/O port (3V pin)
External bus · Address bit14 output pin
HS_SPI SSEL1 Output pin(MB91F59A/B only)
General-purpose I/O port (3V pin)
External bus · Address bit15 output pin
HS_SPI SSEL2 Output pin(MB91F59A/B only)
General-purpose I/O port (3V pin)
External bus · Address bit16 output pin
HS_SPI SSEL3 Output pin(MB91F59A/B only)
General-purpose I/O port (3V pin)
External bus · Address bit17 output pin
HS_SPI SCLK Output pin(MB91F59A/B only)
General-purpose I/O port (3V pin)
External bus · Address bit18 output pin
General-purpose I/O port(3V pin)
External bus · Address bit19 output pin
General-purpose I/O port(3V pin)
External bus · Address bit20 output pin
Page 18 of 174
MB91590 Series
Pin No.
77
78
79
80
81
127
128
129
130
131
132
133
Pin Name
Polarity
P053
A21
SPI_DO
P054
A22
SPI_DI
P055
A23
SPI_SCK
P056
A24
SPI_XCS
P057
RDY
P060
PWM1P0
AN8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SIN10
–
P061
PWM1M0
AN9
–
–
–
SOT10
–
P062
PWM2P0
AN10
UDCZIN1
–
–
–
–
SCK10
–
P063
PWM2M0
AN11
UDCBIN1
P064
PWM1P1
AN12
UDCAIN1
P065
PWM1M1
AN13
UDCZIN0
P066
PWM2P1
AN14
UDCBIN0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Types*1
O
O
O
O
O
E
E
E
E
E
E
E
Function*2
General-purpose I/O port(3V pin)
External bus · Address bit21 output pin
SPI data output pin
General-purpose I/O port (3V pin)
External bus · Address bit22 output pin
SPI data input pin
General-purpose I/O port (3V pin)
External bus · Address bit23 output pin
SPI clock output pin
General-purpose I/O port (3V pin)
External bus · Address bit24 output pin
SPI chip select output pin
General-purpose I/O port (3V pin)
External bus · Wait input pin
General-purpose I/O port
SMC ch.0 output pin
ADC Analog 8 input pin
Multi-function serial ch.10 serial data input
pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.0 output pin
ADC Analog 9 input pin
Multi-function serial ch.10 serial data output
pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.0 output pin
ADC Analog 10 input pin
Up/down counter ch.1 ZIN input pin(MB91F59A/B only)
Multi-function serial ch.10 clock I/O pin(MB91F59A/B
only)
General-purpose I/O port
SMC ch.0 output pin
ADC Analog 11 input pin
Up/down counter ch.1 BIN input pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.1 output pin
ADC Analog 12 input pin
Up/down counter ch.1 AIN input pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.1 output pin
ADC Analog 13 input pin
Up/down counter ch.0 ZIN input pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.1 output pin
ADC Analog 14 input pin
Up/down counter ch.0 BIN input pin(MB91F59A/B only)
Page 19 of 174
MB91590 Series
Pin No.
134
137
138
139
140
141
142
143
Pin Name
Polarity
P067
PWM2M1
AN15
–
–
–
UDCAIN0
–
SIN9
–
P070
PWM1P2
AN16
–
–
–
SOT9
–
P071
PWM1M2
AN17
SCK9
P072
PWM2P2
AN18
–
–
–
–
–
–
–
SIN8
–
ICU11
P073
PWM2M2
AN19
–
–
–
–
SOT8
–
ICU10
P074
PWM1P3
AN20
PPG12_1
SCK8
ICU9
P075
PWM1M3
AN21
SIN7_1
PPG13_1
ICU8
P076
PWM2P3
AN22
SOT7_1
PPG14_1
ICU7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Types*1
E
E
E
E
E
E
E
E
Function*2
General-purpose I/O port
SMC ch.1 output pin
ADC Analog 15 input pin
Up/down counter ch.0 AIN input pin
(MB91F59A/B only)
Multi-function serial ch.9 serial data input
pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.2 output pin
ADC Analog 16 input pin
Multi-function serial ch.9 serial data output
pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.2 output pin
ADC Analog 17 input pin
Multi-function serial ch.9 clock I/O pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.2 output pin
ADC Analog 18 input pin
Multi-function serial ch.8 serial data input
pin(MB91F59A/B only)
Input capture ch.11 input pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.2 output pin
ADC Analog 19 input pin
Multi-function serial ch.8 serial data output
pin(MB91F59A/B only)
Input capture ch.10 input pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.3 output pin
ADC Analog 20 input pin
PPG ch.12 output pin (1)
Multi-function serial ch.8 clock I/O pin(MB91F59A/B only)
Input capture ch.9 input pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.3 output pin
ADC Analog 21 input pin
LIN-UART ch.7 serial data input pin
PPG ch.13 output pin (1)
Input capture ch.8 input pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.3 output pin
ADC Analog 22 input pin
LIN-UART ch.7 serial data output pin
PPG ch.14 output pin (1)
Input capture ch.7 input pin(MB91F59A/B only)
Page 20 of 174
MB91590 Series
Pin No.
144
147
148
149
150
151
152
153
Pin Name
Polarity
P077
PWM2M3
AN23
SCK7_1
PPG15_1
ICU6
P080
PWM1P4
AN24
SIN6
PPG16
–
–
–
–
–
–
–
–
–
–
–
UDCAIN0_1
–
P081
PWM1M4
AN25
SOT6
PPG17
–
–
–
–
–
UDCBIN0_1
–
P082
PWM2P4
AN26
SCK6
PPG18
–
–
–
–
–
UDCZIN0_1
–
P083
PWM2M4
AN27
ICU0_2
PPG19
UDCZIN2
P084
PWM1P5
AN28
ICU1_2
PPG20
UDCBIN2
P085
PWM1M5
AN29
ICU2_2
PPG21
UDCAIN2
P086
PWM2P5
AN30
ICU3_2
PPG22
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Types*1
E
E
E
E
E
E
E
E
Function*2
General-purpose I/O port
SMC ch.3 output pin
ADC Analog 23 input pin
LIN-UART ch.7 clock I/O pin
PPG ch.15 output pin (1)
Input capture ch.6 input pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.4 output pin
ADC Analog 24 input pin
LIN-UART ch.6 serial data input pin
PPG ch.16 output pin
Up/down counter ch.0 AIN input pin (1) (MB91F59A/B
only)
General-purpose I/O port
SMC ch.4 output pin
ADC Analog 25 input pin
LIN-UART ch.6 serial data output pin
PPG ch.17 output pin
Up/down counter ch.0 BIN input pin (1) (MB91F59A/B
only)
General-purpose I/O port
SMC ch.4 output pin
ADC Analog 26 input pin
LIN-UART ch.6 clock I/O pin
PPG ch.18 output pin
Up/down counter ch.0 ZIN input pin (1) (MB91F59A/B
only)
General-purpose I/O port
SMC ch.4 output pin
ADC Analog 27 input pin
Input capture ch.0 input pin (2)
PPG ch.19 output pin
Up/down counter ch.2 ZIN input pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.5 output pin
ADC Analog 28 input pin
Input capture ch.1 input pin (2)
PPG ch.20 output pin
Up/down counter ch.2 BIN input pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.5 output pin
ADC Analog 29 input pin
Input capture ch.2 input pin (2)
PPG ch.21 output pin
Up/down counter ch.2 AIN input pin(MB91F59A/B only)
General-purpose I/O port
SMC ch.5 output pin
ADC Analog 30 input pin
Input capture ch.3 input pin (2)
PPG ch.22 output pin
Page 21 of 174
MB91590 Series
Pin No.
154
157
98
99
100
160
106
107
Pin Name
P087
PWM2M5
AN31
ICU4_2
PPG23
P090
ADTG
PPG0_2
TIN7_1
P091
SGA0
SIN2
INT12
TOT2_1
ICU2_1
PPG6_1
P092
SGO0
SCK2
INT13
TOT3_1
ICU0_1
PPG7_1
P093
SGA1
SOT2
INT14
ICU3_1
PPG8_1
TIN8_1
P094
SGO1
SIN3
INT15
ICU1_1
PPG9_1
TIN9_1
P095
TX0
PPG10_1
P096
RX0
INT9
Polarity
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Types*1
E
A
C
C
C
C
A
A
Function*2
General-purpose I/O port
SMC ch.5 output pin
ADC Analog 31 input pin
Input capture ch.4 input pin (2)
PPG ch.23 output pin
General-purpose I/O port
A/D convertor external trigger input pin
PPG ch.0 output pin (2)
Reload timer ch.7 event input pin (1) (MB91F59A/B only)
General-purpose I/O port
Sound generator ch.0 SGA output pin
LIN-UART ch.2 serial data input pin
INT12 External interrupt input pin
Reload timer ch.2 output pin (1)
Input capture ch.2 input pin (1)
PPG ch.6 output pin (1)
General-purpose I/O port
Sound generator ch.0 SGO output pin
LIN-UART ch.2 clock I/O pin
INT13 External interrupt input pin
Reload timer ch.3 output pin (1)
Input capture ch.0 input pin (1)
PPG ch.7 output pin (1)
General-purpose I/O port
Sound generator ch.1 SGA output pin
LIN-UART ch.2 serial data output pin
INT14 External interrupt input pin
Input capture ch.3 input pin (1)
PPG ch.8 output pin (1)
Reload timer ch.8 event input pin (1) (MB91F59A/B only)
General-purpose I/O port
Sound generator ch.1 SGO output pin
LIN-UART ch.3 serial data input pin
INT15 External interrupt input pin
Input capture ch.1 input pin (1)
PPG ch.9 output pin (1)
Reload timer ch.9 event input pin (1) (MB91F59A/B only)
General-purpose I/O port
CAN transmission data0 output pin
PPG ch.10 output pin (1)
General-purpose I/O port
CAN reception data0 input pin
INT9 External interrupt input pin
Page 22 of 174
MB91590 Series
Pin No.
161
114
115
116
117
118
119
120
Pin Name
Polarity
P097
WOT
SOT3
INT8
TIN0
ICU4_1
PPG0_1
P100
SIN4_1
AN0
TIN0_1
PPG8
P101
SOT4_1
AN1
TIN1_1
PPG9
P102
SCK4_1
AN2
TIN2_1
PPG10
ICU6_1
P103
SIN5_1
AN3
TIN3_1
PPG1_1
ICU7_1
P104
SOT5_1
AN4
TOT0_1
PPG2_1
ICU8_1
P105
SCK5_1
AN5
TOT1_1
PPG3_1
ICU9_1
P106
SGA4_1
AN6
PPG4_1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
TIN10_1
–
ICU10_1
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Types*1
C
C
C
C
C
C
C
C
Function*2
General-purpose I/O port
RTC overflow output pin
LIN-UART ch.3 serial data output pin
INT8 External interrupt input pin
Reload timer ch.0 event input pin
Input capture ch.4 input pin (1)
PPG ch.0 output pin (1)
General-purpose I/O port
LIN-UART ch.4 serial data input pin (1)
ADC Analog 0 input pin
Reload timer ch.0 event input pin (1)
PPG ch.8 output pin
General-purpose I/O port
LIN-UART ch.4 serial data output pin (1)
ADC Analog 1 input pin
Reload timer ch.1 event input pin (1)
PPG ch.9 output pin
General-purpose I/O port
LIN-UART ch.4 clock I/O pin (1)
ADC Analog 2 input pin
Reload timer ch.2 event input pin (1)
PPG ch.10 output pin
Input capture ch.6 input pin (1) (MB91F59A/B only)
General-purpose I/O port
LIN-UART ch.5 serial data input pin (1)
ADC Analog 3 input pin
Reload timer ch.3 event input pin (1)
PPG ch.1 output pin (1)
Input capture ch.7 input pin (1) (MB91F59A/B only)
General-purpose I/O port
LIN-UART ch.5 serial data output pin (1)
ADC Analog 4 input pin
Reload timer ch.0 output pin (1)
PPG ch.2 output pin (1)
Input capture ch.8 input pin (1) (MB91F59A/B only)
General-purpose I/O port
LIN-UART ch.5 clock I/O pin (1)
ADC Analog 5 input pin
Reload timer ch.1 output pin (1)
PPG ch.3 output pin (1)
Input capture ch.9 input pin (1) (MB91F59A/B only)
General-purpose I/O port
Sound generator ch.4 SGA output pin
ADC Analog 6 input pin
PPG ch.4 output pin (1)
Reload timer ch.10 event input pin (1) (MB91F59A/B
only)
Input capture ch.10 input pin (1) (MB91F59A/B only)
Page 23 of 174
MB91590 Series
Pin No.
121
101
102
158
159
162
163
164
165
Pin Name
P107
SGO4_1
AN7
PPG5_1
TOT7_1
ICU11_1
P110
TX1
PPG1_2
FRCK5
TOT8_1
P111
RX1
INT10
PPG2_2
FRCK6
TOT9_1
P112
TX2
PPG3_2
TOT10_1
P113
RX2
INT11
PPG4_2
TIN7
P114
SGA2
SCK3
TRG3
TIN1
ICU5_1
FRCK7
P115
SGO2
SIN4
TIN2
FRCK4
P116
SGA3
SOT4
TIN3
FRCK3
P117
SGO3
SCK4
TRG4
TOT0
FRCK2
Polarity
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Types*1
C
C
C
C
C
C
C
C
C
Function*2
General-purpose I/O port
Sound generator ch.4 SGO output pin
ADC Analog 7 input pin
PPG ch.5 output pin (1)
Reload timer ch.7 output pin (1) (MB91F59A/B only)
Input capture ch.11 input pin (1) (MB91F59A/B only)
General-purpose I/O port
CAN transmission data1 output pin
PPG ch.1 output pin (2)
Free-run timer 5 clock input pin(MB91F59A/B only)
Reload timer ch.8 output pin (1) (MB91F59A/B only)
General-purpose I/O port
CAN reception data 1 input pin
INT10 External interrupt input pin
PPG ch.2 output pin (2)
Free-run timer 6 clock input pin(MB91F59A/B only)
Reload timer ch.9 output pin (1) (MB91F59A/B only)
General-purpose I/O port
CAN transmission data 2 output pin
PPG ch.3 output pin (2)
Reload timer ch.10 output pin (1) (MB91F59A/B only)
General-purpose I/O port
CAN reception data 2 input pin
INT11 External interrupt input pin
PPG ch.4 output pin (2)
Reload timer ch.7 event input pin(MB91F59A/B only)
General-purpose I/O port
Sound generator ch.2 SGA output pin
LIN-UART ch.3 clock I/O pin
PPG trigger 3 input pin (ch.12 to ch.15)
Reload timer ch.1 event input pin
Input capture ch.5 input pin (1)
Free-run timer 7 clock input pin(MB91F59A/B only)
General-purpose I/O port
Sound generator ch.2 SGO output pin
LIN-UART ch.4 serial data input pin
Reload timer ch.2 event input pin
Free-run timer 4 clock input pin(MB91F59A/B only)
General-purpose I/O port
Sound generator ch.3 SGA output pin
LIN-UART ch.4 serial data output pin
Reload timer ch.3 event input pin
Free-run timer 3 clock input pin(MB91F59A/B only)
General-purpose I/O port
Sound generator ch.3 SGO output pin
LIN-UART ch.4 clock I/O pin
PPG trigger 4 input pin (ch.16 to ch.19)
Reload timer ch.0 output pin
Free-run timer 2 clock input pin(MB91F59A/B only)
Page 24 of 174
MB91590 Series
Pin No.
166
167
168
108
109
110
90
91
92
Pin Name
Polarity
P120
FRCK1
SIN5
INT6
TOT1
PPG5_2
P121
FRCK0
SOT5
INT7
TOT2
PPG6_2
P122
OCU0
SCK5
TOT3
PPG7_2
P123
OCU1
PPG8_2
TIN8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SIN11
–
P124
OCU2
ICU5_2
PPG9_2
TIN9
–
–
–
–
–
SOT11
–
P125
OCU3
ICU0
PPG10_2
TIN10
–
–
–
–
–
SCK11
–
P126
TRG0
SIN0
INT1
P127
–
–
–
–
–
SOT0
–
P130
–
SCK0
–
INT0
ICU1
TIOA0
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Types*1
C
C
C
A
A
A
A
K
K
Function*2
General-purpose I/O port
Free-run timer 1 clock input pin
LIN-UART ch.5 serial data input pin
INT6 External interrupt input pin
Reload timer ch.1 output pin
PPG ch.5 output pin (2)
General-purpose I/O port
Free-run timer 0 clock input pin
LIN-UART ch.5 serial data output pin
INT7 External interrupt input pin
Reload timer ch.2 output pin
PPG ch.6 output pin (2)
General-purpose I/O port
Output compare ch.0 output pin
LIN-UART ch.5 clock I/O pin
Reload timer ch.3 output pin
PPG ch.7 output pin (2)
General-purpose I/O port
Output compare ch.1 output pin
PPG ch.8 output pin (2)
Reload timer ch.8 event input pin(MB91F59A/B only)
Multi-function serial ch.11 serial data input
pin(MB91F59A/B only)
General-purpose I/O port
Output compare ch.2 output pin
Input capture ch.5 input pin (2)
PPG ch.9 output pin (2)
Reload timer ch.9 event input pin(MB91F59A/B only)
Multi-function serial ch.11 serial data output
pin(MB91F59A/B only)
General-purpose I/O port
Output compare ch.3 output pin
Input capture ch.0 input pin
PPG ch.10 output pin (2)
Reload timer ch.10 event input pin(MB91F59A/B only)
Multi-function serial ch.11 clock I/O pin(MB91F59A/B
only)
General-purpose I/O port
PPG trigger 0 input pin (ch.0 to ch.3)
Multi-function serial ch.0 serial data input pin
INT1 External interrupt input pin
General-purpose I/O port
Multi-function serial ch.0 serial data output pin / I2C ch.0
serial data I/O pin
General-purpose I/O port
Multi-function serial ch.0 clock I/O pin / I2C ch.0 clock I/O
pin
INT0 External interrupt input pin
Input capture ch.1 input pin
Base timer TIOA0 output pin
Page 25 of 174
MB91590 Series
Pin No.
93
94
95
96
103
176
177
178
179
180
181
Pin Name
Polarity
P131
TRG1
SIN1
INT4
ICU2
TIOA1
TOT7
P132
–
–
–
–
–
–
–
–
SOT1
–
INT2
ICU3
TIOB0
TOT8
P133
TRG5
PPG11_1
–
–
–
–
–
–
–
SCK1
–
INT3
ICU4
TIOB1
TOT9
P134
TRG2
PPG1_3
INT5
ICU5
TOT10
DEBUGIF
PA2
RIN2
VIN0
PA3
RIN3
VIN1
PA4
RIN4
VIN2
PA5
RIN5
VIN3
PA6
RIN6
VIN4
PA7
RIN7
VIN5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Types*1
A
K
K
A
G
O
O
O
O
O
O
Function*2
General-purpose I/O port
PPG trigger 1 input pin (ch.4 to ch.7)
Multi-function serial ch.1 serial data input pin
INT4 External interrupt input pin
Input capture ch.2 input pin
Base timer TIOA1 I/O pin
Reload timer ch.7 output pin(MB91F59A/B only)
General-purpose I/O port
Multi-function serial ch.1 serial data output pin / I2C ch.1
serial data I/O pin
INT2 External interrupt input pin
Input capture ch.3 input pin
Base timer TIOB0 input pin
Reload timer ch.8 output pin(MB91F59A/B only)
General-purpose I/O port
PPG trigger 5 input pin ( ch.20 to ch.23)
PPG ch.11 output pin (1)
Multi-function serial ch.1 clock I/O pin / I2C ch.1 clock I/O
pin
INT3 External interrupt input pin
Input capture ch.4 input pin
Base timer TIOB1 input pin
Reload timer ch.9 output pin(MB91F59A/B only)
General-purpose I/O port
PPG trigger 2 input pin ( ch.8 to ch.11)
PPG ch.1 output pin (3)
INT5 External interrupt input pin
Input capture ch.5 input pin
Reload timer ch.10 output pin(MB91F59A/B only)
DEBUG I/F pin
General-purpose I/O port (3V pin)
Capture R2 input pin (RGB mode)
Capture VIN0 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture R3 input pin (RGB mode)
Capture VIN1 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture R4 input pin (RGB mode)
Capture VIN2 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture R5 input pin (RGB mode)
Capture VIN3 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture R6 input pin (RGB mode)
Capture VIN4 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture R7 input pin (RGB mode)
Capture VIN5 input pin (656 mode)
Page 26 of 174
MB91590 Series
Pin No.
182
183
184
185
186
187
190
191
192
193
194
195
2
3
4
5
6
7
8
9
10
11
12
Pin Name
PB2
GIN2
VIN6
PB3
GIN3
VIN7
PB4
GIN4
PB5
GIN5
PB6
GIN6
PB7
GIN7
PC2
BIN2
PC3
BIN3
PC4
BIN4
PC5
BIN5
PC6
BIN6
PC7
BIN7
PD2
ROUT2
PD3
ROUT3
PD4
ROUT4
PD5
ROUT5
PD6
ROUT6
PD7
ROUT7
PE2
GOUT2
PE3
GOUT3
PE4
GOUT4
PE5
GOUT5
PE6
GOUT6
Polarity
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Types*1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Function*2
General-purpose I/O port (3V pin)
Capture G2 input pin (RGB mode)
Capture VIN6 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture G3 input pin (RGB mode)
Capture VIN7 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture G4 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture G5 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture G6 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture G7 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture B2 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture B3 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture B4 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture B5 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture B6 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture B7 input pin (RGB mode)
General-purpose I/O port (3V pin)
Display digital R2 output pin
General-purpose I/O port (3V pin)
Display digital R3 output pin
General-purpose I/O port (3V pin)
Display digital R4 output pin
General-purpose I/O port (3V pin)
Display digital R5 output pin
General-purpose I/O port (3V pin)
Display digital R6 output pin
General-purpose I/O port (3V pin)
Display digital R7 output pin
General-purpose I/O port (3V pin)
Display digital G2 output pin
General-purpose I/O port (3V pin)
Display digital G3 output pin
General-purpose I/O port (3V pin)
Display digital G4 output pin
General-purpose I/O port (3V pin)
Display digital G5 output pin
General-purpose I/O port (3V pin)
Display digital G6 output pin
Page 27 of 174
MB91590 Series
Pin No.
13
14
15
16
17
21
22
200
197
198
199
23
24
25
26
196
204
203
205
111
201, 207
112
113
202, 206
124
73
20
Pin Name
Polarity
PE7
GOUT7
PF2
BOUT2
PF3
BOUT3
PF4
BOUT4
PF5
BOUT5
PF6
BOUT6
PF7
BOUT7
PG0
DCKIN
CMDTRG
PG1
VSIN
PG2
HSIN
PG3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P
–
P
–
CSOUT
–
PG4
DCKOUT
PG5
–
–
–
VSYNC
–
PG6
–
HSYNC
–
PG7
DEOUT
PH3
CCLK
REFOUT
AVR3
VIN
AVCC5
AVCC3
AVRH5
AVSS5/
AVRL5
AVSS3
C_1
C_2
C_3
–
P
–
–
–
–
–
–
–
–
I/O Circuit
Types*1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
T
S
S
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
Function*2
General-purpose I/O port (3V pin)
Display digital G7 output pin
General-purpose I/O port (3V pin)
Display digital B2 output pin
General-purpose I/O port (3V pin)
Display digital B3 output pin
General-purpose I/O port (3V pin)
Display digital B4 output pin
General-purpose I/O port (3V pin)
Display digital B5 output pin
General-purpose I/O port (3V pin)
Display digital B6 output pin
General-purpose I/O port(3V pin)
Display digital B7 output pin
General-purpose I/O port (3V pin)
Display reference clock input pin (for External sync)
GDC command trigger input pin
General-purpose I/O port (3V pin)
Capture vertical sync signal input pin
General-purpose I/O port (3V pin)
Capture horizontal sync signal input pin
General-purpose I/O port (3V pin)
Display composite sync signal output pin, Graphics /
Video switch (for External sync) output pin
General-purpose I/O port (3V pin)
Display reference clock output pin (for Internal sync)
General-purpose I/O port (3V pin)
Display vertical sync signal output pin (for Internal
sync)/Display vertical sync signal input pin (for External
sync)
General-purpose I/O port (3V pin)
Display horizontal sync signal output pin (for Internal
sync)/Display horizontal sync signal input pin (for
External sync)
General-purpose I/O port (3V pin)
Display enable display period output pin
General-purpose I/O port (3V pin)
For capture, capture clock input pin
Clamp level output pin
"L" side reference voltage for NTSC A/D converter pin
NTSC signal input pin
AD convertor analog power supply pin
For NTSC, AD convertor analog power supply pin
AD convertor upper limit reference voltage pin
AD convertor GND/ AD convertor lower limit reference
voltage pin
NTSC AD convertor GND pin
Built-in regulator capacitor connected pin 1
Built-in regulator capacitor connected pin 2
Built-in regulator capacitor connected pin 3
Page 28 of 174
MB91590 Series
Pin No.
126, 136,
146, 156
125, 135,
145, 155
89, 105,
122, 173
1, 18, 37,
53, 71,
175, 189
19, 36,
52, 72,
82, 88,
104, 123,
170, 174,
188, 208
*1
*2
Pin Name
Polarity
I/O Circuit
Types*1
Function*2
DVCC
–
–
SMC large current port power supply pin
DVSS
–
–
SMC large current port GND pin
VCC5
–
–
+5.0V power supply pin
VCC3
–
–
+3.3V power supply pin
VSS
–
–
GND pin
: For the I/O circuit types, see "I/O Circuit Type".
: For switching, see "I/O Port" of Hardware Manual.
Document Number: 002-04727 Rev. *B
Page 29 of 174
MB91590 Series
3.2
MB91F59A/B (BGA320)
BGA Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
23
Pin Name
VSS
VSS
AVCC3
VIN
REFOUT
AVCC3
BIN5
PC5
BIN2
PC2
GIN5
PB5
GIN2
VIN6
PB2
RIN5
VIN3
PA5
RIN2
VIN0
PA2
VSS
P136
(X1A)
P137
(X0A)
VSS
P094
ICU1_1
INT15
SIN3
PPG9_1
TIN9_1
SGO1
ADTG
P090
PPG0_2
TIN7_1
TCK
VSS
TMS
TDO
AN31
P087
ICU4_2
PPG23
PWM2M5
–
–
–
–
–
–
I/O Circuit
Types*1
–
–
–
S
T
–
–
O
–
O
–
O
–
O
–
O
–
O
–
–
–
–
–
A
N
A
N
–
–
C
–
A
–
–
–
–
U
–
U
W
–
E
–
E
Polarity
–
Document Number: 002-04727 Rev. *B
Function*2
GND pin
GND pin
For NTSC, AD convertor analog power supply pin
NTSC signal input pin
Clamp level output pin
For NTSC, AD convertor analog power supply pin
Capture B5 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture B2 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture G5 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture G2 input pin (RGB mode)
Capture VIN6 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture R5 input pin (RGB mode)
Capture VIN3 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture R2 input pin (RGB mode)
Capture VIN0 input pin (656 mode)
General-purpose I/O port (3V pin)
GND pin
General-purpose I/O port (Single clock product)
Sub clock oscillation output pin (Dual clock product)
General-purpose I/O port (Single clock product)
Sub clock oscillation input pin (Dual clock product)
GND pin
General-purpose I/O port
Input capture ch.1 input pin (1)
INT15 External interrupt input pin
LIN-UART ch.3 serial data input pin
PPG ch.9 output pin (1)
Reload timer ch.9 event input pin (1)
Sound generator ch.1 SGO output pin
A/D convertor external trigger input pin
General-purpose I/O port
PPG ch.0 output pin (2)
Reload timer ch.7 event input pin (1)
Test Clock (JTAG Boundary Scan Test)
GND pin
Test Mode State (JTAG Boundary Scan Test)
Test Data Out (JTAG Boundary Scan Test)
ADC Analog 31 input pin
General-purpose I/O port
Input capture ch.4 input pin (2)
PPG ch.23 output pin
SMC ch.5 output pin
Page 30 of 174
MB91590 Series
BGA Pin
No.
24
25
26
27
28
29
30
31
32
33
34
35
Pin Name
AN28
P084
ICU1_2
PPG20
PWM1P5
UDCBIN2
AN25
P081
SOT6
PPG17
PWM1M4
UDCBIN0_1
AN22
P076
ICU7
SOT7_1
PPG14_1
PWM2P3
AN19
P073
ICU10
SOT8
PWM2M2
AN16
P070
SOT9
PWM1P2
AN13
P065
PWM1M1
UDCZIN0
AN10
P062
SCK10
PWM2P0
UDCZIN1
VSS
C_1
AN5
P105
ICU9_1
SCK5_1
PPG3_1
TOT1_1
AVSS5
AVRL5
AVRH5
Polarity
I/O Circuit
Types*1
–
E
–
E
–
E
–
E
–
E
–
E
–
E
–
–
–
–
–
C
–
–
–
–
Document Number: 002-04727 Rev. *B
Function*2
ADC Analog 28 input pin
General-purpose I/O port
Input capture ch.1 input pin (2)
PPG ch.20 output pin
SMC ch.5 output pin
Up/down counter ch.2 BIN input pin
ADC Analog 25 input pin
General-purpose I/O port
LIN-UART ch.6 serial data output pin
PPG ch.17 output pin
SMC ch.4 output pin
Up/down counter ch.0 BIN input pin (1)
ADC Analog 22 input pin
General-purpose I/O port
Input capture ch.7 input pin
LIN-UART ch.7 serial data output pin
PPG ch.14 output pin (1)
SMC ch.3 output pin
ADC Analog 19 input pin
General-purpose I/O port
Input capture ch.10 input pin
Multi-function serial ch.8 serial data output pin
SMC ch.2 output pin
ADC Analog 16 input pin
General-purpose I/O port
Multi-function serial ch.9 serial data output pin
SMC ch.2 output pin
ADC Analog 13 input pin
General-purpose I/O port
SMC ch.1 output pin
Up/down counter ch.0 ZIN input pin
ADC Analog 10 input pin
General-purpose I/O port
Multi-function serial ch.10 clock I/O pin
SMC ch.0 output pin
Up/down counter ch.1 ZIN input pin
GND pin
Built-in regulator capacitor connected pin 1
ADC Analog 5 input pin
General-purpose I/O port
Input capture ch.9 input pin (1)
LIN-UART ch.5 clock I/O pin (1)
PPG ch.3 output pin (1)
Reload timer ch.1 output pin (1)
A/D convertor GND
A/D convertor lower limit reference voltage pin
A/D convertor upper limit reference voltage pin
Page 31 of 174
MB91590 Series
BGA Pin
No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin Name
P125
ICU0
SCK11
OCU3
PPG10_2
TIN10
P123
SIN11
OCU1
PPG8_2
TIN8
VSS
VSS
MD3
DEBUGIF
TX1
FRCK5
P110
PPG1_2
TOT8_1
P091
ICU2_1
INT12
SIN2
PPG6_1
TOT2_1
SGA0
VSS
X0
X1
VSS
A23
P055
SPI_SCK
A22
P054
SPI_DI
C_2
Polarity
I/O Circuit
Types*1
–
A
–
A
–
–
–
–
–
–
F3
G
–
C
–
C
–
–
–
–
–
L
L
–
–
O
–
O
–
–
Document Number: 002-04727 Rev. *B
Function*2
General-purpose I/O port
Input capture ch.0 input pin
Multi-function serial ch.11 clock I/O pin
Output compare ch.3 output pin
PPG ch.10 output pin (2)
Reload timer ch.10 event input pin
General-purpose I/O port
Multi-function serial ch.11 serial data input pin
Output compare ch.1 output pin
PPG ch.8 output pin (2)
Reload timer ch.8 event input pin
GND pin
GND pin
Mode pin 3
DEBUG I/F pin
CAN transmission data1 output pin
Free-run timer 5 clock input pin
General-purpose I/O port
PPG ch.1 output pin (2)
Reload timer ch.8 output pin (1)
General-purpose I/O port
Input capture ch.2 input pin (1)
INT12 External interrupt input pin
LIN-UART ch.2 serial data input pin
PPG ch.6 output pin (1)
Reload timer ch.2 output pin (1)
Sound generator ch.0 SGA output pin
GND pin
Main clock oscillation input pin
Main clock oscillation output pin
GND pin
External bus · Address bit23 output pin
General-purpose I/O port (3V pin)
SPI clock output pin
External bus · Address bit22 output pin
General-purpose I/O port (3V pin)
SPI data input pin
Built-in regulator capacitor connected pin 2
Page 32 of 174
MB91590 Series
BGA Pin
No.
51
52
53
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Pin Name
A17
P047
QSPI_CLK
A15
P045
QSPI_CS2
A12
P042
QSPI_SIO3
A09
P037
QSPI_SIO0
A05
P033
A02
P030
VSS
VSS
VSS
P025
CS1X
P022
D15
P017
GOUT1
D12
P014
D8
P010
D7
P007
PPG7
TOT3_2
D4
P004
SOT3_1
PPG4
TOT0_2
D1
P001
SOT2_1
PPG1
TIN1_2
DCKOUT
PG4
VSS
C_3
BOUT4
PF4
Polarity
I/O Circuit
Types*1
–
O
–
O
–
O
–
O
–
O
–
O
–
O
–
–
–
–
–
–
–
O
–
O
–
O
–
O
–
O
–
O
–
O
–
O
–
O
–
–
–
–
–
O
Document Number: 002-04727 Rev. *B
Function*2
External bus · Address bit17 output pin
General-purpose I/O port (3V pin)
HS_SPI SCLK Output pin
External bus · Address bit15 output pin
General-purpose I/O port (3V pin)
HS_SPI SSEL2 Output pin
External bus · Address bit12 output pin
General-purpose I/O port (3V pin)
HS_SPI SDATA3 I/O pin
External bus · Address bit9 output pin
General-purpose I/O port (3V pin)
HS_SPI SDATA0 I/O pin
External bus · Address bit5 output pin
General-purpose I/O port (3V pin)
External bus · Address bit2 output pin
General-purpose I/O port (3V pin)
GND pin
GND pin
GND pin
General-purpose I/O port (3V pin)
External bus · Chip select 1 output pin
General-purpose I/O port (3V pin)
External bus · Data bit15 I/O pin
General-purpose I/O port (3V pin)
Display digital G1 output pin
External bus · Data bit12 I/O pin
General-purpose I/O port (3V pin)
External bus · Data bit8 I/O pin
General-purpose I/O port (3V pin)
External bus · Data bit7 I/O pin
General-purpose I/O port (3V pin)
PPG ch.7 output pin
Reload timer ch.3 output pin (2)
External bus · Data bit4 I/O pin
General-purpose I/O port (3V pin)
LIN-UART ch.3 serial data output pin (1)
PPG ch.4 output pin
Reload timer ch.0 output pin (2)
External bus · Data bit1 I/O pin
General-purpose I/O port (3V pin)
LIN-UART ch.2 serial data output pin (1)
PPG ch.1 output pin
Reload timer ch.1 event input pin (2)
Display reference clock output pin (for Internal sync)
General-purpose I/O port (3V pin)
GND pin
Built-in regulator capacitor connected pin 3
Display digital B4 output pin
General-purpose I/O port (3V pin)
Page 33 of 174
MB91590 Series
BGA Pin No.
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Pin Name
GOUT7
PE7
GOUT4
PE4
ROUT7
PD7
ROUT4
PD4
VSS
VSS
VSS
AVSS3
AVR3
AVSS3
BIN6
PC6
BIN3
PC3
GIN6
PB6
GIN3
VIN7
PB3
RIN6
VIN4
PA6
RIN3
VIN1
PA3
P122
SCK5
OCU0
PPG7_2
TOT3
VSS
MD2
FRCK7
P114
ICU5_1
SCK3
TRG3
TIN1
SGA2
RX2
P113
INT11
PPG4_2
TIN7
TDI
Polarity
I/O Circuit
Types*1
–
O
–
O
–
O
–
O
–
–
–
–
–
–
–
–
–
–
S
–
–
O
–
O
–
O
–
O
–
O
–
O
–
C
–
–
–
F2
–
C
–
C
–
U
Document Number: 002-04727 Rev. *B
Function*2
Display digital G7 output pin
General-purpose I/O port (3V pin)
Display digital G4 output pin
General-purpose I/O port (3V pin)
Display digital R7 output pin
General-purpose I/O port (3V pin)
Display digital R4 output pin
General-purpose I/O port (3V pin)
GND pin
GND pin
GND pin
NTSC AD convertor GND pin
"L" side reference voltage for NTSC A/D converter pin
NTSC AD convertor GND pin
Capture B6 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture B3 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture G6 input pin (RGB mode)
General-purpose I/O port (3V pin)
Capture G3 input pin (RGB mode)
Capture VIN7 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture R6 input pin (RGB mode)
Capture VIN4 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture R3 input pin (RGB mode)
Capture VIN1 input pin (656 mode)
General-purpose I/O port (3V pin)
General-purpose I/O port
LIN-UART ch.5 clock I/O pin
Output compare ch.0 output pin
PPG ch.7 output pin (2)
Reload timer ch.3 output pin
GND pin
Mode pin 2
Free-run timer 7 clock input pin
General-purpose I/O port
Input capture ch.5 input pin (1)
LIN-UART ch.3 clock I/O pin
PPG trigger 3 input pin (ch.12 to ch.15)
Reload timer ch.1 event input pin
Sound generator ch.2 SGA output pin
CAN reception data 2 input pin
General-purpose I/O port
INT11 External interrupt input pin
PPG ch.4 output pin (2)
Reload timer ch.7 event input pin
Test Data In (JTAG Boundary Scan Test)
Page 34 of 174
MB91590 Series
BGA Pin No.
94
95
96
96
97
98
99
100
101
102
103
104
Pin Name
VSS
TRST
AN30
P086
ICU3_2
PPG22
PWM2P5
AN27
P083
ICU0_2
PPG19
PWM2M4
UDCZIN2
AN24
P080
SIN6
PPG16
PWM1P4
UDCAIN0_1
AN21
P075
ICU8
SIN7_1
PPG13_1
PWM1M3
AN18
P072
ICU11
SIN8
PWM2P2
AN15
P067
SIN9
PWM2M1
UDCAIN0
AN12
P064
PWM1P1
UDCAIN1
AN9
P061
SOT10
PWM1M0
VSS
Polarity
I/O Circuit
Types*1
–
–
–
V
–
E
–
E
–
E
–
E
–
E
–
E
–
E
–
E
–
E
–
–
Document Number: 002-04727 Rev. *B
Function*2
GND pin
Test Reset (JTAG Boundary Scan Test)
ADC Analog 30 input pin
General-purpose I/O port
Input capture ch.3 input pin (2)
PPG ch.22 output pin
SMC ch.5 output pin
ADC Analog 27 input pin
General-purpose I/O port
Input capture ch.0 input pin (2)
PPG ch.19 output pin
SMC ch.4 output pin
Up/down counter ch.2 ZIN input pin
ADC Analog 24 input pin
General-purpose I/O port
LIN-UART ch.6 serial data input pin
PPG ch.16 output pin
SMC ch.4 output pin
Up/down counter ch.0 AIN input pin (1)
ADC Analog 21 input pin
General-purpose I/O port
Input capture ch.8 input pin
LIN-UART ch.7 serial data input pin
PPG ch.13 output pin (1)
SMC ch.3 output pin
ADC Analog 18 input pin
General-purpose I/O port
Input capture ch.11 input pin
Multi-function serial ch.8 serial data input pin
SMC ch.2 output pin
ADC Analog 15 input pin
General-purpose I/O port
Multi-function serial ch.9 serial data input pin
SMC ch.1 output pin
Up/down counter ch.0 AIN input pin
ADC Analog 12 input pin
General-purpose I/O port
SMC ch.1 output pin
Up/down counter ch.1 AIN input pin
ADC Analog 9 input pin
General-purpose I/O port
Multi-function serial ch.10 serial data output pin
SMC ch.0 output pin
GND pin
Page 35 of 174
MB91590 Series
BGA Pin No.
105
106
106
107
108
109
110
111
112
113
114
115
Pin Name
AN7
P107
ICU11_1
PPG5_1
TOT7_1
SGO4_1
AN4
P104
ICU8_1
SOT5_1
PPG2_1
TOT0_1
AN2
P102
ICU6_1
SCK4_1
PPG10
TIN2_1
AVCC5
P124
ICU5_2
SOT11
OCU2
PPG9_2
TIN9
RX0
P096
INT9
VSS
RX1
FRCK6
P111
INT10
PPG2_2
TOT9_1
P093
ICU3_1
INT14
SOT2
PPG8_1
TIN8_1
SGA1
NMIX
TIOA1
P131
ICU2
INT4
SIN1
TRG1
TOT7
Polarity
I/O Circuit
Types*1
–
C
–
C
–
C
–
C
–
–
–
A
–
A
–
–
–
C
–
C
N
F1
–
A
Document Number: 002-04727 Rev. *B
Function*2
ADC Analog 7 input pin
General-purpose I/O port
Input capture ch.11 input pin (1)
PPG ch.5 output pin (1)
Reload timer ch.7 output pin (1)
Sound generator ch.4 SGO output pin
ADC Analog 4 input pin
General-purpose I/O port
Input capture ch.8 input pin (1)
LIN-UART ch.5 serial data output pin (1)
PPG ch.2 output pin (1)
Reload timer ch.0 output pin (1)
ADC Analog 2 input pin
General-purpose I/O port
Input capture ch.6 input pin (1)
LIN-UART ch.4 clock I/O pin (1)
PPG ch.10 output pin
Reload timer ch.2 event input pin (1)
A/D convertor analog power supply pin
General-purpose I/O port
Input capture ch.5 input pin (2)
Multi-function serial ch.11 serial data output pin
Output compare ch.2 output pin
PPG ch.9 output pin (2)
Reload timer ch.9 event input pin
CAN reception data0 input pin
General-purpose I/O port
INT9 External interrupt input pin
GND pin
CAN reception data 1 input pin
Free-run timer 6 clock input pin
General-purpose I/O port
INT10 External interrupt input pin
PPG ch.2 output pin (2)
Reload timer ch.9 output pin (1)
General-purpose I/O port
Input capture ch.3 input pin (1)
INT14 External interrupt input pin
LIN-UART ch.2 serial data output pin
PPG ch.8 output pin (1)
Reload timer ch.8 event input pin (1)
Sound generator ch.1 SGA output pin
Non-masking interrupt input pin
Base timer TIOA1 I/O pin
General-purpose I/O port
Input capture ch.2 input pin
INT4 External interrupt input pin
Multi-function serial ch.1 serial data input pin
PPG trigger 1 input pin (ch.4 to ch.7)
Reload timer ch.7 output pin
Page 36 of 174
MB91590 Series
BGA Pin No.
116
117
118
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
Pin Name
MD0
MD1
P126
INT1
SIN0
TRG0
A24
P056
SPI_XCS
A21
P053
SPI_DO
VSS
A16
P046
QSPI_CS3
A14
P044
QSPI_CS1
A11
P041
QSPI_SIO2
A08
P036
A04
P032
A01
P027
VSS
A00
P026
REX
P023
WEX
P020
BOUT0
D13
P015
ROUT0
D9
P011
D6
P006
PPG6
TOT2_2
D3
P003
SIN3_1
PPG3
TIN3_2
Polarity
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Function*2
Types*1
P
Mode pin 0
P
Mode pin 1
General-purpose I/O port
A
INT1 External interrupt input pin
Multi-function serial ch.0 serial data input pin
A
PPG trigger 0 input pin (ch.0 to ch.3)
External bus · Address bit24 output pin
O
General-purpose I/O port (3V pin)
SPI chip select output pin
External bus · Address bit21 output pin
O
General-purpose I/O port(3V pin)
SPI data output pin
–
GND pin
External bus · Address bit16 output pin
O
General-purpose I/O port (3V pin)
HS_SPI SSEL3 Output pin
External bus · Address bit14 output pin
O
General-purpose I/O port (3V pin)
HS_SPI SSEL1 Output pin
External bus · Address bit11 output pin
O
General-purpose I/O port (3V pin)
HS_SPI SDATA2 I/O pin
External bus · Address bit8 output pin
O
General-purpose I/O port (3V pin)
External bus · Address bit4 output pin
O
General-purpose I/O port (3V pin)
External bus · Address bit1 output pin
O
General-purpose I/O port (3V pin)
–
GND pin
External bus · Address bit0 output pin
O
General-purpose I/O port (3V pin)
External bus · Read enable output pin
O
General-purpose I/O port (3V pin)
External bus · Write enable output pin
O
General-purpose I/O port (3V pin)
Display digital B0 output pin
O
External bus · Data bit13 I/O pin
General-purpose I/O port (3V pin)
Display digital R0 output pin
O
External bus · Data bit9 I/O pin
General-purpose I/O port (3V pin)
External bus · Data bit6 I/O pin
General-purpose I/O port (3V pin)
O
PPG ch.6 output pin
Reload timer ch.2 output pin (2)
External bus · Data bit3 I/O pin
General-purpose I/O port (3V pin)
O
LIN-UART ch.3 serial data input pin (1)
PPG ch.3 output pin
Reload timer ch.3 event input pin (2)
Page 37 of 174
MB91590 Series
BGA Pin No.
136
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
Pin Name
D0
P000
SIN2_1
PPG0
TIN0_2
VSYNC
PG5
BOUT7
PF7
BOUT5
PF5
BOUT3
PF3
GOUT6
PE6
GOUT3
PE3
ROUT6
PD6
ROUT3
PD3
VSS
DCKIN
CMDTRG
PG0
CSOUT
PG3
HSIN
PG2
BIN7
PC7
BIN4
PC4
GIN7
PB7
GIN4
PB4
RIN7
VIN5
PA7
RIN4
VIN2
PA4
FRCK0
P121
INT7
Polarity
–
–
–
–
–
–
–
–
–
–
–
–
–
P
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
I/O Circuit
Function*2
Types*1
O
External bus · Data bit0 I/O pin
General-purpose I/O port (3V pin)
LIN-UART ch.2 serial data input pin (1)
O
PPG ch.0 output pin
Reload timer ch.0 event input pin (2)
Display vertical sync signal output pin (for Internal sync)/
Display vertical sync signal input pin (for External sync)
O
General-purpose I/O port (3V pin)
Display digital B7 output pin
O
General-purpose I/O port(3V pin)
Display digital B5 output pin
O
General-purpose I/O port (3V pin)
Display digital B3 output pin
O
General-purpose I/O port (3V pin)
Display digital G6 output pin
O
General-purpose I/O port (3V pin)
Display digital G3 output pin
O
General-purpose I/O port (3V pin)
Display digital R6 output pin
O
General-purpose I/O port (3V pin)
Display digital R3 output pin
O
General-purpose I/O port (3V pin)
–
GND pin
Display reference clock input pin (for External sync)
O
GDC command trigger input pin
General-purpose I/O port (3V pin)
Display composite sync signal output pin, Graphics /
Video switch (for External sync) output pin
O
General-purpose I/O port (3V pin)
Capture horizontal sync signal input pin
O
General-purpose I/O port (3V pin)
Capture B7 input pin (RGB mode)
O
General-purpose I/O port (3V pin)
Capture B4 input pin (RGB mode)
O
General-purpose I/O port (3V pin)
Capture G7 input pin (RGB mode)
O
General-purpose I/O port (3V pin)
Capture G4 input pin (RGB mode)
O
General-purpose I/O port (3V pin)
Capture R7 input pin (RGB mode)
O
Capture VIN5 input pin (656 mode)
General-purpose I/O port (3V pin)
Capture R4 input pin (RGB mode)
O
Capture VIN2 input pin (656 mode)
General-purpose I/O port (3V pin)
Free-run timer 0 clock input pin
C
General-purpose I/O port
INT7 External interrupt input pin
Page 38 of 174
MB91590 Series
BGA Pin No.
155
156
157
158
158
159
160
161
162
163
164
164
Pin Name
SOT5
PPG6_2
TOT2
FRCK1
P120
INT6
SIN5
PPG5_2
TOT1
FRCK3
P116
SOT4
TIN3
SGA3
P097
ICU4_1
INT8
SOT3
PPG0_1
TIN0
WOT
TX2
P112
PPG3_2
TOT10_1
VSS
AN29
P085
ICU2_2
PPG21
PWM1M5
UDCAIN2
AN26
P082
SCK6
PPG18
PWM2P4
UDCZIN0_1
AN23
P077
ICU6
SCK7_1
PPG15_1
PWM2M3
AN20
P074
ICU9
SCK8
PPG12_1
PWM1P3
Circuit
Polarity I/O
Types*1
–
C
–
C
–
C
–
C
–
C
–
–
–
E
–
E
–
E
–
E
–
E
Document Number: 002-04727 Rev. *B
Function*2
LIN-UART ch.5 serial data output pin
PPG ch.6 output pin (2)
Reload timer ch.2 output pin
Free-run timer 1 clock input pin
General-purpose I/O port
INT6 External interrupt input pin
LIN-UART ch.5 serial data input pin
PPG ch.5 output pin (2)
Reload timer ch.1 output pin
Free-run timer 3 clock input pin
General-purpose I/O port
LIN-UART ch.4 serial data output pin
Reload timer ch.3 event input pin
Sound generator ch.3 SGA output pin
General-purpose I/O port
Input capture ch.4 input pin (1)
INT8 External interrupt input pin
LIN-UART ch.3 serial data output pin
PPG ch.0 output pin (1)
Reload timer ch.0 event input pin
RTC overflow output pin
CAN transmission data 2 output pin
General-purpose I/O port
PPG ch.3 output pin (2)
Reload timer ch.10 output pin (1)
GND pin
ADC Analog 29 input pin
General-purpose I/O port
Input capture ch.2 input pin (2)
PPG ch.21 output pin
SMC ch.5 output pin
Up/down counter ch.2 AIN input pin
ADC Analog 26 input pin
General-purpose I/O port
LIN-UART ch.6 clock I/O pin
PPG ch.18 output pin
SMC ch.4 output pin
Up/down counter ch.0 ZIN input pin (1)
ADC Analog 23 input pin
General-purpose I/O port
Input capture ch.6 input pin
LIN-UART ch.7 clock I/O pin
PPG ch.15 output pin (1)
SMC ch.3 output pin
ADC Analog 20 input pin
General-purpose I/O port
Input capture ch.9 input pin
Multi-function serial ch.8 clock I/O pin
PPG ch.12 output pin (1)
SMC ch.3 output pin
Page 39 of 174
MB91590 Series
BGA Pin No.
165
166
167
167
168
169
170
171
172
173
174
175
176
Pin Name
AN17
P071
SCK9
PWM1M2
AN14
P066
PWM2P1
UDCBIN0
AN11
P063
PWM2M0
UDCBIN1
AN8
P060
SIN10
PWM1P0
VCC5
AN6
P106
ICU10_1
PPG4_1
TIN10_1
SGA4_1
AN3
P103
ICU7_1
SIN5_1
PPG1_1
TIN3_1
AN1
P101
SOT4_1
PPG9
TIN1_1
AN0
P100
SIN4_1
PPG8
TIN0_1
TX0
P095
PPG10_1
VSS
P092
ICU0_1
INT13
SCK2
PPG7_1
TOT3_1
SGO0
Polarity
I/O Circuit
Types*1
–
E
–
E
–
E
–
E
–
–
–
C
–
C
–
C
–
C
–
A
–
–
–
C
Document Number: 002-04727 Rev. *B
Function*2
ADC Analog 17 input pin
General-purpose I/O port
Multi-function serial ch.9 clock I/O pin
SMC ch.2 output pin
ADC Analog 14 input pin
General-purpose I/O port
SMC ch.1 output pin
Up/down counter ch.0 BIN input pin
ADC Analog 11 input pin
General-purpose I/O port
SMC ch.0 output pin
Up/down counter ch.1 BIN input pin
ADC Analog 8 input pin
General-purpose I/O port
Multi-function serial ch.10 serial data input pin
SMC ch.0 output pin
+5.0V power supply pin
ADC Analog 6 input pin
General-purpose I/O port
Input capture ch.10 input pin (1)
PPG ch.4 output pin (1)
Reload timer ch.10 event input pin (1)
Sound generator ch.4 SGA output pin
ADC Analog 3 input pin
General-purpose I/O port
Input capture ch.7 input pin (1)
LIN-UART ch.5 serial data input pin (1)
PPG ch.1 output pin (1)
Reload timer ch.3 event input pin (1)
ADC Analog 1 input pin
General-purpose I/O port
LIN-UART ch.4 serial data output pin (1)
PPG ch.9 output pin
Reload timer ch.1 event input pin (1)
ADC Analog 0 input pin
General-purpose I/O port
LIN-UART ch.4 serial data input pin (1)
PPG ch.8 output pin
Reload timer ch.0 event input pin (1)
CAN transmission data0 output pin
General-purpose I/O port
PPG ch.10 output pin (1)
GND pin
General-purpose I/O port
Input capture ch.0 input pin (1)
INT13 External interrupt input pin
LIN-UART ch.2 clock I/O pin
PPG ch.7 output pin (1)
Reload timer ch.3 output pin (1)
Sound generator ch.0 SGO output pin
Page 40 of 174
MB91590 Series
BGA Pin No.
177
177
178
Pin Name
P134
ICU5
INT5
PPG1_3
TRG2
TOT10
TIOB0
P132
ICU3
INT2
Circuit
Polarity I/O
Types*1
–
A
–
K
–
K
–
K
N
F1
–
O
–
O
–
O
–
O
–
O
–
O
–
O
–
–
–
–
O
O
–
O
–
O
–
O
SOT1
179
TOT8
TIOA0
P130
ICU1
INT0
SCK0
P127
180
181
182
183
184
185
186
187
188
189
189
190
191
192
193
SOT0
RSTX
RDY
P057
A20
P052
A19
P051
A18
P050
A13
P043
QSPI_CS0
A10
P040
QSPI_SIO1
A07
P035
A03
P031
VSS
P024
CS0X
P021
BOUT1
D14
P016
Document Number: 002-04727 Rev. *B
Function*2
General-purpose I/O port
Input capture ch.5 input pin
INT5 External interrupt input pin
PPG ch.1 output pin (3)
PPG trigger 2 input pin ( ch.8 to ch.11)
Reload timer ch.10 output pin
Base timer TIOB0 input pin
General-purpose I/O port
Input capture ch.3 input pin
INT2 External interrupt input pin
Multi-function serial ch.1 serial data output pin / I2C ch.1
serial data I/O pin
Reload timer ch.8 output pin
Base timer TIOA0 output pin
General-purpose I/O port
Input capture ch.1 input pin
INT0 External interrupt input pin
Multi-function serial ch.0 clock I/O pin / I2C ch.0 clock I/O
pin
General-purpose I/O port
Multi-function serial ch.0 serial data output pin / I2C ch.0
serial data I/O pin
External reset input pin
External bus · Wait input pin
General-purpose I/O port (3V pin)
External bus · Address bit20 output pin
General-purpose I/O port(3V pin)
External bus · Address bit19 output pin
General-purpose I/O port(3V pin)
External bus · Address bit18 output pin
General-purpose I/O port (3V pin)
External bus · Address bit13 output pin
General-purpose I/O port (3V pin)
HS_SPI SSEL0 Output pin
External bus · Address bit10 output pin
General-purpose I/O port (3V pin)
HS_SPI SDATA1 I/O pin
External bus · Address bit7 output pin
General-purpose I/O port (3V pin)
External bus · Address bit3 output pin
General-purpose I/O port (3V pin)
GND pin
General-purpose I/O port (3V pin)
External bus · Chip select 0 output pin
General-purpose I/O port (3V pin)
Display digital B1 output pin
External bus · Data bit14 I/O pin
General-purpose I/O port (3V pin)
Page 41 of 174
MB91590 Series
BGA Pin
No.
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
Pin Name
ROUT1
D10
P012
D5
P005
SCK3_1
PPG5
TOT1_2
D2
P002
SCK2_1
PPG2
TIN2_2
DEOUT
PG7
HSYNC
PG6
BOUT6
PF6
BOUT2
PF2
GOUT5
PE5
GOUT2
PE2
ROUT5
PD5
ROUT2
PD2
VSS
CCLK
PH3
VSIN
PG1
VCC3
VSS
VSS
VCC3
VCC3
VSS
VCC5
FRCK2
P117
SCK4
TRG4
TOT0
SGO3
I/O Circuit
Types*1
Polarity
–
O
–
O
–
O
P
–
O
–
O
–
O
–
O
–
O
–
O
–
O
–
O
–
–
–
O
P
–
–
–
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
O
–
–
–
–
–
–
–
C
Function*2
Display digital R1 output pin
External bus · Data bit10 I/O pin
General-purpose I/O port (3V pin)
External bus · Data bit5 I/O pin
General-purpose I/O port (3V pin)
LIN-UART ch.3 clock I/O pin (1)
PPG ch.5 output pin
Reload timer ch.1 output pin (2)
External bus · Data bit2 I/O pin
General-purpose I/O port (3V pin)
LIN-UART ch.2 clock I/O pin (1)
PPG ch.2 output pin
Reload timer ch.2 event input pin (2)
Display enable display period output pin
General-purpose I/O port (3V pin)
Display horizontal sync signal output pin (for Internal
sync)/ Display horizontal sync signal input pin (for
External sync)
General-purpose I/O port (3V pin)
Display digital B6 output pin
General-purpose I/O port (3V pin)
Display digital B2 output pin
General-purpose I/O port (3V pin)
Display digital G5 output pin
General-purpose I/O port (3V pin)
Display digital G2 output pin
General-purpose I/O port (3V pin)
Display digital R5 output pin
General-purpose I/O port (3V pin)
Display digital R2 output pin
General-purpose I/O port (3V pin)
GND pin
For capture, capture clock input pin
General-purpose I/O port (3V pin)
Capture vertical sync signal input pin
General-purpose I/O port (3V pin)
+3.3V power supply pin
GND pin
GND pin
+3.3V power supply pin
+3.3V power supply pin
GND pin
+5.0V power supply pin
Free-run timer 2 clock input pin
General-purpose I/O port
LIN-UART ch.4 clock I/O pin
PPG trigger 4 input pin (ch.16 to ch.19)
Reload timer ch.0 output pin
Sound generator ch.3 SGO output pin
Page 42 of 174
MB91590 Series
BGA Pin
No.
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Pin Name
FRCK4
P115
SIN4
TIN2
SGO2
VCC5
VSS
DVCC
DVSS
DVCC
DVSS
DVCC
DVSS
DVCC
DVSS
VCC5
VSS
VCC5
VCC5
VSS
VSS
TIOB1
P133
ICU4
INT3
SCK1
PPG11_1
TRG5
TOT9
VCC5
VCC5
VSS
VSS
VSS
VCC3
VCC3
VSS
VCC3
A06
P034
VSS
VSS
VCC3
GOUT0
D11
P013
VCC3
VSS
VSS
I/O Circuit
Types*1
Polarity
–
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
K
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
O
–
–
–
–
–
–
–
O
–
–
–
–
–
–
Document Number: 002-04727 Rev. *B
Function*2
Free-run timer 4 clock input pin
General-purpose I/O port
LIN-UART ch.4 serial data input pin
Reload timer ch.2 event input pin
Sound generator ch.2 SGO output pin
+5.0V power supply pin
GND pin
SMC large current port power supply pin
SMC large current port GND pin
SMC large current port power supply pin
SMC large current port GND pin
SMC large current port power supply pin
SMC large current port GND pin
SMC large current port power supply pin
SMC large current port GND pin
+5.0V power supply pin
GND pin
+5.0V power supply pin
+5.0V power supply pin
GND pin
GND pin
Base timer TIOB1 input pin
General-purpose I/O port
Input capture ch.4 input pin
INT3 External interrupt input pin
Multi-function serial ch.1 clock I/O pin / I2C ch.1 clock I/O
pin
PPG ch.11 output pin (1)
PPG trigger 5 input pin ( ch.20 to ch.23)
Reload timer ch.9 output pin
+5.0V power supply pin
+5.0V power supply pin
GND pin
GND pin
GND pin
+3.3V power supply pin
+3.3V power supply pin
GND pin
+3.3V power supply pin
External bus · Address bit6 output pin
General-purpose I/O port (3V pin)
GND pin
GND pin
+3.3V power supply pin
Display digital G0 output pin
External bus · Data bit11 I/O pin
General-purpose I/O port (3V pin)
+3.3V power supply pin
GND pin
GND pin
Page 43 of 174
MB91590 Series
BGA Pin
No.
251
252
253
254
255
256
257
:
:
:
320
Pin Name
VSS
VCC3
VCC3
VSS
VCC3
VCC3
GND
:
:
:
GND
I/O Circuit
Types*1
Polarity
–
–
–
–
–
–
–
:
:
:
–
–
–
–
–
–
–
–
:
:
:
–
Function*2
GND pin
+3.3V power supply pin
+3.3V power supply pin
GND pin
+3.3V power supply pin
+3.3V power supply pin
GND pin
:
:
:
GND pin
*1
*2
: For the I/O circuit types, see "I/O Circuit Type".
: For switching, see "I/O Port" of Hardware Manual.
Document Number: 002-04727 Rev. *B
Page 44 of 174
MB91590 Series
4. I/O Circuit Type
Type
A
Circuit
Pull-up control
Digital output
Digital output
Pull-down control
•
•
•
•
•
•
•
•
Remarks
General-purpose I/O port
Output 1mA,2mA
Pull-up resistor control 50kΩ
Pull-down resistor control 50kΩ
CMOS input
Schmitt input
TTL input
Automotive input
•
•
•
•
•
•
•
•
Analog I/O, General-purpose I/O port
Output 1mA,2mA
Pull-up resistor control 50kΩ
Pull-down resistor control 50kΩ
CMOS input
Schmitt input
TTL input
Automotive input
CMOS-hys input
Standby control
CMOS input
Standby control
Automotive input
Standby control
TTL input
Standby control
C
Pull-up control
Digital output
Digital output
Pull-down control
CMOS-hys input
Standby control
CMOS input
Standby control
Automotive input
Standby control
TTL input
Standby
control input
Analog
Document Number: 002-04727 Rev. *B
Page 45 of 174
MB91590 Series
Type
E
Circuit
Remarks
• Analog input, General-purpose I/O port
• Output 1mA,2mA,30mA (large current for
SMC)
• Pull-up resistor control 50kΩ
• Pull-down resistor control 50kΩ
• CMOS input
• Schmitt input
• TTL input
• Automotive input
Pull-up control
Digital output
Digital output
Pull-down control
CMOS-hys input
Standby control
CMOS input
Standby control
Automotive input
Standby control
TTL input
Standby control
Analog input
F1
• Schmitt input
• Pull-up resistor control 50kΩ (5V cont)
CMOS-hys input
F2
• Schmitt input
• Pull-down resistor control 50kΩ (5V cont)
CMOS-hys input
F3
• Schmitt input
• Automotive input
• Pull-down resister control 50kΩ (5V cont)
CMOS-hys input
Automotive input
Document Number: 002-04727 Rev. *B
Page 46 of 174
MB91590 Series
Type
G
Circuit
Digital output
Remarks
• Open-drain I/O
• Output 25mA (NOD)
• TTL input
TTL input
J
Automotive input
Automotive input
K
Pull-up control
Digital output
Digital output
Pull-down control
•
•
•
•
•
•
•
•
Analog input, General-purpose I/O port
Output 1mA,2mA,3mA(I2C)
Pull-up resistor control 50kΩ
Pull-down resistor control 50kΩ
CMOS input
Schmitt input
TTL input
Automotive input
CMOS-hys input
Standby control
CMOS input
Standby control
Automotive input
Standby control
TTL input
Standby control
Analog input
L
Main oscillation I/O
Input
Standby control
N
Sub oscillation I/O
Input
Standby control
Document Number: 002-04727 Rev. *B
Page 47 of 174
MB91590 Series
Type
O
Circuit
•
•
•
•
•
Pull-up control
Digital output
Remarks
Output 2mA,5mA,10mA and 20mA
Pull-up resistor control 33kΩ
Pull-down resistor control 33kΩ
Schmitt input
TTL input
Digital output
Pull-down control
CMOS-hys input
Standby control
TTL input
Standby control
P
• Mode I/O
• Schmitt input
Mode input
Control
S
Analog input(3V)
Analog input
T
Analog output(3V)
Analog output
U
• TDI/TMS/TCK (JTAG)
• CMOS input
• Pull-up resistor control 50kΩ (1.2V Cont)
CMOS input
Document Number: 002-04727 Rev. *B
Page 48 of 174
MB91590 Series
Type
V
Circuit
Remarks
• TRST (JTAG)
• CMOS input
• Pull-up resistor control 50kΩ (1.2V Cont)
CMOS input
Standby control
W
Digital output
• TDO (JTAG)
In case of Boundary Scan Test mode.
• High Impedance state
In other case of Boundary Scan Test Mode.
• 5mA output
Digital output
Document Number: 002-04727 Rev. *B
Page 49 of 174
MB91590 Series
5. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
5.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
 Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
 Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
 Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected
through an appropriate resistance to a power supply pin or ground pin.
 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
 Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-04727 Rev. *B
Page 50 of 174
MB91590 Series
 Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
5.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
 Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
 Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
 Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-04727 Rev. *B
Page 51 of 174
MB91590 Series
 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance
(on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
5.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin
to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04727 Rev. *B
Page 52 of 174
MB91590 Series
6. Handling Devices
This section explains the latch-up prevention and treatment of a pin.
 For latch-up prevention
If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding the ratings is applied
between VCC pin and VSS pin, a latch-up may occur in CMOS IC. If the latch-up occurs, the power supply current increases
excessively and device elements may be damaged by heat. Take care to prevent any voltage from exceeding the maximum ratings
in device application.
Also, the analog power supply (AVCC5, AVRH5), the NTSC power supply (AVCC3, AVR3), analog input and power supply to
high-current output buffer pins must not be exceed the digital power supply (VCC5 or VCC3) when the power supply to the analog
system and high-current output buffer pins is turned on or off.
In the correct power-on sequence of the microcontroller, turn on the digital power supply (VCC5), analog power supplies (AVCC5,
AVRH5), and the power supply of high-current output buffer pins (DVCC) simultaneously. Or, turn on the digital power supply
(VCC5), and then turn on analog power supplies (AVCC5, AVRH5) and the power supply of high-current output buffer pins (DVCC).
In the correct power-on sequence of GDC, similarly turn on the digital power supply (VCC3) and the NTSC analog power supply
(AVCC3) simultaneously. Or, turn on the digital power supply (VCC3), and then turn on the NTSC analog power supply (AVCC3).
 Treatment of unused pins
If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or latch-up. Connect a
2kΩ resistor to each of unused pins for pull-up or pull-down processing.
Also, if I/O pins are not used, they must be set to the output state for opening or they must be set to the input state and treated in the
same way as for the input pins.
 Power supply pins
The device is designed to ensure that if the device contains multiple VCC pin or VSS pin, the pins that should be at the same
potential are interconnected to prevent latch-up or other malfunctions. Further, connect these pins to an external power supply or
ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised ground level, and fulfill the total
output current standard, etc. As shown in Figure 1, all Vss power supply pins must be treated in the similar way. If multiple Vcc or
Vss systems are connected, the device cannot operate correctly even within the guaranteed operating range.
Figure 1. Power Supply Input Pins
Vcc
Vss
Vss
Vcc
Vss
Vcc
Vcc
Vss
Vss
Vcc
The power supply pins should be connected to VCC pin and VSS pin of this device at the low impedance from the power supply
source.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin is recommended to
use as a bypass capacitor between the VCC pin and the VSS pin.
As for BGA package product, the solder balls of VSS and VCC are placed in the most internal circumference of
solder-ball-placement. In order to connect bypass capacitor close to these balls, the capacitors had better be implemented on the
back side of a system board surface on which BGA package is implemented.
Document Number: 002-04727 Rev. *B
Page 53 of 174
MB91590 Series
 Crystal oscillation circuit
An external noise to the X0 pin or X1 pin may cause a device malfunction. The printed circuit board must be designed to lay out the
X0 pin and the X1 pin, crystal oscillator (or ceramic resonator), and the bypass capacitor to be grounded to the close position to the
device.
The printed circuit board artwork is recommended to surround the X0 pin and X1 pin by ground circuits.
 Mode pins (MD2, MD1, MD0)
Connect the MD2, MD1and MD0 mode pin to the VCC pin or VSS pin directly. To prevent an erroneous selection of test mode
caused by the noise, reduce the pattern length between each mode pin and the VCC pin or VSS pin on the printed circuit board. Also,
use the low-impedance pin connection.
 During power-on
To prevent a malfunction of the voltage step-down circuit built in the device, set the voltage rising time to have 50μs or longer
(between 0.2V and 2.7V) during power-on.
 Notes during PLL clock operation
When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue to operate at
the free running frequency of the self-oscillator circuit built in the PLL clock. This operation is not guaranteed.
 Treatment of A/D converter power supply pins
Connect the pins to have AVCC5=AVRH5=VCC5 and AVSS5/AVRL5=VSS even if the A/D converter is not used.
Also, similarly connect the pins of NTSC A/D converter power supply to have AVCC3=VCC3 and AVSS3=VSS. At this time, open
VIN/REFOUT.
 Notes on using external clock
An external clock is not supported. None of the external direct clock input can be used for both main clock and sub clock.
 Power-on sequence of A/D converter analog inputs
Be sure to turn on the digital power supply (Vcc5) first, and then turn on the A/D converter power supplies (AVcc5, AVRH5, AVRL5)
and analog inputs (AN0 to AN31). Also, turn off the A/D converter power supplies and analog inputs first, and then turn off the digital
power supply (Vcc5). When the AVRH5 pin voltage is turned on or off, it must not exceed AVCC5. Even if a common analog input
pin is used as an input port, its input voltage must not exceed AVcc5. (However, the analog power supply and digital power supply
can be turned on or off simultaneously.)
Be sure to similarly turn on the digital power supply (VCC3) first, and then turn on the A/D converter power supply (AVCC3) for
NTSC and NTSC inputs (VIN, AVR). Also, turn off the A/D converter power supplies and analog inputs first, and then turn off the
digital power supply (VCC3).
 Treatment of power supplies for high current output buffer pins (DVcc, DVss)
Be sure to turn on the digital power supply (Vcc) first, and then turn on the power supplies for high current output buffer pins (DVcc,
DVss). Also, turn off the power supplies for high current output buffer pins first, and then turn off the digital power supply (Vcc).
Even if the high current output buffer pins are used as general-purpose ports, the power supplies of high current output buffer pins
(DVcc, DVss) must be powered. (The power supplies of high current output buffer pins and the digital power supplies can be turned
on or off simultaneously. )
 Treatment of C pin
This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to assure the internal
stabilization of the device. For the standard values, see the "Recommended Operating Conditions" of the latest data sheet.
 Function switching of a multiplexed port
To switch between the port function and the multiplexed pin function, use the PFR (port function register).
 Low-power consumption mode
To transit to the sleep mode, watch mode, stop mode, watch mode(power-off) or stop mode(power-off), follow the procedure
explained in the "Activating the sleep mode, watch mode, or stop mode" or the "Activating the watch mode (power-off) or stop
mode(power-off)" of " POWER CONSUMPTION CONTROL".
Power supply for GDC can be turned off separately from the microcontroller.
Take the following notes when using a monitor debugger.
• Do not set a break point for the low-power consumption transition program.
• Do not execute an operation step for the low-power consumption transition program.
Document Number: 002-04727 Rev. *B
Page 54 of 174
MB91590 Series
 Precautions when writing to registers including the status flag
When writing data in the register that has a status flag (especially, an interrupt request flag) to control function, taking care not to
clear its status flag erroneously must be followed.
The program must be written not to clear the flag to the status bit, and then to set the control bits to have the desired value.
Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can access to a single bit only.) By
the Byte, Half-word, or Word access, data is written to the control bits and status flag simultaneously. During this time, take care not
to clear other bits (in this case, the bits of status flag) erroneously.
Note:
These points can be ignored because the bit instructions to a register which supports RMW are already taken the points into
consideration. Care must be taken when the bit instruction is used to a register which does not support RMW.
Document Number: 002-04727 Rev. *B
Page 55 of 174
MB91590 Series
7. Block Diagram
clamp
ADC
FR81S CPU Core
NTSC
Decoder
Video
capture
Frame buffer
Regulator
MPU
Power-on Reset
Instruction
External
I/O ( Digital RGB)
Pixel
FIFO
Debug Interface
Data
CR oscillator
Line
Buffer
Line
Engine
Sprite
Engine
Wild register
XBS
Camera
XBS Crossbar Switch
Display
Controller
LCD
RAM
Command
decoder
RAM
Bus Bridge
AHB
bus
bridge
asynchro
nous
type
SIG
RLD
DMA
Flash
· Main Flash
· WorkFlash 64KB
From Master
On chip bus layer 2
To Slave
From Master
On chip bus layer 1
To Slave
Ext.
BUS
On chip bus
I/O
 MB91F591/592/594/596/597/599
Bus master
Ext.bus I/F
RAM ECC Control
(XBS-RAM)
DMAC
Regi ster
Peripheral Bus
Bridge
CAN (3ch)
I/O (Ext. bus)
Bus bridge
External bus pin
(For GDC external memory)
RDY, A00-24,
WEX,REX,
CS0X,CS1X,
D0-15
16
Bus performance
counter
32
Operation mode
register
RAM ECC Backup
-RAM
Control
MD0,MD1,MD2,P127
RTC/WDT1 Calibration
I/O port setting
SOT2-7,SIN2-7,
Lin-UART (6ch)
SCK2-7
I/O Port
FRCK0-1
ICU0-5
OCU0-3
TIOA0-1,
TIOB0-1
TRG0-5,
PPG0-23
ADTG, AN0-31
Multi-function serial interface (2ch)
Free-run timer (2ch)
Input capture (6ch)
Output compare(4ch)
Base-timer (2ch)
16-bit Peripheral bus
SOT0-1,SIN0-1,
SCK0-1
Asynchronous BUS
bridge
(PCLK1 ↔ PCLK2)
CRC
Sound generator (5ch)
SGO0-4,SGA0-4
I/O Port
CAN Prescaler
16-bit Peripheral bus
32-bit Peripheral bus
Asynchronous BUS
bridge
(PCLK1 ↔ PCLK2)
RX0-2,
TX0-2
External
FLASH
memory
(For video)
Bus Bridge
(32-bit → 16-bit)
External interrupt input (16ch)
PPG (24ch)
Real time clock
A/D converter
Clock supervisor
INT0-15
Input interception
inhibiting signal
WOT
GDC external control
NMI
Stepping motor controller (6ch)
NMIX
Low-voltage detection (Int. power supply low-voltage detection)
PWM1M0-5,
Low-voltage detection (Ext. power supply low-voltage detection)
PWM1P0-5,
PWM2M0-5
Clock control
(Clock setting, Main timer, Sub timer, PLL timer)
Reload timer (4ch)
TIN0-3,TOT0-3
Watchdog timer (SW and HW)
Clock control (divide setting),
Reset control,
Low-power consumption
control
RSTX
Delay interrupt
Generation and clear of DMA transfer request
Interrupt controller
Interrupt request batch read
Document Number: 002-04727 Rev. *B
Page 56 of 174
MB91590 Series
clamp
ADC
FR81S CPU Core
NTSC
Decoder
Video
capture
Frame buffer
Regulator
MPU
Power-on Reset
Instruction
External
I/O ( Digital RGB)
Pixel
FIFO
Debug Interface
Data
CR oscillator
Line
Buffer
Line
Engine
Sprite
Engine
Wild register
XBS
Camera
XBS Crossbar Switch
Display
Controller
LCD
RAM
Command
decoder
RAM
Bus Bridge
AHB
bus
bridge
asynchro
nous
type
HS-SPI
SIG
RLD
DMA
Flash
· Main Flash
· WorkFlash 64KB
From Master
On chip bus layer 2
To Slave
From Master
On chip bus layer 1
To Slave
Ext.
BUS
Ext.bus I/F
RAMECC
control
(AHB-RAM)
RAM ECC Control
(XBS-RAM)
RAM
Bus master
DMAC
Regi ster
Peripheral Bus
Bridge
CAN (3ch)
I/O (Ext. bus)
Bus bridge
External bus pin
(For GDC external memory)
RDY, A00-24,
WEX,REX,
CS0X,CS1X,
D0-15
On chip bus
I/O
 MB91F59A/59B
16
Bus performance
counter
32
Operation mode
register
RAM ECC Backup
-RAM
Control
MD0,MD1,MD2,P127
RTC/WDT1 Calibration
I/O port setting
SOT2-7,SIN2-7,
Lin-UART (6ch)
SCK2-7
I/O Port
FRCK0,1,2 -7
ICU0-5,6-11
OCU0-3
TIOA0-1,
TIOB0-1
TRG0-5,
PPG0-23
ADTG, AN0-31
Multi-function serial interface (6ch)
Free-run timer (8ch)
Input capture (12ch)
Output compare(4ch)
Base-timer (2ch)
16-bit Peripheral bus
SOT0,1,8 -11,
SIN0,1,8 -11,
SCK0,1,8 -11
Asynchronous BUS
bridge
(PCLK1 ↔ PCLK2)
CRC
Sound generator (5ch)
SGO0-4,SGA0-4
I/O Port
CAN Prescaler
16-bit Peripheral bus
32-bit Peripheral bus
Asynchronous BUS
bridge
(PCLK1 ↔ PCLK2)
RX0-2,
TX0-2
External
FLASH
memory
(For video)
Bus Bridge
(32-bit → 16-bit)
External interrupt input (16ch)
PPG (24ch)
Real time clock
A/D converter
Clock supervisor
INT0-15
Input interception
inhibiting signal
WOT
GDC external control
NMI
NMIX
Up/down counter (3ch)
Stepping motor controller (6ch)
Low-voltage detection (Int. power supply low-voltage detection)
PWM1M0-5,
Low-voltage detection (Ext. power supply low-voltage detection)
PWM1P0-5,
PWM2M0-5
Clock control
(Clock setting, Main timer, Sub timer, PLL timer)
Reload timer (4ch)
TIN0-3,TOT0-3
Reload timer (4ch)
Watchdog timer (SW and HW)
Clock control (divide setting),
Reset control,
Low-power consumption
control
RSTX
Delay interrupt
Generation and clear of DMA transfer request
Interrupt controller
Interrupt request batch read
Note: I/O of peripheral functions can be confirmed at "PIN ASSIGNMENT" and "PIN DESCRIPTION".
Document Number: 002-04727 Rev. *B
Page 57 of 174
MB91590 Series
8. Memory Map
 Memory map
MB91F59B
0000 0000H
0000 4000H
0000 6000H
I/O
Back up RAM (8KB)
I/O
0001 0000H
RAM (192KB)
0004 0000H
AHB
Access inhibit
0007 0000H
Flash memory
(1024+1024+64) KB
0028 0000H
0033 0000H
0034 0000H
Access inhibit
WorkFlash (64KB)
Access inhibit
0040 0000H
AHB
GDC control +
External area (288MB)
1240 0000H
7FFF 0000H
Access inhibit
RAM (64KB)
AHB
8000 0000H
Access inhibit
FFFF FFFFH
Document Number: 002-04727 Rev. *B
Page 58 of 174
MB91590 Series
 GDC memory map
MB91F59B
GDC Block
0040 0000H
0000 0000H
Video RAM (1792KB)
005B 5800H
0000 4000H
0000 6000H
Reserved
00C0 0000H
00C0 2000H
00E0 0000H
Command RAM (8KB)
0230 0000H
0239 F000H
023A 0000H
023B 0000H
023B 1000H
023B 2000H
023B 3000H
023B 4000H
023B 5000H
023B 6000H
023B 7000H
023B 8000H
023C 0000H
023D 0000H
023D 8000H
023E 0000H
023F 0000H
023F 8000H
0240 0000H
Reserved (636KB)
I/O
Back up RAM (8KB)
I/O
0001 0000H
Reserved
RAM (192KB)
Access prohibit
0004 0000H
AHB
Command (4KB)
Reserved (64KB)
SIG (4KB)
Access inhibit
NTSC (4KB)
MCNT (4KB)
MEMC (4KB)
GDC I/O
HDMAC (4KB)
RLD (4KB)
Reserved (64KB)
0007 0000H
CMDSEQ (4KB)
Flash memory
(1024+1024+64) KB
SPRITE (32KB)
GDC_Bridge (64KB)
063F FFFCH
0640 0000H
123F FFFCH
Display (32KB)
Capture (32KB)
Reserved (64KB)
0028 0000H
Draw (32KB)
Reserved (32KB)
0033 0000H
External FLASH
(64MB) *1)
0034 0000H
External FLASH
(192MB) *2)
0040 0000H
1240 0000H
7FFF 0000H
Access inhibit
WorkFlash (64KB)
Access inhibit
GDC control +
External area
(288MB)
AHB
Access inhibit
RAM (64KB)
AHB
8000 0000H
Access inhibit
FFFF FFFFH
Note: The GDC area is executed mapping with the little endian.
*1) Parallel interface supports 64MB of memory space from 0240_0000H to 063F_FFFCH for External FLASH.
*2) HS-SPI supports additional 192MB of memory space from 0640_0000H to 123F_FFFFH.
(HS-SPI totally supports 256MB of memory space from 0240_0000H to 123F_FFFFH for External FLASH)
Document Number: 002-04727 Rev. *B
Page 59 of 174
MB91590 Series
 Memory map
MB91F59A
0000 0000H
0000 4000H
0000 6000H
I/O
Back up RAM (8KB)
I/O
0001 0000H
RAM (192KB)
0004 0000H
AHB
Access inhibit
0007 0000H
Flash memory
(1024+512+64) KB
0020 0000H
0033 0000H
0034 0000H
Access inhibit
WorkFlash (64KB)
Access inhibit
0040 0000H
AHB
GDC control +
External area (288MB)
1240 0000H
7FFF 0000H
Access inhibit
RAM (64KB)
AHB
8000 0000H
Access inhibit
FFFF FFFFH
Document Number: 002-04727 Rev. *B
Page 60 of 174
MB91590 Series
 GDC memory map
MB91F59A
GDC Block
0040 0000H
0000 0000H
Video RAM (1792KB)
005B 5800H
0000 4000H
0000 6000H
Reserved
00C0 0000H
00C0 2000H
00E0 0000H
Command RAM (8KB)
0230 0000H
0239 F000H
023A 0000H
023B 0000H
023B 1000H
023B 2000H
023B 3000H
023B 4000H
023B 5000H
023B 6000H
023B 7000H
023B 8000H
023C 0000H
023D 0000H
023D 8000H
023E 0000H
023F 0000H
023F 8000H
0240 0000H
Reserved (636KB)
I/O
Back up RAM (8KB)
I/O
0001 0000H
Reserved
RAM (192KB)
Access prohibit
0004 0000H
AHB
Command (4KB)
Reserved (64KB)
SIG (4KB)
Access inhibit
NTSC (4KB)
MCNT (4KB)
MEMC (4KB)
GDC I/O
HDMAC (4KB)
RLD (4KB)
Reserved (64KB)
0007 0000H
CMDSEQ (4KB)
Flash memory
(1024+512+64) KB
SPRITE (32KB)
GDC_Bridge (64KB)
063F FFFCH
0640 0000H
123F FFFCH
Display (32KB)
Capture (32KB)
Reserved (64KB)
0020 0000H
Draw (32KB)
Reserved (32KB)
0033 0000H
External FLASH
(64MB) *1)
0034 0000H
External FLASH
(192MB) *2)
0040 0000H
1240 0000H
7FFF 0000H
Access inhibit
WorkFlash (64KB)
Access inhibit
GDC control +
External area
(288MB)
AHB
Access inhibit
RAM (64KB)
AHB
8000 0000H
Access inhibit
FFFF FFFFH
Note: The GDC area is executed mapping with the little endian.
*1) Parallel interface supports 64MB of memory space from 0240_0000H to 063F_FFFCH for External FLASH.
*2) HS-SPI supports additional 192MB of memory space from 0640_0000H to 123F_FFFCH.
(HS-SPI totally supports 256MB of memory space from 0240_0000H to 123F_FFFCH for External FLASH)
Document Number: 002-04727 Rev. *B
Page 61 of 174
MB91590 Series
 Memory map
MB91F594,
MB91F599
0000 0000H
0000 4000H
0000 6000H
I/O
Back up RAM (8KB)
I/O
0001 0000H
RAM (64KB)
0002 0000H
Reserved
0003 0000H
AHB
Access inhibit
0007 0000H
Flash memory
(1024+64) KB
0018 0000H
0023 0000H
0024 0000H
Access inhibit
WorkFlash (64KB)
Access inhibit
0040 0000H
AHB
GDC control +
External area (96MB)
0640 0000H
8000 0000H
Access inhibit
FFFF FFFFH
Document Number: 002-04727 Rev. *B
Page 62 of 174
MB91590 Series
 GDC memory map
MB91F594,
MB91F599
GDC Block
0040 0000H
0000 0000H
Video RAM (800KB)
004C 8000H
0000 4000H
0000 6000H
Reserved
00C0 0000H
00C0 2000H
00E0 0000H
Command RAM (8KB)
0230 0000H
0239 F000H
023A 0000H
023B 0000H
023B 1000H
023B 2000H
023B 3000H
023B 4000H
023B 5000H
023B 6000H
023B 7000H
023B 8000H
023C 0000H
023D 0000H
023D 8000H
023E 0000H
023F 0000H
023F 8000H
0240 0000H
Reserved (636KB)
I/O
Back up RAM (8KB)
I/O
0001 0000H
Reserved
RAM (64KB)
Access prohibit
0002 0000H
Reserved
Command (4KB)
Reserved (64KB)
0003 0000H
SIG (4KB)
AHB
NTSC (4KB)
MCNT (4KB)
MEMC (4KB)
GDC I/O
Access inhibit
HDMAC (4KB)
RLD (4KB)
Reserved (64KB)
0007 0000H
CMDSEQ (4KB)
Flash memory
(1024+64) KB
SPRITE (32KB)
GDC_Bridge (64KB)
063F FFFCH
Display (32KB)
Capture (32KB)
Reserved (64KB)
0018 0000H
Draw (32KB)
Reserved (32KB)
0023 0000H
External FLASH
(64MB)
0024 0000H
0040 0000H
Access inhibit
WorkFlash (64KB)
Access inhibit
GDC control +
External area
(96MB)
AHB
0640 0000H
8000 0000H
Access inhibit
FFFF FFFFH
Note: The GDC area is executed mapping with the little endian.
Document Number: 002-04727 Rev. *B
Page 63 of 174
MB91590 Series
 Memory map
MB91F592,
MB91F597
0000 0000H
0000 4000H
0000 6000H
I/O
Back up RAM (8KB)
I/O
0001 0000H
RAM (40KB)
0001 A000H
Reserved
0003 0000H
AHB
Access inhibit
0007 0000H
Flash memory
(512+64) KB
0010 0000H
0023 0000H
0024 0000H
Access inhibit
WorkFlash (64KB)
Access inhibit
0040 0000H
AHB
GDC control +
External area (96MB)
0640 0000H
8000 0000H
Access inhibit
FFFF FFFFH
Document Number: 002-04727 Rev. *B
Page 64 of 174
MB91590 Series
 GDC memory map
MB91F592,
MB91F597
GDC Block
0040 0000H
0000 0000H
Video RAM (800KB)
004C 8000H
0000 4000H
0000 6000H
Reserved
00C0 0000H
00C0 2000H
00E0 0000H
Command RAM (8KB)
0230 0000H
0239 F000H
023A 0000H
023B 0000H
023B 1000H
023B 2000H
023B 3000H
023B 4000H
023B 5000H
023B 6000H
023B 7000H
023B 8000H
023C 0000H
023D 0000H
023D 8000H
023E 0000H
023F 0000H
023F 8000H
0240 0000H
Reserved (636KB)
I/O
Back up RAM (8KB)
I/O
0001 0000H
Reserved
RAM (40KB)
Access inhibit
0001 A000H
Reserved
Command( 4KB)
Reserved (64KB)
0003 0000H
SIG (4KB)
AHB
NTSC (4KB)
MCNT (4KB)
MEMC (4KB)
GDC I/O
Access inhibit
HDMAC (4KB)
RLD (4KB)
Reserved (64KB)
0007 0000H
CMDSEQ (4KB)
Flash memory
(512+64) KB
SPRITE (32KB)
GDC_Bridge (64KB)
063F FFFCH
Display (32KB)
Capture (32KB)
Reserved (64KB)
0010 0000H
Draw (32KB)
Reserved (32KB)
0023 0000H
External FLASH
(64MB)
0024 0000H
Access inhibit
WorkFlash (64KB)
Access inhibit
0040 0000H
AHB
GDC control +
External area (96MB)
0640 0000H
8000 0000H
Access inhibit
FFFF FFFFH
Note: The GDC area is executed mapping with the little endian.
Document Number: 002-04727 Rev. *B
Page 65 of 174
MB91590 Series
 Memory map
MB91F591,
MB91F596
0000 0000H
0000 4000H
0000 6000H
I/O
Back up RAM (8KB)
I/O
0001 0000H
RAM (40KB)
0001 A000H
Reserved
0003 0000H
AHB
Access inhibit
0007 0000H
Flash memory
(512+64) KB
0010 0000H
0023 0000H
0024 0000H
Access inhibit
WorkFlash (64KB)
Access inhibit
0040 0000H
AHB
GDC control +
External area (96MB)
0640 0000H
8000 0000H
Access inhibit
FFFF FFFFH
Document Number: 002-04727 Rev. *B
Page 66 of 174
MB91590 Series
 GDC memory map
MB91F591,
MB91F596
GDC Block
0040 0000H
0000 0000H
Video RAM (260KB)
0044 1000H
0000 4000H
0000 6000H
Reserved
00C0 0000H
00C0 2000H
00E0 0000H
Command RAM (8KB)
0230 0000H
0239 F000H
023A 0000H
023B 0000H
023B 1000H
023B 2000H
023B 3000H
023B 4000H
023B 5000H
023B 6000H
023B 7000H
023B 8000H
023C 0000H
023D 0000H
023D 8000H
023E 0000H
023F 0000H
023F 8000H
0240 0000H
Reserved (636KB)
I/O
Back up RAM (8KB)
I/O
0001 0000H
Reserved
RAM (40KB)
Access prohibit
0001 A000H
Reserved
Command (4KB)
Reserved (64KB)
0003 0000H
SIG (4KB)
AHB
NTSC (4KB)
MCNT (4KB)
MEMC (4KB)
GDC I/O
Access inhibit
HDMAC (4KB)
RLD (4KB)
Reserved (64KB)
0007 0000H
CMDSEQ (4KB)
Flash memory
(512+64) KB
SPRITE (32KB)
GDC_Bridge (64KB)
063F FFFCH
Display (32KB)
Capture (32KB)
Reserved (64KB)
0010 0000H
Draw (32KB)
Reserved (32KB)
0023 0000H
External FLASH
(64MB)
0024 0000H
Access inhibit
WorkFlash (64KB)
Access inhibit
0040 0000H
AHB
GDC control +
External area (96MB)
0640 0000H
8000 0000H
Access inhibit
FFFF FFFFH
Note: The GDC area is executed mapping with the little endian.
Document Number: 002-04727 Rev. *B
Page 67 of 174
MB91590 Series
9. I/O Map
The following I/O map shows the relationship between memory space and registers for peripheral resources.
 Legend of I/O Map
Read/Write attribute (R: Read W: Write)
Address
Address Offset Value/ Register Name
+1
+2
+0
+3
000090H
BT1TMR[R] H
00000000 00000000
000094 H
-
000098 H
BT1PCSR/BT1PRLL[R /W] H
00000000 00000000
BT1PDUT/BT1PRLH/BT1DTBF[R/W] H
00000000 00000000
00009C H
BTSEL[R/W] B
----000 0
BTSSSR[W] B,H
-------- ------11
0000A0 H
ADERH [R/W]B, H, W
00000000 00000000
0000A4 H
ADCS1 [R/W] B, H,W
00000000
ADCS0 [R/W] B, H,W
00000000
ADCR1 [R] B, H,W
------XX
0000A8 H
ADCT1 [R/W] B, H,W
00010000
ADCT0 [R/W] B, H,W
00101100
ADSCH [R/W] B, H,W ADECH [R/W] B, H,W
---00000
---00000
Block
BT1TMCR[R/W]B,H,W
00000000 00000000
BT1STC[R/W] B
00000000
-
-
Base timer 1
ADERL [R/W]B, H, W
00000000 00000000
ADCR0 [R] B, H,W
XXXXX XXX
A/D converter
Data access attribute
B: Byte
H: Half-word
W: Word
(Note) The access by the data
access attribute not described is
disabled.
Initial register value after reset
The initial register value after reset indicates as follows:
•
•
•
•
•
"1": Initial value "1"
"0": Initial value "0"
"X": Initial value undefined
"-": Reserved bit/Undefined bit
"*": Initial value "0" or "1" according to the setting
Note: The access by the data access attribute not described is disabled.
Document Number: 002-04727 Rev. *B
Page 68 of 174
MB91590 Series
 I/O map
Address
000000H
000004H
000008H
00000CH
000010H
000014H
000018H
to
000028H
00002CH
to
000030H
000034H
to
000038H
00003CH
000040H
000044H
000048H
to
00005CH
000060H
000064H
000068H
to
00007CH
000080H
000084H
000088H
00008CH
+0
PDR00[R/W]
B,H,W
XXXXXXXX
PDR04[R/W]
B,H,W
XXXXXXXX
PDR08[R/W]
B,H,W
XXXXXXXX
PDR12[R/W]
B,H,W
XXXXXXXX
PDRA[R/W]
B,H,W
XXXXXX-PDRE[R/W]
B,H,W
XXXXXX--
Address Offset Value / Register Name
+1
+2
+3
PDR01[R/W]
PDR02[R/W]
PDR03[R/W]
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR05[R/W]
PDR06[R/W]
PDR07[R/W]
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR09[R/W]
PDR10[R/W]
PDR11[R/W]
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR13[R/W]
B,H,W
―
―
XX-XXXXX
PDRB[R/W]
PDRC[R/W]
PDRD[R/W]
B,H,W
B,H,W
B,H,W
XXXXXX-XXXXXX-XXXXXX-PDRF[R/W]
PDRG[R/W]
PDRH[R/W]
B,H,W
B,H,W
B,H,W
XXXXXX-XXXXXXXX
----X---
Block
Port data register
―
―
―
―
Reserved
―
―
―
―
Reserved
―
―
―
―
Reserved
WDTCR0[R/W]
B,H,W
-0--0000
―
DICR [R/W]
B
XXXXXXX0
WDTCPR0[W]
B,H,W
00000000
―
WDTCR1[R]
B,H,W
----0110
―
WDTCPR1[W]
B,H,W
00000000
―
―
―
―
Delay interrupt
―
―
―
―
Reserved
Watchdog timer [S]
Reserved
TMRLRA0 [R/W] H
XXXXXXXX XXXXXXXX
TMRLRB0 [R/W] H
XXXXXXXX XXXXXXXX
TMR0 [R] H
XXXXXXXX XXXXXXXX
TMCSR0 [R/W] B, H,W
00000000 0-000000
Reload timer 0
―
―
Reserved
―
BT0TMR [R] H
00000000 00000000
BT0STC
―
[R/W] B
0000-000
BT0PCSR/BT0PRLL
[R/W] H
XXXXXXXX XXXXXXXX
―
―
Document Number: 002-04727 Rev. *B
―
BT0TMCR [R/W] H
-0000000 00000000
―
―
Base timer 0
BT0PDUT/BT0PRLH/BT0DTBF
[R/W] H
XXXXXXXX XXXXXXXX
―
―
Page 69 of 174
MB91590 Series
Address
000090H
000094H
000098H
00009CH
0000A0H
0000A4H
0000A8H
0000ACH
0000B0H
0000B4H
0000B8H
0000BCH
0000C0H
0000C4H
0000C8H
0000CCH
0000D0H
0000D4H
0000D8H
0000DCH
Address Offset Value / Register Name
+0
+1
+2
+3
BT1TMR [R] H
BT1TMCR [R/W] H
00000000 00000000
-0000000 00000000
BT1STC
―
[R/W] B
―
―
0000-000
BT1PCSR/BT1PRLL
BT1PDUT/BT1PRLH/BT1DTBF
[R/W] H
[R/W] H
00000000 00000000
00000000 00000000
BTSEL01
BTSSSR
[R/W] B
―
[W] B,H
----0000
-------- ------11
ADERH [R/W] B, H, W
ADERL [R/W] B, H, W
00000000 00000000
00000000 00000000
ADCS1
ADCS0
ADCR1
ADCR0
[R/W] B, H,W
[R/W] B, H,W
[R] B, H,W
[R] B, H,W
000000000000000
------XX
XXXXXXXX
ADCT1 [R/W]
ADCT0 [R/W]
ADSCH [R/W]
ADECH [R/W] B,
B, H,W
B, H,W
B, H,W
H,W
00010000
00101100
---00000
---00000
―
―
―
―
SCR0/(IBCR0)
SMR0
SSR0
ESCR0/(IBSR0)
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
[R/W] B,H,W
0--00000
000-0000
0-000011
-0000000
RDR0/(TDR0)[R/W] B,H,W *1
BGR0 [R/W] H,W
-------0 00000000
00000000 00000000
― / (ISMK0) [R/W] ― / (ISBA0) [R/W]
B,H,W
B,H,W
―
―
-------- *2
-------- *2
FCR10 [R/W]
FCR00 [R/W]
FBYTE20 [R/W] FBYTE10 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
---00100
-0000000
00000000
00000000
SCR1/(IBCR1)
SMR1 [R/W]
SSR1 [R/W]
ESCR1/(IBSR1)
[R/W] B,H,W
B,H,W
B,H,W
[R/W] B,H,W
0--00000
000-0000
0-000011
-0000000
*1
RDR1/(TDR1)[R/W] B,H,W
BGR1 [R/W] H,W
-------0 00000000
00000000 00000000
― / (ISMK1) [R/W] ― /( ISBA1) [R/W]
B,H,W
B,H,W
―
―
-------- *2
-------- *2
FCR11 [R/W]
FCR01[R/W]
FBYTE21 [R/W] FBYTE11[R/W]
B, H, W
B, H, W
B,H,W
B,H,W
---00100
-0000000
00000000
00000000
SCR2 [R/W]
SMR2 [R/W]
SSR2 [R/W]
RDR2 /TDR2
B, H, W
B, H, W
B, H, W
[R/W] B, H, W
00000000
00000000
00001000
00000000
ESCR2 [R/W]
ECCR2 [R/W]
BGR2 [R/W] B, H, W
B, H, W
B, H, W
-0000000 00000000
00000X00
-0000-XX
SCR3 [R/W]
SMR3 [R/W]
SSR3 [R/W]
RDR3 /TDR3
B, H, W
B, H, W
B, H, W
[R/W] B, H, W
00000000
00000000
00001000
00000000
ESCR3 [R/W]
ECCR3 [R/W]
BGR3 [R/W] B, H, W
B, H, W
B, H, W
-0000000 00000000
00000X00
-0000-XX
Document Number: 002-04727 Rev. *B
Block
Base timer 1
Base timer 0,1
A/D converter
Reserved
Multi-function serial 0
*1: Byte access is
possible only for access
to lower 8 bits
*2: Reserved because
2
I C mode is not set
immediately after reset.
Multi-function serial 1
*1: Byte access is
possible only for access
to lower 8 bits
*2: Reserved because
2
I C mode is not set
immediately after reset.
LIN-UART2
LIN-UART3
Page 70 of 174
MB91590 Series
Address
0000E0H
0000E4H
0000E8H
0000ECH
0000F0H
0000F4H
0000F8H
0000FCH
000100H
000104H
000108H
00010CH
000110H
000114H
000118H
to
000140H
000144H
000148H
00014CH
000150H
000154H
Address Offset Value / Register Name
+0
+1
+2
+3
SCR4 [R/W]
SMR4 [R/W]
SSR4 [R/W]
RDR4 /TDR4
B, H, W
B, H, W
B, H, W
[R/W] B, H, W
00000000
00000000
00001000
00000000
ESCR4 [R/W]
ECCR4 [R/W]
BGR4 [R/W] B, H, W
B, H, W
B, H, W
-0000000 00000000
00000X00
-0000-XX
SCR5 [R/W]
SMR5 [R/W]
SSR5 [R/W]
RDR5 /TDR5
B, H, W
B, H, W
B, H, W
[R/W] B, H, W
00000000
00000000
00001000
00000000
ESCR5 [R/W]
ECCR5 [R/W]
BGR5 [R/W] B, H, W
B, H, W
B, H, W
-0000000 00000000
00000X00
-0000-XX
SCR6 [R/W]
SMR6 [R/W]
SSR6 [R/W]
RDR6 /TDR6
B, H, W
B, H, W
B, H, W
[R/W] B, H, W
00000000
00000000
00001000
00000000
ESCR6 [R/W]
ECCR6 [R/W]
BGR6 [R/W] B, H, W
B, H, W
B, H, W
-0000000 00000000
00000X00
-0000-XX
SCR7 [R/W]
SMR7 [R/W]
SSR7 [R/W]
RDR7 /TDR7
B, H, W
B, H, W
B, H, W
[R/W] B, H, W
00000000
00000000
00001000
00000000
ESCR7 [R/W]
ECCR7 [R/W]
BGR7 [R/W] B, H, W
B, H, W
B, H, W
-0000000 00000000
00000X00
-0000-XX
TMRLRA1 [R/W] H
TMR1 [R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB1 [R/W] H
TMCSR1 [R/W] B, H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
TMRLRA2 [R/W] H
TMR2 [R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB2 [R/W] H
TMCSR2 [R/W] B, H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
TMRLRA3 [R/W] H
TMR3 [R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB3 [R/W] H
TMCSR3 [R/W] B, H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
―
―
GCN13
[R/W] H
00110010 00010000
GCN14
[R/W] H
00110010 00010000
GCN15
[R/W] H
00110010 00010000
PTMR11 [R] H,W
11111111 11111111
PDUT11 [W] H,W
XXXXXXXX XXXXXXXX
Document Number: 002-04727 Rev. *B
―
―
―
―
―
GCN23
[R/W] B
----0000
GCN24
[R/W] B
----0000
GCN25
[R/W] B
----0000
PCSR11 [W] H, W
XXXXXXXX XXXXXXXX
PCN11 [R/W] B, H,W
0000000- 000000-0
Block
LIN-UART4
LIN-UART5
LIN-UART6
LIN-UART7
Reload timer 1
Reload timer 2
Reload timer 3
Reserved
PPG12,13,14,15 control
PPG16,17,18,19 control
PPG20,21,22,23 control
PPG11
Page 71 of 174
MB91590 Series
Address
000158H
00015CH
000160H
000164H
000168H
00016CH
000170H
000174H
000178H
00017CH
000180H
000184H
000188H
00018CH
000190H
000194H
000198H
00019CH
0001A0H
0001A4H
0001A8H
0001ACH
0001B0H
0001B4H
0001B8H
0001BCH
Address Offset Value / Register Name
+0
+1
+2
PTMR12 [R] H,W
PCSR12 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT12 [W] H,W
PCN12 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR13 [R] H,W
PCSR13 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT13 [W] H,W
PCN13 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR14 [R] H,W
PCSR14 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT14 [W] H,W
PCN14 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR15 [R] H,W
PCSR15 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT15 [W] H,W
PCN15 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR16 [R] H,W
PCSR16 [W] H, W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT16 [W] H,W
PCN16 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR17 [R] H,W
PCSR17 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT17 [W] H,W
PCN17 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR18 [R] H,W
PCSR18 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT18 [W] H,W
PCN18 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR19 [R] H,W
PCSR19 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT19 [W] H,W
PCN19 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR20 [R] H,W
PCSR20 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT20 [W] H,W
PCN20 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR21 [R] H,W
PCSR21 [W] H, W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT21 [W] H,W
PCN21 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR22 [R] H,W
PCSR22 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT22 [W] H,W
PCN22 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR23 [R] H,W
PCSR23 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT23 [W] H,W
PCN23 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
TMRLRA7 [R/W] H
TMR7 [R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB7 [R/W] H
TMCSR7 [R/W] B, H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
Document Number: 002-04727 Rev. *B
Block
+3
PPG12
PPG13
PPG14
PPG15
PPG16
PPG17
PPG18
PPG19
PPG20
PPG21
PPG22
PPG23
Reload timer 7
MB91F59A/B only
Page 72 of 174
MB91590 Series
Address
0001C0H
0001C4H
0001C8H
0001CCH
0001D0H
0001D4H
Address Offset Value / Register Name
+0
+1
+2
TMRLRA8 [R/W] H
TMR8 [R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB8 [R/W] H
TMCSR8 [R/W] B, H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
TMRLRA9 [R/W] H
TMR9 [R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB9 [R/W] H
TMCSR9 [R/W] B, H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
TMRLRA10 [R/W] H
TMR10 [R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB10 [R/W] H
TMCSR10 [R/W] B, H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
0001D8H
to
―
―
0001DCH
SCR10 [R/W]
SMR10 [R/W]
0001E0H B,H,W
B,H,W
0--00000
000-0000
RDR10/(TDR10)[R/W] B,H,W *1
0001E4H
-------0 00000000
0001E8H ―
―
FCR110 [R/W]
FCR010 [R/W]
0001ECH B,H,W
B,H,W
---00100
-0000000
SCR11 [R/W]
SMR11 [R/W]
0001F0H B,H,W
B,H,W
0--00000
000-0000
RDR11/(TDR11)[R/W] B,H,W *1
0001F4H
-------0 00000000
0001F8H ―
―
FCR111 [R/W]
FCR011 [R/W]
0001FCH B,H,W
B,H,W
---00100
-0000000
Document Number: 002-04727 Rev. *B
―
+3
―
SSR10 [R/W]
ESCR10 [R/W]
B,H,W
B,H,W
0-000011
-0000000
BGR10 [R/W] H,W
00000000 00000000
―
―
FBYTE210 [R/W] FBYTE110 [R/W]
B,H,W
B,H,W
00000000
00000000
SSR11 [R/W]
ESCR11 [R/W]
B,H,W
B,H,W
0-000011
-0000000
BGR11 [R/W] H,W
00000000 00000000
―
―
FBYTE211 [R/W] FBYTE111 [R/W]
B,H,W
B,H,W
00000000
00000000
Block
Reload timer 8
MB91F59A/B only
Reload timer 9
MB91F59A/B only
Reload timer 10
MB91F59A/B only
Reserved
Multi-function serial 10
*1: Byte access is
possible only for access
to lower 8 bits.
MB91F59A/B only
Multi-function serial 11
*1: Byte access is
possible only for access
to lower 8 bits.
MB91F59A/B only
Page 73 of 174
MB91590 Series
Address
000200H
000204H
000208H
00020CH
000210H
000214H
000218H
00021CH
000220H
000224H
000228H
00022CH
000230H
to
00023CH
000240H
000244H
000248H
00024CH
000250H
000254H
000258H
00025CH
000260H
000264H
Address Offset Value / Register Name
+0
+1
+2
+3
PWC20 [R/W] H,W
PWC10 [R/W] H,W
------XX XXXXXXXX
------XX XXXXXXXX
PWS20 [R/W]
PWS10 [R/W]
PWC0 [R/W] B
―
B,H,W
B,H,W
-00000--0000000
--000000
PWC21 [R/W] H,W
PWC11 [R/W] H,W
------XX XXXXXXXX
------XX XXXXXXXX
PWS21 [R/W]
PWS11 [R/W]
PWC1 [R/W] B
―
B,H,W
B,H,W
-00000--0000000
--000000
PWC22 [R/W] H,W
PWC12 [R/W] H,W
------XX XXXXXXXX
------XX XXXXXXXX
PWS22 [R/W]
PWS12 [R/W]
PWC2 [R/W] B
―
B,H,W
B,H,W
-00000--0000000
--000000
PWC23 [R/W] H,W
PWC13 [R/W] H,W
------XX XXXXXXXX
------XX XXXXXXXX
PWS23 [R/W]
PWS13 [R/W]
PWC3 [R/W] B
―
B,H,W
B,H,W
-00000--0000000
--000000
PWC24 [R/W] H,W
PWC14 [R/W] H,W
------XX XXXXXXXX
------XX XXXXXXXX
PWS24 [R/W]
PWS14 [R/W]
PWC4 [R/W] B
―
B,H,W
B,H,W
-00000--0000000
--000000
PWC25 [R/W] H,W
PWC15 [R/W] H,W
------XX XXXXXXXX
------XX XXXXXXXX
PWS25 [R/W]
PWS15 [R/W]
PWC5 [R/W] B
―
B,H,W
B,H,W
-00000--0000000
--000000
―
―
―
CPCLR0 [R/W] W
11111111 11111111 11111111 11111111
TCDT0 [R/W] W
00000000 00000000 00000000 00000000
TCCSH0 [R/W]B, TCCSL0
H, W
[R/W]B, H, W
―
0-----00
-1-00000
CPCLR1 [R/W] W
11111111 11111111 11111111 11111111
TCDT1 [R/W] W
00000000 00000000 00000000 00000000
TCCSH1 [R/W]B, TCCSL1
H, W
[R/W]B, H, W
―
0-----00
-1-00000
―
―
―
GCN10 [R/W] H
―
00110010 00010000
GCN11 [R/W] H
―
00110010 00010000
GCN12 [R/W] H
―
00110010 00010000
Document Number: 002-04727 Rev. *B
―
Block
Stepping motor
controller
Reserved
Free-run timer 0
Free-run timer 1
―
GCN20 [R/W] B
----0000
GCN21 [R/W] B
----0000
GCN22 [R/W] B
----0000
Reserved
PPG0,1,2,3 control
PPG4,5,6,7 control
PPG8,9,10,11 control
Page 74 of 174
MB91590 Series
Address
000268H
00026CH
000270H
000274H
000278H
00027CH
000280H
000284H
000288H
00028CH
000290H
000294H
000298H
00029CH
0002A0H
0002A4H
0002A8H
0002ACH
0002B0H
0002B4H
0002B8H
0002BCH
0002C0H
0002C4H
0002C8H
0002CCH
Address Offset Value / Register Name
+1
+2
+3
PPGDIV [R/W] B
―
―
―
------00
PTMR0 [R] H,W
PCSR0 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT0 [W] H,W
PCN0 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR1 [R] H,W
PCSR1 [W] H, W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT1 [W] H,W
PCN1 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR2 [R] H,W
PCSR2 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT2 [W] H,W
PCN2 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR3 [R] H,W
PCSR3 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT3 [W] H,W
PCN3 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR4 [R] H,W
PCSR4 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT4 [W] H,W
PCN4 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR5 [R] H,W
PCSR5 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT5 [W] H,W
PCN5 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR6 [R] H,W
PCSR6 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT6 [W] H,W
PCN6 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR7 [R] H,W
PCSR7 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT7 [W] H,W
PCN7 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR8 [R] H,W
PCSR8 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT8 [W] H,W
PCN8 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR9 [R] H,W
PCSR9 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT9 [W] H,W
PCN9 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
PTMR10 [R] H,W
PCSR10 [W] H,W
11111111 11111111
XXXXXXXX XXXXXXXX
PDUT10 [W] H,W
PCN10 [R/W] B, H,W
XXXXXXXX XXXXXXXX
0000000- 000000-0
IPCP0 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP1 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICFS01 [R/W]
LSYNS0 [R/W] B, ICS01 [R/W]
B, H, W
―
H, W
B, H, W
------00
--000000
00000000
Block
+0
Document Number: 002-04727 Rev. *B
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
PPG8
PPG9
PPG10
Input Capture 0,1
Page 75 of 174
MB91590 Series
Address
0002D0H
0002D4H
0002D8H
0002DCH
0002E0H
0002E4H
0002E8H
0002ECH
0002F0H
0002F4H
0002F8H
0002FCH
000300H
to
00030CH
Address Offset Value / Register Name
+0
+1
+2
+3
IPCP2 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP3 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICFS23 [R/W]
ICS23 [R/W]
B, H, W
―
―
B, H, W
------00
00000000
IPCP4 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP5 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICFS45 [R/W]
ICS45 [R/W]
B, H, W
―
―
B, H, W
------00
00000000
OCCP0 [R/W] W
00000000 00000000 00000000 00000000
OCCP1 [R/W] W
00000000 00000000 00000000 00000000
OCFS01 [R/W] B,
OCSH01[R/W] B, OCSL01[R/W]
H, W
―
H, W
B, H, W
------11
---0--00
0000--00
OCCP2 [R/W] W
00000000 00000000 00000000 00000000
OCCP3 [R/W] W
00000000 00000000 00000000 00000000
OCFS23 [R/W] B,
OCSH23[R/W] B, OCSL23[R/W]
H, W
―
H, W
B, H, W
------11
---0--00
0000--00
―
―
Document Number: 002-04727 Rev. *B
―
―
Block
Input Capture 2,3
Input Capture 4,5
Output compare 0,1
Output compare 2,3
Reserved
Page 76 of 174
MB91590 Series
Address
+0
Address Offset Value / Register Name
+1
+2
MPUCR [R/W] H
―
000000-0 ----0100
―
―
―
000310H
―
000314H
000318H
00031CH
―
―
―
―
―
DPVAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DPVSR [R/W] H
―
―
-------- 00000--0
DEAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DESR [R/W] H
―
―
-------- 00000--0
PABR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR0 [R/W] H
―
―
000000-0 00000--0
PABR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR1 [R/W] H
―
―
000000-0 00000--0
PABR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR2 [R/W] H
―
―
000000-0 00000--0
PABR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR3 [R/W] H
―
―
000000-0 00000--0
PABR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR4 [R/W] H
―
―
000000-0 00000--0
PABR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR5 [R/W] H
―
―
000000-0 00000--0
PABR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR6 [R/W] H
―
―
000000-0 00000--0
PABR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR7 [R/W] H
―
―
000000-0 00000--0
000320H
000324H
000328H
00032CH
000330H
000334H
000338H
00033CH
000340H
000344H
000348H
00034CH
000350H
000354H
000358H
00035CH
000360H
000364H
000368H
00036CH
Document Number: 002-04727 Rev. *B
+3
Block
MPU [S]
(Only the CPU can
access this area)
MPU [S]
(Only the CPU can
access this area)
Page 77 of 174
MB91590 Series
Address
000370H
000374H
000378H
00037CH
000380H
000384H
000388H
00038CH
000390H
000394H
000398H
00039CH
0003A0H
0003A4H
0003A8H
0003ACH
Address Offset Value / Register Name
+0
+1
+2
PABR8 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR8 [R/W] H
―
―
000000-0 00000--0
PABR9[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR9 [R/W] H
―
―
000000-0 00000--0
PABR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR10 [R/W] H
―
―
000000-0 00000--0
PABR11 [R/W] ,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR11 [R/W] H
―
―
000000-0 00000--0
PABR12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR12 [R/W] H
―
―
000000-0 00000--0
PABR13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR13 [R/W] H
―
―
000000-0 00000--0
PABR14 [R/W]W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR14 [R/W] H
―
―
000000-0 00000--0
PABR15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
PACR15 [R/W] H
―
―
000000-0 00000--0
0003B0H
to
―
0003FCH
―
Document Number: 002-04727 Rev. *B
―
―
+3
Block
MPU [S]
(Only product mounting MPU
12ch or 16ch)
(Only the CPU can
access this area)
Reserved [S]
Page 78 of 174
MB91590 Series
Address
+0
000400H
ICSEL0[R/W]
B, H, W
-----000
000404H
ICSEL4[R/W]
B, H, W
-------0
000408H
ICSEL8[R/W]
B, H, W
------00
00040CH
ICSEL12[R/W]
B, H, W
------00
000410H
000414H
000418H
00041CH
000420H
000424H
000428H
00042CH
ICSEL16[R/W]
B, H, W
*1
--------------0*2
ICSEL20[R/W]
B, H, W
-----000
IRPR0H[R]
B, H, W
*1
00-----0000----*2
IRPR2H[R]
B, H, W
00-----IRPR4H[R]
B, H, W
0000----*1
00000---*2
IRPR6H[R]
B, H, W
*1
00--0--00000---*2
IRPR8H[R]
B, H, W
00------*1
0000----*2
IRPR10H[R]
B, H, W
00------
000430H
IRPR12H[R]
B, H, W
00------
000434H
IRPR14H[R]
B, H, W
00000000
000438H,
―
00043CH
Address Offset Value / Register Name
+1
+2
+3
ICSEL2[R/W]
ICSEL3[R/W]
ICSEL1[R/W]
B, H, W
B, H, W
B, H, W
*1
*1
-------0
-------0
-----000
------00*2
------00*2
ICSEL5[R/W]
ICSEL6[R/W]
ICSEL7[R/W]
B, H, W
B, H, W
B, H, W
-------0
-----000
-----000
ICSEL9[R/W]
ICSEL10[R/W]
ICSEL11[R/W]
B, H, W
B, H, W
B, H, W
*1
*1
------00
------00
------00
-----000*2
-----000*2
ICSEL15[R/W]
ICSEL13[R/W]
ICSEL14[R/W]
B, H, W
B, H, W
B, H, W
--------*1
-------0
-------0
-------0*2
ICSEL17[R/W]
ICSEL18[R/W]
ICSEL19[R/W]
B, H, W
B, H, W
B, H, W
*1
*1
-------------------000
*2
*2
-------0
-------0
ICSEL21[R/W]
ICSEL22[R/W]
B, H, W
B, H, W
―
------00
------00
IRPR0L[R]
IRPR1H[R]
IRPR1L[R]
B, H, W
B, H, W
B, H, W
*1
00-----00-----00-----0000----*2
IRPR2L[R]
IRPR3H[R]
IRPR3L[R]
B, H, W
B, H, W
B, H, W
00-----000000-000000-IRPR4L[R]
IRPR5H[R]
IRPR5L[R]
B, H, W
B, H, W
B, H, W
0000----*1
0000----*1
0-------*1
*2
*2
000000-00000--000-----*2
IRPR6L[R]
IRPR7H[R]
IRPR7L[R]
B, H, W
B, H, W
B, H, W
*1
*1
*1
000-----00----------0*2
*2
0000----0000--------00*2
IRPR8L[R]
IRPR9H[R]
IRPR9L[R]
B, H, W
B, H, W
B, H, W
*1
00-----00-----00-----0000----*2
IRPR10L[R]
IRPR11H[R]
IRPR11L[R]
B, H, W
B, H, W
B, H, W
00-----00-----00-----IRPR13H[R]
IRPR13L[R]
IRPR12L[R]
B, H, W
B, H, W
B, H, W
000-----*1
00000---*1
00-----*2
00000--0000000-*2
IRPR15H[R]
IRPR14L[R]
B, H, W
B, H, W
―
*1
000----00000000
*2
0000---―
Document Number: 002-04727 Rev. *B
―
―
Block
Generation and clear
of DMA transfer
request
*1:MB91F591/2/4/6/7/9
*2:MB91F59A/B
Interrupt request batch read
register
*1:MB91F591/2/4/6/7/9
*2:MB91F59A/B
Interrupt request batch read
register
MB91F59A/B only
Interrupt request batch read
register
*1:MB91F591/2/4/6/7/9
*2:MB91F59A/B
Reserved
Page 79 of 174
MB91590 Series
Address
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
+0
ICR00 [R/W]
B, H, W
---11111
ICR04 [R/W]
B, H, W
---11111
ICR08 [R/W]
B, H, W
---11111
ICR12 [R/W]
B, H, W
---11111
ICR16 [R/W]
B, H, W
---11111
ICR20 [R/W]
B, H, W
---11111
ICR24 [R/W]
B, H, W
---11111
ICR28 [R/W]
B, H, W
---11111
ICR32 [R/W]
B, H, W
---11111
ICR36 [R/W]
B, H, W
---11111
ICR40 [R/W]
B, H, W
---11111
ICR44 [R/W]
B, H, W
---11111
Address Offset Value / Register Name
+1
+2
+3
ICR01 [R/W]
ICR02 [R/W]
ICR03 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
ICR05 [R/W]
ICR06 [R/W]
ICR07 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
ICR09 [R/W]
ICR10 [R/W]
ICR11 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
ICR13 [R/W]
ICR14 [R/W]
ICR15 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
ICR17 [R/W]
ICR18 [R/W]
ICR19 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
ICR21 [R/W]
ICR22 [R/W]
ICR23 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
ICR25 [R/W]
ICR26 [R/W]
ICR27 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
ICR29 [R/W]
ICR30 [R/W]
ICR31 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
ICR33 [R/W]
ICR34 [R/W]
ICR35 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
ICR37 [R/W]
ICR38 [R/W]
ICR39 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
ICR41 [R/W]
ICR42 [R/W]
ICR43 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
ICR45 [R/W]
ICR46 [R/W]
ICR47 [R/W]
B, H, W
B, H, W
B, H, W
---11111
---11111
---11111
000470H
to
00047CH
―
―
―
000480H
RSTRR [R]
B, H, W
XXXX--XX
RSTCR [R/W]
B, H, W
111----0
STBCR [R/W]
B, H, W *3
000---11
―
DIVR0 [R/W]
B, H, W
000----―
―
DIVR1 [R/W]
B, H, W
0001---―
―
DIVR2 [R/W]
B, H, W
0011---―
000484H
000488H
00048CH
Document Number: 002-04727 Rev. *B
―
―
Block
Interrupt controller [S]
Reserved [S]
Reset control [S]
Power consumption control [S]
―
*3: Writing to STBCR by DMA
is disabled
Reserved [S]
―
Clock control [S]
―
Reserved [S]
Page 80 of 174
MB91590 Series
Address
000490H
000494H
000498H
00049CH
0004A0H
0004A4H
0004A8H
0004ACH
0004B0H
0004B4H
0004B8H
0004BCH
0004C0H
0004C4H
0004C8H
0004CCH
0004D0H
0004D4H
0004D8H
0004DCH
0004E0H
0004E4H
0004E8H
0004ECH
Address Offset Value / Register Name
+0
+1
+2
+3
IORR0[R/W]
IORR1[R/W]
IORR2[R/W]
IORR3[R/W]
B, H, W
B, H, W
B, H, W
B, H, W
-0000000
-0000000
-0000000
-0000000
IORR4[R/W]
IORR5[R/W]
IORR6[R/W]
IORR7[R/W]
B, H, W
B, H, W
B, H, W
B, H, W
-0000000
-0000000
-0000000
-0000000
IORR8[R/W]
IORR9[R/W]
IORR10[R/W]
IORR11[R/W]
B, H, W
B, H, W
B, H, W
B, H, W
-0000000
-0000000
-0000000
-0000000
IORR12[R/W]
IORR13[R/W]
IORR14[R/W]
IORR15[R/W]
B, H, W
B, H, W
B, H, W
B, H, W
-0000000
-0000000
-0000000
-0000000
―
―
―
―
CANPRE [R/W]
B,H,W
―
―
―
----0000
CPCLR6 [R/W] W
11111111 11111111 11111111 11111111
TCDT6 [R/W] W
00000000 00000000 00000000 00000000
TCCSH6 [R/W]
TCCSL6 [R/W]
B, H, W
B, H, W
―
0-----00
-1-00000
―
―
―
―
CUCR0 [R/W] B,H,W
CUTD0 [R/W] B,H,W
-------- ---0--00
10000000 00000000
CUTR0 [R] B,H,W
-------- 00000000 00000000 00000000
―
―
―
―
CUCR1 [R/W] B,H,W
CUTD1[R/W] B,H,W
-------- ---0--00
11000011 01010000
CUTR1 [R] B,H,W
-------- 00000000 00000000 00000000
CRTR [R/W]
B,H,W
―
―
―
01111111
CPCLR7 [R/W] W
11111111 11111111 11111111 11111111
TCDT7 [R/W] W
00000000 00000000 00000000 00000000
TCCSH7 [R/W]
TCCSL7 [R/W]
B, H, W
B, H, W
―
0-----00
-1-00000
―
―
―
―
SCR8 [R/W]
SMR8 [R/W]
SSR8 [R/W]
ESCR8 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
0--00000
000-0000
0-000011
-0000000
*1
RDR8/(TDR8)[R/W] B,H,W
BGR8 [R/W] H,W
-------0 00000000
00000000 00000000
―
―
―
―
FCR18 [R/W]
FCR08 [R/W]
FBYTE28 [R/W] FBYTE18 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
---00100
-0000000
00000000
00000000
Document Number: 002-04727 Rev. *B
Block
DMA transfer request from a
peripheral [S]
Reserved
CAN prescaler
Free-run timer 6
MB91F59A/B only
Reserved
RTC/WDT1
calibration (Calibration)
RC trimming
setting register
Free-run timer 7
MB91F59A/B only
Reserved
Multi-function serial 8
*1: Byte access is possible
only for access to lower 8 bits.
MB91F59A/B only
Page 81 of 174
MB91590 Series
Address
0004F0H
0004F4H
0004F8H
0004FCH
Address Offset Value / Register Name
+0
+1
+2
+3
SCR9 [R/W]
SMR9 [R/W]
SSR9 [R/W]
ESCR9 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
0--00000
000-0000
0-000011
-0000000
RDR9/(TDR9)[R/W] B,H,W *1
BGR9 [R/W] H,W
-------0 00000000
00000000 00000000
―
―
―
―
FCR19 [R/W]
FCR09 [R/W]
FBYTE29 [R/W] FBYTE19 [R/W]
B,H,W
B,H,W
B,H,W
B,H,W
---00100
-0000000
00000000
00000000
Block
Multi-function serial 9
*1: Byte access is possible
only for access to lower 8 bits.
MB91F59A/B only
000500H
to
00050CH
―
―
―
―
Reserved
000510H
CSELR [R/W]
B,H,W
001---00
CMONR [R]
B,H,W
001---00
000514H
STMCR [R/W]
B,H,W
0000-111
PTMCR [R/W]
B,H,W
00------
Clock control [S]
PLLCR [R/W] B,H,W
-------- 11110000
000518H
―
―
―
Reset [S]
00051CH
―
CCPSSELR
[R/W] B,H,W
-------0
―
MTMCR [R/W]
B,H,W
00001111
CSTBR [R/W]
B,H,W
-0000000
CPUAR [R/W]
B,H,W
0----XXX
―
Reserved [S]
―
―
CCPLLFBR
[R/W] B,H,W
-0000000
CCSSCCR0
[R/W] B,H,W
----0000
CCCGRCR0
[R/W] B,H,W
00----00
―
―
―
CCSSFBR0
[R/W] B,H,W
--000000
CCSSCCR1
[R/W] H,W
000----- -------CCCGRCR1
[R/W] B,H,W
00000000
CCPMUCR0
[R/W] B,H,W
0-----00
―
―
―
―
CCPSDIVR
[R/W] B,H,W
-000-000
CCSSFBR1
[R/W] B,H,W
---00000
―
―
―
EIRR0
[R/W] B,H,W
XXXXXXXX
EIRR1
[R/W] B,H,W
XXXXXXXX
―
ENIR0
[R/W] B,H,W
00000000
ENIR1
[R/W] B,H,W
00000000
―
ELVR0
[R/W] B,H,W
00000000 00000000
ELVR1
[R/W] B,H,W
00000000 00000000
―
―
000520H
000524H
―
000528H
―
00052CH
―
000530H
000534H
000538H
00053CH
000540H
to
00054CH
000550H
000554H
000558H
CCRTSELR
[R/W] B,H,W
0------0
―
―
―
―
Document Number: 002-04727 Rev. *B
CCCGRCR2
[R/W] B,H,W
00000000
CCPMUCR1
[R/W] B,H,W
0--00000
―
―
―
―
Clock control 2
Clock control 2
Reserved
External interrupt
(INT0 to INT7)
External interrupt
(INT8 to INT15)
Reserved
Page 82 of 174
MB91590 Series
Address
+0
00055CH
―
000560H
―
000564H
―
000568H
WTHR
[R/W] B,H
---00000
Address Offset Value / Register Name
+1
+2
+3
WTDR[R/W] H
―
00000000 00000000
WTCRH
WTCRM
WTCRL
[R/W] B
[R/W] B,H
[R/W] B,H
------00
00000000
----00-0
WTBRH
WTBRM
WTBRL
[R/W] B
[R/W] B
[R/W] B
--XXXXXX
XXXXXXXX
XXXXXXXX
WTMR
WTSR
[R/W] B,H
[R/W] B
―
--000000
--000000
Block
Real-time clock
Clock supervisor
00056CH
―
CSVCR
[R/W] B
-001110-001010-*4
000570H
to
00057CH
―
―
―
―
Reserved
―
―
―
Regulator control
LVD5F
[R/W] B,H,W
0-100--1
GLVD5F[R/W]
B,H,W
0-0100-X
―
PMUCTLR
[R/W] B,H,W
0-00---PMUINTF1
[R/W] B,H,W
00000000
GCTLR[R/W]
B,H,W
0000-111
―
LVD
[R/W] B,H,W
01000--0
GLVD[R/W]
B,H,W
010000-X
―
PWRTMCTL
[R/W] B,H,W
-----011
PMUINTF2
[R/W] B,H,W
0000----
―
000580H
000584H
000588H
00058CH
000590H
000594H
000598H
00059CH
0005A0H
to
0005FCH
000600H
to
00060CH
000610H
to
00063CH
000640H
to
00064CH
000650H
to
00067CH
REGSEL
[R/W] B,H,W
0110011LVD5R
[R/W] B,H,W
-------1
GLVD5R[R/W]
B,H,W
0-01-0-X
―
PMUSTR
[R/W] B,H,W
0-----1X
PMUINTF0
[R/W] B,H,W
00000000
GSTR[R]
B,H,W
0------―
―
―
*4: An initial value is different
by part number. For details,
see the CSVCR register in
chapter "Clock Supervisor"
―
Low-power detection
―
―
Reserved
―
―
PMU
―
―
―
―
―
―
―
Reserved
―
―
―
―
Reserved[S]
―
―
―
―
Reserved[S]
―
―
―
―
Reserved[S]
―
―
―
―
Reserved[S]
Document Number: 002-04727 Rev. *B
Page 83 of 174
MB91590 Series
Address
000680H
to
00068CH
000690H
to
0006BCH
0006C0H
to
0006CCH
0006D0H
to
0006F0H
0006F4 H
0006F8H
to
00070CH
000710H
000714H
000718H
00071CH
000720H
to
0007F8H
+0
Address Offset Value / Register Name
+1
+2
Block
+3
―
―
―
―
Reserved[S]
―
―
―
―
Reserved[S]
―
―
―
―
Reserved[S]
―
―
―
―
Reserved
―
―
―
―
Reserved
―
―
―
―
Reserved
BPCCRA[R/W]
BPCCRB[R/W]
BPCCRC[R/W]
B
B
B
00000000
00000000
00000000
BPCTRA[R/W] W
00000000 00000000 00000000 00000000
BPCTRB[R/W] W
00000000 00000000 00000000 00000000
BPCTRC[R/W] W
00000000 00000000 00000000 00000000
―
BMODR[R]
0007FCH B, H, W
XXXXXXXX
000800H
to
―
00083CH
FCTLR[R/W] H
000840H
-0--1000 0--0---000844H
to
―
000854H
―
Bus performance counter
―
―
―
Reserved
―
―
―
Operation mode
―
―
―
Reserved [S]
―
FSTR[R/W] B
-----001
Flash memory
register [S]
―
―
―
Reserved [S]
000858H
―
―
WREN[R/W] H
00000000 00000000
Wild register [S]
00085CH
to
00087CH
―
―
―
Reserved [S]
Document Number: 002-04727 Rev. *B
―
Page 84 of 174
MB91590 Series
Address
000880H
000884H
000888H
00088CH
000890H
000894H
000898H
00089CH
0008A0H
Address Offset Value / Register Name
+0
+1
+2
WRAR00[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR00[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR01[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR01[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR02[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR02[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR03[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR03[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR04[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
Document Number: 002-04727 Rev. *B
+3
Block
Wild register [S]
Page 85 of 174
MB91590 Series
Address
0008A4H
0008A8H
0008ACH
0008B0H
0008B4H
0008B8H
0008BCH
0008C0H
0008C4H
0008C8H
0008CCH
0008D0H
0008D4H
0008D8H
0008DCH
0008E0H
0008E4H
0008E8H
0008ECH
0008F0H
0008F4H
0008F8H
0008FCH
000900H
to
000BF8H
Address Offset Value / Register Name
+0
+1
+2
WRDR04[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR05[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR05[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR06[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR06[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR07[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR07[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR08[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR08[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR09[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR09[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR10[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR10[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR11[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR11[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR12[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR12[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR13[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR13[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR14[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR14[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR15[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR15[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
―
―
―
000BFCH ―
―
UER [W] B,H,W
-------- -------X
Document Number: 002-04727 Rev. *B
―
Block
+3
Wild register [S]
Reserved
OCDU
Page 86 of 174
MB91590 Series
Address
000C00H
000C04H
000C08H
000C0CH
000C10H
000C14H
000C18H
000C1CH
000C20H
000C24H
000C28H
000C2CH
000C30H
000C34H
000C38H
000C3CH
000C40H
000C44H
000C48H
000C4CH
Address Offset Value / Register Name
+0
+1
+2
DCCR0[R/W] W
0----000 --00--00 00000000 0-000000
DCSR0[R/W] H
DTCR0[R/W] H
0------- -----000
00000000 00000000
DSAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR1[R/W] W
0----000 --00--00 00000000 0-000000
DCSR1[R/W] H
DTCR1[R/W] H
0------- -----000
00000000 00000000
DSAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR2[R/W] W
0----000 --00--00 00000000 0-000000
DCSR2[R/W] H
DTCR2[R/W] H
0------- -----000
00000000 00000000
DSAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR3[R/W] W
0----000 --00--00 00000000 0-000000
DCSR3[R/W] H
DTCR3[R/W] H
0------- -----000
00000000 00000000
DSAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR4[R/W] W
0----000 --00--00 00000000 0-000000
DCSR4[R/W] H
DTCR4[R/W] H
0------- -----000
00000000 00000000
DSAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: 002-04727 Rev. *B
+3
Block
DMA controller [S]
Page 87 of 174
MB91590 Series
Address
000C50H
000C54H
000C58H
000C5CH
000C60H
000C64H
000C68H
000C6CH
000C70H
000C74H
000C78H
000C7CH
000C80H
000C84H
000C88H
000C8CH
000C90H
000C94H
000C98H
000C9CH
000CA0H
000CA4H
000CA8H
Address Offset Value / Register Name
+0
+1
+2
DCCR5[R/W] W
0----000 --00--00 00000000 0-000000
DCSR5[R/W] H
DTCR5[R/W] H
0------- -----000
00000000 00000000
DSAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR6[R/W] W
0----000 --00--00 00000000 0-000000
DCSR6[R/W] H
DTCR6[R/W] H
0------- -----000
00000000 00000000
DSAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR7[R/W] W
0----000 --00--00 00000000 0-000000
DCSR7[R/W] H
DTCR7[R/W] H
0------- -----000
00000000 00000000
DSAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR8[R/W] W
0----000 --00--00 00000000 0-000000
DCSR8[R/W] H
DTCR8[R/W] H
0------- -----000
00000000 00000000
DSAR8[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR8[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR9[R/W] W
0----000 --00--00 00000000 0-000000
DCSR9[R/W] H
DTCR9[R/W] H
0------- -----000
00000000 00000000
DSAR9[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR9[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR10[R/W] W
0----000 --00--00 00000000 0-000000
DCSR10[R/W] H
DTCR10[R/W] H
0------- -----000
00000000 00000000
DSAR10[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: 002-04727 Rev. *B
+3
Block
DMA controller [S]
Page 88 of 174
MB91590 Series
Address
000CACH
000CB0H
000CB4H
000CB8H
000CBCH
000CC0H
000CC4H
000CC8H
000CCCH
000CD0H
000CD4H
000CD8H
000CDCH
000CE0H
000CE4H
000CE8H
000CECH
000CF0H
000CF4H
000CF8H
000CFCH
Address Offset Value / Register Name
+0
+1
+2
DDAR10[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR11[R/W] W
0----000 --00--00 00000000 0-000000
DCSR11[R/W] H
DTCR11[R/W] H
0------- -----000
00000000 00000000
DSAR11[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR11[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR12[R/W] W
0----000 --00--00 00000000 0-000000
DCSR12[R/W] H
DTCR12[R/W] H
0------- -----000
00000000 00000000
DSAR12[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR12[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR13[R/W] W
0----000 --00--00 00000000 0-000000
DCSR13[R/W] H
DTCR13[R/W] H
0------- -----000
00000000 00000000
DSAR13[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR13[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR14[R/W] W
0----000 --00--00 00000000 0-000000
DCSR14[R/W] H
DTCR14[R/W] H
0------- -----000
00000000 00000000
DSAR14[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR14[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR15[R/W] W
0----000 --00--00 00000000 0-000000
DCSR15[R/W] H
DTCR15[R/W] H
0------- -----000
00000000 00000000
DSAR15[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR15[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
000D00H
to
―
000DF0H
―
―
―
000DF4H ―
―
DNMIR[R/W] B
0------0
DILVR[R/W] B
---11111
―
―
000DF8H
000DFCH
DMACR[R/W] W
0------- -------- 0------- -------―
―
Document Number: 002-04727 Rev. *B
Block
DMA controller [S]
Reserved [S]
DMA controller [S]
Reserved [S]
Page 89 of 174
MB91590 Series
Address
000E00H
000E04H
000E08H
000E0CH
000E10H
000E14H
+0
DDR00[R/W]
B,H,W
00000000
DDR04[R/W]
B,H,W
00000000
DDR08[R/W]
B,H,W
00000000
DDR12[R/W]
B,H,W
00000000
DDRA[R/W]
B,H,W
000000-DDRE[R/W]
B,H,W
000000--
000E18H
to
―
000E1CH
PFR00[R/W]
000E20H B,H,W
00000000
PFR04[R/W]
000E24H B,H,W
00000000
PFR08[R/W]
000E28H B,H,W
00000000
PFR12[R/W]
000E2CH B,H,W
0-000000
PFRA[R/W]
000E30H B,H,W
-------PFRE[R/W]
000E34H B,H,W
000000-000E38H
to
―
000E3CH
Address Offset Value / Register Name
+1
+2
+3
DDR01[R/W]
DDR02[R/W]
DDR03[R/W]
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
DDR05[R/W]
DDR06[R/W]
DDR07[R/W]
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
DDR09[R/W]
DDR10[R/W]
DDR11[R/W]
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
DDR13[R/W]
B,H,W
―
―
00-00000
DDRB[R/W]
DDRC[R/W]
DDRD[R/W]
B,H,W
B,H,W
B,H,W
000000-000000-000000-DDRF[R/W]
DDRG[R/W]
DDRH[R/W]
B,H,W
B,H,W
B,H,W
000000-00000000
----0--―
―
―
PFR01[R/W]
B,H,W
00000000
PFR05[R/W]
B,H,W
-0000000
PFR09[R/W]
B,H,W
0-000000
PFR13[R/W]
B,H,W
---00000
PFRB[R/W]
B,H,W
-------PFRF[R/W]
B,H,W
000000--
PFR02[R/W]
B,H,W
00000000
PFR06[R/W]
B,H,W
00000000
PFR10[R/W]
B,H,W
00000000
PFR03[R/W]
B,H,W
00000000
PFR07[R/W]
B,H,W
00000000
PFR11[R/W]
B,H,W
00000000
―
―
PFRC[R/W]
B,H,W
-------PFRG[R/W]
B,H,W
00000---
PFRD[R/W]
B,H,W
000000-PFRH[R/W]
B,H,W
--------
―
―
―
Document Number: 002-04727 Rev. *B
Block
Data direction
register
Reserved
Port function register
Reserved
Page 90 of 174
MB91590 Series
Address
000E40H
000E44H
000E48H
000E4CH
000E50H
000E54H
Address Offset Value / Register Name
Block
+0
+1
+2
+3
PDDR00[R]
PDDR01[R]
PDDR02[R]
PDDR03[R]
B,H,W
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDDR04[R]
PDDR05[R]
PDDR06[R]
PDDR07[R]
B,H,W
B,H,W
B,H,W
B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDDR08[R]
PDDR09[R]
PDDR10[R]
PDDR11[R]
B,H,W
B,H,W
B,H,W
B,H,W
Input data direct read register
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDDR12[R]
PDDR13[R]
B,H,W
B,H,W
―
―
XXXXXXXX
XX-XXXXX
PDDRA[R] B,H,W PDDRB[R] B,H,W PDDRC[R] B,H,W PDDRD[R] B,H,W
XXXXXX-XXXXXX-XXXXXX-XXXXXX-PDDRE[R] B,H,W PDDRF[R] B,H,W PDDRG[R] B,H,W PDDRH[R] B,H,W
XXXXXX-XXXXXX-XXXXXXXX
----X---
000E58H
to
―
000E5CH
―
Document Number: 002-04727 Rev. *B
―
―
Reserved
Page 91 of 174
MB91590 Series
Address
000E60H
000E64H
000E68H
000E6CH
000E70H
000E74H
000E78H
000E7CH
000E80H
000E84H
000E88H
000E8CH
000E90H
000E94H
000E98H
000E9CH
+0
EPFR00[R/W]
B,H,W
00000000
EPFR04[R/W]
B,H,W
---00000
EPFR08[R/W]
B,H,W
---00000
EPFR12[R/W]
B,H,W
--000000
EPFR16[R/W]
B,H,W
00000000
EPFR20[R/W]
B,H,W
-1111111
EPFR24[R/W]
B,H,W
-----000
EPFR28[R/W]
B,H,W
------00
EPFR32[R/W]
B,H,W
00000000
EPFR36[R/W]
B,H,W
---00000
EPFR40[R/W]
B,H,W
--000000
EPFR44[R/W]
B,H,W
00000000
EPFR48[R/W]
B,H,W
00000000
EPFR52[R/W]
B,H,W
-----000
EPFR56[R/W]
B,H,W
--000000
―
Address Offset Value / Register Name
+1
+2
+3
EPFR01[R/W]
EPFR02[R/W]
EPFR03[R/W]
B,H,W
B,H,W
B,H,W
*1
----0000
---00000
---00000
*2
00000000
EPFR05[R/W]
EPFR06[R/W]
EPFR07[R/W]
B,H,W
B,H,W
B,H,W
---00000
---00000
---00000
EPFR09[R/W]
EPFR10[R/W]
EPFR11[R/W]
B,H,W
B,H,W
B,H,W
---00000
-0000000
--000000
EPFR13[R/W]
EPFR14[R/W]
EPFR15[R/W]
B,H,W
B,H,W
B,H,W
--000000
--000000
-0000000
EPFR17[R/W]
EPFR18[R/W]
EPFR19[R/W]
B,H,W
B,H,W
B,H,W
00000000
10000000
11111111
EPFR21[R/W]
EPFR22[R/W]
EPFR23[R/W]
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
EPFR25[R/W]
EPFR26[R/W]
EPFR27[R/W]
B,H,W
B,H,W
B,H,W
-----000
----0000
---00000
EPFR29[R/W]
EPFR30[R/W]
EPFR31[R/W]
B,H,W
B,H,W
B,H,W
00000000
00000000
00000000
EPFR33[R/W]
EPFR34[R/W]
EPFR35[R/W]
B,H,W
B,H,W
B,H,W
---00000
---00000
---00000
EPFR37[R/W]
EPFR38[R/W]
EPFR39[R/W]
B,H,W
B,H,W
B,H,W
00000000
---00000
00000000
EPFR41[R/W]
EPFR42[R/W]
EPFR43[R/W]
B,H,W
B,H,W
B,H,W
-----000
------00
00000000
EPFR45[R/W]
EPFR46[R/W]
EPFR47[R/W]
B,H,W
B,H,W
B,H,W
00000000
--000000
-------0
EPFR49[R/W]
EPFR50[R/W]
EPFR51[R/W]
B,H,W
B,H,W
B,H,W
00000000
00000000
---00000
EPFR53[R/W]
EPFR54[R/W]
EPFR55[R/W]
B,H,W
B,H,W
B,H,W
---00000
----0000
------01
EPFR57[R/W]
EPFR58[R/W]
B,H,W
B,H,W
―
--000000
----0000
―
―
―
Document Number: 002-04727 Rev. *B
Block
Extended port
function register
*1:MB91F591/2/4/6/7/9
*2:MB91F59A/B
Extended port
function register
MB91F59A/B only
Reserved
Page 92 of 174
MB91590 Series
Address
000EA0H
000EA4H
000EA8H
000EACH
000EB0H
000EB4H
+0
PPCR00[R/W]
B,H,W
11111111
PPCR04[R/W]
B,H,W
11111111
PPCR08[R/W]
B,H,W
11111111
PPCR12[R/W]
B,H,W
11111111
PPCRA[R/W]
B,H,W
111111-PPCRE[R/W]
B,H,W
111111--
000EB8H
to
―
000EBCH
PPER00[R/W]
000EC0H B,H,W
00000000
PPER04[R/W]
000EC4H B,H,W
00000000
PPER08[R/W]
000EC8H B,H,W
00000000
PPER12[R/W]
000ECCH B,H,W
00000000
PPERA[R/W]
000ED0H B,H,W
000000-PPERE[R/W]
000ED4H B,H,W
000000-000ED8H
to
―
000EDCH
Address Offset Value / Register Name
+1
+2
+3
PPCR01[R/W]
PPCR02[R/W]
PPCR03[R/W]
B,H,W
B,H,W
B,H,W
11111111
11111111
11111111
PPCR05[R/W]
PPCR06[R/W]
PPCR07[R/W]
B,H,W
B,H,W
B,H,W
11111111
11111111
11111111
PPCR09[R/W]
PPCR10[R/W]
PPCR11[R/W]
B,H,W
B,H,W
B,H,W
11111111
11111111
11111111
PPCR13[R/W]
B,H,W
―
―
11-11111
PPCRB[R/W]
PPCRC[R/W]
PPCRD[R/W]
B,H,W
B,H,W
B,H,W
111111-111111-111111-PPCRF[R/W]
PPCRG[R/W]
PPCRH[R/W]
B,H,W
B,H,W
B,H,W
111111-11111111
----1--―
―
―
PPER01[R/W]
B,H,W
00000000
PPER05[R/W]
B,H,W
00000000
PPER09[R/W]
B,H,W
00000000
PPER13[R/W]
B,H,W
00-00000
PPERB[R/W]
B,H,W
000000-PPERF[R/W]
B,H,W
000000--
PPER02[R/W]
B,H,W
00000000
PPER06[R/W]
B,H,W
00000000
PPER10[R/W]
B,H,W
00000000
PPER03[R/W]
B,H,W
00000000
PPER07[R/W]
B,H,W
00000000
PPER11[R/W]
B,H,W
00000000
―
―
PPERC[R/W]
B,H,W
000000-PPERG[R/W]
B,H,W
00000000
PPERD[R/W]
B,H,W
000000-PPERH[R/W]
B,H,W
----0---
―
―
―
Document Number: 002-04727 Rev. *B
Block
Port pull-up/down control
register
Reserved
Port pull-up/down enable
register
Reserved
Page 93 of 174
MB91590 Series
Address
000EE0H
000EE4H
000EE8H
000EECH
000EF0H
000EF4H
+0
PILR00[R/W]
B,H,W
11111111
PILR04[R/W]
B,H,W
11111111
PILR08[R/W]
B,H,W
11111111
PILR12[R/W]
B,H,W
11111111
PILRA[R/W]
B,H,W
111111-PILRE[R/W]
B,H,W
111111--
000EF8H
to
―
000EFCH
000F00H ―
000F04H
000F08H
000F0CH
000F28H
000F2CH
000F30H
000F34H
000F38H
000F3CH
Block
Port input level selection
register
―
―
―
Reserved
―
―
EPILR06[R/W]
B,H,W
00000000
EPILR10[R/W]
B,H,W
00000000
―
EPILR07[R/W]
B,H,W
00000000
EPILR11[R/W]
B,H,W
00000000
Extended Port input level
selection register
―
―
―
―
―
―
―
―
―
Reserved
―
―
PODR06[R/W]
B,H,W
00000000
PODR10[R/W]
B,H,W
00000000
―
PODR07[R/W]
B,H,W
00000000
PODR11[R/W]
B,H,W
00000000
Port output drive register
―
―
―
―
EPODR08[R/W]
B,H,W
00000000
―
―
―
―
―
―
EPILR08[R/W]
B,H,W
00000000
EPILR12[R/W]
B,H,W
00000000
―
―
EPILR09[R/W]
B,H,W
00000000
EPILR13[R/W]
B,H,W
00-00000
―
―
000F10H
000F14H
000F18H
to
―
000F1CH
000F20H ―
000F24H
Address Offset Value / Register Name
+1
+2
+3
PILR01[R/W]
PILR02[R/W]
PILR03[R/W]
B,H,W
B,H,W
B,H,W
11111111
11111111
11111111
PILR05[R/W]
PILR06[R/W]
PILR07[R/W]
B,H,W
B,H,W
B,H,W
11111111
11111111
11111111
PILR09[R/W]
PILR10[R/W]
PILR11[R/W]
B,H,W
B,H,W
B,H,W
11111111
11111111
11111111
PILR13[R/W]
B,H,W
―
―
11-11111
PILRB[R/W]
PILRC[R/W]
PILRD[R/W]
B,H,W
B,H,W
B,H,W
111111-111111-111111-PILRF[R/W]
PILRG[R/W]
PILRH[R/W]
B,H,W
B,H,W
B,H,W
111111-11111111
----1---
―
―
PODR08[R/W]
B,H,W
00000000
PODR12[R/W]
B,H,W
00000000
―
―
EPODR06[R/W]
B,H,W
00000000
EPODRGD
[R/W]B,H,W
----1010
PODR09[R/W]
B,H,W
00000000
PODR13[R/W]
B,H,W
00-00000
―
―
EPODR07[R/W]
B,H,W
00000000
EPODRGF
[R/W]B,H,W
--101010
Document Number: 002-04727 Rev. *B
―
Extended Port output drive
register
Page 94 of 174
MB91590 Series
Address
000F40H
+0
PORTEN [R/W]
B,H,W
-------0
000F44H
to
―
000F4CH
000F50H
―
000F54H
―
000F58H
―
000F5CH ―
000F60H
―
000F64H
―
Address Offset Value / Register Name
+1
+2
Block
+3
―
―
―
Port input enable register
―
―
―
Reserved
GPLLCR[R/W]
B,H,W
0------0
PDIVCR[R/W]
B,H,W
-0000000
SSSCR0[R/W]
B,H,W
----0000
PGRCR0[R/W]
B,H,W
00----00
SGRCR0[R/W]
B,H,W
00----00
PTIMCR[R/W]
B,H,W
----1111
SDIVCR0[R/W]
B,H,W
--000000
SSSCR1[R/W]
H,W
000----- -------PGRCR1[R/W]
B,H,W
00000000
SGRCR1[R/W]
B,H,W
00000000
GDCTRGR
[R/W]
B,H,W
0000--00
PEDIVCR[R/W]
B,H,W
-000-000
SDIVCR1[R/W]
B,H,W
---00000
GDCCR[R/W]
B,H,W
--000001
000F68H
to
―
―
―
000F6CH
RCRH0[W]
RCRL0[W]
UDCRH0[R]
000F70H H,W
B,H,W
H,W
XXXXXXXX
XXXXXXXX
00000000
CCR0[R/W] B,H
000F74H
―
00000000 -0001000
000F78H
to
―
―
―
000F7CH
RCRH1[W]
RCRL1[W]
UDCRH1[R]
000F80H H,W
B,H,W
H,W
XXXXXXXX
XXXXXXXX
00000000
CCR1[R/W] B,H
000F84H
―
00000000 -0001000
000F88H
to
―
―
―
000F9CH
CPCLR2 [R/W] W
000FA0H
11111111 11111111 11111111 11111111
TCDT2 [R/W] W
000FA4H
00000000 00000000 00000000 00000000
TCCSH2 [R/W]
TCCSL2 [R/W]
000FA8H B, H, W
B, H, W
―
0-----00
-1-00000
Document Number: 002-04727 Rev. *B
PGRCR2[R/W]
B,H,W
00000000
SGRCR2[R/W]
B,H,W
00000000
GDCSWPR
[R/W]
B,H,W
---00101
GDC control register
―
Reserved
UDCRL0[R]
B,H,W
00000000
CSR0[R/W] B
00000000
Up/down counter 0
MB91F59A/B only
―
Reserved
UDCRL1[R]
B,H,W
00000000
CSR1[R/W] B
00000000
Up/down counter 1
MB91F59A/B only
―
Reserved
Free-run timer 2
Page 95 of 174
MB91590 Series
Address
000FACH
000FB0H
000FB4H
000FB8H
000FBCH
000FC0H
000FC4H
000FC8H
000FCCH
000FD0H
000FD4H
000FD8H
000FDCH
000FE0H
000FE4H
000FE8H
000FECH
000FF0H
000FF4H
000FF8H
000FFCH
001000H
001004H
to
00103CH
Address Offset Value / Register Name
+0
+1
+2
+3
CPCLR3 [R/W] W
11111111 11111111 11111111 11111111
TCDT3 [R/W] W
00000000 00000000 00000000 00000000
TCCSH3 [R/W]
TCCSL3 [R/W]
B, H, W
B, H, W
―
0-----00
-1-00000
CPCLR4 [R/W] W
11111111 11111111 11111111 11111111
TCDT4 [R/W] W
00000000 00000000 00000000 00000000
TCCSH4 [R/W]
TCCSL4 [R/W]
B, H, W
B, H, W
―
0-----00
-1-00000
CPCLR5 [R/W] W
11111111 11111111 11111111 11111111
TCDT5 [R/W] W
00000000 00000000 00000000 00000000
TCCSH5 [R/W]
TCCSL5 [R/W]
B, H, W
B, H, W
―
0-----00
-1-00000
IPCP6 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP7 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
LSYNS1 [R/W]
ICS67 [R/W]
ICFS67 [R/W]
B,H,W
B, H, W
B, H, W
―
*1
------00
00000000
------00
*2
--000000
IPCP8 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP9 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICFS89 [R/W]
ICS89 [R/W]
B, H, W
―
―
B, H, W
------00
00000000
IPCP10 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
IPCP11 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICFS1011 [R/W]
ICS1011 [R/W]
B, H, W
―
―
B, H, W
------00
00000000
RCRH2[W]
RCRL2[W]
UDCRH2[R]
UDCRL2[R]
H,W
B,H,W
H,W
B,H,W
XXXXXXXX
XXXXXXXX
00000000
00000000
CCR2[R/W] B,H
CSR2[R/W] B
―
00000000 -0001000
00000000
―
―
―
―
SACR [R/W]
PICD [R/W]
B,H,W
B,H,W
―
―
-------0
----0011
―
―
Document Number: 002-04727 Rev. *B
―
―
Block
Free-run timer 3
Free-run timer 4
MB91F59A/B only
Free-run timer 5
MB91F59A/B only
Input capture 6,7
*1:MB91F591/2/4/6/7/9
*2:MB91F59A/B
Input Capture 8,9
MB91F59A/B only
Input Capture 10,11
MB91F59A/B only
Up/down counter 2
MB91F59A/B only
Reserved
Synchronous/asynchronous
switching control
Reserved
Page 96 of 174
MB91590 Series
Address
001040H
001044H
001048H
00104CH
Address Offset Value / Register Name
+1
+2
+3
SGDER0[R/W]
SGCR0[R/W] B,H,W
―
B,H,W
-0000-0- 000--000
00000000
SGFR0[R/W]
SGNR0[R/W]
SGAR0[R/W] B,H,W
B,H,W
B,H,W
00000000 00000000
00000000
00000000
SGTCR0[R/W]
SGIDR0[R/W]
SGPCR0[R/W] B,H,W
B,H,W
B,H,W
00000000 11111111
00000000
00000000
SGDMAR0[W] B,H,W
00000000 00000000 00000000 00000000
001050H
to
00105CH
―
―
―
001060H
―
SGDER1[R/W]
B,H,W
00000000
SGCR1[R/W] B,H,W
-0000-0- 000--000
001064H
SGAR1[R/W] B,H,W
00000000 00000000
001068H
00106CH
SGFR1[R/W]
B,H,W
00000000
―
SGNR1[R/W]
B,H,W
00000000
―
―
―
001080H
―
SGDER2[R/W]
B,H,W
00000000
SGCR2[R/W] B,H,W
-0000-0- 000--000
001084H
SGAR2[R/W] B,H,W
00000000 00000000
00108CH
SGFR2[R/W]
B,H,W
00000000
―
SGNR2[R/W]
B,H,W
00000000
―
―
―
0010A0H
―
SGDER3[R/W]
B,H,W
00000000
SGCR3[R/W] B,H,W
-0000-0- 000--000
0010A4H
SGAR3[R/W] B,H,W
00000000 00000000
0010ACH
Reserved
Sound generator 1
Reserved
Sound generator 2
SGTCR2[R/W]
SGIDR2[R/W]
SGPCR2[R/W] B,H,W
B,H,W
B,H,W
00000000 11111111
00000000
00000000
SGDMAR2[W] B,H,W
00000000 00000000 00000000 00000000
001090H
to
00109CH
0010A8H
Sound generator 0
SGTCR1[R/W]
SGIDR1[R/W]
SGPCR1[R/W] B,H,W
B,H,W
B,H,W
00000000 11111111
00000000
00000000
SGDMAR1[W] B,H,W
00000000 00000000 00000000 00000000
001070H
to
00107CH
001088H
Block
+0
SGFR3[R/W]
B,H,W
00000000
―
SGNR3[R/W]
B,H,W
00000000
Reserved
Sound generator 3
SGTCR3[R/W]
SGIDR3[R/W]
SGPCR3[R/W] B,H,W
B,H,W
B,H,W
00000000 11111111
00000000
00000000
SGDMAR3[W] B,H,W
00000000 00000000 00000000 00000000
0010B0H
to
―
0010BCH
―
Document Number: 002-04727 Rev. *B
―
―
Reserved
Page 97 of 174
MB91590 Series
Address
0010C0H
0010C4H
0010C8H
0010CCH
Address Offset Value / Register Name
+1
+2
+3
SGDER4[R/W]
SGCR4[R/W] B,H,W
―
B,H,W
-0000-0- 000--000
00000000
SGFR4[R/W]
SGNR4[R/W]
SGAR4[R/W] B,H,W
B,H,W
B,H,W
00000000 00000000
00000000
00000000
SGTCR4[R/W]
SGIDR4[R/W]
SGPCR4[R/W] B,H,W
B,H,W
B,H,W
00000000 11111111
00000000
00000000
SGDMAR4[W] B,H,W
00000000 00000000 00000000 00000000
0010D0H
to
00112CH
―
―
―
―
001130H
―
―
―
CRCCR[R/W]
B,H,W
-0000000
001134H
001138H
00113CH
Block
+0
CRCINIT[R/W] B,H,W
1111111 1111111 1111111 1111111
CRCIN[R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR[R] B,H,W
1111111 1111111 1111111 1111111
001140H
to
―
0013FCH
001400H
to
―
001FFCH
Sound generator 4
Reserved
CRC arithmetic
operation
―
―
―
Reserved
―
―
―
Reserved (3KB)
Document Number: 002-04727 Rev. *B
Page 98 of 174
MB91590 Series
Address
002000H
002004H
002008H
00200CH
002010H
002014H
002018H
00201CH
002020H
002024H
Address Offset Value / Register Name
+0
+1
+2
CTRLR0 [R/W] B,H,W
STATR0[R/W] B,H,W
-------- 000-0001
-------- 00000000
ERRCNT0
BTR0[R/W] B,H,W
[R] B,H,W
-0100011 00000001
00000000 00000000
INTR0
TESTR0[R/W] B,H,W
[R] B,H,W
-------- X00000-00000000 00000000
BRPER0
[R/W] B,H,W
―
-------- ----0000
IF1CREQ0
IF1CMSK0
[R/W] B,H,W
[R/W] B,H,W
0------- 00000001
-------- 00000000
IF1MSK20
IF1MSK10
[R/W] B,H,W
[R/W] B,H,W
11-11111 11111111
11111111 11111111
IF1ARB20
IF1ARB10
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
IF1MCTR0
[R/W] B,H,W
―
00000000 0---0000
IF1DTA10
IF1DTA20[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
IF1DTB10
IF1DTB20
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
002028H,
Reserved
00202CH
002030H,
Reserved (IF1 data mirror)
002034H
002038H,
Reserved
00203CH
IF2CREQ0
002040H [R/W] B,H,W
0------- 00000001
IF2MSK20
002044H [R/W] B,H,W
11-11111 11111111
IF2ARB20
002048H [R/W] B,H,W
00000000 00000000
IF2MCTR0
00204CH [R/W] B,H,W
00000000 0---0000
Document Number: 002-04727 Rev. *B
Block
+3
CAN0
(64msg)
IF2CMSK0
[R/W] B,H,W
-------- 00000000
IF2MSK10
[R/W] B,H,W
11111111 11111111
IF2ARB10
[R/W] B,H,W
00000000 00000000
―
Page 99 of 174
MB91590 Series
Address
002050H
002054H
Address Offset Value / Register Name
+0
+1
+2
IF2DTA10
IF2DTA20
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
IF2DTB10
IF2DTB20
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
002058H,
Reserved
00205CH
002060H,
Reserved (IF2 data mirror)
002064H
002068H
to
Reserved
00207CH
TREQR20
002080H [R] B,H,W
00000000 00000000
TREQR40
002084H [R] B,H,W
00000000 00000000
002088H ―
00208CH ―
NEWDT20
002090H [R] B,H,W
00000000 00000000
NEWDT40
002094H [R] B,H,W
00000000 00000000
002098H ―
00209CH ―
INTPND20
0020A0H [R] B,H,W
00000000 00000000
INTPND40
0020A4H [R] B,H,W
00000000 00000000
0020A8 H ―
0020ACH ―
MSGVAL20
0020B0H [R] B,H,W
00000000 00000000
MSGVAL40
0020B4H [R] B,H,W
00000000 00000000
0020B8H ―
0020BCH ―
0020C0H
to
Reserved
0020FCH
Document Number: 002-04727 Rev. *B
TREQR10
[R] B,H,W
00000000 00000000
TREQR30
[R] B,H,W
00000000 00000000
―
―
NEWDT10
[R] B,H,W
00000000 00000000
NEWDT30
[R]B,H,W
00000000 00000000
―
―
INTPND10
[R] B,H,W
00000000 00000000
INTPND30
[R] B,H,W
00000000 00000000
―
―
MSGVAL10
[R] B,H,W
00000000 00000000
MSGVAL30
[R] B,H,W
00000000 00000000
―
―
Block
+3
CAN0
(64msg)
Page 100 of 174
MB91590 Series
Address
002100H
002104H
002108H
00210CH
002110H
002114H
002118H
00211CH
002120H
002124H
Address Offset Value / Register Name
+0
+1
+2
CTRLR1
STATR1[R/W] B,H,W
[R/W] B,H,W
-------- 00000000
-------- 000-0001
ERRCNT1
BTR1[R/W] B,H,W
[R] B,H,W
-0100011 00000001
00000000 00000000
INTR1
TESTR1[R/W] B,H,W
[R] B,H,W
-------- X00000-00000000 00000000
BRPER1
[R/W] B,H,W
―
-------- ----0000
IF1CREQ1
IF1CMSK1
[R/W] B,H,W
[R/W] B,H,W
0------- 00000001
-------- 00000000
IF1MSK21
IF1MSK11
[R/W] B,H,W
[R/W] B,H,W
11-11111 11111111
11111111 11111111
IF1ARB21
IF1ARB11
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
IF1MCTR1
[R/W] B,H,W
―
00000000 0---0000
IF1DTA11
IF1DTA21
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
IF1DTB11
IF1DTB21
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
002128H,
Reserved
00212CH
002130H,
Reserved (IF1 data mirror)
002134H
002138H,
Reserved
00213CH
IF2CREQ1
002140H [R/W] B,H,W
0------- 00000001
IF2MSK21
002144H [R/W] B,H,W
11-11111 11111111
IF2ARB21
002148H [R/W] B,H,W
00000000 00000000
Document Number: 002-04727 Rev. *B
Block
+3
CAN1
(32msg)
IF2CMSK1
[R/W] B,H,W
-------- 00000000
IF2MSK11
[R/W] B,H,W
11111111 11111111
IF2ARB11
[R/W] B,H,W
00000000 00000000
Page 101 of 174
MB91590 Series
Address
00214CH
002150H
002154H
Address Offset Value / Register Name
+0
+1
+2
IF2MCTR1
[R/W] B,H,W
―
00000000 0---0000
IF2DTA11
IF2DTA21
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
IF2DTB11
IF2DTB21
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
002158H,
Reserved
00215CH
002160H,
Reserved (IF2 data mirror)
002164H
002168H
to
Reserved
00217CH
TREQR21
002180H [R] B,H,W
00000000 00000000
002184H ―
002188H ―
00218CH ―
NEWDT21
002190H [R] B,H,W
00000000 00000000
002194H ―
002198H ―
00219CH ―
INTPND21
0021A0H [R] B,H,W
00000000 00000000
0021A4H ―
0021A8H ―
0021ACH ―
MSGVAL21
0021B0H [R] B,H,W
00000000 00000000
0021B4H ―
0021B8H ―
0021BCH ―
0021C0H
to
Reserved
0021FCH
Document Number: 002-04727 Rev. *B
TREQR11
[R] B,H,W
00000000 00000000
―
―
―
NEWDT11
[R] B,H,W
00000000 00000000
―
―
―
INTPND11
[R] B,H,W
00000000 00000000
―
―
―
MSGVAL11
[R] B,H,W
00000000 00000000
―
―
―
Block
+3
CAN1
(32msg)
Page 102 of 174
MB91590 Series
Address
002200H
002204H
002208H
00220CH
002210H
002214H
002218H
00221CH
002220H
002224H
Address Offset Value / Register Name
+0
+1
+2
CTRLR2
STATR2[R/W] B,H,W
[R/W] B,H,W
-------- 00000000
-------- 000-0001
ERRCNT2[R] B,H,W
BTR2[R/W] B,H,W
00000000 00000000
-0100011 00000001
INTR2[R] B,H,W
TESTR2[R/W] B,H,W
00000000 00000000
-------- X00000-BRPER2
[R/W] B,H,W
―
-------- ----0000
IF1CREQ2[R/W] B,H,W
IF1CMSK2[R/W] B,H,W
0------- 00000001
-------- 00000000
IF1MSK22
IF1MSK12
[R/W] B,H,W
[R/W] B,H,W
11-11111 11111111
11111111 11111111
IF1ARB22
IF1ARB12
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
IF1MCTR2[R/W] B,H,W
―
00000000 0---0000
IF1DTA12
IF1DTA22
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
IF1DTB12
IF1DTB22
[R/W] B,H,W
[R/W] B,H,W
00000000 00000000
00000000 00000000
002228 H,
Reserved
00222CH
002230 H,
Reserved (IF1 data mirror)
002234H
002238H,
Reserved
00223CH
IF2CREQ2[R/W] B,H,W
002240H
0------- 00000001
IF2MSK22
002244H [R/W] B,H,W
11-11111 11111111
IF2ARB22[R/W] B,H,W
002248H
00000000 00000000
IF2MCTR2[R/W] B,H,W
00224CH
00000000 0---0000
IF2DTA12[R/W] B,H,W
002250H
00000000 00000000
IF2DTB12[R/W] B,H,W
002254H
00000000 00000000
Document Number: 002-04727 Rev. *B
Block
+3
CAN2
(32msg)
IF2CMSK2[R/W] B,H,W
-------- 00000000
IF2MSK12[R/W] B,H,W
11111111 11111111
IF2ARB12[R/W] B,H,W
00000000 00000000
―
IF2DTA22[R/W] B,H,W
00000000 00000000
IF2DTB22[R/W] B,H,W
00000000 00000000
Page 103 of 174
MB91590 Series
Address
+0
Address Offset Value / Register Name
+1
+2
002258H,
Reserved
00225CH
002260H,
Reserved (IF2 data mirror)
002264H
002268H
to
Reserved
00227CH
TREQR22[R] B,H,W
002280H
00000000 00000000
002284H ―
002288H ―
00228CH ―
NEWDT22[R] B,H,W
002290 H
00000000 00000000
002294H ―
002298H ―
00229CH ―
INTPND22[R] B,H,W
0022A0H
00000000 00000000
0022A4H ―
0022A8H ―
0022ACH ―
MSGVAL22[R] B,H,W
0022B0H
00000000 00000000
0022B4H ―
0022B8H ―
0022BCH ―
0022C0H
to
―
―
0022FCH
002300H
002304H
002308H
TREQR12[R] B,H,W
00000000 00000000
―
―
―
NEWDT12[R] B,H,W
00000000 00000000
―
―
―
INTPND12[R] B,H,W
00000000 00000000
―
―
―
MSGVAL12[R] B,H,W
00000000 00000000
―
―
―
―
DFCTLR[R/W]B,H,W
-0------ --------
―
―
FLIFCTLR
[R/W] B,H,W
---0--00
―
FLIFFER1
[R/W] B,H,W
--------
―
―
CAN2
(32msg)
―
Reserved
DFSTR
[R/W] B,H,W
-----001
―
FLIFFER2
[R/W] B,H,W
--------
WorkFlash
00230CH
to
―
―
―
―
0023FCH
SEEARX[R] B,H,W
DEEARX[R] B,H,W
002400H
00000000 00000000
00000000 00000000
EECSRX
EFEARX[R/W] B,H,W
002404H [R/W] B,H,W
―
00000000 00000000
----0000
EFECRX[R/W] B,H,W
002408H ―
-------0 00000000 00000000
00240CH
to
―
―
―
―
0024FCH
Document Number: 002-04727 Rev. *B
Block
+3
Reserved
XBS RAM
ECC control register
Reserved
Page 104 of 174
MB91590 Series
Address
002500H
002504H
002508H
Address Offset Value / Register Name
+0
+1
+2
SEEARH[R] B,H,W
DEEARH[R] B,H,W
--000000 00000000
--000000 00000000
EECSRH[R/W]
EFEARH[R/W]B,H,W
B,H,W
―
--000000 00000000
----0000
EFECRH[R/W]B,H,W
―
-------0 00000000 00000000
00250CH
to
―
―
―
―
002FFCH
SEEARA[R] B,H,W
DEEARA[R] B,H,W
003000H
-----000 00000000
-----000 00000000
EECSRA
EFEARA[R/W] B,H,W
003004H [R/W] B,H,W
―
-----000 00000000
----0000
EFECRA[R/W] B,H,W
003008H ―
-------0 00000000 00000000
00300CH
to
―
―
―
―
003FFCH
004000H
to
Backup RAM
005FFCH
006000H
to
―
―
―
―
00EFFCH
00F000H
to
―
―
―
―
00FEFCH
DSUCR [R/W] B,H,W
00FF00H
―
―
-------- -------0
00FF04H
to
―
―
―
―
00FF0CH
PCSR [R/W] B,H,W
00FF10H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PSSR [R/W] B,H,W
00FF14H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF18H
to
―
―
―
―
00FFF4H
EDIR1 [R] B,H,W
00FFF8H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EDIR0 [R] B,H,W
00FFFCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Block
+3
AHB RAM ECC control
register
MB91F59A/B only
Reserved
Backup RAM
ECC control register
Reserved
Backup RAM area
Reserved
Reserved [S]
OCDU [S]
Reserved [S]
OCDU [S]
Reserved [S]
OCDU [S]
[S]:It is a system register. The illegal instruction exception (data access error) is generated in these registers in the user mode when
reading and writing to it.
Document Number: 002-04727 Rev. *B
Page 105 of 174
MB91590 Series
10. Interrupt Vector Table
This list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers.
 Interrupt vector
Interrupt Factor
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Exception of instruction access protection
violation
Exception of data access protection violation
Data access error interrupt
INTE instruction
Instruction break
System Reserved
System Reserved
System Reserved
Exception of invalid instruction
NMI request/
XBS RAM double-bit error generation/
**
AHB RAM double-bit error generation /
Backup RAM double-bit error generation
External interrupt 0-7
External interrupt 8-15
Reload timer 0/1/7**/8**
Reload timer 2/3/9**/10**
Multi-function serial interface ch.0
(reception completed)/
Multi-function serial interface ch.0(status)
Multi-function serial interface ch.0
(transmission completed)
Multi-function serial interface ch.1
(reception completed)/
Multi-function serial interface ch.1(status)
Multi-function serial interface ch.1
(transmission completed)
LIN-UART2(reception completed)
LIN-UART2(transmission completed)
LIN-UART3(reception completed)
LIN-UART3(transmission completed)
LIN-UART4(reception completed)
LIN-UART4(transmission completed)
LIN-UART5(reception completed)
LIN-UART5(transmission completed)
LIN-UART6(reception completed)
LIN-UART6(transmission completed)
CAN0
CAN1
CAN2/UDC0**/1**
Real time clock
Document Number: 002-04727 Rev. *B
Interrupt
Number
HexaDecimal Decimal
0
00
1
01
2
02
3
03
4
04
5
05
Interrupt
Level
Default
Offset Address for RN*1
TBR
-
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
-
6
06
-
3E4H
000FFFE4H
-
7
8
9
10
11
12
13
14
07
08
09
0A
0B
0C
0D
0E
-
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
-
15
0F
15 (FH)
Fixed
3C0H
000FFFC0H
-
16
17
18
19
10
11
12
13
ICR00
ICR01
ICR02
ICR03
3BCH
3B8H
3B4H
3B0H
000FFFBCH
000FFFB8H
000FFFB4H
000FFFB0H
0
1
2
3
20
14
ICR04
3ACH
000FFFACH 4*2
21
15
ICR05
3A8H
000FFFA8H
5
22
16
ICR06
3A4H
000FFFA4H
6*2
23
17
ICR07
3A0H
000FFFA0H
7
24
25
26
27
28
29
30
31
32
33
34
35
36
37
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
ICR19
ICR20
ICR21
39CH
398H
394H
390H
38CH
388H
384H
380H
37CH
378H
374H
370H
36CH
368H
000FFF9CH
000FFF98H
000FFF94H
000FFF90H
000FFF8CH
000FFF88H
000FFF84H
000FFF80H
000FFF7CH
000FFF78H
000FFF74H
000FFF70H
000FFF6CH
000FFF68H
8
9
10
11
12
13
14
15
16
17
Page 106 of 174
MB91590 Series
Interrupt Factor
Sound generator 0 / LIN-UART7
(reception completed)
Sound generator 1 / LIN-UART7
(transmission completed)
PPG0/1/10/11/20/21
PPG2/3/12/13/22/23
PPG4/5/14/15/UDC2**
PPG6/7/16/17/Multi-function serial interface
ch.10 (reception completed)**/
Multi-function serial interface ch.10(status)**
PPG8/9/18/19/ Multi-function serial interface
ch.10 (transmission completed)**
GDC/GDC_ALM/GDC_LVD/Multi-function
serial interface ch.8 (reception completed)**/
Multi-function serial interface ch.8(status)**
Main timer/Sub timer/PLL timer/ Multi-function
serial interface ch.8 (transmission completed)**
Clock calibration unit (Sub oscillation) /
Sound generator 4/Multi-function serial
**
interface ch.9 (reception completed) /
Multi-function serial interface ch.9(status)**
A/D converter
Clock calibration Unit (CR oscillation) /
Multi-function serial interface ch.9 (transmission
completed)**
Free-run timer 0/2/4**/6**
Free-run timer 1/3/5**/7**
ICU0/6(fetching)
ICU1/7(fetching)
ICU2/8** (fetching)
ICU3/9** (fetching)
ICU4/10** (fetching)
ICU5/11** (fetching)
OCU0/1(match)
OCU2/3(match)
Base timer 0 IRQ0 /
Base timer 0 IRQ1 /
Sound generator 2/Multi-function serial
interface ch.11 (reception completed)**/
Multi-function serial interface ch.11(status)**
Base timer 1 IRQ0 /
Base timer 1 IRQ1/
Sound generator3 /
XBS RAM single bit error generation /
AHB RAM single bit error generation**/ Backup
RAM single bit error generation/
Multi-function serial interface ch.11
(transmission completed)**
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
Delay interrupt
System Reserved (Used for REALOSTM*5.)
System Reserved (Used for REALOS.)
Used with the INT instruction.
Document Number: 002-04727 Rev. *B
Interrupt
Number
HexaDecimal Decimal
Interrupt
Level
Default
Offset Address for RN*1
TBR
38
26
ICR22
364H
000FFF64H
22
39
27
ICR23
360H
000FFF60H
23
40
41
42
28
29
2A
ICR24
ICR25
ICR26
35CH
358H
354H
000FFF5CH
000FFF58H
000FFF54H
24
25
26*6
43
2B
ICR27
350H
000FFF50H
27
44
2C
ICR28
34CH
000FFF4CH
28
45
2D
ICR29
348H
000FFF48H
29*7
46
2E
ICR30
344H
000FFF44H
30
47
2F
ICR31
340H
000FFF40H
31*3
48
30
ICR32
33CH
000FFF3CH
32
49
31
ICR33
338H
000FFF38H
33*3
50
51
52
53
54
55
56
57
58
59
32
33
34
35
36
37
38
39
3A
3B
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
334H
330H
32CH
328H
324H
320H
31CH
318H
314H
310H
000FFF34H
000FFF30H
000FFF2CH
000FFF28H
000FFF24H
000FFF20H
000FFF1CH
000FFF18H
000FFF14H
000FFF10H
36
37
38
39
40
41
42
43
60
3C
ICR44
30CH
000FFF0CH
44
61
3D
ICR45
308H
000FFF08H
45*4
62
63
64
65
66
|
255
3E
3F
40
41
42
|
FF
ICR46
ICR47
-
304H
300H
2FCH
2F8H
2F4H
|
000H
000FFF04H
000FFF00H
000FFEFCH
000FFEF8H
000FFEF4H
|
000FFC00H
-
-
-
Page 107 of 174
MB91590 Series
*1
: Does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no RN (Resource Number)
is assigned.
*2
: The status of the multi-function serial interface does not support a DMA transfer caused by I2C reception.
*3
: The clock calibration unit does not support a DMA transfer caused by an interrupt.
*4
: RAM ECC bit error does not support a DMA transfer caused by an interrupt.
*5
: REALOS is a trademark of Cypress
*6
: An interrupt of Up/down counter ch.2 does not support a DMA transfer.
*7
: An interrupt related GDC does not support a DMA transfer.
**
: Only supported by MB91F59A/B
UDCn: Up/down counter ch.n
ICUn: Input capture unit.n
OCUn: Output compare unit.n
Document Number: 002-04727 Rev. *B
Page 108 of 174
MB91590 Series
11. Electrical Characteristics
11.1 Absolute Maximum Ratings
Parameter
Power supply voltage*1,*2
Analog power supply voltage*1,*2
Analog reference voltage*1
Input voltage*1
Analog pin input voltage*1
*1
Output voltage
Maximum clamp current
Total maximum clamp current
"L" level maximum output current *3
"L" level average output current *4
"L" level total output current *5
"H" level maximum output current *3
"H" level average output current *4
"H" level total output current *5
Symbol
Rating
Unit
VCC5
VCC3
DVCC
AVCC5
AVCC3
AVRH5
AVR3
Min
Vss-0.3
Vss-0.3
Vss-0.3
Vss-0.3
Vss-0.3
Vss-0.3
Vss-0.3
Max
Vss+6.0
Vss+4.0
Vss+6.0
Vss+6.0
Vss+4.0
Vss+6.0
Vss+4.0
V
V
V
V
V
V
V
VI1
Vss-0.3
Vcc5+0.3
V
VI2
VI3
VIA5
VIA3
Vss-0.3
Vss-0.3
Vss-0.3
Vss-0.3
Vcc3+0.3
Vcc5+0.3
Vcc5+0.3
Vcc3+0.3
V
V
V
V
VO1
Vss-0.3
Vcc5+0.3
V
VO2
VO3
ICLAMP
Σ|ICLAMP |
IOL1
IOL2
IOL3
IOLAV1
IOLAV2
IOLAV3
ΣIOL1
ΣIOL2
ΣIOL3
IOH1
IOH2
IOH3
IOHAV1
IOHAV2
IOHAV3
ΣIOH1
ΣIOH2
ΣIOH3
Vss-0.3
Vss-0.3
-4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Vcc3+0.3
Vcc5+0.3
4
20
7
40
30
2
30
20
50
250
50
-7
-40
-30
-2
-30
-20
-50
-250
-50
1250
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
–
2500
mW
-40
-55
+105
+150
°C
°C
Power consumption
PD
Operating temperature
Storage temperature
TA
Tstg
Remarks
Vcc3 ≤ Vcc5
DVcc ≤ Vcc5
AVRH5 ≤ AVcc5 ≤ Vcc5
AVR3 ≤ AVcc3 ≤ Vcc3
AVRH5 ≤ AVcc5
AVR3 ≤ AVcc3
5V pins other than SMC
multiplied pins
3.3V dedicated pin
SMC shared pin
5V pins other than SMC
multiplied pins
3.3V dedicated pin
SMC shared pin
*9
*9
When setting to 2mA*6
When setting to 30mA*7
When setting to 20mA*8
When setting to 2mA*6
When setting to 30mA*7
When setting to 20mA*8
*6
*7
*8
When setting to 2mA*6
When setting to 30mA*7
When setting to 20mA*8
When setting to 2mA*6
When setting to 30mA*7
When setting to 20mA*8
*6
*7
*8
LQFP product
BGA product
TEQFP product
HQFP product
*10
*1
: These parameters are based on the condition that VSS=AVSS=DVSS=0.0V
*2
: Caution must be taken that AVCC5 and DVCC do not exceed VCC5.Similarly,AVCC3 must not exceed VCC3.
*3
: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*4
: The average output current is defined as the value of the average current flowing through any one of the corresponding pins for a
10 ms period. The average value is the operation current × the operation ratio.
*5
: The total output current is defined as the maximum current value flowing through all of corresponding pins.
*6
: Outputs other than P60-P87 and 3V pin.
Document Number: 002-04727 Rev. *B
Page 109 of 174
MB91590 Series
*7
: Output of P60-P87 pins.
*8
: Output of 3V pin.
*9
: Corresponding pins: all general-purpose ports except P90/ADTG.(Except for the dedicated analog port)
•
•
•
•
•
•
•
•
Use within recommended operating conditions.
Use at DC voltage (current).
The + B signal should always be applied by connecting a limiting resistor between the + B signal and the microcontroller.
The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values
at any time regardless of instantaneously or constantly when the + B signal is input.
Note that when the microcontroller drive current is low, such as in the low power consumption modes, the + B input potential
can increase the potential at the VCC pin via a protective diode, possibly affecting other devices.
Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied through the pin,
the microcontroller may operate incompletely.
Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function
in the power supply voltage.
Do not leave + B input pins open.
Sample recommended Circuit
MB91590 series
Protective diode
Limiting resistor current
+B input (12 to 16V)
*10
: To use this product at TA=105°C, equip this on a multilayer board with four or more layers.
WARNING
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Document Number: 002-04727 Rev. *B
Page 110 of 174
MB91590 Series
11.2 Recommended Operating Conditions
(VSS=DVSS=AVSS=0.0V)
Parameter
VCC5
DVCC
AVCC5
VCC3
AVCC3
VCC5
DVCC
AVCC5
VCC3
AVCC3
Power supply voltage
Smoothing capacitor
Value
Symbol
*
Operating temperature
Min
4.5
4.5
4.5
3.0
3.0
3.5
3.5
3.5
2.7
2.7
Max
5.5
5.5
5.5
3.6
3.6
5.5
5.5
5.5
3.6
3.6
Unit
V
V
V
V
V
V
V
V
V
V
CS
4.7
(tolerance within ±50%)
µF
TA
-40
°C
+105
Remarks
Recommended operation guarantee
range
Operation guarantee range
Use a ceramic capacitor or a capacitor
that has the similar frequency
characteristics. Use a capacitor with a
capacitance greater than CS as the
smoothing capacitor on the VCC pin.
*:See the following diagram for details on the connection of smoothing capacitor CS.
• C Pin Connection Diagram
C_3
C_1
CS
VSS
C_2
DVSS
AVSS
CS
CS
WARNING
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the
device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than
these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any
use, operating conditions or combinations not represented on this data sheet. If you are considering application under any
conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-04727 Rev. *B
Page 111 of 174
MB91590 Series
11.3 DC Characteristics
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VCC3=3.3V ± 10%, VSS=DVSS=AVSS=0.0V)
Parameter
Symbol
VIH1
VIH2
VIH3
VIH4
Pin Name
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P137
VIH5
RSTX, NMIX,
MD2
VIH7
MD0,MD1
VIH8
DEBUGIF
"H" level input
voltage
VIH10
VIH11
P000 to P007,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
P050 to P057,
PA2 to PA7,
PB2 to PB7,
PC2 to PC7,
PD2 to PD7,
PE2 to PE7,
PF2 to PF7,
PG0 to PG7,
PH3
Conditions
Min
CMOS input
0.7×
level is selected VCC5
CMOS
0.7×
hysteresis input
V 5
level is selected CC
Automotive input 0.8×
level is selected VCC5
TTL input level is
2.0
selected
0.7×
–
VCC5
0.7×
–
VCC5
–
CMOS
0.7×
hysteresis input
V 3
level is selected CC
–
–
–
–
–
–
–
–
Max
VCC5+
0.3
VCC5+
0.3
VCC5+
0.3
VCC5+
0.3
VCC5+
0.3
VCC5+
0.3
VCC5+
0.3
VCC3+
0.3
Unit
Remarks
V
V
V
V
V
V
V
V
3.3V dedicated pin
TTL input level is
2.0
selected
VIH12
MD3
-
VIH13
TDI, TMS,
TRST, TCK
-
Document Number: 002-04727 Rev. *B
2.0
Value
Typ
0.8×
VCC5
0.7×
VCC5
–
-
VCC3+
0.3
VCC5+
0.3
VCC5+
0.3
V
V
BGA product only
V
BGA product only
Page 112 of 174
MB91590 Series
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VCC3=3.3V ± 10%, VSS=DVSS=AVSS=0.0V)
Parameter
Symbol
VOH1
VOH2
VOH3
Pin Name
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P137
VOH7
VOH8
TDO
VOH5
VOH6
Document Number: 002-04727 Rev. *B
Min
Value
Typ
Max
Unit
Remarks
VCC5 = 4.5V
IOH = -1.0mA
VCC50.5
–
VCC5
V
VCC5 = 4.5V
IOH = -2.0mA
VCC50.5
–
VCC5
V
DVCC0.5
–
DVCC
V
SMC shared pin
VCC30.5
–
VCC3
V
3.3V dedicated pin
VCC50.5
–
VCC5
V
BGA product only
P060 to P067,
DVCC = 4.5V
P070 to P077,
IOH = -30.0mA
P080 to P087
P000 to P007,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
P050 to P057,
PA2 to PA7,
PB2 to PB7,
PC2 to PC7,
PD2 to PD7,
PE2 to PE7,
PF2 to PF7,
PG0 to PG7,
PH3
"H" level output VOH4
voltage
Conditions
VCC3 = 3.0V
IOH = -2.0mA
VCC3 = 3.0V
IOH = -5.0mA
VCC3 = 3.0V
IOH = -10.0mA
VCC3 = 3.0V
IOH = -20.0mA
VCC5 = 4.5V
IOH = -5.0mA
Page 113 of 174
MB91590 Series
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VCC3=3.3V ± 10%, VSS=DVSS=AVSS=0.0V)
Parameter
Symbol
Conditions
Min
Value
Typ
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P137
CMOS input
level is selected
CMOS
hysteresis Input
level is selected
Automotive input
level is selected
TTL input level is
selected
VIL5
RSTX, NMIX,
MD2
–
Vss-0.3 –
VIL7
MD0, MD1
–
Vss-0.3 –
VIL8
DEBUGIF
–
Vss-0.3 –
VIL1
VIL2
VIL3
VIL4
"L" level input
voltage
Pin Name
VIL10
VIL11
P000 to P007,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
P050 to P057,
PA2 to PA7,
PB2 to PB7,
PC2 to PC7,
PD2 to PD7,
PE2 to PE7,
PF2 to PF7,
PG0 to PG7,
PH3
Unit
0.3×
VCC5
V
Vss-0.3 –
0.5×
VCC5
V
Vss-0.3 –
0.8
V
0.3×
VCC5
0.3×
VCC5
0.8
0.3×
VCC3
Remarks
V
Vss-0.3 –
CMOS
hysteresis input Vss-0.3 –
level is selected
V
V
V
V
3.3V dedicated pin
TTL input level is Vssselected
0.3
VIL12
MD3
-
VIL13
TDI, TMS,
TRST, TCK
-
Document Number: 002-04727 Rev. *B
Vss-0.3 –
Max
0.3×
VCC5
VSS0.3
VSS0.3
–
-
0.8
0.3×
VCC5
0.3×
VCC5
V
V
BGA product only
V
BGA product only
Page 114 of 174
MB91590 Series
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VCC3=3.3V ± 10%, VSS=DVSS=AVSS=0.0V)
Parameter
Symbol
VOL1
VOL2
VOL3
VOL4
"L" level output VOL5
voltage
Pin Name
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P137
P060 to P067,
P070 to P077,
P080 to P087
P127,
P130,
P132,
P133
DEBUGIF
VOL9
P000 to P007,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
P050 to P057,
PA2 to PA7,
PB2 to PB7,
PC2 to PC7,
PD2 to PD7,
PE2 to PE7,
PF2 to PF7,
PG0 to PG7,
PH3
VOL10
TDO
VOL6
VOL7
VOL8
Document Number: 002-04727 Rev. *B
Conditions
Min
Value
Typ
Max
Unit
Remarks
VCC5 = 4.5V
IOL = 1.0mA
0
–
0.4
V
VCC5 = 4.5V
IOL = 2.0mA
0
–
0.4
V
DVCC = 4.5V
IOL = 30.0mA
0
–
0.55
V
SMC shared pin
VCC5 = 4.5V
IOL = 3.0mA
0
–
0.4
V
I C shared pin
2
(I C is selected)
VCC5 = 2.7V
IOL = 25.0mA
0
–
0.25
V
0
–
0.4
V
3.3V dedicated pin
0
–
0.4
V
BGA product only
2
VCC3 = 3.0V
IOL = 2.0mA
VCC3 = 3.0V
IOL = 5.0mA
VCC3 = 3.0V
IOL = 10.0mA
VCC3 = 3.0V
IOL = 20.0mA
VCC5 = 4.5V
IOH = 5.0mA
Page 115 of 174
MB91590 Series
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VCC3=3.3V ± 10%, VSS=DVSS=AVSS=0.0V)
Parameter
Input leak
current
Pull-up
resistance
Pull-down
resistance
Symbol
Pin Name
IIL
All input pins
RUP1
RSTX, NMIX
RUP2
All 5V port
input pins
RUP3
All 3V port
input pins
RDOWN1
MD2
RDOWN2
All 5V port
input pins
RDOWN3
All 3V port
input pins
CIN1
Input
capacitance
CIN2
Conditions
VCC=DVCC=
AVCC=5.5V
VSS<VI<VCC
–
Pull-up
resistance is
selected
Pull-up
resistance is
selected
–
Pull-down
resistance is
selected
Pull-down
resistance is
selected
Other than
VCC3,
VCC5, VSS,
DVCC, DVSS,
AVCC3,AVSS3,
–
AVCC5,AVSS5,
C1,C2,C3,
P060 to P067,
P070 to P077,
P080 to P087
P060 to P067,
When using
P070 to P077,
SMC
P080 to P087
Document Number: 002-04727 Rev. *B
Min
Value
Typ
Max
Unit
-5
–
+5
µA
25
–
100
kΩ
25
–
100
kΩ
17
–
66
kΩ
25
–
100
kΩ
25
–
100
kΩ
17
–
66
kΩ
–
5
15
pF
–
15
45
pF
Remarks
Page 116 of 174
MB91590 Series
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VCC3=3.3V ± 10%, VSS=DVSS=AVSS=0.0V)
Parameter
Symbol
Pin Name
ICC5
ICCS5
VCC5
ICCBS5
Power supply
current
ICCT5
ICCH5
ICCHS5
IA3
–
–
80
155
mA
*5
–
60
100
mA
*4
–
60
130
mA
*5
–
95
135
mA
*3, *4
–
95
165
mA
*3, *5
–
95
135
mA
*3, *4
–
95
165
mA
*3, *5
–
25
65
mA
*4
–
25
80
mA
*5
–
15
55
mA
*4
–
15
70
mA
*5
At RTC mode,
4 MHz source
oscillation
–
650
1800
µA
–
800
1950
µA
–
130
230
µA
–
280
380
µA
–
250
1400
µA
When using external
clock*1, TA=+25°C
When using crystal
TA=+25°C
When using external
clock*1, TA=+25°C
When using crystal
TA=+25°C
TA=+25°C
–
100
200
µA
TA=+25°C
100
200
mA
*4
200
300
mA
*5
–
2
2
100
155
mA
mA
*4
*5
–
70
200
µA
–
30
60
mA
At AVR3=AVss3
–
5
10
mA
At AVR3=AVss3
When RTC
mode shutdown,
4 MHz source
oscillation
At stop mode
When stop mode
shutdown
ICCTS5
ICC3
At normal
operation
FCP=128MHz,
Fcpp=32MHz
At normal
operation
FCP=80MHz,
Fcpp=40MHz
At FLASH write
FCP=128MHz,
Fcpp=32MHz
At FLASH erase
FCP=128MHz,
Fcpp=32MHz
At sleep mode
FCP=128MHz,
Fcpp=32MHz
At bus sleep
mode
FCP=128MHz,
Fcpp=32MHz
Value
Typ Max
80
120
Conditions
VCC3
AVCC3
Document Number: 002-04727 Rev. *B
Min
When GDC
–
normal operation
FgdC=81MHz,
FgdC-IF=108MHz –
When GDC
operation stop
When GDC side
regulator stop
When NTSC
operates
When NTSC
stop
Unit
Remarks
mA
*4
Page 117 of 174
MB91590 Series
Parameter
Symbol
High current
output drive
capacity
ΔVOH3
Phase-to-phase
deviation1
High current
output drive
capacity
ΔVOL3
Phase-to-phase
deviation2
Pin Name
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
n=0 to 5
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
n=0 to 5
Conditions
Min
Value
Typ
Max
Unit
Remarks
DVcc=4.5V
IOH=-30.0mA
–
Maximum
deviation of VOH3
–
90
mV
*2
DVcc=4.5V
IOL=30.0mA
–
Maximum
deviation of VOL3
–
90
mV
*2
*1
: The power supply current value when the external clock is supplied from the X1 pin. Note that the power supply current value
when using the external clock is different from that using the oscillator.
*2
: If PWM1P0/PWM1M0/PWM2P0/PWM2M0 of ch.0 is turned on simultaneously, the maximum deviation of VOH3 / VOL3 for each pin
is defined. Same for other channels.
*3
: This product contains both program Flash and WorkFlash. This parameter is defined when only one of them is in the write/erase
state.
*4
: MB91F591/2/4/6/7/9
*5
: MB91F59A/B
Document Number: 002-04727 Rev. *B
Page 118 of 174
MB91590 Series
11.4 AC Characteristics
11.4.1
Main Clock Timing
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=DVSS=AVSS=0.0V)
Symbol
Pin
Name
FC
X0, X1
Parameter
Source oscillation
clock frequency
Source oscillation
clock cycle time
Internal operating
clock frequency*1, *2
Internal operating
clock cycle time*1, *2
CAN PLL jitter
(when lock)
Built-in CR oscillation
frequency
Conditions
Min
Value
Typ
Unit
Max
–
4
–
MHz
–
250
–
ns
Remarks
–
tCYL
X0, X1
FCP
FCPP
tCP
tCPP
–
–
–
–
–
–
–
–
2
2
7.8125
25
–
–
–
–
128
40
500
500
MHz
MHz
ns
ns
tPJ
–
–
-10
–
+10
ns
FCCR
–
–
50
100
200
kHz
*1
: The maximum frequency of CPU clock is described in the table of Product Type.
*2
: The maximum / minimum value is defined when using the main clock and PLL clock.
CPU clock
Peripheral bus clock
CPU clock
Peripheral bus clock
• X0,X1 Clock Timing
tCYL
X0
• CAN PLL jitter
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
PLL output
tn-1
t3
t2
t1
tn
Ideal clock
Slow
Deviation time
t1
t2
t3
tn-1
tn
Fast
Document Number: 002-04727 Rev. *B
Page 119 of 174
MB91590 Series
11.4.1.1
Sub clock timing (products without s-suffix)
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=DVSS=AVSS=0.0V)
Parameter
Symbol
Source oscillation clock
FCL
frequency
Source oscillation clock
tLCYL
cycle time
Pin Name
Conditions
Min
Value
Typ
Max
Unit
X0A, X1A
–
–
32.768
–
kHz
X0A, X1A
–
–
30.52
–
µs
Remarks
• X0A,X1A Clock Timing
tLCYL
X0A
Document Number: 002-04727 Rev. *B
Page 120 of 174
MB91590 Series
Guaranteed Operation Range (5V Operating microcontroller Section)
Internal operation clock frequency vs. Power supply voltage
Recommended guaranteed
operation range
Guaranteed
operation range
Power supply voltage VCC5 (V)
5.5
4.5
3.5
PLL guaranteed operation
range
2
4
128
Internal operation clock frequency FCP (MHz)
Note: The CPU will be reset at the power supply voltage 4V±0.3V or less.
Oscillation Clock Frequency vs. Internal Operation Clock Frequency
Main
Clock
Oscillation
4MHz
clock frequency
2MHz
Internal Operation Clock Frequency
PLL Clock
Multiplie Multiplie Multiplie Multiplie
...
d by 1
d by 2
d by 3
d by 4
Multiplie Multiplie
d by 20 d by 32
4MHz
80MHz
8MHz
12MHz
16MHz
...
128MHz
• Example of Oscillation Circuit
X0
X1
R=0Ω
4MHz
C1=10pF
C2=10pF
Note: As to the product with its clock supervisor’s initial value is "ON", when the oscillator is unable to start within
20ms from the stop state the clock supervisor will detect the oscillation stop. As a result, the CPU moves to
the fail safe operation.
Design your printed circuit board so that the oscillator can start oscillation within 20ms.
Document Number: 002-04727 Rev. *B
Page 121 of 174
MB91590 Series
AC characteristics are specified by the following measurement reference voltage values.
• Input Signal Waveform
• Output Signal Waveform
Hysteresis Input Pin (Automotive)
Output Pin
0.8Vcc5
2.4V
0.5Vcc5
0.8V
Hysteresis Input Pin (CMOS Normal)
0.7Vcc5
0.3Vcc5
Hysteresis Input Pin (CMOS Hysteresis)
0.7Vcc5
0.3Vcc5
TTL Input Pin
2.0V
0.8V
Document Number: 002-04727 Rev. *B
Page 122 of 174
MB91590 Series
11.4.1.2
Reset Input
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Symbol
Pin
Name
Value
Min
Conditions
Max
10
Reset input time
tRSTL
RSTX
–
Width for reset
input removal
Oscillation time of
oscillator* + 100μs
100μs
1μs
Unit
Remarks
–
µs
When normal
operation
–
ms
At Stop mode
–
µs
At RTC mode
–
µs
*:The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For crystal oscillators, this
time is between several ms and several tens of ms, for ceramic oscillators the time is between several hundred µs and several ms,
and for an external clock, the time is 0 ms.
tRSTL
RSTX
0.2Vcc5
• At Stop Mode
0.2Vcc5
tRSTL
RSTX
0.2 VCC5
X0
0.2 VCC5
90%
of
amplitude
100 μs
Oscillation time
of oscillator
Internal reset
Document Number: 002-04727 Rev. *B
Oscillation stabilization
waiting time
Instruction
execution
Page 123 of 174
MB91590 Series
11.4.1.3
Power-on Conditions
(TA: Recommended operating conditions, VSS=0.0V)
Parameter
Level detection
voltage
Level detection
hysteresis width
Level detection
time
Specification for
voltage slope
detection
Power off time
Symbol
Pin
Name
Conditions
Value
Min Typ Max
Unit
Remarks
–
VCC5
–
2.1
2.3
2.5
V
When turning on
power for
microcontroller
–
VCC5
–
–
–
125
mV
During voltage drop
–
–
–
–
–
30
us
*1
–
VCC5
–
4
mV/µs *2
tOFF
VCC5
–
–
ms
VCC5 = at level
detection release –
level time
–
50
*3
*1
: If the fluctuation of the power supply is faster than the low voltage detection time, there is the possibility to generate or release
after the power supply voltage has exceeded the detection voltage range.
*2
: When setting the power supply fluctuation to this specification or less, it is possible to suppress the voltage slope detection. This
is the specification when the power supply fluctuation is stable.
*3
: This time is to start the voltage slope detection at next power on after power down and internal charge loss.
Document Number: 002-04727 Rev. *B
Page 124 of 174
MB91590 Series
11.4.1.4
Multi-function Serial
UART Timing
 Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=0, SCR: SPI=0
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Serial clock cycle
time
SCK ↓ →
SOT delay time
Valid SIN →
SCK ↑ setup time
SCK ↑ →
Valid SIN hold time
Serial clock
"H"pulse width
Serial clock
"L" pulse width
SCK ↓ →
SOT delay time
Valid SIN →
SCK ↑ setup time
SCK ↑ →
Valid SIN hold time
SCK fall time
SCK rise time
Symbol
Pin Name
tSCYC
SCKx
tSLOVI
SCKx, SOTx
Value
Min
Max
Conditions
Unit
4tCPP
–
ns
-30
+30
ns
34
–
ns
0
–
ns
tCPP+10
–
ns
2tCPP-10
–
ns
–
33
ns
10
–
ns
20
–
ns
–
–
5
5
ns
ns
–
tIVSHI
SCKx, SINx
tSHIXI
tSHSL
SCKx
tSLSH
tSLOVE
SCKx, SOTx
–
tIVSHE
SCKx, SINn
tSHIXE
tF
tR
SCKx
SCKx
Remarks
Internal shift clock
mode:
CL=50pF
(When drive capability
is 2mA or more.)
CL=20pF
(When drive capability
is 1mA)
External shift clock
mode:
CL=50pF
(When drive capability
is 2mA or more.)
CL=20pF
(When drive capability
is 1mA)
Notes:
•
•
•
•
•
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by internal operation clock used and other parameters.
See Hardware Manual for details.
"x" means channel number of 0, 1, 8, 9, 10, and 11 for SCKx, SINx and SOTx.
Document Number: 002-04727 Rev. *B
Page 125 of 174
MB91590 Series
• Internal shift clock mode
tSCYC
2.4V
SCKx
0.8V
0.8V
tSLOVI
2.4V
SOTx
0.8V
tIVSHI
SINx
tSHIXI
VIH
VIH
VIL
VIL
• External shift clock mode
tSLSH
SCKx
tSHSL
VIH
VIH
VIL
tF
SOTx
tSLOVE
Document Number: 002-04727 Rev. *B
VIL
tR
2.4V
0.8V
tIVSHE
SINx
VIH
VIL
tSHIXE
VIH
VIH
VIL
VIL
Page 126 of 174
MB91590 Series
 Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=1, SCR: SPI=0
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Serial clock cycle
time
SCK ↑ →
SOT delay time
Valid SIN →
SCK ↓ setup time
SCK ↓ →
Valid SIN hold time
Serial clock
"H" pulse width
Serial clock "L"pulse
width
SCK ↑ →
SOT delay time
Valid SIN →
SCK ↓ setup time
SCK ↓ →
Valid SIN hold time
SCK fall time
SCK rise time
Symbol
Pin Name
tSCYC
SCKx
tSHOVI
SCKx, SOTx
Value
Min
Max
Conditions
Unit
4tCPP
–
ns
-30
+30
ns
34
–
ns
0
–
ns
tCPP+10
–
ns
2tCPP-10
–
ns
–
33
ns
10
–
ns
20
–
ns
–
–
5
5
ns
ns
–
tIVSLI
SCKx, SINx
tSLIXI
tSHSL
SCKx
tSLSH
tSHOVE
SCKx, SOTx
–
tIVSLE
SCKx, SINx
tSLIXE
tF
tR
SCKx
SCKx
Remarks
Internal shift clock
mode:
CL=50pF
(When drive capability
is 2mA or more.)
CL=20pF
(When drive capability
is 1mA)
External shift clock
mode:
CL=50pF
(When drive capability
is 2mA or more.)
CL=20pF
(When drive capability
is 1mA)
Notes:
•
•
•
•
•
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by internal operation clock used and other parameters.
See Hardware Manual for details.
"x" means channel number of 0, 1, 8, 9, 10, and 11 for SCKx, SINx and SOTx.
Document Number: 002-04727 Rev. *B
Page 127 of 174
MB91590 Series
• Internal Shift Clock Mode
tSCYC
2.4V
2.4V
SCKx
0.8V
tSHOVI
2.4V
SOTx
0.8V
tIVSLI
SINx
tSLIXI
VIH
VIH
VIL
VIL
• External Shift Clock Mode
tSLSH
tSHSL
VIH
VIH
VIL
SCKx
tR
SOTx
VIH
VIL
VIL
tSHOVE
tF
2.4V
0.8V
tIVSLE
SINx
Document Number: 002-04727 Rev. *B
tSLIXE
VIH
VIH
VIL
VIL
Page 128 of 174
MB91590 Series
 Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=0, SCR: SPI=1
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Serial clock cycle
time
SCK ↑ → SOT delay
time
Valid SIN → SCK ↓
setup time
SCK ↓ →
Valid SIN hold time
SOT → SCK ↓
delay time
Serial clock
"H" pulse width
Serial clock
"L" pulse width
SCK ↑ →
SOT delay time
Valid SIN → SCK ↓
setup time
SCK ↓ →
Valid SIN hold time
SCK fall time
SCK rise time
Symbol
Pin Name
tSCYC
SCKx
tSHOVI
SCKx, SOTx
tIVSLI
SCKx, SINx
tSLIXI
tSOVLI
Value
Conditions
Internal shift clock mode
CL=50pF (When drive
capability is 2mA or more.)
CL=20pF (When drive
capability is 1mA)
SCKx, SOTx
tSHSL
Min
Unit
Max
4tCPP
–
ns
-30
+30
ns
34
–
ns
0
–
ns
2tCPP-30
–
ns
tCPP+10
–
ns
2tCPP-10
–
ns
–
33
ns
10
–
ns
20
–
ns
–
–
5
5
ns
ns
SCKx
tSLSH
tSHOVE
SCKx, SOTx
tIVSLE
SCKx, SINx
tSLIXE
tF
tR
SCKx
SCKx
External shift clock mode
CL=50pF (When drive
capability is 2mA or more.)
CL=20pF (When drive
capability is 1mA)
Notes:
•
•
•
•
•
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by internal operation clock used and other parameters.
See Hardware Manual for details.
"x" means channel number of 0, 1, 8, 9, 10, and 11 for SCKx, SINx and SOTx.
Document Number: 002-04727 Rev. *B
Page 129 of 174
MB91590 Series
• Internal Shift Clock Mode
tSCYC
2.4V
SCKx
tSHOVI
0.8V
0.8V
tSOVLI
SOTx
2.4V
2.4V
0.8V
0.8V
tIVSLI
SINx
tSLIXI
VIH
VIH
VIL
VIL
• External Shift Clock Mode
tSLSH
VIH
SCKx
VIH
VIL
VIL
tR
tSHOVE
2.4V
2.4V
0.8V
0.8V
tIVSLE
SINx
VIH
VIL
tF
*
SOTx
tSHSL
tSLIXE
VIH
VIH
VIL
VIL
*: Changes when Writing to TDR Register
Document Number: 002-04727 Rev. *B
Page 130 of 174
MB91590 Series
 Bit setting: SMR: MD2=0, SMR: MD1=1, SMR: MD0=0, SMR: SCINV=1, SCR: SPI=1
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Serial clock cycle
time
SCK ↓ → SOT delay
time
Valid SIN → SCK ↑
setup time
SCK ↑ →
Valid SIN hold time
SOT → SCK ↑ delay
time
Serial clock
"H"pulse width
Serial clock
"L" pulse width
SCK ↓ → SOT delay
time
Valid SIN → SCK ↑
setup time
SCK ↑ →
Valid SIN hold time
SCK fall time
SCK rise time
Symbol
Pin Name
tSCYC
SCKx
tSLOVI
SCKx, SOTx
tIVSHI
SCKx, SINx
tSHIXI
tSOVHI
Value
Conditions
Internal shift clock mode
CL=50pF(When drive
capability is 2mA or more.)
CL=20pF(When drive
capability is 1mA)
SCKx, SOTx
tSHSL
Min
Unit
Max
4tCPP
–
ns
-30
+30
ns
34
–
ns
0
–
ns
2tCPP-30
–
ns
tCPP+10
–
ns
2tCPP-10
–
ns
–
33
ns
10
–
ns
20
–
ns
–
–
5
5
ns
ns
SCKx
tSLSH
tSLOVE
SCKx, SOTx
tIVSHE
SCKx, SINx
tSHIXE
tF
tR
SCKx
SCKx
External shift clock mode
CL=50pF(When drive
capability is 2mA or more.)
CL=20pF(When drive
capability is 1mA)
Notes:
•
•
•
•
•
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by internal operation clock used and other parameters.
See Hardware Manual for details.
"x" means channel number of 0, 1, 8, 9, 10, and 11 for SCKx, SINx and SOTx.
Document Number: 002-04727 Rev. *B
Page 131 of 174
MB91590 Series
• Internal Shift Clock Mode
tSCYC
2.4V
SCKx
2.4V
0.8V
tSOVHI
SOTx
tSLOVI
2.4V
2.4V
0.8V
0.8V
tIVSHI
SINx
tSHIXI
VIH
VIH
VIL
VIL
• External Shift Clock Mode
tSHSL
tSLSH
tR
tF
VIH
SCKx
VIH
VIL
VIL
VIL
tSLOVE
*
SOTx
VIH
2.4V
2.4V
0.8V
0.8V
tIVSHE
SINx
tSHIXE
VIH
VIH
VIL
VIL
*: Changes when Writing to TDR Register
Document Number: 002-04727 Rev. *B
Page 132 of 174
MB91590 Series
External Clock (EXT = 1): Asynchronous Only
(TA: Recommended operating conditions, VCC5=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Serial clock
"H" pulse width
Serial clock
"L" pulse width
SCK fall time
SCK rise time
Symbol
Pin Name
Min
CL=50pF
(When drive capability is
2mA or more.)
CL=20pF
(When drive capability is
1mA)
tSHSL
tSLSH
Value
Conditions
SCKx
tF
tR
Unit
Max
tCPP+10
-
ns
tCPP+10
-
ns
-
5
5
ns
ns
Note: "x" means channel number of 0, 1, 8, 9, 10, and 11 for SCKx, SINx and SOTx.
tR
SCK
Document Number: 002-04727 Rev. *B
VIL
VIH
tF
tSLSH
tSHSL
VIH
VIL
VIL
VIH
Page 133 of 174
MB91590 Series
I2C Timing
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Symbol
SCL clock frequency fSCL
Repeat "start"
condition hold time
SDA ↓ → SCL ↓
tHDSTA
Period of "L" for SCL
tLOW
clock
Period of "H" for SCL
tHIGH
clock
Repeat "start"
condition setup time tSUSTA
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
"Stop" condition setup
time
tSUSTO
SCL ↑ → SDA ↑
Bus-free time
between "stop"
t
condition and "start" BUF
condition
Noise filter
tSP
Pin Name
Conditions
SCK0, SCK1
SOT0, SOT1,
(SDA)
SCK0, SCK1,
(SCL)
SCK0, SCK1,
(SCL)
SCK0, SCK1,
(SCL)
SCK0, SCK1, CL=50pF (When
drive capability is
(SCL)
2mA or more.)
SOT0, SOT1,
CL=20pF (When
(SDA)
drive capability is
SCK0, SCK1,
1mA)
(SCL)
R = (VP/IOL) *1
SOT0, SOT1,
(SDA) SCK0,
SCK1, (SCL)
SOT0, SOT1,
(SDA) SCK0,
SCK1, (SCL)
–
–
–
Standard High-Speed
Mode
Mode
Unit Remarks
Min Max Min Max
0
100 0
400
kHz
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
4.0
–
0.6
–
μs
4.7
–
0.6
–
μs
0
3.45*2 0
0.9
μs
250*3 –
100
–
ns
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
2tCPP*4 –
ns
2tCPP*4 –
*1
: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively.
Vp shows that the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.
*2
: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
*3
: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns".
*4
: tCPP is the peripheral clock cycle time. Adjust the peripheral clock frequency to 8MHz or more when use I2C.
Document Number: 002-04727 Rev. *B
Page 134 of 174
MB91590 Series
SDA
tSUDAT
tSUSTA
tBUF
tLOW
SCL
tHDSTA
Document Number: 002-04727 Rev. *B
tHDDAT
tHIGH
tHDSTA
tSP
tSUSTO
Page 135 of 174
MB91590 Series
11.4.1.5
LIN-UART timing
 Bit setting: ESCR: SCES=0, ECCR: SCDE=0
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Symbol
Serial clock cycle time tSCYC
SCK ↓ →
SOT delay time
tSLOVI
Valid SIN →
SCK ↑ setup time
tIVSHI
SCK ↑ →
Valid SIN hold time
tSHIXI
Serial clock
"L" pulse width
Serial clock
"H" pulse width
SCK ↓ →
SOT delay time
tSLSH
tSHSL
tSLOVE
Valid SIN →
SCK ↑ setup time
tIVSHE
SCK ↑ →
Valid SIN hold time
tSHIXE
SCK fall time
tF
SCK rise time
tR
Pin Name
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SIN2,SIN3,
SIN4,SIN5,
SIN6,SIN7
Min
Max
Unit
5tCPP
–
ns
-50
+50
ns
tCPP+80
–
ns
0
–
ns
3tCPP-tR
–
ns
tCPP+10
–
ns
–
2tCPP+60 ns
–
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SIN2,SIN3,
SIN4,SIN5,
SIN6,SIN7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7
Value
Conditions
–
30
–
ns
tCPP+30
–
ns
–
10
ns
–
40
ns
Remarks
Internal shift clock
mode:
CL=80pF + 1 ∙ TTL
External shift clock
mode:
CL=80pF + 1 ∙ TTL
Notes:
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by internal operation clock used and other parameters.
• See Hardware Manual for details.
Document Number: 002-04727 Rev. *B
Page 136 of 174
MB91590 Series
• Internal Shift Clock Mode
tSCYC
2.4V
SCKx
0.8V
tSLOVI
2.4V
SOTx
0.8V
tIVSHI
SINx
tSHIXI
VIH
VIH
VIL
VIL
• External Shift Clock Mode
tSLSH
tSHSL
VIH
SCKx
VIH
VIL
tF
SOTx
VIH
VIL
VIL
tR
tSLOVE
2.4V
0.8V
tIVSHE
SINx
Document Number: 002-04727 Rev. *B
tSHIXE
VIH
VIH
VIL
VIL
Page 137 of 174
MB91590 Series
 Bit setting: ESCR: SCES=1, ECCR: SCDE=0
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Symbol
Serial clock cycle time tSCYC
SCK ↑ →
SOT delay time
tSHOVI
Valid SIN →
SCK ↓ setup time
tIVSLI
SCK ↓ →
Valid SIN hold time
tSLIXI
Serial clock
"H" pulse width
Serial clock
"L" pulse width
SCK ↑ →
SOT delay time
tSHSL
tSLSH
tSHOVE
Valid SIN →
SCK ↓ setup time
tIVSLE
SCK ↓ →
Valid SIN hold time
tSLIXE
SCK fall time
tF
SCK rise time
tR
Pin Name
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SIN2,SIN3,
SIN4,SIN5,
SIN6,SIN7
Min
Max
Unit
5tCPP
–
ns
-50
+50
ns
tCPP+80
–
ns
0
–
ns
3tCPP-tR
–
ns
tCPP+10
–
ns
–
2tCPP+60 ns
–
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SIN2,SIN3,
SIN4,SIN5,
SIN6,SIN7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7
Value
Conditions
–
30
–
ns
tCPP+30
–
ns
–
10
ns
–
40
ns
Remarks
Internal shift clock
mode:
CL=80pF+1 • TTL
External shift clock
mode:
CL=80pF+1 • TTL
Notes:
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by internal operation clock used and other parameters.
• See Hardware Manual for details.
Document Number: 002-04727 Rev. *B
Page 138 of 174
MB91590 Series
• Internal Shift Clock Mode
tSCYC
2.4V
SCKx
0.8V
tSHOVI
2.4V
SOTx
0.8V
tIVSLI
tSLIXI
VIH
VIH
VIL
SINx
VIL
• External Shift Clock Mode
tS LS H
tS H S L
VIH
VIH
SCKx
SOTx
tS HO V E
tF
2 .4 V
0 .8 V
tIV SLE
S IN x
Document Number: 002-04727 Rev. *B
VIL
VIL
VIL
tR
VIH
tS LIX E
VIH
VIH
VIL
VIL
Page 139 of 174
MB91590 Series
 Bit setting: ESCR: SCES=0, ECCR: SCDE=1
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Symbol
Serial clock cycle time tSCYC
SCK ↑ →
SOT delay time
tSHOVI
Valid SIN →
SCK ↓ setup time
tIVSLI
SCK ↓ →
Valid SIN hold time
tSLIXI
SOT →
SCK ↓ delay time
tSOVLI
Pin Name
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SIN2,SIN3,
SIN4,SIN5,
SIN6,SIN7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
Value
Conditions
–
Min
Unit
Max
5tCPP
–
ns
-50
+50
ns
tCPP+80
–
ns
0
–
ns
3tCPP-70
–
ns
Remarks
Internal shift clock
Mode:
CL=80pF + 1 • TTL
Notes:
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by internal operation clock used and other parameters.
• See Hardware Manual for details.
• Internal Shift Clock Mode
tSCYC
2.4V
SCKx
0.8V
tSHOVI
0.8V
t SOVLI
SOTx
2.4V
2.4V
0.8V
0.8V
t IVSLI
SINx
Document Number: 002-04727 Rev. *B
t SLIXI
VIH
VIH
VIL
VIL
Page 140 of 174
MB91590 Series
 Bit setting: ESCR: SCES=1, ECCR: SCDE=1
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Symbol
Serial clock cycle time tSCYC
SCK ↓ →
SOT delay time
tSLOVI
Valid SIN →
SCK ↑ setup time
tIVSHI
SCK ↑ →
Valid SIN hold time
tSHIXI
SOT →
SCK ↑ delay time
tSOVHI
Pin Name
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SIN2,SIN3,
SIN4,SIN5,
SIN6,SIN7
SCK2,SCK3,
SCK4,SCK5,
SCK6,SCK7,
SOT2,SOT3,
SOT4,SOT5,
SOT6,SOT7
Value
Conditions
–
Min
Unit
Max
5tCPP
–
ns
-50
+50
ns
tCPP+80
–
ns
0
–
ns
3tCPP-70
–
ns
Remarks
Internal shift clock
mode:
CL=80pF+1 • TTL
Notes:
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by internal operation clock used and other parameters.
• See Hardware Manual for details.
• Internal Shift Clock Mode
tSCYC
2.4V
SCKx
2.4V
0.8V
tSOVHI
SOTx
2.4V
2.4V
0.8V
0.8V
tIVSHI
SINx
Document Number: 002-04727 Rev. *B
tSLOVI
VIH
VIL
tSHIXI
VIH
VIL
Page 141 of 174
MB91590 Series
11.4.1.6
Timer input timing
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Symbol
Input pulse width
tTIWH,
tTIWL
Pin Name
Value
Min Max
Conditions
TIN0 to TIN3,
TIN7 to TIN10,
ICU0 to ICU11,
FRCK0 to FRCK7,
TIOA,TIOB,
UDCAIN0 to 2,
UDCBIN0 to 2,
UDCZIN0 to 2
–
4tCPP –
Unit
Remarks
ns
• Timer Input Timing
tTIWH
TINx,
ICUx,
FRCK0,
FRCK1,
TIOA, TIOB
tTIWL
VIH
VIH
VIL
VIL
Note:
The description can be applied to FRCK2 to 7, UDCAIN0 to 2, UDCBIN0 to 2, and UDCZIN0 to 2 as well.
11.4.1.7
Trigger input timing
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Symbol
Input pulse width
tTRGH,
tTRGL
Pin Name
INT0 to INT15,
ADTG, RX0,
RX1, RX2
Value
Conditions
Min
Unit
Max
5tCPP
–
ns
1
–
μs
–
Remarks
At stop mode
• Trigger Input Timing
tTRGL
tTRGH
INTx,
ADTG,
RXx
Document Number: 002-04727 Rev. *B
VIH
VIH
VIL
VIL
Page 142 of 174
MB91590 Series
11.4.1.8
NMI input timing
(TA: Recommended operating conditions, VCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Symbol
Input pulse width
tNMIL
Pin Name
NMIX
Conditions
–
Value
Min
4tCPP
Unit
Max
–
Remarks
ns
• NMIX Input Timing
tNMIL
NMIX
VIH
VIH
VIL
Document Number: 002-04727 Rev. *B
VIL
Page 143 of 174
MB91590 Series
11.4.1.9
Low voltage detection (External low-voltage detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0V)
Parameter
Power supply voltage
range
Detection voltage
Hysteresis width
Low voltage detection
time
Power supply voltage
fluctuation rate
Pin
Symbol Name
VCC5
VCC5
VCC3
VCC3
Conditions
–
–
Value
Unit
Remarks
Min Typ Max
–
–
5.5
V
Microcontroller unit
–
–
3.6
V
GDC unit
When power-supply
voltage falls at
microcontroller unit
3.9
4.1
4.3
V
and detection level is
set initially
When power-supply
voltage falls at GDC
2.2
2.4
2.6
V
unit and detection
level is set initially
When power-supply
–
–
125 mV
voltage rises
VCC5
*1
VCC3
*1
VHYS
VCC5/
VCC3
–
Td
–
–
–
–
30
μs
–
VCC5,
VCC3
–
-2
–
2
V/ms *2
VDL
*1: If the fluctuation of the power supply is faster than the low voltage detection time(Td), there is a possibility to generate or release
after the power supply voltage has exceeded the detection voltage range.
*2: In order to perform the low-voltage detection at the detection voltage (VDL), be sure to suppress fluctuation of the power supply
voltage within the limits of the power supply voltage fluctuation rate.
Document Number: 002-04727 Rev. *B
Page 144 of 174
MB91590 Series
11.4.1.10 Low voltage detection (Internal low-voltage detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0V)
Parameter
Symbol
Power supply voltage
range
VRDP5
Detection voltage
VRDL
Hysteresis width
VRHYS
Low voltage detection
time
Td
Pin
Name
VCC
–
Conditions
Value
Min Typ Max
Unit
–
–
–
1.3
V
*
0.8
0.9
1.0
V
–
–
–
50
mV
–
–
–
30
µs
Remarks
When power-supply
voltage falls
When power-supply
voltage rises
*: If the fluctuation of the power supply is faster than the low voltage detection time(Td), there is a possibility to generate or release
after the power supply voltage has exceeded the detection voltage range.
Document Number: 002-04727 Rev. *B
Page 145 of 174
MB91590 Series
11.4.1.11 High current output slew rate
(TA: Recommended operating conditions, VCC5=AVCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Output rise /fall time
Symbol
tR2,
tF2
Pin Name
P060 to P067,
P070 to P077,
P080 to P087
Conditions
–
Min
15
Value
Typ Max
Unit
–
ns
100
Remarks
load capacitance
85pF
• Slew Rate Output Timing
VH
VH
VL
tR2
Document Number: 002-04727 Rev. *B
VH=VOL2+0.9 (VOH2-VOL2)
VL=VOL2+0.1 (VOH2-VOL2)
+ +
VL
tF2
Page 146 of 174
MB91590 Series
11.4.1.12 External memory interface
Memory Controller
(TA: Recommended operating conditions, VCC3=3.3V ± 10%, VSS=AVSS=0.0V)
Parameter
Symbol
Pin Name
Chip Select delay time
tcso
MEM_XCS0,
MEM_XCS1
Address delay time
tao
MEM_EA[24:0]
Data output delay time
tdo
Data output → HiZ time
tdoz
Conditions
NOR Flash data setup time tdsr
MEM_ED[15:0]
NOR Flash data hold time
NOR Flash page Read
data setup time
NOR Flash page Read
data hold time
tdhr
tdsp
tdhp
XRD delay time
trdo
MEM_XRD
XWR delay time
twro
MEM_XWR
12pF/10mA
Value
Min
Max
–
18
–
14
–
18
–
14
–
18
–
17
–
18
–
17
20
–
11
–
0
–
0
–
20
–
8.5
–
0
–
0
–
–
18
–
14
–
18
–
14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remarks
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
Output delay is reference clock is an internal clock. The reference clock of MEM_RDY is an internal clock.
*1: MB91F591/2/4/6/7/9
*2: MB91F59A/B
Document Number: 002-04727 Rev. *B
Page 147 of 174
MB91590 Series
 NOR Flash read timing
Internal CLK
t cso
t cso
t ao
t ao
MEM_XCS0
MEM_XCS1
MEM_EA[24:0]
MEM_RDY
t rdo
t rdo
MEM_XRD
t dsr
t dhr
MEM_ED[15:0]
Document Number: 002-04727 Rev. *B
Page 148 of 174
MB91590 Series
 NOR Flash write timing
Internal CLK
t cso
t cso
t ao
t ao
MEM_XCS0
MEM_XCS1
MEM_EA[24:0]
MEM_RDY
twro
t wro
MEM_XWR
t do
t do
MEM_ED[15:0]
tdo
X
 NOR Flash Page read timing
Internal CLK
t cso
t cso
MEM_XCS0
MEM_XCS1
t ao
t ao
t ao
MEM_EA[24:0]
MEM_RDY
t rdo
MEM_XRD
t dsp
t dhp
t dsp
t dhp
MEM_ED[15:0]
Document Number: 002-04727 Rev. *B
Page 149 of 174
MB91590 Series
HS-SPI
(TA: Recommended operating conditions, VCC3=3.3V ± 10%, VSS=AVSS=0.0V)
Parameter
Serial clock cycle
time
Valid CS → CLK
start time
(mode0/mode2)
Valid CS → CLK
start time
(mode1/mode3)
CLK end → Invalid
CS time
(mode0/mode2)
CLK end → Invalid
CS time
(mode1/mode3)
SIO data output
time
SIO setup
SIO hold
Symbol
Pin Name
Value
Conditions
Min
Max
Unit
25
tSCYCM
SPI_CLK
–
ns
1.5×tSCYCM-5
–
ns
tSCYCM-5
–
ns
tSCYCM-3
–
ns
1.5×tSCYCM-3
–
ns
-3
5
ns
7
–
ns
14
–
ns
0.5×tSCYCM
–
ns
50
tOSLSK02
tOSLSK13
tOSKSL02
SPI_CLK,
SPI_CS0,
SPI_CS1,
SPI_CS2,
SPI_CS3
tOSKSL13
tOSDAT
tDSSET
SPI_CLK,
SPI_SIO0,
SPI_SIO1,
SPI_SIO2,
SPI_SIO3
tSDHOLD
Document Number: 002-04727 Rev. *B
CL=12pF
(When drive
capability is
10mA)
Remarks
RTM=1,
Mode=0,1,3
Other than
those above
RTM=1 and
Mode=0,1,3
Other than
those above
Page 150 of 174
MB91590 Series
SPI_CS0,
SPI_CS1,
SPI_CS2,
SPI_CS3
t SCYCM
mode0
mode2
t OSLSK02
SPI_CLK
t OSKSL02
mode1
mode3
t OSKSL13
t OSLSK13
SPI_SIO0,
SPI_SIO1,
SPI_SIO2,
SPI_SIO3
input
t SDHOLD
t DSSET
output
t OSDAT
Document Number: 002-04727 Rev. *B
Page 151 of 174
MB91590 Series
11.4.1.13 GDC display signal
Clock
AC timing of video interface clock signal
(TA: Recommended operating conditions, VCC3=3.3V ± 10%, VSS=AVSS=0.0V)
Parameter
DCLKI frequency
DCLKI "H"width
DCLKI "L"width
DCLK frequency
DCLKO frequency
Symbol
Fdclki0
Thdclki0
Tldclki0
Tldclk0
Fdclko0
Value
Pin Name
Min
Unit
Max
–
18
18
DCLK (internal) –
DCLKO
–
54
–
–
54
54
DCLKI
MHz
ns
ns
MHz
MHz
Remarks
*1
*2
*1: The internal display clock of PLL synchronous mode is generated with internal PLL of display clock prescaler.
*2: DCLKI or PLL internal display clock is output.
Apply only DCLKI synchronous mode. (reference clock= DCLKI)
• AC timing of video interface input signal
(TA: Recommended operating conditions, VCC3=3.3V ± 10%, VSS=AVSS=0.0V)
Parameter
HSYNC input setup time
HSYNC input hold time
VSYNC input pulse width
Symbol
Tshsync0
Thhsync0
Twvsync0
Pin Name
HSYNC(i)
VSYNC(i)
Value
Typ
Min
4
1
1
–
–
–
Max
–
–
–
Unit
Remarks
ns
ns
HSYNC
 Display input signal timing
DCLK In
1/Fdclkin
Thdclkin
Tldclkin
Twhsyncn
HSYNCn (i)
Tshsyncn Thhsyncn
Twvsyncn
VSYNCn (i)
Tsvsyncn
Document Number: 002-04727 Rev. *B
Thvsyncn
Page 152 of 174
MB91590 Series
AC Characteristics of Display Output Signal
 Clock Mode
There are multiple clock modes for display output clocks, as shown in Table 1. The AC timing parameters vary depending on modes.
The AC timing parameters are specified for each mode.
Table 1. Clock Mode for Display Output
DCM1
CKS
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Setting Register Bit Field
DCM3
DCKed
DCKD
0
0
0
0
Other than 0
Other than 0
Other than 0
Other than 0
0
0
0
0
Other than 0
Other than 0
Other than 0
Other than 0
Document Number: 002-04727 Rev. *B
Clock Mode Name
DCKinv
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Built-in PLL standard mode
Built-in PLL reverse edge mode
Cannot be used.
Built-in PLL delay mode
Built-in PLL reverse edge and delay mode
Built-in PLL both edge and delay mode
DCLKI input standard mode
DCLKI input reverse edge mode
Cannot be used.
Page 153 of 174
MB91590 Series
 AC Timing Parameters
This section describes parameters used for AC timing specifications. Select whether you use the DCLKO reverse edge mode,
depending on the use/non-use of delay mode.
When the delay mode is not used:
Use the DCLKO reverse edge mode when the external display device (TFT) receives the signal at the rising edge of DCLKO.
Use the DCLKO standard mode when the external display device (TFT) receives the signal at the falling edge of DCLKO.
When the delay mode is used:
Use the DCLKO standard mode when the external display device (TFT) receives the signal at the rising edge of DCLKO.
Use the DCLKO reverse edge mode when the external display device (TFT) receives the signal at the falling edge of DCLKO.
Note: Clock duty ratio when the clock frequency division ratio is even or odd
AC specifications use the half-cycle of the display output clock DCLKO as a parameter. In AC specifications, the first half-cycle is
indicated as tdcyc_f, and the second half-cycle is indicated as tdcyc_l.
Note that clock duty ratio will not be 50%:50% when the clock frequency division ratio (specified in SC field of DCM1 register) is odd.
If the clock frequency division ratio is odd, the first half-cycle tdcyc_f becomes different from the second half-cycle tdcyc_l.
Figure 2. Clock Duty Ratio when the Clock Frequency Division Ratio is even or Odd
• When the frequency division ratio is even
tdcyc
tdcyc_f
tdcyc_l
tdcyc / 2
tdcyc / 2
DCLKO
(DCKinv=1)
• Example: When the frequency division ratio is odd (frequency division ratio = 3)
tdcyc
tdcyc_f
tdcyc_l
DCLKO
(DCKinv=1)
tdcyc / 3
2×(tdcyc / 3)
When the clock frequency division ratio is 5, tdcyc_f : tdcyc_l will be 2:3.
Document Number: 002-04727 Rev. *B
Page 154 of 174
MB91590 Series
Built-in PLL reverse edge mode (DCM3.DCKinv=1)
Figure 3 shows the setup/hold definition when the external display device receives the signal at the rising edge of DCLKO.
Figure 3. Built-in PLL Reverse Edge Mode Setup/Hold Definition
Use the clock mode of DCM3 register DCKinv=1
tdcyc
tdcyc_f
tdcyc_l
DCLKO
(DCKinv=1)
tdosu
tdohd
Data signal
Data signal:
ROUT7~0, GOUT7~0, BOUT7~0, HSYNC, VSYNC, CSOUT/GV, DEOUT
Built-in PLL standard mode (DCM3.DCKinv=0)
Figure 4 shows the setup/hold definition when the external display device receives the signal at the falling edge of DCLKO.
Figure 4. Built-in PLL Standard Mode Setup/Hold Definition
Use the clock mode of DCM3 register DCKinv=0
tdcyc
tdcyc_l
tdcyc_f
DCLKO
(DCKinv=0)
tdosu
tdohd
Data signal
Data signal:
ROUT7~0, GOUT7~0, BOUT7~0, HSYNC, VSYNC, CSOUT/GV, DEOUT
Document Number: 002-04727 Rev. *B
Page 155 of 174
MB91590 Series
Built-in PLL delay mode (DCM3.DCKinv=0)
Figure 5 shows the setup/hold definition when the external display device receives the signal at the rising edge of DCLKO.
(Example: When frequency division ratio = 4)
Figure 5. Built-in PLL Delay Mode Setup/Hold Definition
tdcyc
tpllcyc
DCLKO
(DCKinv=0)
(delay=0)
tdcyc_l
tdcyc_f
DCLKO
(DCKinv=0)
(delay=3)
ROUT7-0
GOUT7-0
BOUT7-0
HSYNC
VSYNC
DEOUT
CSOUT/GV
Document Number: 002-04727 Rev. *B
tdosu
tdohd
Page 156 of 174
MB91590 Series
Built-in PLL reverse edge and delay mode (DCM3.DCKinv=1)
Figure 6 shows the setup/hold definition when the external display device receives the signal at the falling edge of DCLKO.
(Example: When frequency division ratio = 4)
Figure 6. Built-in PLL Reverse Edge and Delay Mode Setup/Hold Definition
tdcyc
tpllcyc
DCLKO
(DCKinv=1)
(delay=0)
tdcyc_l
tdcyc_f
DCLKO
(DCKinv=1)
(delay=3)
tdosu
ROUT7-0
GOUT7-0
BOUT7-0
HSYNC
VSYNC
DEOUT
CSOUT/GV
tdohd
Built-in PLL both edge and delay mode (DCM3.DCKinv=0)
Figure 7 shows the setup/hold definition when the external display device (TFT) receives the signal both at the rising edge and
the falling edge of DCLKO. (Example: When frequency division ratio = 4) Although there are two sampling locations in both edge
mode; one at the rising edge and the other at the falling edge, the values of setup/hold definition are same.
Figure 7. Built-in PLL Both Edge and Delay Mode Setup/Hold Definition
tdcyc
tpllcyc
DCLKO
(delay=0)
tdcyc_f
tdcyc_l
DCLKO
(delay=3)
ROUT7-0
GOUT7-0
BOUT7-0
HSYNC
VSYNC
DEOUT
CSOUT/GV
Document Number: 002-04727 Rev. *B
tdosu
tdohd
tdosu
tdohd
Page 157 of 174
MB91590 Series
Setup/Hold Definition in Delay Mode
The delay mode is a mode realized with DCLKO delay function, and it can provide delay to DCLKO signal output itself. This can
be used when both the following conditions are satisfied.
• The internal PLL is used to generate DCLKO (CKS field of DCM register = 0)
• The frequency division ratio to the internal PLL of DCLKO is 2 or more (SC field of DCM register > 0)
The delay value is set as the unit for internal PLL clock by DCKD field of DCM3 register. The meanings of DCKD setting value are
shown below.
When the internal PLL
frequency division ratio = 2
DCKD
000000
000100
When the internal PLL frequency
division ratio > 2
Delay
No additional delay
+1 PLL clock
DCKD
000000
000010
000100
000110
:
111110
Delay
No additional delay
+2 PLL clock
+3 PLL clock
+4 PLL clock
:
+17 PLL clock
In delay mode, tdcyc_f and tdcyc_l are defined by the delay value above (e.g. "2" of "+2 PLL clock") as shown below.
tdcyc_f = Delay value × tpllcyc
tdcyc_l = tdcyc – tdcyc_f
Document Number: 002-04727 Rev. *B
Page 158 of 174
MB91590 Series
DCLKI Input Standard Mode (DCM3.DCKinv=0)
Figure 8 shows the setup/hold definition when the external display device (TFT) receives the signal at the falling edge of DCLKO.
Figure 8. DCLKI Input Standard Mode Setup/Hold Definition
Use the clock mode of DCM3 register DCKinv=0
tdcyc
tdcyc_l
tdcyc_f
DCLKO
(DCKinv= 0)
tdohd
tdosu
Data signal
Data signal:
ROUT7~0, GOUT7~0, BOUT7~0, HSYNC, VSYNC, CSOUT/GV, DEOUT
DCLKI Input Reverse Edge Mode (DCM3.DCKinv=1)
Figure 9 shows the setup/hold definition when the external display device (TFT) receives the signal at the rising edge of DCLKO.
Figure 9. DCLKI Input Reverse Edge Mode Setup/Hold Definition
Use the clock mode of DCM3 register DCKinv=1
tdcyc
tdcyc_l
tdcyc_f
DCLKO
(DCKinv=1)
tdosu
tdohd
Data signal
Data signal:
ROUT7~0, GOUT7~0, BOUT7~0, HSYNC, VSYNC, CSOUT/GV, DEOUT
Document Number: 002-04727 Rev. *B
Page 159 of 174
MB91590 Series
 AC Timing Specifications
Parameter
Display clock cycle time
Symbol
tdcyc
min.
18.5 ns
External Load Condition 50 pF
Parameter
Setup time
Hold time
Symbol
tdosu
tdohd
DCLKO Reference Edge
neg, pos
-
*1
IO Drive capability Setting
10 mA
2 mA
tdcyc_f - 8.5ns
tdcyc_f - 10.2ns
tdcyc_l - 1.7ns
tdcyc_l - 3.3ns
tdcyc_l - 3.2ns
tdcyc_l – 5.1ns
Remark
*2
*3
*1: DCLKO reference edge: This is the reference clock edge for setup time and hold time.
Pos = The external display device receives the signal at the rising edge of DCLKO.
Neg = The external display device receives the signal at the falling edge of DCLKO.
*2: Should be applied to RGB666.
*3: Should be applied to RGB888.
Document Number: 002-04727 Rev. *B
Page 160 of 174
MB91590 Series
Video Capture Input
1/Fc i
CCLK
BIN7-2
GIN7-2
RIN7-2
HSIN
VSIN
VIN7-0
Parameter
Symbol
Value
Pin Name
Min
Unit
Capture input frequency
Fci
CCLK
–
Max
81.0
Capture input setup time
Tcisu
3.0
–
ns
Capture input hold time
Tcihd
BIN7-2, GIN7-2,
RIN7-2,
HSIN, VSIN,
VIN7-0
0.0
–
ns
Document Number: 002-04727 Rev. *B
Tc ih d
Tc is u
MHz
Remarks
Page 161 of 174
MB91590 Series
11.4.1.14 GDC ommand trigger signal
Parameter
Input trigger pulse width
Symbol
Ttrg
Pin Name
CMDTRG
Value
Min
160
Unit
Max
–
Remarks
ns
CMDTRG
Ttrg
Document Number: 002-04727 Rev. *B
Page 162 of 174
MB91590 Series
11.5 A/D Converter
11.5.1
Electrical Characteristics
(TA: Recommended operating conditions, VCC5=AVCC5=5.0V ± 10%, VSS=AVSS=0.0V)
Parameter
Resolution
Total error
Non linearity error
Differential linearity
error
–
–
–
–
–
–
–
–
–
Value
Typ
Max
–
10
–
±3
–
±2.5
–
–
–
–
AN0 to
AN31
AN0 to
AN31
–
–
–
AN0 to
AN31
AN0 to
AN31
AVRH5
AVSS
AVSS 1.5LSB
AVRH5 3.5LSB
1.2
1.8
3.0
Symbol
Zero transition voltage VOT
Full-scale transition
voltage
Sampling time
Compare time
A/D conversion time
Analog port input
current
Analog input voltage
Reference voltage
Power supply current
Variation between
channels
VFST
tSMP
tCMP
tCNV
IAIN
VAIN
AVRH
AVRL
IA
IAH
IR
IRH
–
Pin Name
AVCC
AVRH5
AN0 to
AN31
Min
±1.9
–
–
–
AVSS +
2.5LSB
AVRH5 +
0.5LSB
–
–
–
-5
–
AVSS
–
–
Unit
bit
LSB
LSB
LSB
V
V
Remarks
1LSB = (AVCC - AVSS)
/1024
μs
μs
μs
*1
*1
*1
+5
μA
VAVSS ≤ VAIN ≤ VAVCC
–
AVRH5
V
4.5
–
–
–
–
–
–
0.0
–
–
600
–
5.5
–
4.0
6.0
900
5
V
V
mA
μA
μA
μA
–
–
4
LSB
AVRH5 ≤ AVCC5
*2
*2
*1: Time for each channel.
*2: Power supply current (VCC = AVCC = 5.0 V) is specified if A/D converter is not operating and CPU is stopped.
Note:
Be sure to use the clock with a frequency between 8MHz and 17MHz for the ADC compare clock in order to ensure its accuracy.
Document Number: 002-04727 Rev. *B
Page 163 of 174
MB91590 Series
11.5.2
Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Non linearity error
: Deviation of the actual conversion characteristics from a straight line that
connects the zero transition point ("00 0000 0000"← →"00 0000 0001") to the
full-scale transition point ("111111 1110"← →"11 1111 1111").
Differential linearity
error
: Deviation of the input voltage from the ideal value that is required to change the
output code by LSB.
Total error
: Difference between the actual value and the theoretical value. The total error
includes zero transition error, full-scale transition error, and non linearity error.
Total error
3FF
3FE
Actual conversion
characteristics
1.5 LSB
Digital output
3FD
{1 LSB × (N - 1) + 0.5 LSB}
004
VNT
(Actually-measured value)
003
Actual conversion
characteristics
Ideal characteristics
002
001
0.5 LSB
AVSS
AVRH5
Analog input
VNT - {1LSB} × (N - 1) + 0.5LSB}
1LSB
AVRH5 - AVSS
[V]
1024
Total error of digital output N =
1LSB (Ideal value) =
[LSB]
N: A/D converter digital output value.
VOT (Ideal value) = AVSS + 0.5 LSB[V]
VFST (Ideal value) = AVRH5 - 1.5 LSB[V]
VNT: Voltage at which the digital output changes from (N - 1) to N.
Document Number: 002-04727 Rev. *B
Page 164 of 174
MB91590 Series
Non linearity error
Differential linearity error
Ideal
characteristics
3FF
Actual conversion
characteristics
{1 LSB × (N - 1)
+ VOT}
Digital output
3FD
N+1
(actual
measurement
value)
VNT (actual
measurement value)
004
Actual conversion
characteristics
003
Actual conversion
characteristics
VFST
Digital output
3FE
N
V(N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
N-1
002
Ideal characteristics
Actual conversion
characteristics
N-2
001
VOT (actual measurement value)
AVRH5
AVSS
(AVRL)
Analog input
AVSS
(AVRL)
Linearity error of digital output N =
Differential linearity error of digital output N =
AVRH5
Analog input
VNT - {1LSB} × (N - 1) + VOT
1LSB
V(N + 1) T - VNT
[LSB]
- 1 [LSB]
1LSB
1LSB =
VOT
VFST
VFST - VOT
1022
[V]
: Voltage at which the digital output changes from “000H” to “001 H”.
: Voltage at which the digital output changes from “3FE H” to “3FF H”.
Document Number: 002-04727 Rev. *B
Page 165 of 174
MB91590 Series
11.5.3 Notes on Using A/D Converter
<About the output impedance of the analog input of external circuit>
• External impedance values of the external input of 4.2 kΩ or lower (sampling time = 1.2 μs@ machine clock of 16 MHz) are
recommended. When the external impedance is too high, the sampling time for analog voltages may not be sufficient. In this
case, it is recommended to connect the capacitor (approx. 0.1 μF) to the analog input pin.
• Analog Input Circuit model
R
Comparator
Analog input
C
During sampling: ON
MB91590series
R
4.0kΩ (Max)
C
16.1pF (Max)
Note: Listed values must be considered as reference values.
Document Number: 002-04727 Rev. *B
Page 166 of 174
MB91590 Series
11.6 Flash Memory
11.6.1
Electrical Characteristics
Parameter
Value
Typ
Min
Unit
Max
–
200
800
ms
–
300
1100
ms
–
400
2000
ms
–
700
3700
ms
8-bit writing time
–
9
288
µs
16-bit writing time
–
12
384
µs
ECC writing time
–
9
288
µs
Erase cycle*2/
Data retain time
1,000 cycles/
20 years,
10,000 cycles/
–
10 years,
100,000 cycles/
5 years
–
–
Sector erase time
Remarks
8 Kbyte sector*1, excluding
internal preprogramming time
8 Kbyte sector*1, including
internal preprogramming time
64 Kbyte sector*1, excluding
internal preprogramming time
64 Kbyte sector*1, including
internal preprogramming time
Exclusive of overhead time at
system level*1
Exclusive of overhead time at
system level*1
Exclusive of overhead time at
system level*1
Average TA=+85°C*3
*1
: The guaranteed value for erasure up to 100,000 cycles.
*2
: Number of erase cycles for each sector.
*3
: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into
normalized value at + 85°C).
11.6.2 Notes
While the Flash memory is written or erased, shutdown of the external power (Vcc5) is prohibited.
In the application system where Vcc5 might be shut down while writing or erasing, be sure to turn the power off by using an external
voltage detection function.
*
To put it concretely, after the external power supply voltage falls below the detection voltage (VDL ), hold Vcc5 at 2.7V or more within
the duration calculated by the following expression:
*
Td [µs] + (period of PCLK [µs] x 257) + 50 [µs]
*: See " AC Characteristics Low voltage detection (External low-voltage detection) "
Document Number: 002-04727 Rev. *B
Page 167 of 174
MB91590 Series
12. Ordering Information
Package*1
Part Number
MB91F591BPMC-GSE1
MB91F591BSPMC-GSE1
MB91F591BHPMC-GSE1
MB91F591BHSPMC-GSE1
MB91F592BPMC-GSE1
MB91F592BSPMC-GSE1
MB91F592BHPMC-GSE1
208-pin plastic LQFP
(LQR208)
MB91F592BHSPMC-GSE1
MB91F594BPMC-GSE1
MB91F594BSPMC-GSE1
MB91F594BHPMC-GSE1
MB91F594BHSPMC-GSE1
MB91F59BCEQ-GSE1
MB91F59BCHSEQ-GSE1
208-pin plastic TEQFP
(LET208)
MB91F59ACPB-GSE1
MB91F59ACSPB-GSE1
MB91F59ACHPB-GSE1
MB91F59ACHSPB-GSE1
MB91F59BCPB-GSE1
320-Ball Grid Array Package
(BYA320)
MB91F59BCSPB-GSE1
MB91F59BCHPB-GSE1
MB91F59BCHSPB-GSE1
*1
: For details of the package, see "Package Dimensions ".
Document Number: 002-04727 Rev. *B
Page 168 of 174
MB91590 Series
13. Package Dimensions
 Dimension of LQFP-208(LQR208)
4
D
5 7
D1
156
105
105
157
156
157
104
104
E1
E
5
7
4
3
6
208
208
53
53
1
52
52
e
1
2 5 7
3
0.10 C A-B D
0.20 C A-B D
b
C A-B
0.08
D
BOTTOM VIEW
8
TOP VIEW
2
A
θ
9
A
A'
0.08 C
SEATI NG
PLA NE
L1
0.25
L
A1
c
10
b
SECTION A-A'
SIDE VIEW
SYM BOL
DIM ENSIONS
M IN.
NOM . M AX.
0.05
0.15
1.70
A
A1
b
0.17
c
0.09
0.22
0.27
0.20
D
30.00 BSC
D1
28.00 BSC
e
0.50 BSC
E
30.00 BSC
28.00 BSC
E1
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
θ
0°
8°
002-15151 **
PACKAGE OUTLINE, 208 LEAD LQFP
28.0X28.0X1.7 M M LQR208 REV**
Document Number: 002-04727 Rev. *B
Page 169 of 174
MB91590 Series
 Dimension of TEQFP-208(LET208)
D
D1
4
D2
D3
5 7
E3 E2
E1 E
EXPOSED PAD
BOTTOM VIEW
0.10 C A-B D
0.20 C A-B D
TOP VIEW
2
DETAIL A
A
A A2
A'
A1
e
11
SEATING
PLANE
0.08 C
b
0.08
C A-B
10
PLANE
c
R2
b
L
L1
D
8
SIDE VIEW
R1
L2
GAUGE
θ
SECTION A-A'
DETAIL A
DIMENSION
SYMBOL
M IN.
NOM.
A1
0.05
A2
1.35
0.15
1.40
D
30.00 BSC
D1
28.00 BSC
D2
9.90 REF
D3
8.71 REF
E
30.00 BSC
E1
28.00 BSC
E2
9.90 REF
R1
0.08
R2
0.08
0°
c
0.12
b
0.17
L
0.45
L 1
L 2
e
1.45
8.71 REF
E3
θ
MAX.
1.70
A
0.20
4°
8°
0.20
0.22
0.27
0.60
0.75
1.00 REF
0.25
0.50 BSC
002-13651 *A
PACKAGE OUTLINE, 208 LEAD TEQFP
28.0X28.0X1.7 M M LET208 REV*A
Document Number: 002-04727 Rev. *B
Page 170 of 174
MB91590 Series
 Dimension of BGA-320(BYA320)
D
D2
D1
A
eD
0.20 C
2X
eE
E2 E
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
7
SE
E1
Y W V U T R P N M L K J H G F E D C B A
PIN A1
CORNER
SD
B
8
320xφb
0.20 C
6
2X
TOP VIEW
7
0.30
C A B
0.15 C
BOTTOM VIEW
0.20 C
A1
0.15 C
DETAIL A
A
C
SIDE VIEW
DETAIL A
NOTES
DIM ENSIONS
SYM BOL
M IN.
NOM .
A
A1
1. ALL DIM ENSIONS ARE IN M ILLIM ETERS.
2.46
2. D IM ENSIONS AND TOLERANCES M ETHODS PER ASM E Y14.5-2009 .
THIS OUTLINE CONFORM S TO JEP95, SECTION 4.5.
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010.
0.35
D
4. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
27.00 BSC
E
27.00 BSC
D1
24.00 BSC
E1
24.00 BSC
MD
20
ME
20
n
320
Φb
M AX.
0.60
0.75
eD
1.27 BSC
eE
1.27 BSC
SD / SE
0.635
5. SYM BOL "M D" IS THE BALL M ATRIX SIZE IN THE "D"DIRECTION.
SYM BOL "M E" IS THE BALL M ATRIX SIZE IN THE "E"DIRECTION.
n IS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX
SIZE M D X M E.
6. DIM ENSION "b " IS M EASURED AT THE M AXIM UM BALL DIAM ETER
IN A PLANE PARALLEL TO DATUM C.
0.90
7. "SD" AND "SE" ARE M EASURED W ITH RESPECT TO DATUM S A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW .
W HEN THERE IS AN ODD NUM BER
OF SOLDER BALLS IN THE OUTER ROW ,
"SD" OR "SE"= 0.
W HEN THERE IS AN
EVEN NUM BER OF SOLDER BALLS IN THE OUTER ROW ,
"SD" = eD/2 AND "SE" = eE/2.
8. A1 CORNER TO BE IDENTIFIED BY CHAM FER, LASER OR INK M ARK.
M ETALLIZED M ARK INDEN TATION OR OTHER M EANS.
9. "+ " INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
10. JEDEC SPECIFICATION NO. REF: N/A.
002-16414 **
PACKAGE OUTLINE, 320 BALL FBGA
27.00X27.00X2.46 M M BYA320 REV**
Document Number: 002-04727 Rev. *B
Page 171 of 174
MB91590 Series
14. Major Changes
Spansion Publication Number: MB91590_DS705-00010
Page
Revision 3.1
-
Section
-
Change Results
Company name and layout design change
See Supplementary Information as described in Document Definition.
NOTE: Please see “Document History” about later revised information.
Document Number: 002-04727 Rev. *B
Page 172 of 174
MB91590 Series
Document History
Document Title: MB91590 Series FR Family FR81S 32-Bit Microcontroller
Document Number: 002-04727
Revision
ECN
**
-
Orig. of
Submission
Change
Date
NNAS
06/19/2015
Description of Change
Migrated to Cypress and assigned document number 002-04712.
No change to document contents or format.
*A
5139796
NNAS
02/19/2016
Updated to Cypress format.
12. Ordering Information
[Improve] Updated "Ordering Information"
*2
[Improve] Delete : Under consideration
*B
5973870
HMIZ
12/01/2017
13. Package Dimensions
[Improve] Updated PKG figure for LQR208, LET208 and BYA320
Updated Sales page.
Document Number: 002-04727 Rev. *B
Page 173 of 174
MB91590 Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
Products
®
®
PSoC® Solutions
ARM Cortex Microcontrollers
cypress.com/arm
Automotive
cypress.com/automotive
Clocks & Buffers
cypress.com/clocks
Interface
cypress.com/interface
Internet of Things
cypress.com/iot
Memory
cypress.com/memory
Microcontrollers
cypress.com/mcu
Technical Support
PSoC
cypress.com/psoc
cypress.com/support
Power Management ICs
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
cypress.com/usb
Wireless Connectivity
cypress.com/wireless
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Cypress Developer Community
Forums | WICED IOT Forums| Projects | Videos | Blogs |
Training| Components
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or
other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software,
then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source
code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form
externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are
infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction,
modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It
is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress
products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support
devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the
failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform
can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress
from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs,
damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04727 Rev. *B
December 1, 2017
Page 174 of 174