Fujitsu MB82DP02183F-65L Memory mobile fcram cmos 32 m bit (2 m word x 16 bit) mobile phone application specific memory Datasheet

FUJITSU MICROELECTRONICS
DATA SHEET
DS05-11460-1E
MEMORY Mobile FCRAMTM
CMOS
32 M Bit (2 M word × 16 bit)
Mobile Phone Application Specific Memory
MB82DP02183F-65L
■ DESCRIPTION
The MB82DP02183F is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous Static
Random Access Memory (SRAM) interface containing 33, 554, 432 storages accessible in a 16-bit format.
This MB82DP02183F is suited for mobile applications such as Cellular Handset and PDA.
*: FCRAM is a trademark of Fujitsu Microelectronics Limited, Japan
■ FEATURES
•
•
•
•
•
•
•
Asynchronous SRAM Interface
Fast Access Time : tAA = tCE = 65 ns Max
8 words Page Access Capability : tPAA = 20 ns Max
Low Voltage Operating Condition : VDD = 2.6 V to 3.1 V
Operating Temperature: TA = 0 °C to + 70 °C
Byte Control by LB and UB
Low Power Consumption : IDDA1 = 30 mA Max
IDDS1 = 120 μA Max
• Various Power Down mode : Sleep
4 M-bit Partial
8 M-bit Partial
■ MAIN SPECIFICATIONS
Parameter
MB82DP02183F-65L
Access Time (Max) (tCE, tAA)
65 ns
Active Current (Max) (IDDA1)
30 mA
Standby Current (Max) (IDDS1)
120 μA
Power Down Current (Max) (IDDPS)
10 μA
Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.8
MB82DP02183F-65L
■ PIN ASSIGNMENT
(TOP VIEW)
A
B
8
NC
NC
7
NC
NC
D
E
F
G
H
J
A15
NC
NC
A16
NC
VSS
A11
A12
A13
A14
NC
DQ15
DQ7
DQ14
6
A8
A19
A9
A10
DQ6
DQ13 DQ12
DQ5
5
WE
CE2
A20
DQ4
VDD
NC
4
DU
DU
DU
DQ3
VDD
DQ11
3
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
A7
A6
A5
A4
VSS
OE
DQ0
DQ8
A3
A2
A1
A0
NC
CE1
2
NC
1
NC
C
NC
K
L
M
NC
NC
NC
NC
NC
NC
NC
NC
(BGA-71P-M03)
■ PIN DESCRIPTION
Pin Name
A20 to A0
2
Description
Address Input
CE1
Chip Enable 1 (Low Active)
CE2
Chip Enable 2 (High Active)
WE
Write Enable (Low Active)
OE
Output Enable (Low Active)
LB
Lower Byte Control (Low Active)
UB
Upper Byte Control (Low Active)
DQ7 to DQ0
Lower Byte Data Input/Output
DQ15 to DQ8
Upper Byte Data Input/Output
VDD
Power Supply Voltage
VSS
Ground
NC
No Connection
DU
Don't Use
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MB82DP02183F-65L
■ BLOCK DIAGRAM
VDD
VSS
A20 to A0
Address
Latch
&
Buffer
Row
Decoder
I/O Data
Buffer
Input Data
Latch
& Control
DQ7 to DQ0
DQ15 to DQ8
Memory Cell
Array
33,554,432 bits
Sense/Switch
Output Data
Control
Column Decoder
Address Latch
&
Buffer
CE2
CE1
Power
Control
Timing Control
WE
LB
UB
OE
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MB82DP02183F-65L
■ FUNCTION TRUTH TABLE
CE2
CE1
WE
OE
LB
UB
A20 to A0
DQ7 to
DQ0
DQ15 to
DQ8
H
H
X
X
X
X
X
High-Z
High-Z
H
H
X
X
*3
High-Z
High-Z
Output Disable (No Read)
H
H
Valid
High-Z
High-Z
Read (Upper Byte)
H
L
Valid
High-Z
Output
Valid
L
H
Valid
Output
Valid
High-Z
L
L
Valid
Output
Valid
Output
Valid
H
H
Valid
Invalid
Invalid
H
L
Valid
Invalid
Input Valid
Write (Lower Byte)
L
H
Valid
Input Valid
Invalid
Write (Word)
L
L
Valid
Input Valid Input Valid
X
X
X
Mode
Standby (Deselect)
Output Disable*1
H
L
Read (Lower Byte)
Read (Word)
H
L
No Write
Write (Upper Byte)
L
Power Down*2
L
X
X
H*4
X
High-Z
High-Z
Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High impedance
*1 : Should not be kept this logic condition longer than 1 μs.
*2 : Power Down mode can be entered from standby state and all DQ pins are in High-Z state.
Data retention depends on the selection of Power Down program. Refer to “■ POWER DOWN” for the detail.
*3 : Can be either VIL or VIH but must be valid before read or write.
*4 : OE can be VIL during write operation if the following conditions are satisfied;
(1) Write pulse is initiated by CE1. Refer to “(12) Read/Write Timing 1-1 (CE1 Control)” in “■ TIMING
DIAGRAMS”.
(2) OE stays VIL during write cycle.
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MB82DP02183F-65L
■ POWER DOWN
• Power Down
The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in Power Down mode
and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from Power Down
mode.
This device has three Power Down modes, Sleep, 4 M-bit Partial and 8 M-bit Partial. The selection of Power
Down mode can be programmed by series of read/write operation. Each mode has following data retention
features.
Mode
Data Retention
Retention Address
Sleep (default)
No
N/A
4 M-bit Partial
4 M bits
000000h to 03FFFFh
8 M-bit Partial
8 M bits
000000h to 07FFFFh
The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought
to Low for Power Down. It is not required to program to Sleep mode after power-up.
• Power Down Program Sequence
The program requires total six read/write operations with unique address and data. The device should be in
standby mode in the interval between each read/write operation. The following table shows the detail sequence.
Cycle #
Operation
Address
Data
#1
Read
1FFFFFh (MSB)
Read Data (RDa)
#2
Write
1FFFFFh
RDa
#3
Write
1FFFFFh
RDa
#4
Write
1FFFFFh
Don't Care (X)
#5
Write
1FFFFFh
X
#6
Read
Address Key
Read Data (RDb)
The Cycle#1 is to read from most significant address (MSB).
The Cycle#2 and Cycle#3 are to write to MSB. If the Cycle#2 or Cycle#3 is written into the different address,
the program is cancelled and the data written by the Cycle#2 or Cycle#3 is valid as a normal write operation. It
is recommended to write back the data (RDa) read by Cycle#1 to MSB in order to secure the data.
The Cycle#4 and Cycle#5 are to write to MSB. The data of Cycle#4 and Cycle#5 becomes the same arbitrary
data (Don't-Care). If the Cycle#4 or Cycle#5 is written into different address, the program is also cancelled but
write data may not be written as normal write operation.
The Cycle#6 is to read from specific address key for mode selection. And read data (RDb) is invalid.
Once this program sequence is performed from a Partial mode to the other Partial mode, the written data stored
in memory cell array may be lost. Therefore, this program should be performed prior to regular read/write
operation if Partial Power Down mode is used.
• Address Key
The address key has following format.
Mode
Address
A20
A19
A18 to A0
Hexadecimal
Sleep (default)
1
1
1
1FFFFFh
4 M-bit Partial
1
0
1
17FFFFh
8 M-bit Partial
0
1
1
0FFFFFh
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MB82DP02183F-65L
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Min
Max
Unit
Power Supply Voltage*
VDD
− 0.5
+ 3.6
V
Input Voltage*
VIN
− 0.5
+ 3.6
V
Output Voltage*
VOUT
− 0.5
+ 3.6
V
Short Circuit Output Current
IOUT
− 50
+ 50
mA
Storage Temperature
TSTG
− 55
+ 125
o
C
* : All voltages are referenced to VSS.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min
Max
VDD
2.6
3.1
V
VSS
0
0
V
Input High Voltage *1, *2
VIH
VDD × 0.8
VDD + 0.2
V
Input Low Voltage *1, *3
VIL
− 0.3
VDD × 0.2
V
Ambient Temperature
TA
0
+ 70
°C
Power Supply Voltage*1
*1 : All voltages are referenced to VSS.
*2 : Maximum DC voltage on input or I/O pins is VDD + 0.2 V. During voltage transitions, inputs may overshoot to
VDD + 1.0 V for periods of up to 5 ns.
*3 : Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, inputs may undershoot VSS to
-1.0 V for periods of up to 5 ns.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
■ PACKAGE PIN CAPACITANCE
(f = 1 MHz, TA = +25 °C)
Parameter
Symbol
Test conditions
Address Input Capacitance
CIN1
Control Input Capacitance
Data Input/Output Capacitance
6
Value
Unit
Min
Typ
Max
VIN = 0 V
⎯
⎯
5
pF
CIN2
VIN = 0 V
⎯
⎯
5
pF
CIO
VIO = 0 V
⎯
⎯
8
pF
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MB82DP02183F-65L
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(Under recommended operating conditions unless otherwise noted)
Parameter
Symbol
Value
Test conditions
Min
Max
Unit
Input Leakage Current
ILI
VSS ≤ VIN ≤ VDD
−1.0
+1.0
μA
Output Leakage Current
ILO
VSS ≤ VOUT ≤ VDD, Output Disable
−1.0
+1.0
μA
Output High Voltage
VOH
VDD = VDD Min, IOH = −0.5 mA
2.4
⎯
V
Output Low Voltage
VOL
IOL = 1 mA
⎯
0.4
V
IDDPS
VDD = VDD Max,
VIN = VDD or VSS,
CE2 = VSS
Sleep
⎯
10
μA
4 M-bit Partial
⎯
75
μA
8 M-bit Partial
⎯
85
μA
VDD Power Down Current
IDDP4
IDDP8
IDDS
VDD = VDD Max, VIN = VIH or VIL,
CE1 = CE2 = VIH
⎯
1.5
mA
IDDS1
VDD = VDD Max, VIN = VDD or VSS,
CE1 = CE2 = VDD
⎯
120
μA
tRC/tWC = Min
⎯
30
mA
tRC/tWC = 1 μs
⎯
3
mA
⎯
10
mA
VDD Standby Current
IDDA1
VDD Active Current
IDDA2
VDD Page Read Current
IDDA3
VDD = VDD Max,
VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH,
IOUT = 0 mA
VDD = VDD Max, VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH,
IOUT = 0 mA, tPRC = Min
Notes : • All voltages are referenced to VSS.
• IDD depends on the output termination, load conditions, and AC characteristics.
• After power on, initialization following power-up timing is required.
DC characteristics are guaranteed after the initialization.
• IDDPS, IDDP4, IDDP8, and IDDS1 might be higher for up to 200 ms after power-up or Power Down/standby mode
entry.
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MB82DP02183F-65L
2. AC Characteristics
(1) Read Operation
(Under recommended operating conditions unless otherwise noted)
Parameter
Symbol
Value
Min
Max
Unit
Notes
Read Cycle Time
tRC
65
1000
ns
*1, *2
CE1 Access Time
tCE
⎯
65
ns
*3
OE Access Time
tOE
⎯
40
ns
*3
Address Access Time
tAA
⎯
65
ns
*3, *5
LB, UB Access Time
tBA
⎯
30
ns
*3
Page Address Access Time
tPAA
⎯
20
ns
*3, *6
Page Read Cycle Time
tPRC
20
1000
ns
*1, *6, *7
Output Data Hold Time
tOH
5
⎯
ns
*3
CE1 Low to Output Low-Z
tCLZ
5
⎯
ns
*4
OE Low to Output Low-Z
tOLZ
10
⎯
ns
*4
LB, UB Low to Output Low-Z
tBLZ
0
⎯
ns
*4
CE1 High to Output High-Z
tCHZ
⎯
12
ns
*3
OE High to Output High-Z
tOHZ
⎯
12
ns
*3
LB, UB High to Output High-Z
tBHZ
⎯
12
ns
*3
Address Setup Time to CE1 Low
tASC
−5
⎯
ns
Address Setup Time to OE Low
tASO
10
⎯
ns
Address Invalid Time
tAX
⎯
10
ns
*5, *8
Address Hold Time from CE1 High
tCHAH
−6
⎯
ns
*9
Address Hold Time from OE High
tOHAH
−6
⎯
ns
WE High to OE Low Time for Read
tWHOL
10
1000
ns
tCP
10
⎯
ns
CE1 High Pulse Width
*10
*1 : Maximum value is applicable if CE1 is kept at Low without change of address input of A20 to A3.
*2 : Address should not be changed within minimum tRC.
*3 : The output load 50 pF.
*4 : The output load 5 pF.
*5 : Applicable to A20 to A3 when CE1 is kept at Low.
*6 : Applicable only to A2, A1 and A0 when CE1 is kept at Low for the page address access.
*7 : In case page read cycle is continued with keeping CE1 stays Low, CE1 must be brought to High within
4 μs. In other words, page read cycle must be closed within 4 μs.
*8 : Applicable when at least two of address inputs among applicable are switched from previous state.
*9 : tRC(Min) and tPRC(Min) must be satisfied.
*10 : If the actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read may
become longer by the amount of subtracting the actual value from the specified minimum value.
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MB82DP02183F-65L
(2) Write Operation
(Under recommended operating conditions unless otherwise noted)
Parameter
Symbol
Value
Min
Max
Unit
Notes
Write Cycle Time
tWC
65
1000
ns
*1, *2
Address Setup Time
tAS
0
⎯
ns
*3
CE1 Write Pulse Width
tCW
40
⎯
ns
*2, *3
WE Write Pulse Width
tWP
40
⎯
ns
*2, *3
LB, UB Write Pulse Width
tBW
40
⎯
ns
*2, *3
LB, UB Byte Mask Setup Time
tBS
−5
⎯
ns
*4
LB, UB Byte Mask Hold Time
tBH
−5
⎯
ns
*5
Write Recovery Time
tWR
0
⎯
ns
*2, *6
CE1 High Pulse Width
tCP
10
⎯
ns
WE High Pulse Width
tWHP
10
1000
ns
*7
LB, UB High Pulse Width
tBHP
10
1000
ns
*7
Data Setup Time
tDS
12
⎯
ns
Data Hold Time
tDH
0
⎯
ns
OE High to CE1 Low Setup Time for Write
tOHCL
−5
⎯
ns
*8
OE High to Address Setup Time for Write
tOES
0
⎯
ns
*9
*1 : Maximum value is applicable if CE1 is kept at Low without any address change.
*2 : The sum of actual write pulse (tCW,tWP or tBW) and actual write recovery time (tWR) must be equal or greater
than specified minimum tWC.
*3 : Write pulse is defined from High to Low transition of CE1, WE, LB or UB, whichever occurs last.
*4 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE
whichever occurs last.
*5 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE
whichever occurs first.
*6 : Write recovery is defined from Low to High transition of CE1, WE, LB or UB, whichever occurs first.
*7 : Maximum specification values of tWHP and tBHP are applicable to Output Disable mode when CE1 = L,
WE = OE = H after write operation. Refer to “(7) Write Timing 2 (WE Control)” in “■TIMING DIAGRAMS”.
*8 : If OE is Low after minimum tOHCL, read cycle is initiated. In other words, OE must be brought to High within
5 ns after CE1 is brought to Low.
*9 : If OE is Low after a new address input, read cycle is initiated. In other words, OE must be brought to High
at the same time or before the new address valid.
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MB82DP02183F-65L
(3) Power Down Parameters
(Under recommended operating conditions unless otherwise noted)
Parameter
Value
Symbol
Min
Max
Unit
Notes
CE2 Low Setup Time for Power Down Entry
tCSP
10
⎯
ns
CE2 Low Hold Time after Power Down Entry
tC2LP
65
⎯
ns
CE1 High Hold Time following CE2 High
after Power Down Exit [Sleep mode only]
tCHH
300
⎯
μs
*1
CE1 High Hold Time following CE2 High
after Power Down Exit [not in Sleep mode]
tCHHP
65
⎯
ns
*2
CE1 High Setup Time following CE2 High
after Power Down Exit
tCHS
0
⎯
ns
*1
*1 : Applicable also to power-up.
*2 : Applicable when Partial mode is set.
(4) Other Timing Parameters
(Under recommended operating conditions unless otherwise noted)
Parameter
Value
Symbol
Min
Max
Unit
CE1 High to OE Invalid Time for Standby Entry
tCHOX
10
⎯
ns
CE1 High to WE Invalid Time for Standby Entry
tCHWX
10
⎯
ns
CE2 Low Hold Time after Power-up
tC2LH
50
⎯
μs
CE1 High Hold Time following CE2 High after Power-up
tCHH
300
⎯
μs
tT
1
25
ns
Input Transition Time
Notes
*1
*2
*1 : Some data might be written into any address location if tCHWX(Min) is not satisfied.
*2 : The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may
violate AC specification of some timing parameters.
(5) AC Test Conditions
Parameter
Symbol
Test Setup
Value
Unit
Input High Voltage
VIH
⎯
VDD × 0.8
V
Input Low Voltage
VIL
⎯
VDD × 0.2
V
VREF
⎯
VDD × 0.5
V
tT
Between VIL and VIH
5
ns
Input Timing Measurement Level
Input Transition Time
• AC Measurement Output Load Circuit
VDD
0.1 μF
VSS
10
Device under
Test
Output
50 pF
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MB82DP02183F-65L
■ TIMING DIAGRAMS
(1) Read Timing 1 (Basic Timing)
tRC
Address
Address Valid
tASC
tCHAH
tCE
CE1
tASC
tCP
tCHZ
tOE
OE
tOHZ
tBA
LB, UB
tBHZ
tBLZ
tOLZ
DQ
(Output)
tOH
tCLZ
Valid Data Output
Note : This timing diagram assumes CE2 = H and WE = H.
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MB82DP02183F-65L
(2) Read Timing 2 (OE Control & Address Access)
tRC
Address
tAX
Address Valid
tRC
Address Valid
tAA
tOHAH
tAA
CE1
Low
tASO
tOE
OE
LB, UB
tOHZ
tOLZ
DQ
(Output)
tOH
Valid Data
Output
tOH
Valid Data
Output
Note : This timing diagram assumes CE2 = H and WE = H.
12
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(3) Read Timing 3 (LB , UB Byte Control Access)
tAX
tRC
tAX
Address Valid
Address
tAA
CE1, OE
Low
tBA
tBA
LB
tBA
UB
tBHZ
tBLZ
tBHZ
tOH
tBLZ
tOH
DQ7 to DQ0
(Output)
Valid Data Output
Valid Data Output
tBLZ
tBHZ
tOH
DQ15 to DQ8
(Output)
Valid Data Output
Note : This timing diagram assumes CE2 = H and WE = H.
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MB82DP02183F-65L
(4) Read Timing 4 (Page Address Access after CE1 Control Access)
tRC
Address
(A20 to A3)
Address Valid
tRC
Address
(A2 to A0)
Address Valid
tASC
tPRC
tPRC
Address Valid
Address Valid
tPAA
tPRC
Address Valid
tPAA
tPAA
tCHAH
CE1
tCE
tCHZ
OE
LB, UB
tCLZ
tOH
tOH
tOH
tOH
DQ
(Output)
Valid Data Output
(Normal Access)
Valid Data Output
(Page Access)
Note : This timing diagram assumes CE2 = H and WE = H.
14
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MB82DP02183F-65L
(5) Read Timing 5 (Random and Page Address Access)
tAX
tRC
Address
(A20 to A3)
Address Valid
tRC
Address
(A2 to A0)
tRC
tPRC
Address Valid
Address Valid
tAA
CE1
Address Valid
tPRC
Address Valid
tAX
tRC
tPAA
Address Valid
tAA
tPAA
LOW
tASO
tOE
OE
tBA
LB, UB
tOLZ
DQ
(Output)
tOH
tOH
tOH
tOH
tBLZ
Valid Data Output
(Normal Access)
Valid Data Output
(Page Access)
Notes : • This timing diagram assumes CE2 = H and WE = H.
• Either or both LB and UB must be Low when both CE1 and OE are Low.
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MB82DP02183F-65L
(6) Write Timing 1 (Basic Timing)
tWC
Address
Address Valid
tAS
tWR
tCW
tAS
CE1
tCP
tAS
tWR
tWP
WE
tAS
tWHP
tAS
tWR
tBW
LB, UB
tAS
tBHP
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note : This timing diagram assumes CE2 = H.
16
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(7) Write Timing 2 (WE Control)
Address
tWC
tWC
Address Valid
Address Valid
tOHAH
CE1
Low
tAS
tWP
tWR
WE
tAS
tWP
tWR
tWHP
LB, UB
tOES
OE
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H.
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MB82DP02183F-65L
(8) Write Timing 3-1 (WE, LB, UB Byte Write Control)
tWC
Address Valid
Address
CE1
tWC
Address Valid
Low
tAS
tWP
tAS
WE
tWP
tWHP
tWR
tBH
tBS
LB
tBH
tBS
tWR
UB
tDS
tDH
DQ7 to DQ0
(Input)
tDS
DQ15 to DQ8
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H and OE = H.
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(9) Write Timing 3-2 (WE, LB, UB Byte Write Control)
tWC
Address Valid
Address
CE1
tWC
Address Valid
Low
tWR
WE
tWR
tWHP
tAS
tBW
tBS
tBH
LB
tBH
tBS
tAS
tBW
UB
tDS
tDH
DQ7 to DQ0
(Input)
tDS
DQ15 to DQ8
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H and OE = H.
DS05-11460-1E
19
MB82DP02183F-65L
(10) Write Timing 3-3 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
WE
tWHP
tAS
tBW
tWR
tBH
tBS
LB
tBS
tBH
tAS
tWR
tBW
UB
tDS
tDH
DQ7 to DQ0
(Input)
tDS
DQ15 to DQ8
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H and OE = H.
20
DS05-11460-1E
MB82DP02183F-65L
(11) Write Timing 3-4 (WE, LB, UB Byte Write Control)
Address
CE1
tWC
tWC
Address Valid
Address Valid
Low
WE
tAS
tBW
LB
tBW
tWR
tBHP
tDS
DQ7 to DQ0
(Input)
tDS
tDH
Valid Data Input
tAS
tBW
tDH
Valid Data Input
tAS
tWR
UB
tBW
tWR
tBHP
tDS
DQ15 to DQ8
(Input)
tAS
tWR
tDH
Valid Data Input
tDS
tDH
Valid Data Input
Note : This timing diagram assumes CE2 = H and OE = H.
DS05-11460-1E
21
MB82DP02183F-65L
(12) Read / Write Timing 1-1 (CE1 Control)
tWC
tRC
Write Address
Address
tCHAH
tAS
Read Address
tWR
tCHAH
tASC
tCW
tCE
CE1
tCP
tCP
WE
UB, LB
tOHCL
OE
tCHZ
tOH
tDS
tDH
tCLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H.
• Write address is valid from either CE1 or WE of last falling edge.
22
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MB82DP02183F-65L
(13) Read / Write Timing 1-2 (CE1, WE, OE Control)
tWC
tRC
Write Address
Address
tCHAH
tAS
Read Address
tWR
tASC
tCHAH
tCE
CE1
tCP
tCP
tWP
WE
UB, LB
tOHCL
tOE
OE
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H.
• OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read sequence.
DS05-11460-1E
23
MB82DP02183F-65L
(14) Read / Write Timing 2 (OE, WE Control)
tWC
tRC
Write Address
Address
Read Address
tAA
tOHAH
CE1
tOHAH
Low
tAS
tWR
tWP
WE
tOES
UB, LB
tASO
OE
tOE
tWHOL
tOHZ
tOH
tOHZ
tDS
tDH
tOLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H.
• CE1 can be tied to Low for WE and OE controlled operation.
• Read data will be available after tAA from WE = H if read address are not changed from write address.
24
DS05-11460-1E
MB82DP02183F-65L
(15) Read / Write Timing 3 (OE, WE, LB, UB Control)
tWC
Address
tRC
Read Address
Write Address
tAA
tOHAH
CE1
tOHAH
Low
WE
tOES
tAS
tBW
tWR
tBA
UB, LB
tASO
tBHZ
OE
tWHOL
tBHZ
tOH
tDS
tDH
tBLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H.
• CE1 can be tied to Low for WE and OE controlled operation.
• Read data will be available after tAA from WE = H if read address are not changed from write address.
(16) Power-up Timing 1
CE1
tCHS
tC2LH
tCHH
CE2
VDD (Min)
VDD
0V
Note : The tC2LH specifies after VDD reaches specified minimum level.
DS05-11460-1E
25
MB82DP02183F-65L
(17) Power-up Timing 2
CE1
tCHH
CE2
VDD (Min)
VDD
0V
Notes : • The tCHH specifies after VDD reaches specified minimum level.
• The tCHH applicable to both CE1 and CE2.
• If transition time of VDD (from 0 V to VDD Min) is longer than 50 ms, “ (16) Power-up Timing 1”
must be applied.
(18) Power Down Entry and Exit Timing
CE1
tCHS
CE2
tCSP
tC2LP
tCHH (tCHHP)
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Notes : • This Power Down mode can be also used as a reset timing if “Power-up timing” above could not
be satisfied and Power Down program was not performed prior to this reset.
• CE2 can be brought to Low after the completion of previous read/write operation.
• CE2 must be kept at High during the specified minimum time of tCP.
26
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MB82DP02183F-65L
(19) Standby Entry Timing after Read or Write
CE1
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for standby mode.
DS05-11460-1E
27
MB82DP02183F-65L
(20) Power Down Program Timing
Address
tRC
tWC
tWC
tWC
tWC
tRC
MSB*1
MSB*1
MSB*1
MSB*1
MSB*1
Key*2
tCP
tCP
tCP
tCP
tCP*3
tCP
CE1
OE
WE
LB, UB*4
DQ
RDa
Cycle #1
RDa
Cycle #2
RDa
Cycle #3
X
Cycle #4
X
Cycle #5
RDb
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #5.
*2 : The address key must conform to the format specified in “■ POWER DOWN”. If not, the operation and data
are not guaranteed.
*3 : After tCP following Cycle #6, the Power Down program is completed and returned to the normal operation.
*4 : Byte read or write is available in addition to word read or write. At least one byte control signal (LB or UB)
needs to be Low.
28
DS05-11460-1E
MB82DP02183F-65L
■ ORDERING INFORMATION
Part Number
MB82DP02183F-65LTBG
DS05-11460-1E
Package
71-ball plastic FBGA
(BGA-71P-M03)
29
MB82DP02183F-65L
■ PACKAGE DIMENSION
71-ball plastic FBGA
Ball pitch
0.80 mm
Package width ×
package length
7.00 × 11.00 mm
Lead shape
Soldering ball
Sealing method
Plastic mold
Ball size
∅0.45 mm
Mounting height
1.20 mm Max.
Weight
0.14 g
(BGA-71P-M03)
71-ball plastic FBGA
(BGA-71P-M03)
11.00±0.10(.433±.004)
B
0.20(.008) S B
1.09
.043
+0.11
–0.10
+.004
–.004
0.80(.031)
REF
0.40(.016)
REF
(Seated height)
0.80(.031)
REF
8
7
6
5
4
3
2
1
A
7.00±0.10
(.276±.004)
0.40(.016)
REF
0.10(.004) S
0.39±0.10
(Stand off)
(.015±.004)
INDEX-MARK AREA
S
0.20(.008) S A
M L K J H G F E D C B A
71-ø0.45 +0.10
–0.05
71-ø.018 +.004
–.002
ø0.08(.003)
M
S AB
0.10(.004) S
©2003-2008 FUJITSU MICROELECTRONICS LIMITED B71003S-c-1-2
C
2003 FUJITSU LIMITED B71003S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
30
DS05-11460-1E
MB82DP02183F-65L
MEMO
DS05-11460-1E
31
MB82DP02183F-65L
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3329
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department