TI AFE8406 14-bit, 85 msps dual adc, 8-channel wideband receiver Datasheet

14-Bit, 85 MSPS Dual ADC,
8-Channel Wideband Receiver
SLWS168 - OCTOBER 2005
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AFE8406
FEATURES
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14-bit 85 MSPS high performance dual ADC
The dual ADC can be configured into single ADC
At Fin=140MHz, SNR>=68dB, SFDR>=70dBc
At Fin = 70MHz, SNR>=70dB, SFDR>=82dBc
Independent clocks for ADC and DDC with build-in FIFO
Programmable closed loop VGA control with 6-bit outputs for each ADC
Provide Received Total Wide band Power (RTWP) measurement for the composite power across carriers with
programmable time window for measurement
8 UMTS Digital Down Converter (DDC) channels or 16 CDMA/TD-SCDMA DDC channels with programmable 18 bit
filter coefficients
Each DDC channel includes
o Real or complex DDC inputs
o UMTS mode Rx Filtering: 6 stage CIC (m=1 or 2), up to 40 tap CFIR, up to 64 tap PFIR
o CDMA mode Rx Filtering: 6 stage CIC (m=1 or 2), up to 64 tap CFIR, up to 64 tap PFIR
o Each DDC channel provides individual channel specific power measurements
o Each DDC channel has a dedicated final AGC
Test Bus to monitor data at different stages of the DDC signal path
3.3V analog supplies, 1.5V digital core supply, 3.3V digital I/O supply
484 ball plastic BGA (23mm x 23mm) with 1.0 mm pitch
Power dissipation: ~2.1W
APPLICATIONS
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Wireless base station receiver
Multi-carrier digital receiver
UMTS (4 carriers-1 sector with diversity)
CDMA (8 carriers-1 sector with diversity)
TD-SCDMA (16 carriers-1 sector without diversity, 8 carriers-1-sector with diversity)
Digital radio receivers
Wide band receivers
Software radios
Wireless local loop
Intelligent antenna systems
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Functional Block Diagram
General Description
The AFE8406 is a multi-channel communications signal processor that provides analog to digital
conversion and digital downconversion optimized for cellular base transceiver systems. The device
supports UMTS, CDMA-1X and TD-SCDMA air interface cellular standards.
The AFE8406 provides up to 8 UMTS digital downconverter channels (DDC), 16 CDMA DDCs or 16 TDSCDMA DDCs. The DDC channels are independent and operate simultaneously.
At the AFE8406 inputs, there are four input ports; two are hardwired to internal 14-bit analog-to-digital
converters and two are 16-bit digital inputs. Each DDC channel can be programmed to accept data from
any one of the four input ports.
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Table of Contents
1
2
Analog to Digital Converters ................................................................................................................... 4
Receive Digital Signal Processing........................................................................................................... 5
2.1
Receive Input Interface.................................................................................................................... 6
2.1.1
Receive FIFO ........................................................................................................................... 7
2.1.2
Receive Input Power Meters ...................................................................................................... 9
2.1.3
Receive Input AGC (RAGC) .................................................................................................... 11
2.1.4
Test and Noise Signal Generator ............................................................................................. 16
2.1.5
Sample Delay Lines ................................................................................................................ 19
2.1.6
Test Bus ................................................................................................................................ 20
2.2
DDC Organization ......................................................................................................................... 22
2.2.1
Downconverter Function Blocks............................................................................................... 24
2.2.2
DDC Mixer ............................................................................................................................. 25
2.2.3
DDC Number Controlled Oscillator (NCO) ................................................................................ 26
2.2.4
DDC Filtering and Decimation.................................................................................................. 30
2.2.5
DDC Channel Delay Adjust and Zero Insertion ......................................................................... 31
2.2.6
DDC CIC Filter ....................................................................................................................... 32
2.2.7
DDC Compensating FIR Filter ................................................................................................. 33
2.2.8
DDC Programmable FIR Filter................................................................................................. 38
2.2.9
DDC RMS Power Meter .......................................................................................................... 45
2.2.10 DDC AGC .............................................................................................................................. 47
2.2.11 DDC Output Interface.............................................................................................................. 51
2.2.11.1 Serial Output Interface ..................................................................................................... 51
2.2.11.2 Parallel Output Interface .................................................................................................. 53
2.2.12 DDC Checksum Generator ...................................................................................................... 54
3
AFE8406 General Control .................................................................................................................... 55
3.1
Microprocessor Interface Control Data, Address, and Strobes .......................................................... 55
3.2
MPU Timing diagrams: .................................................................................................................. 56
3.3
Synchronization Signals ................................................................................................................ 59
3.4
Interrupt Handling ......................................................................................................................... 60
3.5
AFE8406 Programming ................................................................................................................. 60
3.5.1
Control Register Index ............................................................................................................ 64
3.5.2
Global Control Variables ......................................................................................................... 67
3.5.3
Receive Input Interface Controls .............................................................................................. 73
3.5.4
Receive AGC Controls ............................................................................................................ 86
3.5.5
DDC Channel Controls.......................................................................................................... 104
4
AFE8406 Pins ................................................................................................................................... 120
4.1
Analog Section Signals................................................................................................................ 120
4.2
Digital Receive Section Signals.................................................................................................... 121
4.3
Microprocessor Signals ............................................................................................................... 126
4.4
JTAG Signals ............................................................................................................................. 127
4.5
Factory Test and No Connect Signals .......................................................................................... 127
4.6
Power and Ground Signals .......................................................................................................... 128
4.7
Digital Supply Monitoring............................................................................................................. 128
4.8
JTAG ......................................................................................................................................... 129
5
Specifications .................................................................................................................................... 129
5.1
Absolute Maximum Ratings ......................................................................................................... 129
5.2
Recommended Operating Conditions ........................................................................................... 130
5.3
Thermal Characteristics............................................................................................................... 130
5.4
Power Consumption .................................................................................................................... 130
5.5
Analog Electrical Characteristics.................................................................................................. 131
5.6
Digital Chip DC Characteristics .................................................................................................... 134
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5.7
Digital Chip AC Timing Characteristics ......................................................................................... 135
Package/Ordering Information ............................................................................................................ 137
Analog to Digital Converters
The AFE8406 includes a high performance dual channel 14bit 85MSPS Analog-to-Digital Converter. To
provide a complete solution, each channel includes a high bandwidth linear sample-and-hold stage (S&H)
and internal reference. An internal reference is provided, simplifying system design requirements, yet
external reference can be used optionally to suit the accuracy and low drift requirements of the application.
REFPA
REFMA
Internal
Reference
INPA
S&H
INMA
Dual 14 bit 85Msps ADC
14bit
Pipelined
ADC Core
Digital
Error
Correction
Output
Control
CLKPA
CLKMB
CLKOUTB
Timing circuitry
CLKPB
INMB
S&H
INPB
REFMB
REFPB
OVFA
CLKOUTA
Timing circuitry
CLKMA
DA13:DA0
14bit
Pipelined
ADC Core
Digital
Error
Correction
Output
Control
DB13:DB0
OVFB
Internal
Reference
The ADC digital output data and output clocks are connected directly to the rxin_a and rxin_b ports of the
AFE8406 digital section. The OVFA and OVFB outputs connect directly to the AFE8406 digital section and
also to package balls. The ADC outputs can be accessed through the test bus in a decimate by 32x only.
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Receive Digital Signal Processi ng
The down conversion section of the AFE8406 consists of the receive input interface, the rx_distribution
bus, and 8 digital downconverter blocks.
The purpose of the receive input interface is to accept signal data from four input ports (2 from the
integrated 14 bit analog-to-digital converters, and 2 from the 16 bit input ports), measure the input signal
power, provide control signals for external Digital Variable Gain Amplifiers (DVGAs) for controlling signal
amplitude at each ADC input and to distribute the data to the DDC blocks. The input interface also has a
user-controlled test generator and noise source.
The rx_distribution bus distributes the four channels of signal data to each of the 8 DDC blocks.
Each DDC block selects one of the four channels (or 2 for complex input data) from the rx_distribution bus
and then performs downconversion tuning, programmable delay, channel filtering with decimation, power
measurement, fixed gain adjust, and automatic gain control. Each DDC block can support 1 UMTS
channel, 2 CDMA channels, or 2 TD-SCDMA channels. An optional mode permits stacking two DDC
blocks in UMTS mode to provide double-length final pulse shaping filtering.
Tuned, filtered, and decimated signal data is output in bit serial or parallel format.
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Receive Input Interface
dvga _a
6
18
hard wired to
internal ADCA
rxin_a
16
test & noise
signal
generator
16
FIFO
16
dual real or
single complex
Power Meter
to testbus
dual real or
single complex
AGC
1 to 64
sample
delay
line
delay_a
hard wired to
internal ADCB
rxin_b
16
FIFO
16
dvga_b
6
1 to 64
sample
delay
line
dvga _c
6
delay_b
16
test & noise
signal
generator
18
rx_distribution
bus to DDC
channels
18
rxin_c
16
test & noise
signal
generator
16
test bus select
and decimation
FIFO
16
dual real or
single complex
Power Meter
testbus
sources
dual real or
single complex
AGC
1 to 64
sample
delay
line
delay_c
rxin_d
16
test & noise
signal
generator
16
FIFO
16
dvga_d
6
18
1 to 64
sample
delay
line
delay_d
The AFE8406’s receive input data interface accepts data from several sources:
• Signal data from the two integrated 14-bit ADCs.
• Signal data presented at the two 16-bit digital data input ports.
• A LFSR test signal generator allows the AFE8406 to be tested using a known repetitive data sequence.
For the rxin_c and rxin_d input ports, signal data can be provided in binary or 2’s complement form. The
location of the ADC’s MSB can be programmed to allow for additional AGC headroom if desired. For
example, a 14-bit ADC may be connect with the MSBs aligned, or shifted down to allow the AGC additional
gain range before clipping the signal.
Signal data can be accepted at rates up to rxclk in UMTS mode for either 8 normal channels or 4 double
length final pulse shaping filter channels. In CDMA mode the maximum input rate is rxclk for real inputs, or
rxclk/2 for complex inputs. For maximum filter performance, higher clock rates generally allow longer filters.
Complex signal data is input with I data driving one input port and Q data driving another. This means that
there are only two signal data ports available when using complex input mode. The mapping of I and Q
data onto the four input ports is programmable.
Signal input data is clocked into 8-stage FIFOs using a matching external clock signal adcclk_a/b/c/d.
Signal data is clocked out of the FIFO from a gated rxclk (the AFE8406 receive section clock). The FIFO
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allows arbitrary phase relationship between adcclk_a/b/c/d and rxclk. The frequency relationship is
mandated by the programmed configuration.
The test and noise generator can supply test sequences or add noise to the input signal data. The test
sequences, when combined with the checksum generators, are useful for initial board debug or power-on
self-test.
For applications that require receiver desensitization, the noise generator can add noise to user selected
bits to input data stream to reduce receiver sensitivity.
The two ADC input ports, rxin_a and rxin_b, can be passed to the testbus control block, decimated by 32x,
and routed directly to the AFE8406 testbus output pins. The key requirement of this function is to be able
to verify the performance of the ADC by reconstructing the samples, while limiting the output sample rate
to less than 5MHz using a 85MHz ADC sample rate.
Many other internal chip signals can be routed to the testbus for evaluation and debug purposes. When the
testbus is enabled, the rxin_c and rxin_d ports are driven as digital outputs.
Each of the four outputs to the DDC channels includes a 1 to 64 sample delay lines.
Programming
Variable
ssel_ddc(2:0)
offset_bin_X
msb_pos_X(2:0)
2.1.1
Description
Selects the sync source for the DDC data input mux and mixer. This sets the sync
source for DDC input clock generation and synchronization for all DDC channels.
Selects offset binary input when set, 2’s complement input when cleared.
X={a,b,c,d} Note that the internal ADCs use 2’s complement format, so
offset_bin_A and offset_bin_B must be set.
Identifies the connection location of the ADC’s MSB. Programmed values of
{0..7} corresponds to msb at {rxin_x_15.. rxin_x_8}. X={a,b,c,d}
Receive FIFO
The receive FIFO consists of an 8 stage memory and 2 counters generating the input write pointer and
output read pointer. When the FIFO receives a sync signal, the input and output pointers are initialized
with a write to read pointer offset of four samples. Input samples from rxin_X (writes) are clocked with the
adcclk_X input clock rising edges, and the input pointer advances on each clock rising edge. Output
samples (reads) and the output pointer are clocked with the rxclk input signal rising edges, divided by the
programmed sample rate loaded into the rate_sel(1:0) control register.
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Programming
Variable
adc_fifo_bypass
ssel_adc_fifo(2:0)
rate_sel(1:0)
adc_fifo_strap_ab
adc_fifo_strap_cd
Description
When set, bypasses the input FIFOs and input data is latched directly using the
rxclk. When cleared, input data is latched using the adcclk_a/b/c/d inputs.
Selects the sync source for the FIFO state machines. This sync signal initializes
the FIFO input and output pointers.
This selects the FIFO input and output rate; {rxclk, rxclk/2, rxclk/4 or rxclk/8 }. For
example, with rxclk at 153.6MHz, set rate_sel to 0, 1, 2 or 3 respectively for
adcclk_a/b/c/d 153.6, 76.8, 38.4 or 19.2MHz. MUST BE SET THE SAME AS
REGISTER ch_rate_sel(1:0).
When set, the rxin_a and rxin_b FIFO input and output pointers are synchronized
to support complex input signals.
When set, the rxin_c and rxin_d FIFO input and output pointers are synchronized
to support complex input signals.
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Receive Input Power Meters
from rxin_a FIFO output
I
power meter 0
power meter 0 results
power meter 1
power meter 1 results
power meter 2
power meter 2 results
power meter 3
power meter 3 results
pmeter_iq0
Q
from rxin_b FIFO output
pmeter_iq1
from rxin_c FIFO output
I
Q
I
pmeter_iq2
Q
from rxin_d FIFO output
pmeter_iq3
I
Q
Four Receive Input RMS power meters are provided. For real inputs, the four power meters can be used
to measure the RMS power of the combined carriers in each of the four input signals (the Q input is held at
zero). For complex inputs, two power meters can be use to measure the combined complex power and
two can be disabled.
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16
I
32
33
16
Q
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58-bit
Integrator
RMS power
58-bit
Register
32
clear
9-bit
sync delay
counter
sync
21-bit
interval
counter
9
21-bit
integration
counter
21
delay
(in 8 sample
increments)
transfer
interrupt
21
interval
(in 8 sample
increments)
integration
(in 8 sample
increments)
interrupt
interrupt
interrupt
sync
delay
integration time
integration time
interval time
sync
event
integration
start
integration time
interval time
integration
start
integration
start
Power is calculated by squaring each 16 bit I (I and Q for complex inputs) sample, summing, and then
integrating the summed-squared results into a 58 bit accumulator over a programmable integration period.
The integration period is programmed into the 21 bit counter, in 8 sample increments. The power read is:
2
power = [ (I )x (Nx8 + 1) ]
2
2
power = [ (I + Q )x (Nx8 + 1) ]
for real inputs where N is the integration count.
for complex inputs where N is the integration count.
A programmable 21 bit interval counter sets the power measurement interval (how often power will be
measured) in 8 sample increments. A measurement integration period is started at the beginning of each
interval period.
The process begins with a sync event starting the 9 bit delay counter. After (8*sync_delay + 2) samples,
the integration interval is started. Integration continues until the integration count is met, at which point the
58 bit integrator results are transferred to the read only register and an interrupt is generated. A new
measurement period will start at the end of the interval period.
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Note: Each of the four composite RMS power meter blocks has its own delay sync, interval, and integration
period counters, as well as separate sync source registers.
The 21-bit counters in 8 sample increments allow up to 104.8mS interval times at 160MHz clock.
Programming
Variable
Description
recv_pmeterX (57:0)
58 bit power measurement result. X= {0,1,2,3}.
recv_pmeterX_sqr_sum(20:0)
21 bit integration (square and sum) period. X= {0,1,2,3}.
recv_pmeterX_sync_delay(8:0)
Power meter delay sync period. X= {0,1,2,3}.
recv_pmeterX_strt_intrvl(20:0)
21 bit measurement interval. X= {0,1,2,3}.
The strt_intrvl value must be greater than the sqr_sum value.
2.1.3
ssel_recv_pmeter_X(2:0)
Sync source. X= {0,1,2,3}.
pmeterX_iq
selects complex power measurement input mode when set. X= {0,1,2,3}.
recv_pmeterX_ena
enables power meter when set. X= {0,1,2,3}.
Receive Input AGC (RAGC)
Input signals from the ADCs can be used to create a front end composite AGC loop when combined with a
digitally controlled variable gain amplifier (DVGA) connected before the ADCs. The AGC system operates
by integrating the square of the ADC samples over a programmable interval and applying a table driven
error signal to a loop integrator based on the squared integration output. The error table maps the signal
power to a user programmed error value. The loop integrator output is used to drive map tables to control
the DVGA output pins and a gain adjustment multiplier. Fast updates can be enabled if desired, to cause
the loop integrator to quickly adjust to interfering signals. The ADC input signals can also be passed
through a high pass filter to remove DC offset before squaring the input.
The programmable error table, integrator mapping tables, and clip thresholds, when combined with the
user programmable interval timers provide a highly flexible AGC function.
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integrate and dump signal power measurement
enable
Samples
from
ADC FIFO
corner
55
16
31
X2
Highpass
Filter
acc_offset
6
-
acc_shift
6
shift
&
limit
0
1
7
128w x 8b ram
7
limit
+
Error
Map
Table
{127..0}
8
update
err_shift 5
sd_thresh
signal detect
mode controls
Signal
Level
Detect
error
shift
64w x 22b ram
loop accumulator
no_signal
6 MSBs DVGA
Map
Table
freeze control register bit
freeze from sync source
Gain
Map
Table
clear control register bit
clear sync source
clip_error
Mag
16
to DVGA
pins
6
16
32
Clip
Detect
16
delay adjust
16
clip_hi_thresh
16
clip_low_thresh
clip detect controls
5
to DDC
channels
Delay
sync
update
sync
delay
update interval
The AGC measurement interval timer is a 24-bit timer initialized by a sync after a programmable 8-bit
delay. During the integration interval, the squared input signal is shifted by the programmed value and
accumulated. At the end of the interval time, an update pulse is generated, and the selected 7 bits of the
55-bit accumulated power is upper limit checked and transferred to the power holding register. A
programmable offset is applied, and the following limit check produces a 7 bit address value for the error
map table RAM. The user programmable error map table and following gain shift setting are used to
determine the loop error signal to be added to the 32-bit AGC loop accumulator. The error value is only
added to the loop accumulator once per update. The loop accumulator upper 6 MSBs are used as the
address for the programmable DVGA map table and gain map table. The gain map table address can be
delayed from 0 to 31 clock cycles to align DVGA changes to signal level changes at the output of the AGC.
The AGC includes four sources for freezing the loop and holding the loop accumulator constant. A general
sync source can be used to directly control the freeze; when the selected sync source is high, the AGC will
be held, and when low, the AGC will operate. A control register bit freezes the AGC in the same fashion;
when the bit is set, the AGC is held, and when cleared, the AGC will operate. A signal level detector is
provided that can be used to automatically freeze the AGC loop in the event of input signal loss. A
programmable signal detection threshold value, number of samples below the signal detection threshold,
and window timer are used to determine when no signal is present. Finally, a programmable number of
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AGC updates after sync can be programmed, and the AGC will he held until the next sync event. Freeze
holds the loop accumulator constant, the integrate and dump accumulator constant and the interval timer
constant. When freeze is released, the interval timer will resume counting.
A sync event will always reinitialize the integrate and dump interval timer, and terminate the pending
update to the loop accumulator from the current integrate and dump measurement interval. For example, if
a sync event occurs during an integrate and dump interval, that interval will be terminated without updating
the loop, and the integrate and dump accumulator will be cleared. After the programmed sync delay, a
new interval will start.
The AGC includes a dual threshold clip detect function, using two programmable 16-bit thresholds and
programmable counters. The clip detector will cause immediate loop accumulator updates while the clip
event is active. The 16-bit clip error value is aligned at the MSBs of the loop accumulator. Clip events are
qualified when a programmed number of samples are above the high clip threshold during the
programmable clip window time. For example, a clip event can be defined as 8 samples above the clip
high threshold in a 256 sample window; the clip high threshold, the number of samples above the high clip
threshold and the sample window time are programmable. Once the clip event has occurred, the clip
duration is controlled by the clip low threshold value, clip low samples value and clip low timer. The clip
event is cleared when the number of samples below the low clip threshold exceeds the programmed value
within the clip low timer window. The clip low threshold, number of clip low samples and the clip low
window timer are programmable.
The AGC blocks can be paired together, rxin_a with rxin_b, and rxin_c with rxin_d, to produce a complex
input AGC mode. The clip detector output from the rxin_b/d AGCs is logically OR’ed with the rxin_a/c clip
detect outputs. The squared input function before the integrate and dump and signal level detector is
2
2
replaced with a I + Q power calculation. The accumulator MSBs from the rxin_a/c AGCs are connected
to the rxin_c/d DVGA map table and gain map table inputs. This arrangement allows the AGCs to operate
2
2
in a direct conversion receiver system by controlling the I + Q complex signal level.
The highpass filter is a 32 bit accumulator followed by an adjustable shift to control the corner frequency, a
subtractor to remove the accumulated offset and a final limiter to produce a 16 bit result. The highpass
filter function is enabled by setting hp_ena; clearing hp_ena holds the accumulator reset.
32
Samples
from
ADC FIFO
-
16
hp_corner
3
17
shift
&
limit
+
hp_ena
16
17
16
limit
Samples to
X 2 block
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Programming
Variable
Description
ragc_bypass_X
Bypasses the entire receive AGC circuit when set. X = {0,1,2,3}
hp_ena_X
enables high pass filter when set
hp_corner_X(2:0)
adjusts the corner frequency of the high pass filter
integ_interval_X(23:0)
integrate and dump signal power measurement interval in samples.
acc_shift_X(4:0)
Shift down amount following the integrate and dump accumulator.
acc_offset_X(5:0)
offset value applied to the shifted integrate and dump output.
ragc_sync_delay_X(7:0)
AGC sync delay interval, from 1 to 256 samples.
ssel_ragc_interval_X(2:0)
Sync source selection for the interval timer.
ssel_ragc_freeze_X(2:0)
Sync source selection for AGC freeze
ssel_ragc_clear_X(2:0)
Sync source selection for the AGC loop accumulator clear
ragc_freeze_X
Register bit to freeze the AGC when set
ragc_clear_X
Register bit to clear the AGC accumulator when set
ragc_update_X(7:0)
Sets the number of updates per sync event, after which no further
updates will occur until the next sync event. Program to 0x00 to
continually update.
sd_ena_X
enables freezing the AGC with the signal detector when set
sd_thresh_X(15:0)
signal detection threshold for AGC channel X. This 16 bit word is lined up
with bits 23 down to 8 of the square output. The smallest signal level is
that can be programmed is therefor 16 LSBs on the ADC input, and the
largest is 4095 LSBs at the ADC input.
sd_samples_X(15:0)
the number of samples below the signal detect threshold within the signal
detect sample timer window required to freeze on the AGC.
sd _timer_X(15:0)
window timer to qualify signal detection.
clip_hi_thresh_X(15:0)
clip detector high threshold
clip_lo_thresh_X(15:0)
clip detector low threshold
clip_hi_samples_X(7:0)
a clip event is detected when this number of samples above the clip high
threshold within the clip high sample timer window exceeds this value.
clip_lo_samples_X(7:0)
a clip event ends when this number of samples below the clip low
threshold within the clip low sample timer window exceeds this value.
clip_hi_timer_X(15:0)
window timer to qualify clip events.
clip_lo_timer_X(15:0)
window timer to determine when the clip event ends.
clip_error_X(15:0)
error signal applied to the AGC accumulator when a clip event is active.
This data is MSB aligned, and therefor can cause immediate changes to
the accumulator.
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Programming (continued)
Variable
Description
ragc_error_map_X
128w x 8b memory holding the log to error look up table.
dvga_map_X
64w x 6b memory holding the accumulator to DVGA look up table
gain_map_X
64w x 16b memory holding the accumulator to GAIN look up table
(256 decimal is unity gain)
delay_adj_X(4:0)
Delay between DVGA output updates and gain map updates to
compensate for ADC pipeline delays, etc.
err_s hift_X(4:0)
error map table output shift up before adding to loop accumulator
complex_01
enables complex AGC mode on inputs rxin_a and rxin_b when set
complex_23
enables complex AGC mode on inputs rxin_c and rxin_d when set
ragc_accum_X(31:0)
32-bit read only register holding the current contents of the loop
accumulator.
tristate(10:7)
Tristate controls for the dvga_d/c/b/a output pins; pins are in tristate when
the tristate bits are set.
ragc_mpu_ram_read
What set, the receive AGC map rams are readable via the MPU control
interface. The AFE8406 signal path is not operational when this bit is
set, it is intended for debug purposes only.
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Test and Noise Signal Generator
The test and noise generator can generate test signals replacing the rxin_a/b/c/d inputs as a tool for debug,
evaluation and self test. Checksum generators included in the individual DDC channels at the outputs can
be used in conjunction with the noise generator and the internal sync timer block to create the built in self
test function.
The test and noise signal source included in this block is a 23-bit linear feedback shift register (LFSR) with
a fixed polynomial and fixed initialization state. A sync input is required to initialize the LFSR, and the sync
source is connected to the ddc_counter output signal.
sync
adcclk_X
LFSR
lfsr(22:0)
initialized on sync event - each of the four generators has a different seed
22
Receive Input Port
rxin_a
rxin_b
rxin_c
rxin_d
5
0
LFSR seed value, msb to lsb
100 0000 0000 0000 0001 0000 (0x400010)
010 0110 1110 0110 1100 1110 (0x26E6CE)
110 1110 1010 0010 1001 1000 (0x6EA298)
000 1011 0001 1110 1011 0111 (0x0B1EB7)
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The 23-bit LFSR output signal if used to create a 16-bit “dout(15:0)” test signal using XOR combinations of the
LFSR bits.
lfsr(22)
lfsr(20)
lfsr(22)
lfsr(16)
lfsr(22)
lfsr(15)
lfsr(22)
lfsr(14)
lfsr(22)
lfsr(13)
lfsr(22)
lfsr(12)
lfsr(22)
lfsr(11)
lfsr(19)
dout(15)
lfsr(18)
dout(14)
lfsr(17)
dout(13)
lfsr(16)
dout(12)
lfsr(15)
dout(11)
lfsr(14)
dout(10)
lfsr(13)
lfsr(12)
lfsr(11)
lfsr(10)
dout(9)
dout(8)
dout(7)
dout(6)
dout(5)
dout(4)
dout(3)
dout(2)
dout(1)
dout(0)
To enable the test signal generator, the slf_tst_ena control bit should be set. The rxin_a/b/c/d signals will be
then replaced by the four generator output streams. To use this test signal generator as a signal source for self
test, the user must also set the adc_fifo_bypass control bit. Setting the adc_fifo_bypass control bit causes the
adcclk_a/b/c/d input clocks to be internally replaced with rxclk/N, where N is as programmed with the
rate_sel(1:0) control bits to {1,2,4 or 8}.
The test signal generators can also output a programmable constant value. All four test signal generators
output the same programmable constant value.
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16
rxin_a
16
data to FIFO for rxin_a
16
sync
Test and
Noise
Generator
16
rxin_b
16
data to FIFO for rxin_b
16
Test and
Noise
Generator
16
rxin_c
16
data to FIFO for rxin_c
16
Test and
Noise
Generator
16
rxin_d
16
data to FIFO for rxin_d
16
Test and
Noise
Generator
rduz_sens_ena
slf_tst_ena
The LFSR circuits can also be used to add noise to the rxin_a/b/c/d input signals by setting the rduz_sens_ena
control register bit. The magnitude of the noise added can be adjusted by programming the nz_pwr_mask(15:0)
control register. In the figure below, X = {a,b,c or d}.
16
rxin_X(15:0)
lfsr(15:0)
nz_pwr_mask(15:0)
16
to FIFO for rxin_X
16
16
16
16 XORs
16 ANDs
lfsr(17)
lfsr(16)
rduz_sens_ena
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Programming
Variable
slf_tst_ena
rduz_sens_ena
nz_pwr_mask(15:0)
adc_fifo_bypass
ddc_counter(31:0)
ddc_counter_width(7:0)
ssel_ddc_counter(2:0)
self_test_constant(17:0)
self_test_const_ena
2.1.5
Description
When set, the test signal generators replace the rxin_a/b/c/d input
signals with internally generated psuedo random sequences. The
fifo_bypass bit must be set when this bit is set.
Enables the LFSR, adding noise to the ADC input data when set.
Selects the power of the noise added to the ADC input data.
When set, the FIFO is essentially bypassed, and the adcclk_a/b/c/d
clock input ports are ignored.
32 bit general purpose counter interval
8 bit general purpose counter timeout width pulse
Sync source selection for the general purpose counter
18-bit self test constant value applied to all 4 rxin_a/b/c/d inputs when
self_test_const_ena is set.
Enables the self test constant value for rxin_a/b/c/d
Sample Delay Lines
The four sample delay line blocks each consist of a 64 register memory and a state machine. The state
machine uses a counter to control the write (input) pointer, and the programmed read offset register data to
create the read (output) pointer. Programming larger read offset register values increases the effective
delay at a resolution equal to the sample rate.
The read offset registers, delay_line_X, are double buffered. Writes to these registers may occur anytime,
but the actual values used by the circuit will not be updated until a delay line sync event occurs.
Programming
Variable
delay_line_X(5:0)
ssel_delay_line_X(2:0)
Description
Read offset into the 64 element memory for each delay line. X= {0,1,2,3}.
Selects the sync source used to update the double buffered delay line
register.
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Test Bus
When the test bus is enabled, the rxin_c(15:0) and rxin_d(15:0) ports become outputs, and the dvga_c and
dvga_d pins are combined with these pins to allow 36 bit wide signals from the DDC channels and the
receive input interface to be multiplexed to this test output port. Many of these sources are decimated to
reduce the output sample rates.
DDC0
MUX
ddc_tst_sel(5:0)
zeros
pfir output
cfir output
tadj channel A
tadj channel B
nco sin
nco cos
cic output
mixer i*cos & i*sin
mixer q*cos & q*sin
ddc mux channel A
ddc mux channel B
MUX
DECIMATE
tst_select(3:0)
tst_decim17
tst_decim_delay
(35:20)
(19:18)
(17:2)
(1:0)
tst_clk
tst_aflag
tst_sync
rxin_d(15:0)
dvga_c(3:2)
rxin_c(15:0)
dvga_c(5:4)
dvga_c(1)
dvga_d(5)
dvga_c(0)
DDC1
sync
DDC2
DDC3
DDC4
DDC5
DDC6
DDC7
Receive Interface
rxin_a & rxin_b FIFO outputs
Programming
Variable
ssel_tst_decim(2:0)
tst_decim_delay(3:0)
tst_decim17
tst_on
Description
Selects the sync source for the testbus decimator
Sets the testbus decimator delay from sync
Not functional. Decimation is 32x regardless of setting.
enables the test bus; rxin_c(15:0) and rxin_d(15:0) are changed from inputs to
outputs, dvga_c(5:0) and dvga_d(5) are used as part of the test bus.
tst_select(3:0)
selects the source block for the testbus output; DDC0-7 or Receive Interface.
ddc_tst_sel(5:0)
selects the signal to be output from the DDC block
tst_rate_sel(4:0)
Sets the testbus output clock tst_clk period to (tst_rate_sel + 1) rxclk cycles. When
the test bus source is set to the ADC FIFO, tst_rate_sel(4:0) must be set to 0 for an
output.
tst_clk_pol
Selects the polarity of the test clock output at dvga_c(1) when the test bus is
enabled; 0 for rising edge in the center of valid data, 1 for falling edge in the center
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of valid data. No effect when tst_rate_sel is “00000”.
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DDC Organization
18
18
18
18
4 to 2 (complex) or
4 to 1 (real) switch
CDMA DDC A
Output
Interface
or 1 UMTS DDC
4 to 2 (complex) or
CDMA DDC B
4 to 1 (real) switch
DDC0
DDC1
DDC2
DDC3
DDC4
DDC5
DDC6
DDC7
The AFE8406 provides downconversion for up to 8 UMTS receive channels, 16 CDMA2000 receive
channels or 16 TD-SCDMA receive channels. Downconversion channels are organized into 8 DDC
blocks. Each individual DDC block provides 2 CDMA2000 or 2 TD -SCDMA DDC channels, A and B, or 1
UMTS channel.
Both CDMA DDC channels in a DDC block can be independently tuned, though they would likely be used
as diversity pairs and tuned to the same frequency. Filter coefficients are shared between the two CDMA
DDC channels within a block.
Two adjacent DDC blocks (for example, DDC0 and DDC1) can be strapped together to form a single
UMTS DDC channel with double-length final pulse shaping filtering. The AFE8406 can therefore provide 4
UMTS DDC channels with double-length final PFIR filtering as shown in the following diagram.
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4 UMTS DDCs with up to 128 tap PFIR
18
18
18
18
4 to 2 (complex) or
4 to 1 (real) switch
CDMA DDC A
Output
Interface
4 to 2 (complex) or
CDMA DDC B
4 to 1 (real) switch
DDC0
DDC1
4 to 2 (complex) or
4 to 1 (real) switch
CDMA DDC A
or 1 UMTS DDC
4 to 2 (complex) or
Output
Interface
CDMA DDC B
4 to 1 (real) switch
DDC0 plus DDC1
DDC2 plus DDC3
DDC4 plus DDC5
DDC6 plus DDC7
Programming
Variable
ddc_ena
cdma_mode
gbl_ddc_write
Description
When set, turns on the DDC.
When set, puts the DDC block in dual channel CDMA mode.
When set, all subsequent programming (writes only) for DDC0 and
DDC1 is also written to DDC2/4/6 and DDC3/5/7.
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SLWS168 - OCTOBER 2005
Downconverter Function Blocks
from
rx_distribution
bus
18
18
18
18
4 to 2
Select
Delay
Adjust
Frequency 32
Phase
16
NCO
Zero
Pad
CFIR
Filter
Dec by 2
Six Stage
CIC Filter
Dec 4 to 32
PFIR
Filter
Dec by 1
Checksum
Generator
AGC
RMS Power
Measure
Serial
Interface
serial I, Q
up to 18-bits
(25-bits with
AGC disabled)
parallel I, Q
Each AFE8406 downconversion block can process two CDMA carriers or a single UMTS carrier. Signal
data is selected from one of four ports for real inputs, or two of four ports for complex inputs. Data from the
selected port(s) is multiplied with a complex, programmable numerically controlled oscillator (NCO) which
tunes the signal of interest to baseband. The delay adjust and zero pad blocks permits adjustment of the
delay in the end-to-end channel. Zero padding interpolates the signal to the rxclk rate. Filtering consists of
a six stage CIC filter which decimates the tuned data by a factor from 4 to 32, a compensating FIR filter
(CFIR) which decimates by a factor of two, followed by a programmable FIR filter (PFIR) which does not
decimate. The output interface block can be programmed to decimate by 2 if desired.
The RMS power meter measures the power within the channel’s bandwidth. The AGC automatically drives
the gain and keeps the magnitude of the signal at a user-specified level. This allows fewer bits to represent
the signal. The serial output interface formats and rounds the output data. Each of the above blocks is
described in greater detail in the following sections.
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SLWS168 - OCTOBER 2005
DDC Mixer
from
rx_distribution
bus
18
18
18
18
4 to 2
Select
Demux
and
Round
18
18
18
18
18
18
IA
QA
IB
QB
to
channel
delay
20
20
cos
sin
mixer_gain
from NCO
The receive mixer translates the input (from one of the input signal sources) to baseband where
subsequent filtering is performed to isolate the signal of interest. The mixer is a complex multiplier that
accepts 18 bit I and 18 bit Q signal data from the receive input interface and 20 bit Sine and Cosine
sequences from the NCO. The NCO generates a mixing frequency (sometimes referred to as a local
oscillator, or LO) specified by the user so that the desired signal of interest is tuned to 0 Hertz.
A DDC channel can support one UMTS signal directly, or two CDMA channels at half the input rate. When
in CDMA mode each channel may set independently; the path selection and the mixer tuning and phase.
The mixer output produces two complex streams; one representing the signal path for the A -side DDC, the
other the B-side. Each of these streams drives a channel delay and zero pad block.
The maximum input rate for UMTS is rxclk for either real or complex input data.
The maximum input rate in CDMA mode with real inputs is rxclk (remix_only is set, see below).
The maximum input rate in CDMA mode with complex inputs is rxclk/2 due to sharing of multiplier
resources.
Programming
Variable
ddcmux_sel_a(3:0)
ddcmux_sel_b(3:0)
remix_only
zero_qsample
ch_rate_sel(1:0)
mixer_gain
Description
Programs the I and Q complex input data routing onto two of the four input
ports for stream A of CDMA DDC
Programs the I and Q complex input data routing onto two of the four input
ports for stream B of CDMA DDC
For CDMA mode only, set this bit for real input data at the rxclk rate.
For complex inputs in CDMA mode, the maximum input data rate is
rxclk/2, and this bit must be cleared.
For CDMA mode with real inputs at the rxclk/2 rate or lower, this bit must
be cleared
When set, the Q samples used by the mixer are always zero. This bit
should be set for real only inputs in UMTS mode, or real only inputs in
CDMA mode when the input sample rate is rxclk/2 or lower.
Specifies the input channel data rate (rxclk, rxclk/2, rxclk/4, or rxclk/8
MSPS). MUST BE SET THE SAME AS REGISTER rate_sel(1:0).
When asserted, adds 6dB of gain in the mixer. This gain is highly
recommended.
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SLWS168 - OCTOBER 2005
DDC Number Controlled Oscillator (NCO)
Frequency Sync
Frequency Word
32
Reg
32
Reg
32
23
23
Clear
Aligned
to top
32 bits
Zero Phase Sync
Phase Offset Sync
5
sin/cos
table
20
cos
20
sin
Aligned
to bottom
5 bits
Dither
Generator
Phase Offset
16
Reg
16
Dither Sync
The NCO is a digital complex oscillator that is used to translate (or downconvert) an input signal of interest
to baseband. The block produces programmable complex digital sinusoids by accumulating a frequency
word which is programmed by the user. The output of the accumulator is a phase argument that indexes
into a sin/cos ROM table which produces the complex sinusoid. A phase offset can be added prior to
indexing if desired for channel calibration purposes. This will change the sin/cos phase with respect to
other channels’ NCOs.
A 5-bit dither generator is provided and generates a small level of digital pseudo-noise that is added to the
phase argument below the bottom bits and is useful for reducing NCO spurious outputs. This dither
generation is enabled by setting the dither_ena bit; the magnitude of the dither can be reduced by setting
one or both of the dither_mask bits.
Dither Programming
Variable
Description
dither_ena
dither_mask(1:0)
When set turns dither on. Clearing turns dither off.
Masks the MSB and MSB-1 dither bits, respectively, when set.
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The NCO spurious levels are better than –115 dBc. Added phase dither randomizes the periodic nature of
the phase accumulation process and reduces low-level spurious energy. For some frequencies (K*Fs /24)
dither is ineffective – in these cases an initial phase of 4 reduces NCO spurs. The figures below show the
spur level performance of the NCO without dither, with dither, and with a phase offset value.
a) Worst case spectrum without dither
Figure 1.
b) Spectrum with dither (tuned to same Frequency)
Example NCO spurs with and without dithering
a) Plot without dither or phase initialization
Figure 2.
b) Plot with dither and phase initialization
NCO Peak Spur Plot
The tuning frequency is specified as a 32 bit Frequency Word and is programmed as two sequential 16 bit
32
words over the control port. The NCO frequency resolution is simply the Fclk/ 2 , where Fclk is the
ADCCLK frequency. As an example, at an input clock rate of 61.44 MHz, the frequency step size would be
approximately 14 milli-Hertz. The Frequency Word is determined by the formula:
32
Frequency Word (in decimal)= 2 x Tuning Frequency / Fclk
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Note that frequency tuning words can be positive or negative valued. Specifying a positive frequency value
translates negative frequencies upwards towards 0 Hertz. Specifying a negative tuning frequency
translates positive frequencies downwards towards 0 Hertz.
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Programming
Variable
phase_add_a(31:0)
Description
32 bit tuning frequency word for the A-side DDC when
in CDMA mode. Also for UMTS mode.
32 bit tuning frequency word for the B-side DDC when
in CDMA mode. Not used in UMTS mode.
phase_add_b(31:0)
Each of the 12 CDMA DDC channels can be loaded with unique frequency words.
The phase of the NCO’s Sin/Cos output can be adjusted relative to the phase of other channel NCOs by
specifying a Phase Offset. The Phase Offset is programmed as a 16 bit word, yielding a step size of about
5.5 milliDegrees. The Phase Offset Word is determined by the formula:
16
x Offset_in_Degrees / 360
16
x Offset_in_Radians / 2p
Phase Offset Word= 2
or,
Phase Offset Word= 2
Programming
Variable
phase_offset_a(15:0)
phase_offset_b(15:0)
Description
16 bit phase offset word for the A-side DDC when in
CDMA mode. Also for UMTS mode.
16 bit phase offset word for the B-side DDC when in
CDMA mode. Not used in UMTS mode.
Each of the 16 CDMA DDC blocks can be loaded with unique phase offset words.
Various synchronization signals are available which are used to synchronize the NCOs of all channels with
respect to each other. Frequency Sync and Phase Offset Sync determine when frequency and phase
offset changes occur. For example, generating a Frequency Sync after programming the two frequency
words will cause the NCO (or multiple NCOs) to change frequency at that time, rather than after each of
the three frequency words is programmed over the control bus. The Zero Phase Sync signal is used to
force the sine and cosine oscillators to their zero phase state. Dither Sync can be used to synchronize the
dither generators of multiple NCOs. The NCOs used in the transmit section are identical to what is
described for the receive section. Note that there is one set of sync’s provided for each DDC. When one
DDC is used to process two CDMA signal the sync’s are shared between them.
Sync Programming
Variable
ssel_nco(2:0)
ssel_dither(2:0)
ssel_freq(2:0)
Description
Sync source for NCO accumulator reset
Sync source for NCO dither reset
Sync source for NCO frequency register loading
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ssel_phase(2:0)
2.2.4
SLWS168 - OCTOBER 2005
Sync source for NCO phase register loading
DDC Filtering and Decimation
The purpose of the receive filter chain is to isolate the signal of interest (and reject all other others) that has
been previously translated to baseband via the mixer and NCO. The overall decimation through the chain
needs to be considered. The goal, generally, is to output the isolated signal at a rate that is twice (2X) the
signal’s chip rate. For UMTS this would be 7.68 MSPS and for CDMA the output rate should be 2.4576
MSPS. TD-SCDMA systems require the output rate be the chip rate of 1.28 MSPS. The output interface
is programmed to decimate by 2 for the TD-SCDMA case.
Receive filtering and decimation is performed in several stages:
-
Zero padding to interpolate the input sample rate (if needed) up to the rxclk rate
-
High rate decimation (4 to 32) using a six stage cascade-integrate-comb filter (CIC)
-
Decimate by two compensation filtering using the programmable compensating FIR filter (CFIR)
-
Pulse-shape filtering via the programmable FIR filter (PFIR) with no decimation
-
Output interface, serial or parallel format, with no decimation or decimate by 2
From
Mixer
Delay
Adjust
Zero Pad
Interp by {1,2,4,8}
Six Stage
CIC Filter
Dec by {4 - 32}
CFIR Filter
Dec by 2
PFIR Filter
no decimation
Output Interface
Dec by {1,2}
The table below contains some examples of decimation and sample rates at the output of each block for
UMTS, CDMA and TD -SCDMA standards at various supported input samples. For each example, the
differential ADC clocks are provided to the AFE8406 at the input sample rate and the rxclk is provided at
the zero pad output rate.
Input
Sample
Rate
(MSPS)
rxclk(MHz)
and Zero
CIC
Pad Output
Zeros
Rate
DeciAdded (MSPS)
mation
CIC
Output
Rate
(MSPS)
CFIR
Decimation
CFIR
Output
Rate
(MSPS)
PFIR
Decimation
PFIR
Output
Rate
(MSPS)
Output
Decimation
UMTS
UMTS
76.80
61.44
1
1
153.6
122.88
10
8
15.36
15.36
2
2
7.68
7.68
1
1
7.68
7.68
1
1
CDMA
CDMA
CDMA
78.6432
78.6432
61.44
0
1
1
78.6432
157.2864
122.88
16
32
25
4.9152
4.9152
4.9152
2
2
2
2.4576
2.4576
2.4576
1
1
1
2.4576
2.4576
2.4576
1
1
1
81.92
76.80
76.80
61.44
0
0
1
1
81.92
76.80
153.6
122.88
16
15
30
24
5.12
5.12
5.12
5.12
2
2
2
2
2.56
2.56
2.56
2.56
1
1
1
1
2.56
2.56
2.56
2.56
2
2
2
2
TD-SCDMA
TD-SCDMA
TD-SCDMA
TD-SCDMA
Note: The DDC output interfaces, both serial and parallel formats, can be programmed to decimate by 2. For
the TD-SCDMA examples listed above, the DDC output rate is 1.28Msps (1x chip rate).
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DDC Channel Delay Adjust and Zero Insertion
interpolation
(number of zeros stuffed between samples)
I
input rate
samples from
Q
Mixer
read offset
18
Delay Memory
I:8 slots x 18-bits
Q:8 slots x 18-bits
18
3
18
18
Zero
Pad
18
I
18
Q
full rxclk rate
samples to
CIC Filter
3
sync (offset registers)
sync (zero stuff moment)
insert offset
3
The Receive Channel Delay Adjust function is used to add programmable delays in the channel
downconvert path. Adjusting channel delay can be used to compensate for analog elements external to the
AFE8406 digital downconversion such as cables, splitters, analog downconverters, filters, etc.
The Delay Memory block consists of an 8 register memory and a state machine. The state machine uses
a counter to control the write (input) pointer, and the programmed read offset register data to create a read
(output) pointer. Programming larger read offset register values increases the effective delay at a
resolution equal to the input sample rate.
The Zero Pad block is used in conjunction with the Delay Memory for delay adjustments. For example, with
input rates of rxclk/8, the Zero Pad block interpolates the input data to rxclk by inserting 7 zeros. The Zero
Pad’s sync insert offset 3-bit control specifies when the zeros are inserted relative to the Sync signal. This
permits a fine adjustment at the rxclk resolution.
The read offset register, tadf_offset_course_a/b, and the insert offset register, tadj_offset_fine_a/b, are
double buffered. Writes to these registers may occur anytime, but the actual values used by the circuit will
not be updated until a register sync .
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Programming
Variable
tadj_offset_coarse_a(2:0)
tadj_offset_coarse_b(2:0)
tadj_offset_fine_a(2:0)
tadj_offset_fine_b(2:0)
tadj_interp(2:0)
ssel_tadj_fine(2:0)
ssel_tadj_reg(2:0)
2.2.6
Description
Read offset into the 8 element memory for the UMTS or CDMA mode A
channel DDC.
Read offset into the 8 element memory for the CDMA mode B channel
DDC when in CDMA mode.
Controls the zero pad (or stuff) insert offset (fine adjust) for the UMTS or
CDMA mode A channel of the DDC.
Controls the zero pad (or stuff) insert offset (fine adjust) for the CDMA
mode B channel of the DDC when in CDMA mode.
The interpolation value (1, 2, 4, or 8). Same used for both the A and B
channels when in CDMA mode. Selects the number of zeros to be
inserted.
Selects the sync source for the fine time adjust zero stuff moment. Same
for A and B channels when in CDMA mode.
Selects the sync source used to update the double buffer course and fine
delay selection registers. Same for A and B channels when in CDMA
mode.
DDC CIC Filter
Shift
18
Z
-1
N
Z
-1
Z - m1
Z
Z -m 2
-1
Z
Z
-1
-m 3
Z
Z -m 4
-1
Z
Z
-m 5
Z
-1
54
24
-m 6
24
Decimate
by 4-32
Sh ift
0-3 1
Round
&
L imit
18
m1, m2, m3 , m 4, m5, m6 = 1 or 2
The CIC filter provides the first stage of filtering and large-value decimation. The filter consists of six stages
and decimates over a range from 4 to 32.
I data and Q data are handled separately with two CIC filters. In addition, when in CDMA mode (two CDMA
channels processed within a single DDC), another pair of CIC filters handles the B-side channel.
The filter response is 6*(Sin(x)/x) in character where the key attribute is that the resulting response nulls
reject signal aliases from decimation. A consequence of this desirable behavior is that only a small portion
of the passband can be used, less than 25% generally. This means that the CIC decimation value should
be chosen so that the signal exiting the CIC filter is oversampled by at least a factor of four.
The filter is equivalent to 6 stages of a FIR filter with uniform coefficients (6 combined boxcar filter stages).
Each filter would be of length N if m=1, or 2N if m=2.
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The filter is made up of six banks of 54 bit accumulator sections followed by six banks of 24 bit subtractor
sections. Each of the subtractor sections can be independently programmed with a differential delay of
either one or two. A shift block follows the last integration stage and can shift the 54 bit accumulated data
down by 36-rcic_shift (a programmable factor from 0 to 31 bits).
The CIC filter exhibits a droop across its frequency response. The following CFIR filter compensates for
the CIC droop with a gradually rising frequency response. It is also possible to compensate for CIC droop
in the PFIR filter.
The gain of the receive CIC filter is:
6
(number of stages where M=2)
Ncic * 2
(-36+RCIC_SHIFT)
*2
where RCIC_SHIFT is 0 to 31.
There is no rollover protection internal to the CIC or at the final round so the user must guarantee no
sample exceeds full scale prior to rounding. For practical purposes this means the CIC gain can only
compensate for peak gain less than one or must be less than or equal to one. A fixed gain of +12 dB at the
output of the CIC can also be programmed.
Programming
Variable
cic_decim(4:0)
cic_scale_a(4:0)
cic_scale_b(4:0)
cic_gain_ddc
cic_m2_ena_a(5:0)
cic_m2_ena_b (5:0)
cic_bypass
ssel_cic(2:0)
2.2.7
Description
The CIC decimation ratio (4 to 32). The ratio is cic_decim + 1. This ratio
applies to both A and B channels of the DDC block in CDMA mode.
The shift value for the A channel. A value of 0 is no shift, each
increment in value increases the amplitude of the shifter output by a
factor of 2.
The shift value for the B channel. A value of 0 is no shift, each
increment in value increases the amplitude of the s hifter output by a
factor of 2.
When asserted, adds a gain of 12 dB at the CIC output.
Sets the differential delay value M for each of the CIC subtractor stages
for the UMTS or CDMA mode A channel.
Sets the differential delay value M for each of the CIC subtractor stages
for the CDMA mode B channel.
Bypasses the CIC filter when set, for factory use only.
Sets syncing (1 of 8 sources) for the CIC decimation moment.
DDC Compensating FIR Filter
The receive compensating FIR filter (CFIR) decimates the output of the CIC filter by a fixed factor of two.
Filter coefficient size, input data size, and output data size are 18 bits. The CFIR length can be
programmed. This permits “turning off” taps and saving power if shorter filters are appropriate (the CFIR
power dissipation is proportional to its length).
The filter is organized in two partial filter blocks, each containing a data RAM, a coefficient RAM and a dual
multiplier, a common state machine and output accumulator.
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MPU control
interface
read data
write data
write pointer
COEF
RAM
32x18
mpu
ram_read
COEF
RAM
32x18
MUX
reg
complex
output
samples
read pointer
complex
input
samples
DATA
RAM
64x36
DATA
RAM
64x36
write
pointer
read
pointer
crastarttap
State Machine
output
sample
valid
The maximum CFIR filter length is a function of AFE8406 rxclk clock rate, output sample rate and the
number of coefficient memory registers. The maximum number of taps is 64 and the minimum number is
14. Lengths between these limits can be specified in increments of 2.
Subject to the above minimum and maximum values, in the general case, the number of taps available is:
UMTS Mode: 2 * (rxclk ÷ output sample rate)
CDMA Mode if cic_decim is even (decimating by an odd number): 2 * (cic_decim)
CDMA Mode if cic_decim is odd (decimating by an even number): 2 * (cic_decim + 1)
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Example CFIR filter lengths available based on mode and rxclk frequency:
Mode
UMTS
UMTS
CDMA
CDMA
CDMA
CDMA
CDMA
CDMA
rxclk
(MHz)
153.60
122.88
157.2864
122.88
78.6432
153.60
81.92
76.80
CIC
decimation
10
8
32
25
16
30
16
15
CFIR
max length
40
32
64
48
32
60
32
28
CFIR
min length
14
14
14
14
14
14
14
14
comments
UMTS
UMTS
CDMA2000
CDMA2000
CDMA2000 low power configuration
TD-SCDMA
TD-SCDMA
TD-SCDMA low power configuration
A single set of programmed tap values are used for both the A-side and B-side DDC channels (two CDMA
channels) within a single DDC block when in CDMA mode.
After the CFIR filter performs the convolution, gain is applied at full precision, the signal is rounded, and
then hard limited. A shifter at the output of the filter then scales the data by either 2e-19 or 2e-18. The gain
through the filter is therefore:
Sum(CFIR coefficients) * 2
-(18 or 19)
Coefficients are organized in two groups of 32 words, each 18 bits wide. For fully utilized filters, the 64
coefficients are loaded 0 through 31 into the first RAM, and 32 through 63 into the second RAM. The 16
bit MSBs and 2 bit LSBs are written into the RAMs using different page register values. Shorter filters
require the coefficients be loaded into the 2 rams equally, starting from address 0.
For example, a CFIR coefficient set for a symmetric 58 tap TD -SCDMA CFIR is
taps
0 = 57
1 = 56
2 = 55
3 = 54
4 = 53
5 = 52
6 = 51
7 = 50
8 = 49
9 = 48
10 = 47
11 = 46
12 = 45
13 = 44
14 = 43
Coefficient
-13
-20
14
101
184
133
-147
-562
-768
-364
719
1905
2126
567
-2416
taps
15 = 42
16 = 41
17 = 40
18 = 39
19 = 38
20 = 37
21 = 36
22 = 35
23 = 34
24 = 33
25 = 32
26 = 31
27 = 30
28 = 29
Coefficient
-4975
-4649
-232
6581
11266
8917
-1957
-16736
-25469
-17599
11560
56455
102215
131071
The first 29 coefficients are loaded into addresses 0 through 28 in the first coefficient RAM, and the
remaining 29 are loaded into addresses 0 through 28 in the second coefficient RAM. Loading the 18 bit
coefficients requires 2 writes per coefficient, one for the upper 16 bits and another for the lower 2 bits.
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To program this coefficient set for the DDC2 CFIR, the following control microprocessor interface
sequence would be used.
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Address
a[5:0]
0x21
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x21
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Data
d[15:0]
0x0480
0x0003
0x0000
0x0002
0x0001
0x0000
0x0001
0x0001
0x0002
0x0000
0x0000
0x0003
0x0001
0x0002
0x0003
0x0000
0x0001
0x0003
0x0000
0x0001
0x0002
0x0001
0x0003
0x0000
0x0003
0x0001
0x0000
0x0003
0x0003
0x0003
0x0000
0x0000
0x0000
0x04A0
0x0003
0x0003
0x0003
0x0000
0x0001
0x0003
0x0000
0x0003
0x0001
0x0002
0x0001
0x0000
0x0003
0x0001
0x0000
0x0003
Description
Page register for DDC2 CFIR Coefficient RAM 0-31, LSBs.
2 lower bits of coefficient 0
2 lower bits of coefficient 1
2 lower bits of coefficient 2
2 lower bits of coefficient 3
2 lower bits of coefficient 4
2 lower bits of coefficient 5
2 lower bits of coefficient 6
2 lower bits of coefficient 7
2 lower bits of coefficient 8
2 lower bits of coefficient 9
2 lower bits of coefficient 10
2 lower bits of coefficient 11
2 lower bits of coefficient 12
2 lower bits of coefficient 13
2 lower bits of coefficient 14
2 lower bits of coefficient 15
2 lower bits of coefficient 16
2 lower bits of coefficient 17
2 lower bits of coefficient 18
2 lower bits of coefficient 19
2 lower bits of coefficient 20
2 lower bits of coefficient 21
2 lower bits of coefficient 22
2 lower bits of coefficient 23
2 lower bits of coefficient 24
2 lower bits of coefficient 25
2 lower bits of coefficient 26
2 lower bits of coefficient 27
2 lower bits of coefficient 28
2 lower bits of unused coefficient RAM location
2 lower bits of unused coefficient RAM location
2 lower bits of unused coefficient RAM location
Page register for DDC2 CFIR Coefficient RAM 32-63, LSBs.
2 lower bits of coefficient 29
2 lower bits of coefficient 30
2 lower bits of coefficient 31
2 lower bits of coefficient 32
2 lower bits of coefficient 33
2 lower bits of coefficient 34
2 lower bits of coefficient 35
2 lower bits of coefficient 36
2 lower bits of coefficient 37
2 lower bits of coefficient 38
2 lower bits of coefficient 39
2 lower bits of coefficient 40
2 lower bits of coefficient 41
2 lower bits of coefficient 42
2 lower bits of coefficient 43
2 lower bits of coefficient 44
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51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x21
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x21
0x00
0x01
0x02
0x03
0x04
0x0002
0x0001
0x0003
0x0000
0x0000
0x0002
0x0001
0x0001
0x0000
0x0001
0x0002
0x0000
0x0003
0x0000
0x0000
0x0000
0x04C0
0xFFFC
0xFFFB
0x0003
0x0019
0x002E
0x0021
0xFFDB
0xFF73
0xFF40
0xFFA5
0x00B3
0x01DC
0x0213
0x008D
0xFDA4
0xFB24
0xFB75
0xFFC6
0x066D
0x0B00
0x08B5
0xFE16
0xEFA8
0xE720
0xEED0
0x0B4A
0x3721
0x63D1
0x7FFF
0x0000
0x0000
0x0000
0x04E0
0x7FFF
0x63D1
0x3721
0x0B4A
0xEED0
SLWS168 - OCTOBER 2005
2 lower bits of coefficient 45
2 lower bits of coefficient 46
2 lower bits of coefficient 47
2 lower bits of coefficient 48
2 lower bits of coefficient 49
2 lower bits of coefficient 50
2 lower bits of coefficient 51
2 lower bits of coefficient 52
2 lower bits of coefficient 53
2 lower bits of coefficient 54
2 lower bits of coefficient 55
2 lower bits of coefficient 56
2 lower bits of coefficient 57
2 lower bits of unused coefficient RAM location
2 lower bits of unused coefficient RAM location
2 lower bits of unused coefficient RAM location
Page register for DDC2 CFIR Coefficient RAM 0-31, MSBs.
Upper 16 bits of coefficient 0
Upper 16 bits of coefficient 1
Upper 16 bits of coefficient 2
Upper 16 bits of coefficient 3
Upper 16 bits of coefficient 4
Upper 16 bits of coefficient 5
Upper 16 bits of coefficient 6
Upper 16 bits of coefficient 7
Upper 16 bits of coefficient 8
Upper 16 bits of coefficient 9
Upper 16 bits of coefficient 10
Upper 16 bits of coefficient 11
Upper 16 bits of coefficient 12
Upper 16 bits of coefficient 13
Upper 16 bits of coefficient 14
Upper 16 bits of coefficient 15
Upper 16 bits of coefficient 16
Upper 16 bits of coefficient 17
Upper 16 bits of coefficient 18
Upper 16 bits of coefficient 19
Upper 16 bits of coefficient 20
Upper 16 bits of coefficient 21
Upper 16 bits of coefficient 22
Upper 16 bits of coefficient 23
Upper 16 bits of coefficient 24
Upper 16 bits of coefficient 25
Upper 16 bits of coefficient 26
Upper 16 bits of coefficient 27
Upper 16 bits of coefficient 28
Upper 16 bits of unused coefficient RAM location
Upper 16 bits of unused coefficient RAM location
Upper 16 bits of unused coefficient RAM location
Page register for DDC2 CFIR Coefficient RAM 32-63, MSBs.
Upper 16 bits of coefficient 29
Upper 16 bits of coefficient 30
Upper 16 bits of coefficient 31
Upper 16 bits of coefficient 32
Upper 16 bits of coefficient 33
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106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x21
0x00
0x01
0xE720
0xEFA8
0xFE16
0x08B5
0x0B00
0x066D
0xFFC6
0xFB75
0xFB24
0xFDA4
0x008D
0x0213
0x01DC
0x00B3
0xFFA5
0xFF40
0xFF73
0xFFDB
0x0021
0x002E
0x0019
0x0003
0xFFFB
0xFFFC
0x0000
0x0000
0x0000
0x0500
0x8EE0
0x2000
SLWS168 - OCTOBER 2005
Upper 16 bits of coefficient 34
Upper 16 bits of coefficient 35
Upper 16 bits of coefficient 36
Upper 16 bits of coefficient 37
Upper 16 bits of coefficient 38
Upper 16 bits of coefficient 39
Upper 16 bits of coefficient 40
Upper 16 bits of coefficient 41
Upper 16 bits of coefficient 42
Upper 16 bits of coefficient 43
Upper 16 bits of coefficient 44
Upper 16 bits of coefficient 45
Upper 16 bits of coefficient 46
Upper 16 bits of coefficient 47
Upper 16 bits of coefficient 48
Upper 16 bits of coefficient 49
Upper 16 bits of coefficient 50
Upper 16 bits of coefficient 51
Upper 16 bits of coefficient 52
Upper 16 bits of coefficient 53
Upper 16 bits of coefficient 54
Upper 16 bits of coefficient 55
Upper 16 bits of coefficient 56
Upper 16 bits of coefficient 57
Upper 16 bits of unused coefficient RAM location
Upper 16 bits of unused coefficient RAM location
Upper 16 bits of unused coefficient RAM location
Page register for DDC2 control registers 0-31
DDC2 FIR_MODE register; cdma_mode enabled, 60 tap PFIR, 58 tap CFIR
DDC2 PFIR gain = sum(taps)*2^-18 and CFIR gain = sum(taps)*2^-19
Programming
Variable
crastarttap_cfir(4:0)
Description
Number of DDC CFIR filter taps is 2*(crastarttap + 1)
mpu_ram_read
What set, the PFIR and CFIR coefficient rams are readable via the MPU
control interface. The AFE8406 signal path is not operational when this bit
is set, it is intended for debug purposes only.
0= 2e-19, 1= 2e-18
cfir_gain
The CFIR filter’s 18 bit coefficients are loaded in two 32 word memories.
Note: CFIR filter coefficients are shared between A and B channels of a DDC block in CDMA mode.
2.2.8
DDC Programmable FIR Filter
The receive programmable FIR filter (PFIR) provides final pulse shaping of the baseband signal data. It
does not perform any decimation. Filter coefficient size, input, and output data size is 18 bits. A special
strapped mode can be employed for UMTS where two adjacent DDCs (2k & 2k+1, k=0 to 3) can be
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combined to yield a filter with twice the number of coefficients. This means the AFE8406 can support 4
UMTS DDC channels with double-length filter coefficients (up to 128 taps).
The filter is organized in four partial filter blocks, each containing a data RAM, a coefficient RAM and a
dual multiplier, a common state machine and output accumulator.
MPU control
interface
read data
write data
write pointer
Filter cell 1
cell 2
cell 3
cell 4
COEF
RAM
16x18
mpu
ram_read
MUX
reg
read pointer
from adjacent DDC
(if double_tap=“10”)
complex input
samples from cfir
(or adjacent DDC if
double_tap=“01”)
to adjacent DDC
(if double_tap =“10”)
DATA
RAM
32x36
read
pointer
write
pointer
crastarttap
complex
output
samples
State Machine
output
sample
valid
The PFIR length is programmable. This permits turning off taps and saving power if short filters are
appropriate. The filter’s output data can be shifted over a range of 0 to 7 bits where it is then rounded and
hard limited to 18 bits. The shift range results in a gain that ranges from 2e-19 to 2e-12.
-shift
The gain of the PFIR block is: sum(coefficients) * 2
, where shift ranges from 12 to 19.
The maximum PFIR filter length is a function of AFE8406 clock rate and output sample rate and is limited
by the number of coefficient memory registers. The maximum number of taps is 64 and the minimum
number is 32 (for both CDMA and UMTS). Lengths between these limits can be specified in increments of
4. For strapped UMTS with double length filters, the range of taps available is 64 to 128 in increments of 8
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Subject to the above minimum and maximum values, the number of maximum taps available is:
UMTS Mode: 4 * (rxclk ÷ output sample rate)
Strapped UMTS Mode: 8 * (rxclk ÷ output sample rate)
CDMA Mode: 2 * (rxclk ÷ output sample rate)
PFIR coefficients and gain shift values are shared between both A and B CDMA channels in a DDC block.
Example PFIR filter lengths available based on mode and rxclk frequency:
Mode
UMTS
UMTS
UMTS
rxclk
(MHz)
153.60
122.88
153.60
CIC
decimation
10
8
10
PFIR
max length
64
64
128
PFIR
min length
32
32
64
UMTS
122.88
8
128
64
CDMA
CDMA
CDMA
CDMA
CDMA
CDMA
157.2864
122.88
78.6432
153.60
81.92
76.80
32
25
16
30
16
15
64
64
64
64
64
60
32
32
32
32
32
32
comments
UMTS, 1 to 8 DDC channels
UMTS, 1 to 8 DDC channels
Strapped UMTS double length PFIR
configuration; 1 to 4 DDC channels.
Strapped UMTS double length PFIR
configuration; 1 to 4 DDC channels.
CDMA2000
CDMA2000
CDMA2000 low power configuration
TD-SCDMA
TD-SCDMA
TD-SCDMA low power configuration
Coefficients are organized in four groups of 16 words, each 18 bits wide. For fully utilized filters, the 64
coefficients are loaded 0 through 31 into the first and second RAMs, and 32 through 63 into the third and
fourth RAMs. The 16 bit MSBs and 2 bit LSBs are written into the RAMs using different page register
values. Shorter filters require the coefficients be loaded into the 4 rams equally, starting from address 0
and address 16.
For example, a PFIR coefficient set for a symmetric 60 tap TD -SCDMA PFIR is
taps
0 = 59
1 = 58
2 = 57
3 = 56
4 = 55
5 = 54
6 = 53
7 = 52
8 = 51
9 = 50
10 = 49
11 = 48
12 = 47
13 = 46
14 = 45
Coefficient
-2
1
4
-8
-2
21
-13
-28
46
1
-85
96
82
-266
38
taps
15 = 44
16 = 43
17 = 42
18 = 41
19 = 40
20 = 39
21 = 38
22 = 37
23 = 36
24 = 35
25 = 34
26 = 33
27 = 32
28 = 31
29 = 30
Coefficient
420
-331
-319
744
-440
-1005
2389
514
-6182
1845
12959
-8691
-27246
34166
131071
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The first 15 coefficients are loaded into addresses 0 through 14 in the first coefficient RAM, the second
group of 15 are loaded into addresses 16 through 30 corresponding to the second coefficient RAM, the
third group of 15 are loaded into the third coefficient ram at addresses 0 through 14, and the fourth group
of 15 are loaded into addresses 16 through 30 in the fourth coefficient RAM. Loading the 18 bit
coefficients requires 2 writes per coefficient, one for the upper 16 bits and another for the lower 2 bits.
To program this coefficient set for the DDC2 PFIR, the following control microprocessor interface sequence
would be used.
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Address
a[5:0]
0x21
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x21
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
Data
d[15:0]
0x0400
0x0002
0x0001
0x0000
0x0000
0x0002
0x0001
0x0003
0x0000
0x0002
0x0001
0x0003
0x0000
0x0002
0x0002
0x0002
0x0000
0x0000
0x0001
0x0001
0x0000
0x0000
0x0003
0x0001
0x0002
0x0002
0x0001
0x0003
0x0001
0x0002
0x0002
0x0003
0x0000
0x0420
0x0003
0x0002
0x0002
0x0001
0x0003
0x0001
0x0002
0x0002
0x0001
Description
Page register for DDC2 PFIR Coefficient RAMs 0-15 and 16-31, LSBs.
2 lower bits of coefficient 0
2 lower bits of coefficient 1
2 lower bits of coefficient 2
2 lower bits of coefficient 3
2 lower bits of coefficient 4
2 lower bits of coefficient 5
2 lower bits of coefficient 6
2 lower bits of coefficient 7
2 lower bits of coefficient 8
2 lower bits of coefficient 9
2 lower bits of coefficient 10
2 lower bits of coefficient 11
2 lower bits of coefficient 12
2 lower bits of coefficient 13
2 lower bits of coefficient 14
2 lower bits of unused coefficient RAM location
2 lower bits of coefficient 15
2 lower bits of coefficient 16
2 lower bits of coefficient 17
2 lower bits of coefficient 18
2 lower bits of coefficient 19
2 lower bits of coefficient 20
2 lower bits of coefficient 21
2 lower bits of coefficient 22
2 lower bits of coefficient 23
2 lower bits of coefficient 24
2 lower bits of coefficient 25
2 lower bits of coefficient 26
2 lower bits of coefficient 27
2 lower bits of coefficient 28
2 lower bits of coefficient 29
2 lower bits of unused coefficient RAM location
Page register for DDC2 PFIR Coefficient RAMs 32-47 and 48-63, LSBs.
2 lower bits of coefficient 30
2 lower bits of coefficient 31
2 lower bits of coefficient 32
2 lower bits of coefficient 33
2 lower bits of coefficient 34
2 lower bits of coefficient 35
2 lower bits of coefficient 36
2 lower bits of coefficient 37
2 lower bits of coefficient 38
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44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x21
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x0003
0x0000
0x0000
0x0001
0x0001
0x0000
0x0000
0x0002
0x0002
0x0002
0x0000
0x0003
0x0001
0x0002
0x0000
0x0003
0x0001
0x0002
0x0000
0x0000
0x0001
0x0002
0x0000
0x0440
0xFFFF
0x0000
0x0001
0xFFFE
0xFFFF
0x0005
0xFFFC
0xFFF9
0x000B
0x0000
0xFFEA
0x0018
0x0014
0xFFBD
0x0009
0x0000
0x0069
0xFFAD
0xFFB0
0x00BA
0xFF92
0xFF04
0x0255
0x0080
0xF9F6
0x01CD
0x0CA7
0xF783
0xE564
0x215D
0x7FFF
SLWS168 - OCTOBER 2005
2 lower bits of coefficient 39
2 lower bits of coefficient 40
2 lower bits of coefficient 41
2 lower bits of coefficient 42
2 lower bits of coefficient 43
2 lower bits of coefficient 44
2 lower bits of unused coefficient RAM location
2 lower bits of coefficient 45
2 lower bits of coefficient 46
2 lower bits of coefficient 47
2 lower bits of coefficient 48
2 lower bits of coefficient 49
2 lower bits of coefficient 50
2 lower bits of coefficient 51
2 lower bits of coefficient 52
2 lower bits of coefficient 53
2 lower bits of coefficient 54
2 lower bits of coefficient 55
2 lower bits of coefficient 56
2 lower bits of coefficient 57
2 lower bits of coefficient 58
2 lower bits of coefficient 59
2 lower bits of unused coefficient RAM location
Page register for DDC2 PFIR Coefficient RAMs 0-15 and 16-31, MSBs.
Upper 16 bits of coefficient 0
Upper 16 bits of coefficient 1
Upper 16 bits of coefficient 2
Upper 16 bits of coefficient 3
Upper 16 bits of coefficient 4
Upper 16 bits of coefficient 5
Upper 16 bits of coefficient 6
Upper 16 bits of coefficient 7
Upper 16 bits of coefficient 8
Upper 16 bits of coefficient 9
Upper 16 bits of coefficient 10
Upper 16 bits of coefficient 11
Upper 16 bits of coefficient 12
Upper 16 bits of coefficient 13
Upper 16 bits of coefficient 14
Upper 16 bits of unused coefficient RAM location
Upper 16 bits of coefficient 15
Upper 16 bits of coefficient 16
Upper 16 bits of coefficient 17
Upper 16 bits of coefficient 18
Upper 16 bits of coefficient 19
Upper 16 bits of coefficient 20
Upper 16 bits of coefficient 21
Upper 16 bits of coefficient 22
Upper 16 bits of coefficient 23
Upper 16 bits of coefficient 24
Upper 16 bits of coefficient 25
Upper 16 bits of coefficient 26
Upper 16 bits of coefficient 27
Upper 16 bits of coefficient 28
Upper 16 bits of coefficient 29
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99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
0x1F
0x21
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x21
0x00
0x01
0x0000
0x0460
0x7FFF
0x215D
0xE564
0xF783
0x0CA7
0x01CD
0xF9F6
0x0080
0x0255
0xFF04
0xFF92
0x00BA
0xFFB0
0xFFAD
0x0069
0x008D
0x0009
0xFFBD
0x0014
0x0018
0xFFEA
0x0000
0x000B
0xFFF9
0xFFFC
0x0005
0xFFFF
0xFFFE
0x0001
0x0000
0xFFFF
0x0000
0x0500
0x8EE0
0x2000
SLWS168 - OCTOBER 2005
Upper 16 bits of unused coefficient RAM location
Page register for DDC2 PFIR Coefficient RAMs 32-47 and 48-63, MSBs.
Upper 16 bits of coefficient 30
Upper 16 bits of coefficient 31
Upper 16 bits of coefficient 32
Upper 16 bits of coefficient 33
Upper 16 bits of coefficient 34
Upper 16 bits of coefficient 35
Upper 16 bits of coefficient 36
Upper 16 bits of coefficient 37
Upper 16 bits of coefficient 38
Upper 16 bits of coefficient 39
Upper 16 bits of coefficient 40
Upper 16 bits of coefficient 41
Upper 16 bits of coefficient 42
Upper 16 bits of coefficient 43
Upper 16 bits of coefficient 44
Upper 16 bits of unused coefficient RAM location
Upper 16 bits of coefficient 45
Upper 16 bits of coefficient 46
Upper 16 bits of coefficient 47
Upper 16 bits of coefficient 48
Upper 16 bits of coefficient 49
Upper 16 bits of coefficient 50
Upper 16 bits of coefficient 51
Upper 16 bits of coefficient 52
Upper 16 bits of coefficient 53
Upper 16 bits of coefficient 54
Upper 16 bits of coefficient 55
Upper 16 bits of coefficient 56
Upper 16 bits of coefficient 57
Upper 16 bits of coefficient 58
Upper 16 bits of coefficient 59
Upper 16 bits of unused coefficient RAM location
Page register for DDC2 control registers 0-31
DDC2 FIR_MODE register; cdma_mode enabled, 60 tap PFIR, 58 tap CFIR
DDC2 PFIR gain = sum(taps)*2^-18 and CFIR gain = sum(taps)*2^-19
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Programming
Variable
crastarttap_pfir(4:0)
cdma_mode
mpu_ram_read
pfir_gain(2:0)
double_tap(1:0)
Description
Number of DDC PFIR filter taps is 4*(crastartap+1)
For double length PFIR the number of taps is 8*(crastartap+1)
When set, puts the CFIR & PFIR blocks in CDMA mode.
What set, the PFIR and CFIR coefficient rams are readable via the MPU
control interface. The AFE8406 signal path is not operational when this bit is
set, it is intended for debug purposes only.
Sets the gain of the PFIR filter.
The range is from 2e-19 to 2e-12; “000”= 2e-19 and “111”= 2e -12
When set, puts two adjacent DDC (2k & 2k+1, k=0 to 3) in double length (from
64 to128 tap) UMTS mode.
Set to “00” for normal mode.
In double tap mode, data out of the last PFIR ram in the main DDC (DDC0,
DDC2, DDC4 or DDC6) is sent to the adjacent secondary DDC (DDC1, DDC3,
DDC5 or DDC7) PFIR as input thus forming a 128-tap delay line. Data
received from the adjacent PFIR summers is added into the Main DDC’s PFIR
sum to form the final output.
When using double tap mode, set double_tap to “10” for the main DDC, and to
“01” for the secondary DDC.
When in double tap mode, the first half of the coefficients should be loaded
into the main DDC (DDC0, DDC2, DDC4 or DDC6), the remaining coefficients
are loaded into the secondary DDC (DDC1, DDC3, DDC5 or DDC7).
In double tap mode, the main DDC must be turned on (ddc_ena=1), and the
secondary DDC must be turned off (ddc_ena=0).
The PFIR filter’s 18 bit coefficients are loaded in four 16 word memories.
Note: PFIR filter coefficients are shared between A and B channels of a DDC block when in CDMA mode.
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SLWS168 - OCTOBER 2005
DDC RMS Power Meter
18
I
36
37
18
Q
55-bit
Integrator
RMS power
55-bit
Register
36
clear
8-bit
sync delay
counter
sync
18-bit
interval
counter
8
18-bit
integration
counter
8
delay
(in samples)
transfer
interrupt
16
interval
(in 1024 sample
increments)
interrupt
integration
(in 4 sample
increments)
interrupt
interrupt
sync
delay
integration time
integration time
interval time
sync
event
integration
start
integration time
interval time
integration
start
integration
start
Each DDC channel includes an RMS power meter which is used to measure the total power within the
channel pass band.
The power meter samples the I and Q data stream after the PFIR filter. Both 18 bit I and Q data are
squared, summed, and then integrated over a period determined by a programmable counter. The
integration time is a 16 bit word which is programmed into the 18 bit counter.
There is a programmable 18 bit interval timer which sets the interval over which power measurements are
made. The timer counts in increments of 1024 samples. This allows the user to select intervals from 1 x
1024 samples up to 256 x 1024 samples. For UMTS systems with sample rate rate at 7.68MHz, the power
meter interval range is from 133uS to 34.1mS. For a CDMA system with the sample rate at 2.4576MHz,
the power meter interval range is 417uS to 107mS.
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The power measurement process starts with a sync event. The integration will start at sync event + 3 chips
+ sync_delay. The 8 bit delay register permits delays from 1 to 256 samples after sync. The integration will
continue until the integration count is met. At that point, the result in the 55 bit accumulator is transferred to
the read holding register and an interrupt is generated indicating the power value is ready to read. The
interval counter continues until the programmed interval count is reached. When reached, the integration
counter and the interval counter start over again. Each time the integration count is reached, the 55 result
bits are again transferred to the read register overwriting the previous value and an interrupt is generated
signifying the data is ready to be read. Failure to read the data timely will result in overwriting the previous
interval measurement.
Sync starts the process. Whenever a sync is received, all the counters are reset to zero no matter what the
status.
For UMTS, I and Q are calculated and the integrated power is read. When in CDMA mode the power is
calculated for both the A ( Signal ) path and the B ( Diversity) signal. As a result, there are two 55-bit words
representing the Signal and Diversity when in CDMA mode.
The power read is:
2
2
power = [ (I + Q )* (X*4 + 1) ]
where X is the integration count.
Programming
Variable
pmeter_result_a(54:0)
pmeter_result_b(54:0)
pmeter_sqr_sum_ddc(15:0)
pmeter_sync_delay_ddc(7:0)
pmeter_interval_ddc(7:0)
ssel_pmeter(2:0)
pmeter_sync_disable
Description
55 bit UMTS or CDMA mode A channel power
measurement result.
55 bit CDMA mode B channel power measurement
result.
Integration (square and sum) count in increments of
four samples.
Sync delay count in samples.
The measurement interval in increments of 2048
samples. This value must be greater than SQR_SUM.
Sync source selection.
Turns off the sync to the channel power meter. This can
be used to individually turn off syncs to a channels
power meter while still having syncs to other power
meters on the chip.
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2.2.10 DDC AGC
I, Q
limit &
round
18
18
I, Q outputs (up to 25-bits in AGC bypass mode)
threshold zero mask
12 integer &
12 fractional
8
24
magnitude
8
4
compare
shift
29
accumulate
ocnt
8
2
clear
Freeze
(from register bit
Freeze
(from sync source)
ucnt
4
29
amin
16
limit
dzro dsat
4
4
2
under/over
detect
amax
16
dblw dabv
4
4
shift select
S=+/-1, D=4-bit shift
24
min limit
max limit
Gain
gain adjust
24
The AFE8406 automatic gain control circuit is shown above. The basic operation of the circuit is to multiply
the 18 bit input data from the PFIR by a 24-bit gain word that represents a gain or attenuation in the range
of 0 to 4096. The gain format is mixed integer and fraction. The 12-bit integer allows the gain to be boosted
by up to factor of 4096 (72 dB). The 12-bit fractional part allows the gain to be adjusted up or down in
steps of one part in 4096, or approximately 0.002 dB. If the integer portion is zero, then the circuit
attenuates the signal. The gain adjusted output data is saturated to full scale and then rounded to between
4 and 18 bits in steps of one bit.
The AGC portion of the circuit is used to automatically adjust the gain so that the “median” magnitude of
the output data matches a target value, which is performed by comparing the magnitude of the output data
with a target threshold. If the magnitude is greater than the threshold, then the gain is decreased,
otherwise it is increased. The gain is adjusted as: G(t) = G + A(t), where G is the default, user supplied
-D
gain value, and A(t) is the time varying adjustment. A(t) is updated as A(t) = A(t) + G(t)*S*2 , where S=1
if the magnitude is less than the threshold and is -1 if the magnitude exceeds the threshold, and where D
sets the adjustment step size. Note that the adjustment is a fraction of the current gain. This is designed to
set the AGC noise level to a known and acceptable level while keeping the AGC convergence and tracking
-D
rate constant, independent of the gain level. The AGC noise will be equal to +- 2 and the AGC attack and
decay rate will be exponential, with a time constant equal to 2-D. Hence, the AGC will increase or decrease
D
by 0.63 times G(t) in 2 updates.
If one assumes the data is random with a Gaussian distribution, which is valid for UMTS if more than 12
users with different codes have been overlaid, then the relationship between the RMS level and the
median is MEDIAN = 0.6745*RMS, hence the threshold should be set to 0.6745 times the desired RMS
level.
The gain step size can be set using four different values of “D”, each of which is a 4 bit integer. D can
range from 3 to 18. The user can specify values of D for different situations, ie, when the signal magnitude
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is below the user-specified threshold (Dblw), is above the threshold (Dabv), is consistently equal to zero
(Dzro) or is consistently equal to maximum (Dsat). It is important to note that D represents a gain step size.
Smaller values of D represent larger gain steps. The definition of “equal to zero” is any number when
masked by zero_mask is considered to be zero. This permits consistently very small amplitude signals to
have their gain increased rapidly.
Separate programmable D values allow the user to set different attack and decay time constants, and to
set shorter time constants for when the signal falls too low (equal to zero), or is too high (saturates). The
magnitude is considered to be consistently equal to zero by using a 4-bit counter that counts up every time
the 8-bit magnitude value is zero, and counts down otherwise. If the counter’s value exceeds a user
specified threshold, then “Dabv” is used. Similarly the magnitude is considered too high by using a counter
that counts up when the magnitude is maximum, and counts down otherwise. If this counter exceeds
another user specified threshold, then “Dsat” is used.
As an example, if the AGC’s current gain at a particular moment in time is 5.123, and the magnitude of the
signal is greater than zero, but less than the user-programmed threshold. Step size Dblw will be used to
modify the gain for the next sample. This represents the AGC attack profile. If Dblw is set to a value of 5,
-5
then the gain for the next sample will be 5.123 + 5.123 x 2 = 5.123 + 0.160 = 5.283. If the signal’s
magnitude is still less than the user-programmed threshold, then the gain for the next sample will be 5.283
-5
+ 5.283 x 2 = 5.283 + 0.165 = 5.448. This continues until the signal’s magnitude exceeds the userprogrammed threshold. When the magnitude exceeds threshold (but is not saturated), then step size Dabv
is automatically employed as a size rather than Dblw.
The AGC converges linearly in dB with a step size of 40log(1+2^-D) when the error is greater than 12 dB
(I.E. the gain is off by 12 dB or more). Within 6dB the behavior is approximately a exponential decay with a
time constant of 2^(D-0.5) samples.
The suggested value of D is 5 or 6 when the error is greater than 12dB (i.e., in the fast range detected by
consistently zero or saturated data). This gives a step size of 0.5 or 0.25 dB per sample.
The suggested value when the gain is off by less than 12dB is D=10, giving a exponential time constant for
delay of around 724 samples (63% decay every 724 samples).
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AGC GAIN ERROR
7
D=3
D=4
6
D=5
5
D=6
D=7
D=8
D=9
4
D=10
3
D=11
D=12
2
D=13
D=14
D=15
D=3
1
D=18
D=16
D=17
D=18
0
1
10
100
1000
10000
100000
1000000
SAMPLES
The AGC noise once the AGC has converged is a random error of amplitude +/-2^-D relative to the RMS
signal level. This means that the error level is -6*D dB below the signal RMS level. At D=10 (-60dB) the
error is negligible. The plot above shows the AGC response for vales of D ranging from 3 to 18. “Error dB”
represents the distance the signal level is from the desired target threshold.
The AGC is also subject to user specified upper and lower adjustment limits. The AGC stops incrementing
the gain if the adjustment exceeds Amax. It stops decrementing the gain if the adjustment is less than
Amin.
The input data is received with a valid flag that is high when a valid sample is received. For complex data
the I and Q samples are on the same data input line and are not treated independently. An adjustment is
made for the magnitude of the I sample, and then another adjustment is made for the Q sample.
The AGC operates on UMTS and CDMA data. When in UMTS mode the I and Q data are each used to
produce the AGC level. There is no separate I path gain and Q path gain. When in CDMA mode there are
separate gain levels for the Signal and Diversity I and Q data. The I and Q for A (or the Signal ) pair is
calculated and then the I' and Q' for the B (or Diversity) pair is calculated.
There is a freeze mode for holding the accumulator at its current level. This will put the AGC in a hold
mode using the user-programmed gain along with the current gain_adjust value. To only use the user
programmed gain value as the gain, set the freeze bit and then clear the accumulator. When using the
freeze bit the full 25 bit output is sent out of the AGC block to support transferring up to 25 bits when the
AGC is disabled.
For TDD applications, freeze mode can be controlled using a sync source. This allows rxsync_a/b/c/d to
be assigned as a AGC hold signal to keep the AGC from responding during the transmit interval and run
during the receive interval. The freeze register bit is logically Ored with the freeze sync source.
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The current AGC gain and state can also be optionally output with the DDCs I and Q output data by setting
the gain_mon variable. When in this mode, the top 14 bits of the current AGC gain word are appended to
the 8 bit AGC-modified I and Q output data.
Output
I
Q
Bits(17:10)
I output data
Q output data
Bits(9:4)
Bits(3:2)
Gain(23:16)
Gain(15:10)
AGC State(1:0)
Bits(1:0)
“00”
“00”
Programming
Variable
agc_dblw(3:0)
agc_dabv(3:0)
agc_dzro(3:0)
agc_dsat (3:0)
agc_zero_msk(3:0)
agc_md(3:0)
agc_thresh(7:0)
agc_rnd_disable
agc_freeze
agc_clear
agc_gaina(23:0)
agc_gainb(23:0)
agc_zero_cnt(3:0)
agc_max_cnt(3:0)
agc_amax(15:0)
agc_amin(15:0)
gain_mon
Description
Below threshold gain. Sets the value of gain step size Dblw (data * current
gain below threshold). Ranges from 3 to 18, and maps to a 4 bit field. For
example: 3 = “0000”, 4= “0001”, … 18= “1111”
Above threshold gain. Sets the value of gain step size Dabv (data * current
gain above threshold). Ranges from 3 to 18, and maps to a 4 bit field. For
example: 3 = “0000”, 4= “0001”, … 18= “1111”
Zero signal gain. Sets the value of gain step size Dzro (data * current gain
consistently zero). Ranges from 3 to 18, and maps to a 4 bit field. For
example: 3 = “0000”, 4= “0001”, … 18= “1111”
Saturated signal gain. Sets the value of gain step size Dsat (data * current
gain consistently saturated). Ranges from 3 to 18, and maps to a 4 bit field.
For example: 3 = “0000”, 4= “0001”, … 18= “1111”
Masks the lower 4 bits of signal data so as to be considered zeros.
AGC rounding. 0000= 18 bits out, 1111= 3 bits out.
AGC threshold. Compared with magnitude of 8 bits of input * gain.
AGC rounding is disabled when this bit is set.
The AGC gain adjustment updates are disable when set.
The AGC gain adjustment accumulator is cleared when set
24 bit gain word for DDC A
24 bit gain word for DDC B (in CDMA mode)
When the AGC output (input * gain) is zero value this number of times, the
shoft value is changed to agc_dzero.
When the AGC output (input * gain) is zero value this number of times, the
shift value is changed to agc_dsat.
The maximum value that gain can be adjus ted up to. Top 12 bits are integer,
bottom 4 bits are fractional.
The minimum value that gain can be adjusted down to. Top 12 bits are
integer, bottom 4 bits are fractional.
When set, combines current AGC gain with I and Q data. The 18 bit output
format thus becomes:
I Portion: 8 bits of AGC’d I data - Gain(23:16) - 00
Q Portion: 8 bits of AGC’d Q data - Gain(15:10) - Status(1:0) - 00.
ssel_agc_freeze(2:0)
ssel_gain(2:0)
ssel_ddc_agc(2:0)
Note: Bit 0 of Status, when set, indicates the data is saturated. Bit 1 of
Status, when set, indicates the data is zero.
Sync selection for freeze mode, 1 of 8 sources. This source is ORed with
the freeze register bit
Sync selection for the double buffered agc_gaina and agc_gainb register.
Sync selection used to initialize the AGC, primarily for test purposes.
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2.2.11 DDC Output Interface
The baseband I/Q sample interface can be configured as serial or parallel formatted data. The serial
interface closely matches the GC5316 style interface. The parallel interface is provided to interface directly
to the TMS320TCI110 when delayed antenna streams used to implement channel estimation buffering
and/or transport format combination indicator (TFCI) buffering are not required.
The DDC output data is 2’s complement format.
2.2.11.1 Serial Output Interface
Serial Outputs
UMTS
rxout_X_a
I ch A
I msb
DDC Block
rxout_X_b
I ch B
I msb-1
I msb-1
1 UMTS mode channel or
2 CDMA mode channels
rxout_X_c
Q ch A
Q msb
I msb-2
rxout_X_d
Q ch B
Q msb-1
I msb-3
sync
clkdiv
frame
strobe
delay
4
2
double length
PFIR UMTS
I msb
CDMA
rx_sync_out_X
Q msb
four outputs from
adjacent DDC block
Q msb-1
Q msb-2
Q msb-3
Each DDC block can be assigned four serial output data pins. These pins are used to transfer
downconverted I/Q baseband data out of the AFE8406 for subsequent processing. The usage of these
pins changes depending on how the DDC block is configured.
When the block is configured for two CDMA channels, a pair of serial data pins provides separate I and Q
data output for the two DDC channels. Word size is selectable from 4 to 25 bits with the most significant bit
first.
When the DDC block is configured for a single UMTS channel, even and odd I and Q data drive the four
serial pins separately, most significant bit first.
Four serial pins each for I and Q data can be optionally employed (instead of two for I and two for Q) at half
the output rate. This would most likely be used when two DDC channels (2k & 2k + 1, k= 0 to 3) are
combined to support double-length PFIR filtering (a channel is sacrificed). Formatting for I data is then:
Imsb, Imsb-1, Imsb-2, Imsb-3. Q data formatting is: Qmsb, Qmsb-1, Qmsb-2, Qmsb-3.
The frame strobe signal provided on the rx_sync_out_X pins can be programmed to arrive from 0 to 3 bit
clocks early via a 2 bit control parameter. The frame interval can be programmed from 1 to 63 bits. A
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programmable 4-bit clock divider circuit is used to specify the serial bit rate. The clock divider circuit is
synchronized using a sync block discussed later in this document.
Programming the serial port clock divider requires some thought and depends upon the channel’s overall
decimation ratio, frame sync interval, number of output bits, and CDMA-UMTS mode.
In general:
the serial clock divide ratio * the frame sync interval = the total receive decimation
The relationship between the number of serial bits output, clock divide ratio, and overall decimation ratio is:
CDMA: [overall decimation * (pser_recv_8pin + 1) ] / (pser_recv_clkdiv + 1) > pser_recv_bits + 1
UMTS: 2 * [overall decimation * (pser_recv_8pin + 1) ] / (pser_recv_clkdiv + 1) > pser_recv_bits + 1
where overall decimation = CIC decimation * CFIR decimation
Decimation by 2 in the output interface can be achieved by setting the frame strobe interval and clock
divider to 1/2 the PFIR output rate. The serial interface samples the PFIR output each time the transfer
interval defined by these two settings has completed. The decimation moment can be controlled using the
rxsync_X input signal selected as the sync source for the serial interface.
The timing diagram below shows the DDC serial output timing.
tsetup
tpd
thold
rxclk
rxsync_X
rxsync_X can be a pulse or level - interface will generate periodic frame strobes using programmed frame sync interval
rxsync_out_X
3 rxclk + 1 Programmed bit time
rxout_X_Y
Programmed bit time
(2 rxclk cycles for this example)
MSB
Programming
Variable
Description
pser_recv_fsinvl(6:0)
pser_recv_bits(4:0)
pser_recv_clkdiv(3:0)
Frame sync interval in bits
Number of data output bits - 1. ie: 10001= 18 bits
Receive serial interface clock divider rate - 1.
0= rxclk, 15= rxclk/16
pser_recv_8pin
When set, configures the serial out pins for 4I and 4Q in UMTS
mode. When clear, the mode is 2I and 2Q. Used in conjunction
with pser_recv_alt.
pser_recv_alt
When set, outputs Q data from adjacent DDC channel.
pser_recv_fsdel(1:0)
Number of bit clocks the frame sync is output early with respect to
serial data.
ssel_serial(2:0)
Sync source selection, 1 of 8.
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Tristate controls for the rx_sync_out_X and rxout_X_X pins. Pins
are in tristate when the tristate register bits are set.
2.2.11.2 Parallel Output Interface
DDC5
DDC4
rx_sync_out_6
par_sync_out
rxclk_out
rxclk_out
rxout_7_d
rxout_7_c
rxout_7_b
I(15)
I(14)
I(13)
rxout_4_b
rxout_4_a
I(1)
I(0)
rxout_3_d
rxout_3_c
rxout_3_b
Q(15)
Q(14)
Q(13)
rxout_0_b
rxout_0_a
Q(1)
Q(0)
Output
format
DDC3
DDC2
DDC1
Parallel I/Q
DDC0
When a parallel I/Q interface is required, a 32 bit time division multiplexed output mode can be selected
using the rxout_X_X pins. This interface is provided for direct connection to the TMS320TCI110 Receive
Chip Rate ASSP when delayed antenna streams are not required. The output sample rate, rxclk_out clock
polarity, par_sync_out position and number of channels to be output are all programmable.
rxclk_out
par_sync_out
Parallel I/Q
IQ DDC0
IQ DDC1
IQ DDC2
IQ DDC3
IQ DDC4
IQ DDC5
The DDC channel serial interface synchronization source selections should all be programmed to the same
value when using this parallel output interface (each DDC channel ssel_serial(2:0) in the SYNC_0 register
should be programmed to the same rxsync_A/B/C/D value).
Decimation by 2 in the output interface can be achieved by setting the frame strobe interval and clock
divider to 1/2 the PFIR output rate. The parallel interface samples the PFIR outputs each time the transfer
interval defined by these two settings has completed.
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Programming
Variable
Description
par_recv_fsinvl(6:0)
par_recv_clkdiv(6:0)
par_recv_chan(3:0)
par_recv_sync_del(6:0)
rx_sync_out (frame strobe) sync interval. 0 is 1 rxclk cycle and 127 is 128 rxclk cycles.
rxclk_out cycles per IQ channel sample; 1 is full rate, 2 is rxclk/2, etc.
Number channels to be output. 0 is 1 channel, and 15 is 16 channels.
delays the DDC0 pser sync source to establish the timing of IQ DDC0. Increasing the
value delays the par_sync_out location.
delays the rx_sync_out position with respect to IQ DDC0. Setting to 0 moves the
rx_sync_out pulse one rxclk_out cycle before the IQ DDC0 word, setting to 1 places it as
shown above, lined up with IQ DDC0, etc.
rxclk_out polarity. Outputs data on falling edges when cleared, rising edges when set.
parallel interface par_sync_out polarity. 0 is active low, 1 for active high
Parallel TCI110 style interface enabled when set, serial interface enabled when cleared.
DDC channel serial interface sync source selection. All DDCs should be programmed to
the same sync source when using this parallel output interface.
When set, the parallel output data includes 8b I at I(15:8), 8b Q at Q(15:8), 14b AGC gain
at I(7:0) & Q(7:2) and 2b AGC state at Q(1:0).
Tristate controls for the rx_sync_out_X and rxout_X_X pins. Pins are in tristate when the
tristate register bits are set.
par_recv_syncout_del(3:0)
par_recv_rxclk_pol
par_recv_sync_pol
par_recv_ena
ssel_serial(2:0)
gain_mon
tristate(6:3)
2.2.12 DDC Checksum Generator
The checksum generator is used in conjunction with the input test signal generator to implement a self test
capability.
sync
rxclk
rxout_X_a
rxout _X_b
rxout_X_c
rxout _X_d
checksum
generator
16
checksum read-only
results updated on
each sync event
results
register
initialized on sync event to “0000 0000 0000 0010”
15
14
1312
11
10
9
3
2 1
0
rxout_X_a
rxout_X_b
rxout_X_c
rxout_X_d
The sync for the checksum generator is internally connected to the ddc_counter output.
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Programming
3
Variable
Description
ddc_chk_sum(15:0)
Read only DDC channel checksum results
AFE8406 General Control
The AFE8406 is configured over a bi-directional 16 bit parallel data microprocessor control port. The
control port permits access to the control registers which configure the chip. The control registers are
organized using a paged-access scheme using 6 address lines. Half of the 64 addresses (Address 32
through Address 63) represent global registers. The other 32 (Address 0 through Address 31) are paged
resisters. This arrangement permits accessing a large number of control registers using relatively few
address lines.
Global registers (Address 32 through Address 63) are used to read/write AFE8406 parameters that are
global in nature and can benefit from single read/write operations. Examples include chip status, reset,
sync options, checksum ramp parameters, interrupt sources, interrupt masks, tri-state controls and the
page register.
Global Address 33 is the page register. Writing a 16 bit value to this register sets the page to which future
write or read operations performed. These paged-registers contain the actual parameters that configure
the chip and are accessed by writing/reading address 0 through address 31.
The global tristate register can be used to tristate the output drivers on the AFE8406, and also includes the
capability of disabling the chip’s internal rxclk.
Programming
Variable
Description
rxclk_ena
Enables the internal rxclk when set. When cleared, the AFE8406 will ignore the
rxclk input signal and hold the internal clock low.
Various output pins are forced into tristate mode when these bits are asserted.
See the GBL_TRISTATE register description for pin groups to bit assignments.
When asserted, the internal datapath is held reset. The control register
programming is not affected.
tristate(10:0)
arst_func
3.1
Microprocessor Interface Control Data, Address, and Strobes
The microprocessor control bus consists of 16 bi-directional control data lines d[15:0], 6 address lines
a[5:0], a read enable line rd_n, a write enable line wr_n, and a chip enable line ce_n. These lines usually
interface to a microprocessor or DSP chip and is intended to look like a block of memory.
The interface can be operated in a 3 pin control mode (using rd_n, wr_n and ce_n) or 2 pin control mode
(using wr_n and ce_n with rd_n always low).
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MPU Timing diagrams:
tREC
ce_n
wr_n
rd_n
tCSU
tHIZ
a[5:0]
t CDLY
d[15:0]
tCOH
valid data
Read Operation – 3 pin control mode
tREC
ce_n
wr_n
t CSU
tHIZ
a[5:0]
tCDLY
d[15:0]
t COH
valid data
Read Operation – 2 pin control mode (rd_n tied low)
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tREC
ce_n
tCSPW
wr_n
tCSU
rd_n
a[5:0]
tCHD
d[15:0]
valid data
tEWCSU
Write Operation – 3 pin control mode
t REC
ce_n
tCSPW
wr_n
tCSU
a[5:0]
tCHD
d[15:0]
valid data
t EWCSU
Write Operation – 2 pin control mode (rd_n tied low)
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Synchronization Signals
Various function blocks within the AFE8406 need to be synchronized in order to realize predictable results.
The AFE8406 provides a flexible system where each function block that requires synchronization can be
independently synchronized from either device pins or from a software “one-shot”. The one-shot option is
setup and triggered through control registers. The four sync input pins, rxsync_a, rxsync_b, rxsync_c and
rxsync_d are qualified on the rxclk rising clock edge.
The table below shows the different sync modes available:
Sync Select Code
000
001
010
011
100
101
110
111
Receive Sync Source
rxsync_a
rxsync_b
rxsync_c
rxsync_d
ddc sync counter terminal count
ddc sync triggered by s/w oneshot (register bit)
0 (always off)
1 (always on)
The tables below summarizes the blocks which have functions that can be synchronized using the above
eight sync source options:
Receive Common Syncs
Sync Name
sync_ddc_counter
sync_ddc
sync_rxsync_out
sync_adc_fifo
sync_tst_decim
sync_recv_pmeterX
sync_ragc_interval_X
sync_ragc_freeze_X
sync_ragc_clear_X
Purpose
Initializes the receive sync counter
Initializes the receive ADC interface & clock generation circuits
selects sync signal to be output on the rx_sync_out pin.
Initializes the input and output pointers in the ADC fifo circuits.
Initializes the testbus decimation counter.
Initializes the rxin power meters. {X = 0,1,2 or 3}
Initializes the rxin receive AGC timers. {X = 0,1,2 or 3}
rxin receive AGC freeze mode control. {X = 0,1,2 or 3}
Initializes the receive AGC error accumulator. {X = 0,1,2 or 3}
DDC Channel Syncs
Sync Name
sync_ddc_tadj
sync_ddc_tadj_reg
sync_ddc_nco
sync_ddc_freq
sync_ddc_phase
sync_ddc_dither
sync_ddc_cic
sync_ddc_pmeter
sync_ddc_gain
sync_ddc_agc
sync_ddc_agc_freeze
sync_ddc_serial
Purpose
Selects zero stuff moment in the tadj fine adjustment section.
Updates the tadj output pointer register delay in the tadj coarse adjustment section.
Resets the NCO accumulator.
Updates the NCO freq registers.
Updates the NCO phase register.
Initializes the NCO dither circuits.
Selects the CIC decimation moment.
Initializes the receive channel power meters.
Updates the DDC channel AGC gain registers
Initializes the AGC accumulator.
AGC freeze mode control.
Initializes the receive serial interface.
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A 32-bit general purpose timer is included in the synchronization function. The timer loads the user
programmed terminal count on a sync event, and counts down to zero using rxclk. The width of the
terminal count pulse can also be programmed up to rxclk cycles. The timers output can be used as a sync
source for any other circuits requiring a sync if desired, and can also be routed to the rx_sync_out pin.
Programming
3.4
Variable
Description
ddc_counter(31:0)
ddc_counter_width(7:0)
ssel_ddc_counter(2:0)
ssel_rxsync_out(2:0)
tristate(0)
rx_oneshot
32-bit programmable terminal count
8-bit programmable terminal count pulse width
Sync source selection for the ddc counter
Sync source selection for the rx_sync_out pin
When set, the interrupt and rx_sync_out pins are tristated.
Register bit used to generate the S/W oneshot signal for sync.
This bit must be programmed from cleared to set in order to
generate a rising edge sync signal.
Interrupt Handling
When a AFE8406 block sets an interrupt, the interrupt pin will go active
masked. The microprocessor should then read the interrupt register to
interrupt. The microprocessor will then have to write the interrupt register to
interrupt source. The interrupt register and interrupt mask are located in the
control registers.
if the interrupt source is not
determine the source of the
clear the interrupt pin and the
global registers section of the
The AFE8406 has 16 interrupt sources; power meters in each of the eight DDC blocks, power meters in
the four receive input interface, and four rxin_X_ovr (adc overflow) input pins where X={a,b,c,d}.
Programming
Variable
Description
pmeterX_im (7:0)
recv_pmeterX_im(3:0)
rxin_X_ovr_im
pmeterX(7:0)
recv_pmeterX(3:0)
rxin_X_ovr
intr_clr
Channel pmeter interrupt mask bits. Interrupt source is masked when set.
Receive input power meter interrupt masks.
ADC overflow input pin interrupt masks.
Channel pmeter interrupt status.
Receive input power meter interrupt status.
ADC overflow input pin interrupt status.
When asserted, holds all interrupt status bits cleared. The interrupt pin will be
inactive (always low) when this bit is set. Intended for lab/debug use only
When set, the interrupt and rx_sync_out pins are tristated.
tristate(0)
3.5
AFE8406 Programming
The AFE8406 includes over 2000 internal configuration registers and therefore implements a paged
addressing scheme. The register map includes a “global control variables” register address space that is
accessed directly when the a5 signal is high. This “global control variables” address space includes the
page register. All other registers are addressed using a combination of an address comprised of the
internal page register contents and the 6-bit external address; a5, a4, a3, a2, a1 and a0.
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The page register is accessed when the 6-bit address a5:a0 is 0x21 (or binary “100001”).
Page Register Contents
in Hex
don’t care
Address
pin a5
1
Registers Addressed with 5 bit address space, pins (a4:a0)
0x0000
0x0020
0x0040
0x0060
0x0080
0x00A0
0x00C0
0x00E0
0x0100
0x0120
0
0
0
0
0
0
0
0
0
0
DDC0 PFIR taps 0 through 31 coefficient lsbs (1:0)
DDC0 PFIR taps 32 through 63 coefficient lsbs (1:0)
DDC0 PFIR taps 0 through 31 coefficient msbs (17:2)
DDC0 PFIR taps 32 through 63 coefficient msbs (17:2)
DDC0 CFIR taps 0 through 31 coefficient lsbs (1:0)
DDC0 CFIR taps 32 through 63 coefficient lsbs (1:0)
DDC0 CFIR taps 0 through 31 coefficient msbs (17:2)
DDC0 CFIR taps 32 through 63 coefficient msbs (17:2)
DDC0 Control Registers 0x00 through 0x1F
DDC0 Control Registers 0x20 through 0x3F
0x0200
0x0220
0x0240
0x0260
0x0280
0x02A0
0x02C0
0x02E0
0x0300
0x0320
0
0
0
0
0
0
0
0
0
0
DDC1 PFIR taps 0 through 31 coefficient lsbs (1:0)
DDC1 PFIR taps 32 through 63 coefficient lsbs (1:0)
DDC1 PFIR taps 0 through 31 coefficient msbs (17:2)
DDC1 PFIR taps 32 through 63 coefficient msbs (17:2)
DDC1 CFIR taps 0 through 31 coefficient lsbs (1:0)
DDC1 CFIR taps 32 through 63 coefficient lsbs (1:0)
DDC1 CFIR taps 0 through 31 coefficient msbs (17:2)
DDC1 CFIR taps 32 through 63 coefficient msbs (17:2)
DDC1 Control Registers 0x00 through 0x1F
DDC1 Control Registers 0x20 through 0x3F
0x0400
0x0420
0x0440
0x0460
0x0480
0x04A0
0x04C0
0x04E0
0x0500
0x0520
0
0
0
0
0
0
0
0
0
0
DDC2 PFIR taps 0 through 31 coefficient lsbs (1:0)
DDC2 PFIR taps 32 through 63 coefficient lsbs (1:0)
DDC2 PFIR taps 0 through 31 coefficient msbs (17:2)
DDC2 PFIR taps 32 through 63 coefficient msbs (17:2)
DDC2 CFIR taps 0 through 31 coefficient lsbs (1:0)
DDC2 CFIR taps 32 through 63 coefficient lsbs (1:0)
DDC2 CFIR taps 0 through 31 coefficient msbs (17:2)
DDC2 CFIR taps 32 through 63 coefficient msbs (17:2)
DDC2 Control Registers 0x00 through 0x1F
DDC2 Control Registers 0x20 through 0x3F
0x0600
0x0620
0x0640
0x0660
0x0680
0x06A0
0x06C0
0x06E0
0x0700
0x0720
0
0
0
0
0
0
0
0
0
0
DDC3 PFIR taps 0 through 31 coefficient lsbs (1:0)
DDC3 PFIR taps 32 through 63 coefficient lsbs (1:0)
DDC3 PFIR taps 0 through 31 coefficient msbs (17:2)
DDC3 PFIR taps 32 through 63 coefficient msbs (17:2)
DDC3 CFIR taps 0 through 31 coefficient lsbs (1:0)
DDC3 CFIR taps 32 through 63 coefficient lsbs (1:0)
DDC3 CFIR taps 0 through 31 coefficient msbs (17:2)
DDC3 CFIR taps 32 through 63 coefficient msbs (17:2)
DDC3 Control Registers 0x00 through 0x1F
DDC3 Control Registers 0x20 through 0x3F
Global Control Variables 0x00 through 0x1F
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Page Register Contents
in Hex
0x0800
0x0820
0x0840
0x0860
0x0880
0x08A0
0x08C0
0x08E0
0x0900
0x0920
Address
pin a5
0
0
0
0
0
0
0
0
0
0
Registers Addressed with 5 bit address space, pins (a4:a0)
0x0A00
0x0A20
0x0A40
0x0A60
0x0A80
0x0AA0
0x0AC0
0x0AE0
0x0B00
0x0B20
0
0
0
0
0
0
0
0
0
0
DDC5 PFIR taps 0 through 31 coefficient lsbs (1:0)
DDC5 PFIR taps 32 through 63 coefficient lsbs (1:0)
DDC5 PFIR taps 0 through 31 coefficient msbs (17:2)
DDC5 PFIR taps 32 through 63 coefficient msbs (17:2)
DDC5 CFIR taps 0 through 31 coefficient lsbs (1:0)
DDC5 CFIR taps 32 through 63 coefficient lsbs (1:0)
DDC5 CFIR taps 0 through 31 coefficient msbs (17:2)
DDC5 CFIR taps 32 through 63 coefficient msbs (17:2)
DDC5 Control Registers 0x00 through 0x1F
DDC5 Control Registers 0x20 through 0x3F
0x0C00
0x0C20
0x0C40
0x0C60
0x0C80
0x0CA0
0x0CC0
0x0CE0
0x0D00
0x0D20
0
0
0
0
0
0
0
0
0
0
DDC6 PFIR taps 0 through 31 coefficient lsbs (1:0)
DDC6 PFIR taps 32 through 63 coefficient ls bs (1:0)
DDC6 PFIR taps 0 through 31 coefficient msbs (17:2)
DDC6 PFIR taps 32 through 63 coefficient msbs (17:2)
DDC6 CFIR taps 0 through 31 coefficient lsbs (1:0)
DDC6 CFIR taps 32 through 63 coefficient lsbs (1:0)
DDC6 CFIR taps 0 through 31 coefficient msbs (17:2)
DDC6 CFIR taps 32 through 63 coefficient msbs (17:2)
DDC6 Control Registers 0x00 through 0x1F
DDC6 Control Registers 0x20 through 0x3F
0x0E00
0x0E20
0x0E40
0x0E60
0x0E80
0x0EA0
0x0EC0
0x0EE0
0x0F00
0x0F20
0
0
0
0
0
0
0
0
0
0
DDC7 PFIR taps 0 through 31 coefficient lsbs (1:0)
DDC7 PFIR taps 32 through 63 coefficient lsbs (1:0)
DDC7 PFIR taps 0 through 31 coefficient msbs (17:2)
DDC7 PFIR taps 32 through 63 coefficient msbs (17:2)
DDC7 CFIR taps 0 through 31 coefficient lsbs (1:0)
DDC7 CFIR taps 32 through 63 coefficient lsbs (1:0)
DDC7 CFIR taps 0 through 31 coefficient msbs (17:2)
DDC7 CFIR taps 32 through 63 coefficient msbs (17:2)
DDC7 Control Registers 0x00 through 0x1F
DDC7 Control Registers 0x20 through 0x3F
0x1000
0x1020
0x1040
0x1080
0x10A0
0
0
0
0
0
Receive Input AGC0 Error RAM addresses 0 through 31
Receive Input AGC0 Error RAM addresses 32 through 63
Receive Input AGC0 DVGA RAM addresses 0 through 31
Receive Input AGC0 Gain RAM addresses 0 through 31
Receive Input AGC0 Gain RAM addresses 32 through 63
0x1100
0x1120
0x1140
0
0
0
Receive Input AGC1 Error RAM addresses 0 through 31
Receive Input AGC1 Error RAM addresses 32 through 63
Receive Input AGC1 DVGA RAM addresses 0 through 31
DDC4 PFIR taps 0 through 31 coefficient lsbs (1:0)
DDC4 PFIR taps 32 through 63 coefficient lsbs (1:0)
DDC4 PFIR taps 0 through 31 coefficient msbs (17:2)
DDC4 PFIR taps 32 through 63 coefficient msbs (17:2)
DDC4 CFIR taps 0 through 31 coefficient lsbs (1:0)
DDC4 CFIR taps 32 through 63 coefficient lsbs (1:0)
DDC4 CFIR taps 0 through 31 coefficient msbs (17:2)
DDC4 CFIR taps 32 through 63 coefficient msbs (17:2)
DDC4 Control Registers 0x00 through 0x1F
DDC4 Control Registers 0x20 through 0x3F
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0x1180
0x11A0
0
0
Receive Input AGC1 Gain RAM addresses 0 through 31
Receive Input AGC1 Gain RAM addresses 32 through 63
0x1400
0x1420
0x1440
0x1480
0x14A0
0
0
0
0
0
Receive Input AGC2 Error RAM addresses 0 through 31
Receive Input AGC2 Error RAM addresses 32 through 63
Receive Input AGC2 DVGA RAM addresses 0 through 31
Receive Input AGC2 Gain RAM addresses 0 through 31
Receive Input AGC2 Gain RAM addresses 32 through 63
0x1500
0x1520
0x1540
0x1580
0x15A0
0
0
0
0
0
Receive Input AGC3 Error RAM addresses 0 through 31
Receive Input AGC3 Error RAM addresses 32 through 63
Receive Input AGC3 DVGA RAM addresses 0 through 31
Receive Input AGC3 Gain RAM addresses 0 through 31
Receive Input AGC3 Gain RAM addresses 32 through 63
0x1800
0x1820
0
0
Receive Input Control Registers 0x00 through 0x1F
Receive Input Control Registers 0x20 through 0x3F
0x1840
0x1860
0
0
Receive Input AGC Control Registers 0x00 through 0x1F
Receive Input AGC Control Registers 0x20 through 0x3F
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3.5.1
SLWS168 - OCTOBER 2005
Control Register Index
Register name: VER................................................................................................................................... 67
Register name: PAGE ................................................................................................................................ 67
Register name: CONFIG............................................................................................................................. 69
Register name: GBL_PAR_CONFIG0.......................................................................................................... 70
Register name: GBL_PAR_CONFIG1.......................................................................................................... 71
Register name: GBL_TRISTATE ................................................................................................................. 71
Register name: GBL_ONESHOT................................................................................................................. 71
Register name: GBL_IMASK0..................................................................................................................... 72
Register name: GBL_INTERRUPT0 ............................................................................................................ 72
Register name: SYNC_DDC_CNTR_LSB .................................................................................................... 73
Register name: SYNC_DDC_CNTR_MSB ................................................................................................... 73
Register name: SSEL_DDC_CNTR ............................................................................................................. 73
Register name: SSEL_RX_0....................................................................................................................... 74
Register name: RECV_CONFIG0................................................................................................................ 74
Register name: RECV_CONFIG1................................................................................................................ 75
Register name: NZ_PWR_MASK ................................................................................................................ 76
Register name: RECV_PMETER_SYNC ..................................................................................................... 76
Register name: RECV_PMETER0_SQR_SUM_LSB .................................................................................... 77
Register name: RECV_PMETER0_STRT_INTVL_LSB................................................................................. 77
Register name: RECV_PMETER0_SYNC_DLY ........................................................................................... 77
Register name: RECV_PMETER0_CONFIG ................................................................................................ 77
Register name: RECV_PMETER1_SQR_SUM_LSB .................................................................................... 78
Register name: RECV_PMETER1_STRT_INTVL_LSB................................................................................. 78
Register name: RECV_PMETER1_SYNC_DLY ........................................................................................... 78
Register name: RECV_PMETER1_CONFIG ................................................................................................ 79
Register name: RECV_PMETER2_SQR_SUM_LSB .................................................................................... 79
Register name: RECV_PMETER2_STRT_INTVL_LSB................................................................................. 79
Register name: RECV_PMETER2_SYNC_DLY ........................................................................................... 79
Register name: RECV_PMETER2_CONFIG ................................................................................................ 80
Register name: RECV_PMETER3_SQR_SUM_LSB .................................................................................... 80
Register name: RECV_PMETER3_STRT_INTVL_LSB................................................................................. 80
Register name: RECV_PMETER3_SYNC_DLY ........................................................................................... 80
Register name: RECV_PMETER3_CONFIG ................................................................................................ 81
Register name: RECV_SLF_TST_VALUE ................................................................................................... 81
Register name: RECV_PMETER0_LSB....................................................................................................... 81
Register name: RECV_PMETER0_MID....................................................................................................... 82
Register name: RECV_PMETER0_LMSB.................................................................................................... 82
Register name: RECV_PMETER0_UMSB ................................................................................................... 82
Register name: RECV_PMETER1_LSB....................................................................................................... 82
Register name: RECV_PMETER1_MID....................................................................................................... 83
Register name: RECV_PMETER1_LMSB.................................................................................................... 83
Register name: RECV_PMETER1_UMSB ................................................................................................... 83
Register name: RECV_PMETER2_LSB....................................................................................................... 83
Register name: RECV_PMETER2_MID....................................................................................................... 84
Register name: RECV_PMETER2_LMSB.................................................................................................... 84
Register name: RECV_PMETER2_UMSB ................................................................................................... 84
Register name: RECV_PMETER3_LSB....................................................................................................... 84
Register name: RECV_PMETER3_MID....................................................................................................... 85
Register name: RECV_PMETER3_LMSB.................................................................................................... 85
Register name: RECV_PMETER3_UMSB ................................................................................................... 85
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Register name: RAGC_CONFIG0 ............................................................................................................... 86
Register name: RAGC_CONFIG1 ............................................................................................................... 86
Register name: RAGC_CONFIG2 ............................................................................................................... 86
Register name: RAGC_CONFIG3 ............................................................................................................... 87
Register name: RAGC0_INTEGINVL_LSB .................................................................................................. 87
Register name: RAGC0_INTEGINVL_MSB.................................................................................................. 87
Register name: RAGC0_CONFIG0 ............................................................................................................. 88
Register name: RAGC0_CONFIG1 ............................................................................................................. 88
Register name: RAGC0_SD_THRESH ........................................................................................................ 88
Register name: RAGC0_SD_TIMER ........................................................................................................... 89
Register name: RAGC0_SD_SAMPLES ...................................................................................................... 89
Register name: RAGC0_CLIP_HITHRESH.................................................................................................. 89
Register name: RAGC0_CLIP_LOTHRESH................................................................................................. 89
Register name: RAGC0_CLIP_HITIMER ..................................................................................................... 90
Register name: RAGC0_CLIP_LOTIMER.................................................................................................... 90
Register name: RAGC0_CLIP_SAMPLES ................................................................................................... 90
Register name: RAGC0_CLIP_ERROR....................................................................................................... 90
Register name: RAGC1_INTEGINVL_LSB .................................................................................................. 91
Register name: RAGC1_INTEGINVL_MSB.................................................................................................. 91
Register name: RAGC1_CONFIG0 ............................................................................................................. 91
Register name: RAGC1_CONFIG1 ............................................................................................................. 92
Register name: RAGC1_SD_THRESH ........................................................................................................ 92
Register name: RAGC1_SD_TIMER ........................................................................................................... 92
Register name: RAGC1_SD_SAMPLES ...................................................................................................... 92
Register name: RAGC1_CLIP_HITHRESH.................................................................................................. 93
Register name: RAGC1_CLIP_LOTHRESH................................................................................................. 93
Register name: RAGC1_CLIP_HITIMER ..................................................................................................... 93
Register name: RAGC1_CLIP_LOTIMER.................................................................................................... 93
Register name: RAGC1_CLIP_SAMPLES ................................................................................................... 94
Register name: RAGC1_CLIP_ERROR....................................................................................................... 94
Register name: RAGC2_INTEGINVL_LSB .................................................................................................. 94
Register name: RAGC2_INTEGINVL_MSB.................................................................................................. 94
Register name: RAGC2_CONFIG0 ............................................................................................................. 95
Register name: RAGC2_CONFIG1 ............................................................................................................. 95
Register name: RAGC2_SD_THRESH ........................................................................................................ 95
Register name: RAGC2_SD_TIMER ........................................................................................................... 96
Register name: RAGC2_SD_SAMPLES ...................................................................................................... 96
Register name: RAGC2_CLIP_HITHRESH.................................................................................................. 96
Register name: RAGC2_CLIP_LOTHRESH................................................................................................. 96
Register name: RAGC2_CLIP_HITIMER ..................................................................................................... 97
Register name: RAGC2_CLIP_LOTIMER.................................................................................................... 97
Register name: RAGC2_CLIP_SAMPLES ................................................................................................... 97
Register name: RAGC2_CLIP_ERROR....................................................................................................... 97
Register name: RAGC3_INTEGINVL_LSB .................................................................................................. 98
Register name: RAGC3_INTEGINVL_MSB.................................................................................................. 98
Register name: RAGC3_CONFIG0 ............................................................................................................. 98
Register name: RAGC3_CONFIG1 ............................................................................................................. 99
Register name: RAGC3_SD_THRESH ........................................................................................................ 99
Register name: RAGC3_SD_TIMER ........................................................................................................... 99
Register name: RAGC3_SD_SAMPLES ...................................................................................................... 99
Register name: RAGC3_CLIP_HITHRESH................................................................................................ 100
Register name: RAGC3_CLIP_LOTHRESH............................................................................................... 100
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Register name: RAGC3_CLIP_HITIMER ................................................................................................... 100
Register name: RAGC3_CLIP_LOTIMER.................................................................................................. 100
Register name: RAGC3_CLIP_SAMPLES ................................................................................................. 101
Register name: RAGC3_CLIP_ERROR..................................................................................................... 101
Register name: RAGC0_ACCUM_LSB ...................................................................................................... 101
Register name: RAGC0_ACCUM_MSB ..................................................................................................... 101
Register name: RAGC1_ACCUM_LSB ...................................................................................................... 102
Register name: RAGC1_ACCUM_MSB ..................................................................................................... 102
Register name: RAGC2_ACCUM_LSB ...................................................................................................... 102
Register name: RAGC2_ACCUM_MSB ..................................................................................................... 102
Register name: RAGC3_ACCUM_LSB ...................................................................................................... 103
Register name: RAGC3_ACCUM_MSB ..................................................................................................... 103
Register name: FIR_MODE ...................................................................................................................... 104
Register name: FIR_GAIN ........................................................................................................................ 104
Register name: SQR_SUM ....................................................................................................................... 104
Register name: STRT_INTRVL ................................................................................................................. 105
Register name: CIC_MODE1 .................................................................................................................... 105
Register name: CIC_MODE2 .................................................................................................................... 105
Register name: TADJC ............................................................................................................................. 106
Register name: TADJF ............................................................................................................................. 106
Register name: PHASEADD0A ................................................................................................................. 107
Register name: PHASEADD1A ................................................................................................................. 107
Register name: PHASEADD0B ................................................................................................................. 107
Register name: PHASEADD1B ................................................................................................................. 108
Register name: PHASE_OFFSETA ........................................................................................................... 108
Register name: PHASE_OFFSETB ........................................................................................................... 108
Register name: CONFIG1 ......................................................................................................................... 109
Register name: CONFIG2 ......................................................................................................................... 110
Register name: AGC_CONFIG1................................................................................................................ 110
Register name: AGC_CONFIG2................................................................................................................ 111
Register name: AGC_CONFIG3................................................................................................................ 111
Register name: AGC_GAINMSB ............................................................................................................... 111
Register name: AGC_GAINA .................................................................................................................... 112
Register name: AGC_GAINB .................................................................................................................... 112
Register name: AGC_AMAX..................................................................................................................... 112
Register name: AGC_AMIN ...................................................................................................................... 113
Register name: PSER_CONFIG1 .............................................................................................................. 113
Register name: PSER_CONFIG2 .............................................................................................................. 113
Register name: DDCCONFIG1.................................................................................................................. 114
Register name: SYNC_0........................................................................................................................... 115
Register name: SYNC_1........................................................................................................................... 116
Register name: SYNC_2........................................................................................................................... 116
Register name: DDC_CHK_SUM .............................................................................................................. 116
Register name: PMETER_RESULT_A_LSB .............................................................................................. 116
Register name: PMETER_RESULT_A_MID............................................................................................... 117
Register name: PMETER_RESULT_A_MSB.............................................................................................. 117
Register name: PMETER_RESULT_B_LSB .............................................................................................. 117
Register name: PMETER_RESULT_B_MID............................................................................................... 118
Register name: PMETER_RESULT_B_MSB.............................................................................................. 118
Register name: PMETER_RESULT_AB_UMSB ......................................................................................... 118
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SLWS168 - OCTOBER 2005
Global Control Variables
These registers are accessed directly without page address extension; when pin a5 is high during a read
or write access, this block of 32 registers are accessed.
Register name: VER
Address: 0x0
READ_ONLY
BIT15
unused
0
BIT7
unused
0
Unused
0
unused
0
unused
0
unused
0
unused
0
unused
0
Unused
0
unused
0
unused
0
VER3
0
VER2
0
VER1
0
BIT8
unused
0
BIT0
VER0
1
VER(3:0) : A hardwired read only register that returns the version of the chip.
Register name: PAGE
Address: 0x1
BIT15
unused
0
BIT7
Y(1)
0
W(2:0)
X
Unused
0
unused
0
Y(0)
0
Zp
0
0
W(2:0)
0
0
X
0
unused
0
unused
0
unused
0
unused
0
BIT8
Y(2)
0
BIT0
unused
0
: Selects which dual DDC block to address.
: The DDC modules are configured as dual DDCs; an even numbered DDC and odd numbered DDC are
contained in each dual DDC module, the X bit selects which DDC gets address. (DDC0/2/4/6=0, DDC1/3/5/7=1)
W(2:0)
X bit
Selected Block
000
0
DDC0
000
1
DDC1
001
0
DDC2
001
1
DDC3
010
0
DDC4
010
1
DDC5
011
0
DDC6
011
1
DDC7
100
0
Receive AGC0/1 RAMs
101
0
Receive AGC2/3 RAMs
110
0
Receive Input Interface
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Y(2:0)
: Within each major block, there are up to 8 different Zones that can be addressed using the Y bits.
Y(2:0)
000
001
010
011
100
101
110
111
Zp
SLWS168 - OCTOBER 2005
:
DDC Zone
PFIR coeffient lower 2 bits
PFIR coeffient upper 16 bits
CFIR coeffient lower 2 bits
CFIR coeffient upper 16 bits
Control registers
Not assigned
Not assigned
Not assigned
Receive Input Interface Zone
CHIPS control registers
RAGC control registers
Not assigned
Not assigned
Not assigned
Not assigned
Not assigned
Not assigned
Receive AGC RAMs Zone
RAGC0/2 ERRMAP
RAGC0/2 DVGAMAP
RAGC0/2 GAINMAP
Not assigned
RAGC1/3 ERRMAP
RAGC1/3 DVGAMAP
RAGC1/3 GAINMAP
Not assigned
The Zp bit is the MSB of the address word sent to the registers and rams. This bit can be thought of as an
upper/lower selector of the 64 word addressing.
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Register name: CONFIG
Address: 0x2
BIT15
slf_
tst_ena
0
BIT7
par_recv_
ena
0
BIT8
rduz_sens
_ena
0
arst_
func
0
gbl_
ddc_write
0
intr_
clr
0
slf_tst_ena
rduz_sens_ena
arst_func
tst_rate_sel(4:0)
par_recv_ena
gbl_ddc_write
intr_clr
tst_select(3:0)
0
0
0
0
tst_select(3:0)
1
1
1
0
0
BIT0
tst_
on
0
: Turns on the checksum LFSR for the receivers. They are located ni the RECEIVE INPUT
INTERFACE and DDC blocks.
: When enabled, adds noise to the LSB’s of the ADC inputs.
: When asserted, resets the functional portion of the circuits. The MPU registers do not get reset
and retain their programmed value.
: Sets the rate of the output test data and clock. The length of the clock cycle is the value in
tst_rate_sel+1 multiplied by the RXCLK period. When the test bus source is set to 1000 (rxin_a
and rxin_b FIFO outputs), tst_rate_sel(4:0) must be set to 0 for output. Therefore, will not output a
clock at the decimated test bus rate.
: When asserted, the rxout_*_* serial pins join to form a 32 bit parallel output using 32 pins as a
data bus, one pin as a output clock and one pin as a sync. This is used to connect to the TCI110
Chip rate processor from TI.
: Factory use only. When asserted, the mpu writes are global. This means that DDC0/2/4/6 or
DDC1/3/5/7 can be programmed simultaneously with the same values. This is an effort to reduce
the amount of time spent programming the device. A common setup can be used to program the
DDC0/2/4/6, then all the DDC1/3/5/7. Afterwards, just individual writes to the registers which differ
between DDCs can be done. To use this feature, this bit must be asserted and the DDC0/1 must
be addressed. Any other DDC address will not work.
: When asserted, this bit forces all interrupts to be cleared. To allow the interrupts to be set again,
this bit must be programmed to zero. This does not stop blocks from generating interrupts, but
rather just keeps the interrupts from being reported.
: This selects which block the test output comes from:
tst_select(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
others
tst_on
tst_rate_sel(4:0)
Test data sent to test bus
rxin_d(15:0), dvga_c(3:2), rxin_c(15:0), dvga_c(5:4)
DDC 0
DDC 1
DDC 2
DDC 3
DDC 4
DDC 5
DDC 6
DDC 7
rxin_a(15:0), “00”, rxin_b(15:0), “00”
from the fifo outputs
none selected
: When asserted, the testbus is active. The ADC input ports rxin_c(15:0), rxin_d(15:0), dvga_c(5:0)
and dvga_d(5:0) become the testbus output ports. When this bit is set, the rxin_c(15:0) and
rxin_d(15:0) ports become chip outputs. The dvga_c(5:0) and dvga_d(5:0) ports are enabled
separately using the GBL_TRISTATE register
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Register name: GBL_PAR_CONFIG0
Address: 0x3
BIT15
0
0
par_recv_sync_del(6:0)
0
0
0
0
0
0
0
BIT7
par_recv_clkdiv(6:0)
0
0
0
0
0
BIT8
tst_clk_pol
0
BIT0
par_recv_
rxclk_pol
0
par_recv_sync_del(6:0) : Delays the sync source from the DDC0 AGC output by (par_recv_sync_del+1) rxclk cycles.
tst_clk_pol
: Selects the polarity of the test clock output at dvga_c(1) when the test bus is enabled; 0 for rising
edge in the center of valid data, 1 for falling edge in the center of valid data.
No effect when tst_rate_sel is “00000”.
par_recv_clkdiv(6:0)
: Selects the parallel interface output clock rate.
par_recv_rxclk_pol
: Selects the polarity of the rxclk_out clock output; 0 for rising edge in the center of valid data, 1 for
falling edge in the center of valid data.
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Register name: GBL_PAR_CONFIG1
Address: 0x4
BIT15
0
BIT8
par_recv_syncout_del(3:0)
0
0
0
0
par_recv_chan(3:0)
0
0
BIT7
par_recv_fsinvl(6:0)
0
0
0
0
0
0
0
0
BIT0
par_recv_
sync_pol
0
par_recv_syncout_del(3:0) : Changes the rx_sync_out position with respect to IQ DDC0. Setting to 0 causes rx_sync_out
to lead IQ DDC0 by 1 output sample, setting to 1 causes rx_sync_out to line up with IQ DDC0,
setting to 2 causes rx_sync_out to trail IQ DDC0 by 1 output sample, etc.
par_recv_chan(3:0)
: Selects the number of channels to be output over the parallel interface, from 1 to 16 channels.
par_recv_fsinvl(6:0)
: Selects the number of rxclk cycles per parallel interface frame, from 1 to 128 cycles.
par_recv_sync_pol
: Selects the polarity of the parallel interface sync pulse; 0 for active low, 1 for active high.
Register name: GBL_TRISTATE
Address: 0x5
BIT15
rxclk_ena
1
BIT7
tristate(7)
1
Unused
0
unused
0
unused
0
unused
0
tristate(10)
1
tristate(9)
1
tristate(6)
1
tristate(5)
1
tristate(4)
1
tristate(3)
1
tristate(2)
1
tristate(1)
1
BIT8
tristate(8)
1
BIT0
tristate(0)
1
rxclk_ena
: Master rxclk enable. When set, the chip’s rxclk is enabled, when cleared, rxclk is disabled.
All tristates are ACTIVE LOW; ‘0’ enables the output and ‘1’ tristates it.
tristate(10)
: When cleared, enables the dvga_d outputs.
tristate(9)
: When cleared, enables the dvga_c outputs.
tristate(8)
: When cleared, enables the dvga_b outputs.
tristate(7)
: When cleared, enables the dvga_a outputs.
tristate(6)
: When cleared, enables the rx_sync_out_6/7, and the rxout_6/7_a/b/c/d outputs (for parallel
interface use only).
tristate(5)
: When cleared, enables the rx_sync_out_4/5, and the rxout_4/5_a/b/c/d outputs.
tristate(4)
: When cleared, enables the rx_sync_out_2/3, and the rxout_2/3_a/b/c/d outputs.
tristate(3)
: When cleared, enables the rx_sync_out_0/1, and the rxout_0/1_a/b/c/d outputs.
tristate(2)
: TBD
tristate(1)
: When cleared, enables the rxclk_out output.
tristate(0)
: When cleared, enables interrupt and rx_sync_out outputs.
Register name: GBL_ONESHOT
Address: 0x6
BIT15
unused
0
BIT7
rx_oneshot
0
rx_oneshot
Unused
0
unused
0
unused
0
unused
0
unused
0
unused
0
Unused
0
unused
0
unused
0
unused
0
unused
0
unused
0
BIT8
unused
0
BIT0
unused
0
: When set, a one shot pulse is sent to the receive blocks for syncing. This only works if the blocks
are programmed to use the oneshot as the sync source. To use the oneshot again, it must be
programmed back to a ‘0’ and then back to a ‘1’.
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Register name: GBL_IMASK0
Address: 0x7
BIT15
unused
Unused
0
0
BIT7
recv_
recv_
pmeter0_im pmeter1_im
0
0
pmeterX_im
recv_pmeterX_im
rxin_X_ovr_im
pmeter5_im pmeter4_im
0
0
recv_
pmeter2_im
0
recv_
pmeter3_im
0
pmeter3_im
0
rxin_a_
ovr_im
0
pmeter2_im pmeter1_im
0
0
rxin_b_
ovr_im
0
rxin_c_
ovr_im
0
BIT8
pmeter0_im
0
BIT0
rxin_d_
ovr_im
0
: When asserted, masks the interrupt for the particular DDC pmeter, X= {0,1,2,3,4,5,6,7}.
: When asserted, masks the interrupt for the particular receive input pmeter, X= {0,1,2,3 }.
: When asserted, masks the interrupt for the particular rxin overflow, X={a,b,c,d}.
Register name: GBL_INTERRUPT0
Address: 0x9
BIT15
unused
0
BIT7
recv_
pmeter0
0
pmeterX
recv_pmeterX
rxin_X_ovr
Unused
0
pmeter5
0
pmeter4
0
pmeter3
0
pmeter2
0
pmeter1
0
recv_
pmeter1
0
recv_
pmeter2
0
recv_
pmeter3
0
rxin_a_ovr
rxin_b_ovr
rcin_c_ovr
BIT8
pmeter0
0
BIT0
rxin_d_ovr
0
0
0
0
: Asserted when an interrupt has been generated by this DDC pmeterX block, X={1,2,3,4,5,6,7}.
: Asserted when an interrupt has been generated by this receive input pmeter, X= {0,1,2,3 }.
: Asserted when a logic high input from the rxin_X_ovr pin occurs, X={a,b,c,d}.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
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Receive Input Interface Controls (Pages: 0x1800 and 0x1820)
Register name: SYNC_DDC_CNTR_LSB
Page: 0x1800
Address: 0x0
BIT15
BIT8
0
0
0
ddc_counter(15:8)
0
0
0
0
0
ddc_counter(7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
Register name: SYNC_DDC_CNTR_MSB
Page: 0x1800
Address: 0x1
BIT15
BIT8
0
0
0
ddc_counter(31:24)
0
0
0
0
0
ddc_counter(23:16)
0
0
0
0
0
0
BIT7
ddc_counter(32:0)
0
BIT0
0
: 32 bit interval timer common to all DDC sync inputs. This timer may be programmed to any interval
count, and each DDC synchronization input can select this counter as a source. The value
programmed into the counter is: (desired number –1). The counter increments on each RX clock
rising edge.
Register name: SSEL_DDC_CNTR
Page: 0x1800
Address: 0x2
BIT15
rxinab_mux rxincd_mux
0
0
BIT7
0
0
unused
0
0
unused
0
unused
0
ddc_counter_width(7:0)
0
0
BIT8
ssel_ddc_counter(2:0)
0
0
0
BIT0
0
0
0
rxinab_mux
: When asserted, the rxin_a and rxin_b inputs are internally driven by the rxin_c and rxin_d ports,
respectively (Factory test use only).
rxincd_mux
: When asserted, the rxin_c and rxin_d inputs are internally driven by the rxin_a and rxin_b ports,
respectively (Factory test use only).
ssel_ddc_counter(2:0) : Selects the sync source for the DDC sync counter.
ddc_counter_width(7:0) : Sets the width of the counter generated sync pulse in RX clock cycles, from 1 to 256.
Sync sources are contained in this and many of the following registers. For all sync source selections:
ssel_ddc_XXXXX(2:0)
000
001
010
011
100
101
Selected sync source
rxsyncA
rxsyncB
rxsyncC
rxsyncD
DDC sync counter
one shot (register write triggered)
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
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110
111
SLWS168 - OCTOBER 2005
always 0
always 1
Register name: SSEL_RX_0
Page: 0x1800
Address: 0x3
BIT15
unused
0
BIT7
unused
0
BIT8
0
ssel_adc_fifo(2:0)
0
0
ssel_rxsync_out(2:0)
0
ssel_adc_fifo(2:0)
ssel_tst_decim(2:0)
ssel_rxsync_out(2:0)
ssel_ddc(2:0)
0
unused
0
0
ssel_tst_decim(2:0)
0
0
unused
0
0
ssel_ddc(2:0)
0
0
BIT0
0
: Selects the sync source for the adc FIFO blocks. Sync reinitializes the read and write pointers of
the FIFO.
: Selects the sync source for the test bus decimator block.
: Selects the sync source for the RXSYNC_OUT pin.
: Selects the sync source for the DDC data input mux and mixer. Controls clock generation in
each DDC block (before the CIC input) which must match because the FIFO output clock is
common for all DDC blocks.
Register name: RECV_CONFIG0
Page: 0x1800
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Address: 0x4
BIT15
rate_sel(1:0)
0
0
adc_
adc_
self_test_
fifo_strap_ab fifo_strap_cd const_ena
0
0
0
adc_
fifo_bypass
0
ragc_mpu
_ram_read
0
pmeter2_iq
0
pmeter1_iq
0
BIT7
0
tst_decim_delay(3:0)
0
0
rate_sel(1:0)
adc_fifo_strap_cd
self_test_const_ena
adc_fifo_bypass
ragc_mpu_ram_read
tst_decim17
tst_decim_delay(3:0)
pmeter3_iq
pmeter2_iq
pmeter1_iq
pmeter0_iq
pmeter3_iq
0
: Tells the RECV_CDRV the input rate. This is the rxin_a/b/c/d input rate and the rate that the
RECEIVE INPUT INTERFACE block sends data to the DDCs.
rate_sel
00
01
10
11
adc_fifo_strap_ab
0
BIT8
tst_
decim17
0
BIT0
pmeter0_iq
0
Input clock rate
rxclk
rxclk/2
rxclk/4
rxclk/8
: When asserted, the input pointers of the rxin_a FIFO and rxin_b FIFO are hooked together in lock
step configuration. This is used for maintaining FIFO delay consistency when complex inputs are
driven on rxin_a(I) and rxin_b(Q). rxin_a is the Master.
: When asserted, the input pointers of the rxin_c FIFO and rxin_d FIFO are hooked together in lock
step configuration. This is used for maintaining FIFO delay consistency when complex inputs are
driven on rxin_c(I) and rxin_d(Q). rxin_c is the Master.
: When asserted, (with slf_tst_ena also asserted), a constant value is output by the test and noise
generator instead of the pseudo random sequence. The constant value is programmable.
: When asserted, the ADC FIFO circuits are bypassed. Input data is then clocked in directly using
the rxclk input. The ssel_ddc selection value will control the location of the internally generated
sample clock when this bit is asserted where rate_sel is rxclk/2, rxclk/4 or rxclk/8.
: When asserted, the RAMs in the RAGC blocks can be read. This bit should only be set when
reading the RAGC map rams via the mpu interface and must be cleared for proper RAGC
operation.
: Factory use only. Will have no effect for user on production part.
: These bits set the delay from the sync occurring until the decimator samples. In other words, the
moment of the decimator is set by this delay value.
: When asserted, the pmeter3 block takes input from both rxin_c and rxin_d as a complex sample
pair. When de-asserted, only input from rxin_d is used for the power measurement.
: When asserted, the pmeter2 block takes input from both rxin_c and rxin_d as a complex sample
pair. When de-asserted, only input from rxin_c is used for the power measurement.
: When asserted, the pmeter1 block takes input from both rxin_a and rxin_b as a complex sample
pair. When de-asserted, only input from rxin_b is used for the power measurement.
: When asserted, the pmeter0 block takes input from both rxin_a and rxin_b as a complex sample
pair. When de-asserted, only input from rxin_a is used for the power measurement.
Register name: RECV_CONFIG1
Page: 0x1800
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Address: 0x5
BIT15
0
msb_pos_d(2:0)
0
0
msb_pos_b(2:0)
0
0
offset_bin_d
0
0
offset_bin_b
0
0
msb_pos_c(2:0)
0
0
0
msb_pos_a(2:0)
0
0
BIT7
msb_pos_X(2:0)
BIT8
offset_bin_c
0
BIT0
offset_bin_a
0
: Places the MSB of the input word from the ADC. The value programmed into the 3 bits is the
number of bit positions to the left of bit16 in the input word, that the MSB is located. For example,
if a 14bit input word is driving rxin_a input and is aligned with rxin_a_0, then msb_pos_a is
programmed to “010” meaning 2 bits shifted down from bit 16 is the MSB. X={a,b,c,d}
: rxin_X input data is in offset binary and not 2’s complement. If set, the input value will be
converted to 2s complement using the MSB from the corresponding msb_pos_X value.
X={a,b,c,d} Note that the internal ADCs use 2’s complement format, so offset_bin_A and
offset_bin_B must be set.
offset_bin_X
Register name: NZ_PWR_MASK
Page: 0x1800
Address: 0x6
BIT15
BIT8
0
0
0
nz_pwr_mask (15:8)
0
0
0
0
0
nz_pwr_mask (7:0)
0
0
0
0
0
0
BIT7
nz_pwr_mask(15:0)
0
BIT0
0
: Used with the rduz_sens_ena and selects the noise bits to be added to the ADC input sample
when asserted.
Register name: RECV_PMETER_SYNC
Page: 0x1800
Address: 0x7
BIT15
recv_pmet
er0_ena
0
BIT7
recv_pmet
er2_ena
0
ssel_recv_pmeter0(2:0)
0
0
0
0
0
recv_pmet
er3_ena
0
0
ssel_ recv_pmeter2(2:0)
0
recv_pmeter0_ena
:
recv_pmeter1_ena
:
recv_pmeter2_ena
:
recv_pmeter3_ena
:
ssel_ recv_pmeter0(2:0) :
ssel_ recv_pmeter1(2:0) :
ssel_ recv_pmeter2(2:0) :
ssel_ recv_pmeter3(2:0) :
0
BIT8
ssel_ recv_pmeter1(2:0)
recv_pmet
er1_ena
0
0
0
BIT0
ssel_ recv_pmeter3(2:0)
0
0
Enables the Receive Input Interface pmeter0 block when set
Enables the Receive Input Interface pmeter1 block when set
Enables the Receive Input Interface pmeter2 block when set
Enables the Receive Input Interface pmeter3 block when set
Selects the sync source for the Receive Input Interface pmeter0 block
Selects the sync source for the Receive Input Interface pmeter1 block
Selects the sync source for the Receive Input Interface pmeter2 block
Selects the sync source for the Receive Input Interface pmeter3 block
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Register name: RECV_PMETER0_SQR_SUM_LSB
Page: 0x1800
Address: 0x8
BIT15
BIT8
0
0
0
recv_pmeter0_sqr_sum (15:8)
0
0
0
0
0
recv_pmeter0_sqr_sum (7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
recv_pmeter0_sqr_sum(15:0) : The sqr_sum register controls the number of samples to accumulate for a power
measurement. Ia is (or Ia & Qa if complex mode is selected are) squared and
accumulated. Eight Ia samples (or eight sample pairs of Ia and Qa samples) equal to one
sqr_sum count. The accumulation interval is initiated when the sync is asserted and the
programmed (8*sync_delay+2) samples has expired or when the interval start time is
reached. When the (8*sqr_sum+1) sample time is reached, the accumulated powers are
made available for MPU access and an interrupt is generated.
Register name: RECV_PMETER0_STRT_INTVL_LSB
Page: 0x1800
Address: 0x9
BIT15
BIT8
0
0
0
recv_pmeter0_strt_intrvl (15:8)
0
0
0
0
0
recv_pmeter0_strt_intrvl (7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
recv_pmeter0_strt_intrvl(15:0) : The start interval timer is the interval over which the sqr_sum is restarted. The timer value
is (8*strt_intrvl + 1) samples and must be larger than (8*sqr_sum+1) samples. The interval
start counter and RMS power accumulation is started at the sync pulse after the
programmed delay and every time the STRT_INTRVL counter reaches its limit.
Register name: RECV_PMETER0_SYNC_DLY
Page: 0x1800
Address: 0xA
BIT15
delay_line_0(5:0)
0
0
0
0
0
0
0
unused
0
0
0
0
0
BIT7
delay_line_0(5:0)
:
recv_pmeter0_sync_delay(8:0) :
recv_pmeter0_sync_delay (7:0)
0
0
BIT8
recv_pmete
r0_sync_del
ay(8)
0
BIT0
0
Pointer offset for the rxin_a path variable delay line. Larger values result in larger
pointer offsets and therefore more path delay.
Programmable start delay from sync, in eight sample units. The actual value is
(8*sync_delay + 2) samples.
Register name: RECV_PMETER0_CONFIG
Page: 0x1800
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Address: 0xB
BIT15
recv_pmeter0_sqr_sum(20:16)
0
0
0
0
unused
unused
unused
0
0
0
0
BIT7
recv_pmeter0_strt_
intrvl(17:16)
0
0
BIT8
recv_pmeter0_strt_intrvl(20:18)
0
0
0
BIT0
ssel_delay_line_0(2:0)
0
0
0
recv_pmeter0_sqr_sum(20:16) : MSBs of sqr_sum value, in 8 sample units.
recv_pmeter0_strt_intrvl(20:16): MSBs of start interval value, in 8 sample units.
ssel_delay_line_0(2:0)
: Sync source selection for the 64 sample delay line pointer value update
Register name: RECV_PMETER1_SQR_SUM_LSB
Page: 0x1800
Address: 0xC
BIT15
BIT8
0
0
0
recv_pmeter1_sqr_sum (15:8)
0
0
0
0
0
recv_pmeter1_sqr_sum (7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
recv_pmeter1_sqr_sum(15:0) : Lower 16bits of the sqr_sum interval timer, in 8 sample units.
Register name: RECV_PMETER1_STRT_INTVL_LSB
Page: 0x1800
Address: 0xD
BIT15
BIT8
0
0
0
recv_pmeter1_strt_intrvl (15:8)
0
0
0
0
0
recv_pmeter1_strt_intrvl (7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
recv_pmeter1_strt_intrvl(15:0) : Lower 16bits of the interval timer, in 8 sample units.
Register name: RECV_PMETER1_SYNC_DLY
Page: 0x1800
Address: 0xE
BIT15
delay_line_1(5:0)
0
0
0
0
0
0
0
unused
0
0
0
0
0
BIT7
delay_line_1(5:0)
:
recv_pmeter1_sync_delay(8:0) :
recv_pmeter1_sync_delay (7:0)
0
0
BIT8
recv_pmet
er1_sync_
delay(8)
0
BIT0
0
Pointer offset for the rxin_b path variable delay line. Larger values result in larger
pointer offsets and therefore more path delay.
Programmable start delay from sync, in 8 sample units.
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Register name: RECV_PMETER1_CONFIG
Page: 0x1800
Address: 0xF
BIT15
recv_pmeter1_sqr_sum(20:16)
0
0
0
0
unused
unused
unused
0
0
0
0
BIT7
recv_pmeter1_strt_
intrvl(17:16)
0
0
BIT8
recv_pmeter1_strt_intrvl(20:18)
0
0
0
BIT0
ssel_delay_line_1(2:0)
0
0
0
recv_pmeter1_sqr_sum(20:16) : MSBs of sqr_sum value, in 8 sample units.
recv_pmeter1_strt_intrvl(20:16): MSBs of start interval value, in 8 sample units.
ssel_delay_line_1(2:0)
: Sync source selection for the 64 sample delay line pointer value update
Register name: RECV_PMETER2_SQR_SUM_LSB
Page: 0x1800
Address: 0x10
BIT15
BIT8
0
0
0
recv_pmeter2_sqr_sum (15:8)
0
0
0
0
0
recv_pmeter2_sqr_sum (7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
recv_pmeter2_sqr_sum(15:0) : Lower 16bits of the sqr_sum interval timer, in 8 sample units.
Register name: RECV_PMETER2_STRT_INTVL_LSB
Page: 0x1800
Address: 0x11
BIT15
BIT8
0
0
0
recv_pmeter2_strt_intrvl (15:8)
0
0
0
0
0
recv_pmeter2_strt_intrvl (7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
recv_pmeter2_strt_intrvl(15:0) : Lower 16bits of the interval timer, in 8 sample units.
Register name: RECV_PMETER2_SYNC_DLY
Page: 0x1800
Address: 0x12
BIT15
delay_line_2(5:0)
0
0
0
0
0
0
0
unused
0
0
0
0
0
BIT7
delay_line_2(5:0)
:
recv_pmeter2_sync_delay (7:0)
0
0
BIT8
recv_pmet
er2_sync_
delay(8)
0
BIT0
0
Pointer offset for the rxin_c path variable delay line. Larger values result in larger
pointer offsets and therefore more path delay.
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recv_pmeter2_sync_delay (8:0) :
SLWS168 - OCTOBER 2005
Programmable start delay from sync, in 8 sample units.
Register name: RECV_PMETER2_CONFIG
Page: 0x1800
Address: 0x13
BIT15
recv_pmeter2_sqr_sum(20:16)
0
0
0
0
unused
unused
unused
0
0
0
0
BIT7
recv_pmeter2_strt_
intrvl(17:16)
0
0
BIT8
recv_pmeter2_strt_intrvl(20:18)
0
0
0
BIT0
ssel_delay_line_2(2:0)
0
0
0
recv_pmeter2_sqr_sum(20:16) : MSBs of sqr_sum value, in 8 sample units.
recv_pmeter2_strt_intrvl(20:16): MSBs of start interval value, in 8 sample units.
ssel_delay_line_2(2:0)
: Sync source selection for the 64 sample delay line pointer value update
Register name: RECV_PMETER3_SQR_SUM_LSB
Page: 0x1800
Address: 0x14
BIT15
BIT8
0
0
0
recv_pmeter3_sqr_sum (15:8)
0
0
0
0
0
recv_pmeter3_sqr_sum (7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
recv_pmeter3_sqr_sum(15:0) : Lower 16bits of the sqr_sum interval timer, in 8 sample units.
Register name: RECV_PMETER3_STRT_INTVL_LSB
Page: 0x1800
Address: 0x15
BIT15
BIT8
0
0
0
recv_pmeter3_strt_intrvl (15:8)
0
0
0
0
0
recv_pmeter3_strt_intrvl (7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
recv_pmeter3_strt_intrvl(15:0) : Lower 16bits of the interval timer, in 8 sample units.
Register name: RECV_PMETER3_SYNC_DLY
Page: 0x1800
Address: 0x16
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BIT15
delay_line_3(5:0)
0
0
0
0
0
0
0
unused
0
0
0
0
0
BIT7
delay_line_3(5:0)
:
recv_pmeter3_sync_delay(8:0) :
recv_pmeter3_sync_delay (7:0)
0
0
BIT8
recv_pme
ter3_sync_
delay(8)
0
BIT0
0
Pointer offset for the rxin_d path variable delay line. Larger values result in larger
pointer offsets and therefore more path delay.
Programmable start delay from sync, in 8 sample units.
Register name: RECV_PMETER3_CONFIG
Page: 0x1800
Address: 0x17
BIT15
recv_pmeter3_sqr_sum(20:16)
0
0
0
0
unused
unused
unused
0
0
0
0
BIT7
recv_pmeter3_strt_
intrvl(17:16)
0
0
BIT8
recv_pmeter3_strt_intrvl(20:18)
0
0
0
BIT0
ssel_delay_line_3(2:0)
0
0
0
recv_pmeter3_sqr_sum(20:16) : MSBs of sqr_sum value, in 8 sample units
recv_pmeter3_strt_intrvl(20:16): MSBs of start interval value, in 8 sample units
ssel_delay_line_3(2:0)
: Sync source selection for the 64 sample delay line pointer value update
Register name: RECV_SLF_TST_VALUE
Page: 0x1800
Address: 0x18
BIT15
BIT8
0
0
0
self_test_constant(15:8)
0
0
0
0
0
self_test_constant(7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
self_test_constant(15:0) : 16 bit constant presented at the test and noise generator output when enabled. Used for test and
debug purposes.
Register name: RECV _PMETER0_LSB
Page: 0x1820
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Address: 0x20
READ ONLY
BIT15
BIT8
0
0
0
recv_pmeter0(15:8)
0
0
0
0
0
recv_pmeter0(7:0)
0
0
0
0
0
0
BIT7
recv_pmeter0(15:0)
0
BIT0
0
: Lower bits of the power meter 0 measurement
Register name: RECV_PMETER0_MID
Page: 0x1820
Address: 0x21
READ ONLY
BIT15
BIT8
0
0
0
recv_pmeter0(31:24)
0
0
0
0
0
recv_pmeter0(23:16)
0
0
0
0
0
0
BIT7
recv_pmeter0(31:16)
0
BIT0
0
: Mid bits of the power meter 0 measurement
Register name: RECV_PMETER0_LMSB
Page: 0x1820
Address: 0x22
READ ONLY
BIT15
BIT8
0
0
0
recv_pmeter0(47:40)
0
0
0
0
0
recv_pmeter0(39:32)
0
0
0
0
0
0
BIT7
recv_pmeter0(47:32)
0
BIT0
0
: Lower MSB bits of the power meter 0 measurement
Register name: RECV_PMETER0_UMSB
Page: 0x1820
Address: 0x23
READ ONLY
BIT15
unused
0
BIT7
0
unused
0
unused
0
0
0
recv_pmeter0(57:48)
unused
0
unused
0
recv_pmeter0(55:48)
0
0
unused
0
0
BIT8
recv_pmeter0(57:56)
0
0
BIT0
0
0
: Upper MSB bits of the power meter 0 measurement
Register name: RECV_PMETER1_LSB
Page: 0x1820
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Address: 0x24
READ ONLY
BIT15
BIT8
0
0
0
recv_pmeter1(15:8)
0
0
0
0
0
recv_pmeter1(7:0)
0
0
0
0
0
0
BIT7
recv_pmeter1(15:0)
0
BIT0
0
: Lower bits of the power meter 1 measurement
Register name: RECV_PMETER1_MID
Page: 0x1820
Address: 0x25
READ ONLY
BIT15
BIT8
0
0
0
recv_pmeter1(31:24)
0
0
0
0
0
recv_pmeter1(23:16)
0
0
0
0
0
0
BIT7
recv_pmeter1(31:16)
0
BIT0
0
: Mid bits of the power meter 1 measurement
Register name: RECV_PMETER1_LMSB
Page: 0x1820
Address: 0x26
READ ONLY
BIT15
BIT8
0
0
0
recv_pmeter1(47:40)
0
0
0
0
0
recv_pmeter1(39:32)
0
0
0
0
0
0
BIT7
recv_pmeter1(47:32)
0
BIT0
0
: Lower MSB bits of the power meter 1 measurement
Register name: RECV_PMETER1_UMSB
Page: 0x1820
Address: 0x27
READ ONLY
BIT15
unused
0
BIT7
0
unused
0
unused
0
0
0
recv_pmeter1(57:48)
unused
0
unused
0
recv_pmeter1(55:48)
0
0
unused
0
0
BIT8
recv_pmeter1(57:56)
0
0
BIT0
0
0
: Upper MSB bits of the power meter 1 measurement
Register name: RECV_PMETER2_LSB
Page: 0x1820
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Address: 0x28
READ ONLY
BIT15
BIT8
0
0
0
recv_pmeter2(15:8)
0
0
0
0
0
recv_pmeter2(7:0)
0
0
0
0
0
0
BIT7
recv_pmeter2(15:0)
0
BIT0
0
: Lower bits of the power meter 2 measurement
Register name: RECV_PMETER2_MID
Page: 0x1820
Address: 0x29
READ ONLY
BIT15
BIT8
0
0
0
recv_pmeter2(31:24)
0
0
0
0
0
recv_pmeter2(23:16)
0
0
0
0
0
0
BIT7
recv_pmeter2(31:16)
0
BIT0
0
: Mid bits of the power meter 2 measurement
Register name: RECV_PMETER2_LMSB
Page: 0x1820
Address: 0x2A
READ ONLY
BIT15
BIT8
0
0
0
recv_pmeter2(47:40)
0
0
0
0
0
recv_pmeter2(39:32)
0
0
0
0
0
0
BIT7
recv_pmeter2(47:32)
0
BIT0
0
: Lower MSB bits of the power meter 2 measurement
Register name: RECV_PMETER2_UMSB
Page: 0x1820
Address: 0x2B
READ ONLY
BIT15
unused
0
BIT7
0
unused
0
unused
0
0
0
recv_pmeter2(57:48)
unused
0
unused
0
recv_pmeter2(55:48)
0
0
unused
0
0
BIT8
recv_pmeter2(57:56)
0
0
BIT0
0
0
: Upper MSB bits of the power meter 2 measurement
Register name: RECV_PMETER3_LSB
Page: 0x1820
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Address: 0x2C
READ ONLY
BIT15
BIT8
0
0
0
recv_pmeter3(15:8)
0
0
0
0
0
recv_pmeter3(7:0)
0
0
0
0
0
0
BIT7
recv_pmeter3(15:0)
0
BIT0
0
: Lower bits of the power meter 3 measurement
Register name: RECV_PMETER3_MID
Page: 0x1820
Address: 0x2D
READ ONLY
BIT15
BIT8
0
0
0
recv_pmeter3(31:24)
0
0
0
0
0
recv_pmeter3(23:16)
0
0
0
0
0
0
BIT7
recv_pmeter3(31:16)
0
BIT0
0
: Mid bits of the power meter 3 measurement
Register name: RECV_PMETER3_LMSB
Page: 0x1820
Address: 0x2E
READ_ONLY
BIT15
BIT8
0
0
0
recv_pmeter3(47:40)
0
0
0
0
0
recv_pmeter3(39:32)
0
0
0
0
0
0
BIT7
recv_pmeter3(47:32)
0
BIT0
0
: Lower MSB bits of the power meter 3 measurement
Register name: RECV_PMETER3_UMSB
Page: 0x1820
Address: 0x2F
READ_ONLY
BIT15
unused
0
BIT7
0
unused
0
unused
0
0
0
recv_pmeter3(57:48)
unused
0
unused
0
recv_pmeter3(55:48)
0
0
unused
0
0
BIT8
recv_pmeter3(57:56)
0
0
BIT0
0
0
: Upper MSB bits of the power meter 3 measurement
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3.5.4
SLWS168 - OCTOBER 2005
Receive AGC Controls (Pages 0x1840 and 0x1860)
Register name: RAGC_CONFIG0
Page: 0x1840
Address: 0x0
BIT15
hp_ena_0
0
BIT7
ragc_
bypass_0
1
Hp_ena_1
0
hp_ena_2
0
hp_ena_3
0
sd_ena_0
0
sd_ena_1
0
sd_ena_2
0
ragc_
bypass_1
1
ragc_
bypass_2
1
ragc_
bypass_3
1
unused
unused
unused
BIT8
sd_ena_3
0
BIT0
unused
0
0
0
0
hp_ena_X
sd_ena_X
ragc_bypass_X
: Enables the high pass filter in receive AGC X when set.
: Enables the Signal Detect block in receive AGC X when set.
: Bypasses the receive AGC X block when set.
Register name: RAGC_CONFIG1
Page: 0x1840
Address: 0x1
BIT15
ragc_
freeze_0
0
BIT7
complex01
0
ragc_
freeze_1
0
ragc_
freeze_2
0
complex23
0
0
ragc_
freeze_3
0
ragc_
clear_0
0
ssel_ragc_interval_0(2:0)
0
0
BIT8
ragc_
clear_3
0
BIT0
ssel_ragc_interval_1(2:0)
0
0
0
ragc_
clear_1
0
ragc_
clear_2
0
ragc_freeze_X
ragc_clear_X
complex01
: Freezes the receive AGC block when set.
: Clears the loop error accumulator when set.
: When set, receive AGC 0 uses complex input with the second sample stream coming from
receive AGC 1. The clip detect, high pass, and squarer from receive AGC 1 are used to
generate inputs for receive AGC 0.
complex23
: When set, receive AGC 2 uses complex input with the second sample stream coming from
receive AGC 3. The clip detect, high pass, and squarer from receive AGC 3 are used to
generate inputs for receive AGC 2.
ssel_ragc_interval_0(2:0) : Selects the sync source for receive AGC 0. After a programmed delay from sync, the interval
update timer is started.
ssel_ragc_interval_1(2:0) : Selects the sync source for receive AGC 1. After a programmed delay from sync, the interval
update timer is started.
Register name: RAGC_CONFIG2
Page: 0x1840
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Address: 0x2
BIT15
ssel_ragc_freeze_0(2:0)
0
BIT7
ssel_ragc_fr
eeze_2(0)
0
0
ssel_ragc_freeze_1(2:0)
0
0
ssel_ragc_freeze_3(2:0)
0
0
0
unused
0
0
BIT8
ssel_ragc_
freeze_2(2:1)
0
0
0
BIT0
ssel_ragc_interval_2(2:0)
0
0
0
ssel_ragc_freeze_X(2:0) : Selects the sync source that will freeze the receive AGC loop when asserted.
ssel_ragc_interval_2(2:0) : Selects the sync source for receive AGC 2. After a programmed delay from sync, the interval
update timer is started.
Register name: RAGC_CONFIG3
Page: 0x1840
Address: 0x3
BIT15
ssel_ragc_clear_0(2:0)
0
BIT7
ssel_ragc_
clear_2(0)
0
0
ssel_ragc_clear_1(2:0)
0
0
ssel_ragc_clear_3(2:0)
0
0
0
unused
0
0
BIT8
ssel_ragc_
clear_2(2:1)
0
0
0
BIT0
ssel_ragc_interval_3(2:0)
0
0
0
ssel_agc_clear_X(2:0) : Controls the selection of the sync that will clear the receive AGC error accumulator.
ssel_agc_interval_3(2:0): Selects the sync source for receive AGC 3. After a programmed delay from sync, the interval
update timer is started.
Register name: RAGC0_INTEGINVL_LSB
Page: 0x1840
Address: 0x4
BIT15
BIT8
0
0
0
integ_interval_0(15:8)
0
0
0
0
0
integ_interval_0(7:0)
0
0
0
0
0
0
BIT7
integ_interval_0(15:0)
0
BIT0
0
: The 16 LSBs of the integration time for receive AGC 0
Register name: RAGC0_INTEGINVL_MSB
Page: 0x1840
Address: 0x5
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BIT15
BIT8
0
0
0
ragc_update_0(7:0)
0
0
0
0
0
integ_interval_0(23:16)
0
0
0
0
0
0
BIT7
0
BIT0
0
ragc_update_0(7:0)
: Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_0(23:16) : The eight MSBs of the integration time for receive AGC 0
Register name: RAGC0_CONFIG0
Page: 0x1840
Address: 0x6
BIT15
BIT8
0
0
0
0
hp_corner_0(2:0)
0
0
ragc_sync_delay_0(7:0)
0
0
0
0
acc_shift_0(4:0)
0
0
BIT7
0
0
0
BIT0
0
ragc_sync_delay_0(7:0) : The input sync to the receive AGC block is delayed by this number of samples.
hp_corner_0(2:0)
: Sets the corner frequency of the high pass filter. Larger values result in higher corner
frequencies
acc_shift_0(4:0)
: Selects the integrated power measurements result bits to be used as the error lookup table
address. A larger number means fewer samples will have to be integrated to achieve the same
result.
Register name: RAGC0_CONFIG1
Page: 0x1840
Address: 0x7
BIT15
acc_offset_0(5:0)
0
0
0
0
0
err_shift_0(2:0)
0
0
0
0
delay_adj_0(4:0)
0
BIT7
acc_offset_0(5:0)
err_shift_0(4:0)
delay_adj_0(4:0)
0
0
BIT8
err_shift_0(4:3)
0
0
BIT0
0
0
: Constant subtracted from the integrated power measurement result before the error lookup table.
: Adjusts the loop gain by controlling the amount of shifting applied to the error lookup table output.
Larger values result in higher gain.
: Sets the delay difference, in samples, between the DVGA outputs and the value applied to the
sample multiplier.
Register name: RAGC0_SD_THRESH
Page: 0x1840
Address: 0x8
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BIT15
BIT8
0
0
0
sd_thresh_0(15:8)
0
0
0
0
0
sd_thresh_0(7:0)
0
0
0
0
0
0
BIT7
sd_thresh_0(15:0)
0
BIT0
0
: This is the threshold used by the Signal Detect block to determine if there is signal on the inputs.
The comparison is done to the output of the squarer block, which is a 32 bit word. Because of
this, these bits are aligned with bits 24 down to 8 of the 32 bit squared value.
Register name: RAGC0_SD_TIMER
Page: 0x1840
Address: 0x9
BIT15
BIT8
0
0
0
sd _timer_0(15:8)
0
0
0
0
0
sd _timer_0(7:0)
0
0
0
0
0
0
BIT7
sd_timer_0(15:0)
0
BIT0
0
: Qualification window timer for loss of input signal.
Register name: RAGC0_SD_SAMPLES
Page: 0x1840
Address: 0xA
BIT15
BIT8
0
0
0
sd_samples_0(15:8)
0
0
0
0
0
sd_samples_0(7:0)
0
0
0
0
0
0
BIT7
sd_samples_0(15:0)
0
BIT0
0
: Number of samples that must be below the sd_thresh_X within the sd_timer_X timer value for the
loss of signal condition to occur.
Register name: RAGC0_CLIP_HITHRESH
Page: 0x1840
Address: 0xB
BIT15
BIT8
0
0
0
clip_hi_thresh_0(15:8)
0
0
0
0
0
clip_hi_thresh_0(7:0)
0
0
0
0
0
0
BIT7
clip_hi_thresh_0(15:0)
0
BIT0
0
: The high threshold value for clip detection.
Register name: RAGC0_CLIP_LOTHRESH
Page: 0x1840
Address: 0xC
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BIT15
BIT8
0
0
0
clip_lo_thresh_0(15:8)
0
0
0
0
0
clip_lo_thresh_0(7:0)
0
0
0
0
0
0
BIT7
clip_lo_thresh_0(15:0)
0
BIT0
0
: The low threshold value for clip detection.
Register name: RAGC0_CLIP_HITIMER
Page: 0x1840
Address: 0xD
BIT15
BIT8
0
0
0
clip_hi_timer_0(15:8)
0
0
0
0
0
clip_hi_timer_0(7:0)
0
0
0
0
0
0
BIT7
clip_hi_timer_0(15:0)
0
BIT0
0
: The high timer value in Samples
Register name: RAGC0_CLIP_LOTIMER
Page: 0x1840
Address: 0xE
BIT15
BIT8
0
0
0
clip_lo_timer_0(15:8)
0
0
0
0
0
clip_lo_timer_0(7:0)
0
0
0
0
0
0
BIT7
clip_lo_timer_0(15:0)
0
BIT0
0
: The low timer value in Samples.
Register name: RAGC0_CLIP_SAMPLES
Page: 0x1840
Address: 0xF
BIT15
BIT8
0
0
0
clip_hi_samples_0(7:0)
0
0
0
0
0
clip_lo_samples_0(7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
clip_hi_samples_0(7:0) : Number of samples above the high threshold within the clip high time to enable the clip event.
clip_lo_samples_0(7:0) : Number of samples below the low threshold within the clip low time to disable the clip event.
Register name: RAGC0_CLIP_ERROR
Page: 0x1840
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Address: 0x10
BIT15
BIT8
0
0
0
clip_error_0(15:8)
0
0
0
0
0
clip_error_0(7:0)
0
0
0
0
0
0
BIT7
clip_error_0(15:0)
0
BIT0
0
: This is the error value that is added into the loop accumulator when a clip is detected.
Register name: RAGC1_INTEGINVL_LSB
Page: 0x1840
Address: 0x11
BIT15
BIT8
0
0
0
integ_interval_1(15:8)
0
0
0
0
0
integ_interval_1(7:0)
0
0
0
0
0
0
BIT7
integ_interval_1(15:0)
0
BIT0
0
: The LSBs of the integration time for receive AGC 1
Register name: RAGC1_INTEGINVL_MSB
Page: 0x1840
Address: 0x12
BIT15
BIT8
0
0
0
ragc_update_1(7:0)
0
0
0
0
0
integ_interval_1(23:16)
0
0
0
0
0
0
BIT7
0
BIT0
0
ragc_update_1(7:0)
: Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_1(23:16) : The MSBs of the integration time for receive AGC 1
Register name: RAGC1_CONFIG0
Page: 0x1840
Address: 0x13
BIT15
BIT8
0
0
0
0
hp_corner_1(2:0)
0
0
ragc_sync_delay_1(7:0)
0
0
0
0
acc_shift_1(4:0)
0
0
BIT7
0
0
0
BIT0
0
ragc_sync_delay_1(7:0) : The input sync to the receive AGC block is delayed by this value of samples.
hp_corner_1(2:0)
: This sets the corner frequency of the High Pass filter. Larger values result in higher corner
frequencies.
acc_shift_1(4:0)
: Selects the integrated power measurements result bits to be used as the error lookup table
address. A larger number means fewer samples will have to be integrated to achieve the same
result.
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Register name: RAGC1_CONFIG1
Page: 0x1840
Address: 0x14
BIT15
acc_offset_1(5:0)
0
0
0
0
0
err_shift_1(2:0)
0
0
0
0
delay_adj_1(4:0)
0
BIT7
acc_offset_1(5:0)
err_shift_1(4:0)
delay_adj_1(4:0)
0
0
BIT8
err_shift_1(4:3)
0
0
BIT0
0
0
: Constant subtracted from the integrated power measurement result before the error lookup table.
: Controls the loop gain by left shifting the error output. Larger values result in higher gain.
: Sets the delay difference, in samples, between the DVGA outputs and the value applied to the
sample multiplier.
Register name: RAGC1_SD_THRESH
Page: 0x1840
Address: 0x15
BIT15
BIT8
0
0
0
sd_thresh_1(15:8)
0
0
0
0
0
sd_thresh_1(7:0)
0
0
0
0
0
0
BIT7
sd_thresh_1(15:0)
0
BIT0
0
: This is the threshold used by the Signal Detect block to determine if there is signal on the inputs.
The comparison is done to the output of the squarer block, which is a 32 bit word. Because of
this, these bits are aligned with bits 24 down to 8 of the 32 bit squared value.
Register name: RAGC1_SD_TIMER
Page: 0x1840
Address: 0x16
BIT15
BIT8
0
0
0
sd_timer_1(15:8)
0
0
0
0
0
sd_timer_1(7:0)
0
0
0
0
0
0
BIT7
sd_timer_1(15:0)
0
BIT0
0
: After the first no signal sample occurs, this is the amount of samples that control the length of
time to determine the loss of signal condition.
Register name: RAGC1_SD_SAMPLES
Page: 0x1840
Address: 0x17
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BIT15
BIT8
0
0
0
sd_samples_1(15:8)
0
0
0
0
0
sd_samples_1(7:0)
0
0
0
0
0
0
BIT7
sd_samples_1(15:0)
0
BIT0
0
: Number of samples that must be below the sd_thresh_X threshold within the sd_timer_X timer
value for the loss of signal condition to occur.
Register name: RAGC1_CLIP_HITHRESH
Page: 0x1840
Address: 0x18
BIT15
BIT8
0
0
0
clip_hi_thresh_1(15:8)
0
0
0
0
0
clip_hi_thresh_1(7:0)
0
0
0
0
0
0
BIT7
clip_hi_thresh_1(15:0)
0
BIT0
0
: The high threshold value for clip detection.
Register name: RAGC1_CLIP_LOTHRESH
Page: 0x1840
Address: 0x19
BIT15
BIT8
0
0
0
clip_lo_thresh_1(15:8)
0
0
0
0
0
clip_lo_thresh_1(7:0)
0
0
0
0
0
0
BIT7
clip_lo_thresh_1(15:0)
0
BIT0
0
: The low threshold value for clip detection.
Register name: RAGC1_CLIP_HITIMER
Page: 0x1840
Address: 0x1A
BIT15
BIT8
0
0
0
clip_hi_timer_1(15:8)
0
0
0
0
0
clip_hi_timer_1(7:0)
0
0
0
0
0
0
BIT7
clip_hi_timer_1(15:0)
0
BIT0
0
: The high timer value in samples.
Register name: RAGC1_CLIP_LOTIMER
Page: 0x1840
Address: 0x1B
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BIT15
BIT8
0
0
0
clip_lo_timer_1(15:8)
0
0
0
0
0
clip_lo_timer_1(7:0)
0
0
0
0
0
0
BIT7
clip_lo_timer_1(15:0)
0
BIT0
0
: The low timer value in samples.
Register name: RAGC1_CLIP_SAMPLES
Page: 0x1840
Address: 0x1C
BIT15
BIT8
0
0
0
clip_hi_samples_1(7:0)
0
0
0
0
0
clip_lo_samples_1(7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
clip_hi_samples_1(7:0) : Number of samples above the high threshold within the clip high time to enable the clip event.
clip_lo_samples_1(7:0) : Number of samples below the low threshold within the clip low time to disable the clip event.
Register name: RAGC1_CLIP_ERROR
Page: 0x1840
Address: 0x1D
BIT15
BIT8
0
0
0
clip_error_1(15:8)
0
0
0
0
0
clip_error_1(7:0)
0
0
0
0
0
0
BIT7
clip_error_1(15:0)
0
BIT0
0
: This is the error value that is added into the loop accumulator when a clip is detected.
Register name: RAGC2_INTEGINVL_LSB
Page: 0x1840
Address: 0x1E
BIT15
BIT8
0
0
0
integ_interval_2(15:8)
0
0
0
0
0
integ_interval_2(7:0)
0
0
0
0
0
0
BIT7
integ_interval_2(15:0)
0
BIT0
0
: The LSBs of the integration time for receive AGC 2
Register name: RAGC2_INTEGINVL_MSB
Page: 0x1840
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Address: 0x1F
BIT15
BIT8
0
0
0
ragc_update_2(7:0)
0
0
0
0
0
integ_interval_2(23:16)
0
0
0
0
0
0
BIT7
0
BIT0
0
ragc_update_2(7:0)
: Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_2(23:16) : The MSBs of the integration time for receive AGC 2
Register name: RAGC2_CONFIG0
Page: 0x1860
Address: 0x20
BIT15
BIT8
0
0
0
0
hp_corner_2(2:0)
0
0
ragc_sync_delay_2(7:0)
0
0
0
0
acc_shift_2(4:0)
0
0
BIT7
0
0
0
BIT0
0
ragc_sync_delay_2(7:0) : The input sync to the receive AGC block is delayed by this value of samples.
hp_corner_2(2:0)
: This sets the corner frequency of the High Pass filter. Larger values result in higher corner
frequencies.
acc_shift_2(4:0)
: Selects the integrated power measurements result bits to be used as the error lookup table
address. A larger number means fewer samples will have to be integrated to achieve the same
result.
Register name: RAGC2_CONFIG1
Page: 0x1860
Address: 0x21
BIT15
acc_offset_2(5:0)
0
0
0
0
0
err_shift_2(2:0)
0
0
0
0
delay_adj_2(4:0)
0
BIT7
acc_offset_2(5:0)
err_shift_2(4:0)
delay_adj_2(4:0)
0
0
BIT8
err_shift_2(4:3)
0
0
BIT0
0
0
: Constant subtracted from the integrated power measurement result before the error lookup table.
: Controls the loop gain by left shifting the error output. Larger values result in higher gain..
: Sets the delay difference, in samples, between the DVGA outputs and the value applied to the
sample multiplier.
Register name: RAGC2_SD_THRESH
Page: 0x1860
Address: 0x22
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BIT15
BIT8
0
0
0
sd_thresh_2(15:8)
0
0
0
0
0
sd_thresh_2(7:0)
0
0
0
0
0
0
BIT7
sd_thresh_2(15:0)
0
BIT0
0
: This is the threshold used by the Signal Detect block to determine if there is signal on the inputs.
The comparison is done to the output of the squarer block, which is a 32 bit word. Because of
this, these bits are aligned with bits 24 down to 8 of the 32 bit squared value.
Register name: RAGC2_SD_TIMER
Page: 0x1860
Address: 0x23
BIT15
BIT8
0
0
0
sd_timer_2(15:8)
0
0
0
0
0
sd_timer_2(7:0)
0
0
0
0
0
0
BIT7
sd_timer_2(15:0)
0
BIT0
0
: After the first no signal sample occurs, this is the amount of samples that control the length of
time to determine the loss of signal condition.
Register name: RAGC2_SD_SAMPLES
Page: 0x1860
Address: 0x24
BIT15
BIT8
0
0
0
sd_samples_2(15:8)
0
0
0
0
0
sd_samples_2(7:0)
0
0
0
0
0
0
BIT7
sd_samples_2(15:0)
0
BIT0
0
: Number of samples that must be below the sd_thresh_X threshold within the sd_timer_X timer
value for the loss of signal condition to occur.
Register name: RAGC2_CLIP_HITHRESH
Page: 0x1860
Address: 0x25
BIT15
BIT8
0
0
0
clip_hi_thresh_2(15:8)
0
0
0
0
0
clip_hi_thresh_2(7:0)
0
0
0
0
0
0
BIT7
clip_hi_thresh_2(15:0)
0
BIT0
0
: The high threshold value for clip detection.
Register name: RAGC2_CLIP_LOTHRESH
Page: 0x1860
Address: 0x26
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BIT15
BIT8
0
0
0
clip_lo_thresh_2(15:8)
0
0
0
0
0
clip_lo_thresh_2(7:0)
0
0
0
0
0
0
BIT7
clip_lo_thresh_2(15:0)
0
BIT0
0
: The low threshold value for clip detection.
Register name: RAGC2_CLIP_HITIMER
Page: 0x1860
Address: 0x27
BIT15
BIT8
0
0
0
clip_hi_timer_2(15:8)
0
0
0
0
0
clip_hi_timer_2(7:0)
0
0
0
0
0
0
BIT7
clip_hi_timer_2(15:0)
0
BIT0
0
: The high timer value in samples
Register name: RAGC2_CLIP_LOTIMER
Page: 0x1860
Address: 0x28
BIT15
BIT8
0
0
0
clip_lo_timer_2(15:8)
0
0
0
0
0
clip_lo_timer_2(7:0)
0
0
0
0
0
0
BIT7
clip_lo_timer_2(15:0)
0
BIT0
0
: The low timer value in samples.
Register name: RAGC2_CLIP_SAMPLES
Page: 0x1860
Address: 0x29
BIT15
BIT8
0
0
0
clip_hi_samples_2(7:0)
0
0
0
0
0
clip_lo_samples_2(7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
clip_hi_samples_2(7:0) : Number of samples above the high threshold within the clip high time to enable the clip event.
clip_lo_samples_2(7:0) : Number of samples below the low threshold within the clip low time to disable the clip event.
Register name: RAGC2_CLIP_ERROR
Page: 0x1860
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Address: 0x2A
BIT15
BIT8
0
0
0
clip_error_2(15:8)
0
0
0
0
0
clip_error_2(7:0)
0
0
0
0
0
0
BIT7
clip_error_2(15:0)
0
BIT0
0
: This is the error value that is added into the loop accumulator when a clip is detected.
Register name: RAGC3_INTEGINVL_LSB
Page: 0x1860
Address: 0x2B
BIT15
BIT8
0
0
0
integ_interval_3(15:8)
0
0
0
0
0
integ_interval_3(7:0)
0
0
0
0
0
0
BIT7
integ_interval_3(15:0)
0
BIT0
0
: The LSBs of the integration time for receive AGC 3
Register name: RAGC3_INTEGINVL_MSB
Page: 0x1860
Address: 0x2C
BIT15
BIT8
0
0
0
ragc_update_3(7:0)
0
0
0
0
0
integ_interval_3(23:16)
0
0
0
0
0
0
BIT7
0
BIT0
0
ragc_update_3(7:0)
: Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_3(23:16) : The MSBs of the integration time for receive AGC 3
Register name: RAGC3_CONFIG0
Page: 0x1860
Address: 0x2D
BIT15
BIT8
0
0
0
0
hp_corner_3(2:0)
0
0
ragc_sync_delay_3(7:0)
0
0
0
0
acc_shift_3(4:0)
0
0
BIT7
0
0
0
BIT0
0
ragc_sync_delay_3(7:0) : The input sync to the receive AGC block is delayed by this value of samples.
hp_corner_3(2:0)
: This sets the corner frequency of the High Pass filter. Larger values result in higher corner
frequencies.
acc_shift_3(4:0)
: Selects the integrated power measurements result bits to be used as the error lookup table
address. A larger number means fewer samples will have to be integrated to achieve the same
result.
.
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Register name: RAGC3_CONFIG1
Page: 0x1860
Address: 0x2E
BIT15
acc_offset_3(5:0)
0
0
0
0
0
err_shift_3(2:0)
0
0
0
0
delay_adj_3(4:0)
0
BIT7
acc_offset_3(5:0)
err_shift_3(4:0)
delay_adj_3(4:0)
0
0
BIT8
err_shift_3(4:3)
0
0
BIT0
0
0
: Constant subtracted from the integrated power measurement result before the error lookup table.
: Controls the loop gain by left shifting the error output. Larger values result in higher gain.
: Sets the delay difference, in samples, between the DVGA outputs and the value applied to the
sample multiplier.
Register name: RAGC3_SD_THRESH
Page: 0x1860
Address: 0x2F
BIT15
BIT8
0
0
0
sd_thresh_3(15:8)
0
0
0
0
0
sd_thresh_3(7:0)
0
0
0
0
0
0
BIT7
sd_thresh_3(15:0)
0
BIT0
0
: This is the threshold used by the Signal Detect block to determine if there is signal on the inputs.
The comparis on is done to the output of the squarer block, which is a 32 bit word. Because of
this, these bits are aligned with bits 24 down to 8 of the 32 bit squared value.
Register name: RAGC3_SD_TIMER
Page: 0x1860
Address: 0x30
BIT15
BIT8
0
0
0
sd_timer_3(15:8)
0
0
0
0
0
sd_timer_3(7:0)
0
0
0
0
0
0
BIT7
sd_timer_3(15:0)
0
BIT0
0
: After the first no signal sample occurs, this is the amount of samples that control the length of
time to determine the loss of signal condition.
Register name: RAGC3_SD_SAMPLES
Page: 0x1860
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Address: 0x31
BIT15
BIT8
0
0
0
sd_samples_3(15:8)
0
0
0
0
0
sd_samples_3(7:0)
0
0
0
0
0
0
BIT7
sd_samples_3(15:0)
0
BIT0
0
: Number of samples that must be below the sd_thresh_X threshold within the sd_timer_X timer
value for the loss of signal condition to occur.
Register name: RAGC3_CLIP_HITHRESH
Page: 0x1860
Address: 0x32
BIT15
BIT8
0
0
0
clip_hi_thresh_3(15:8)
0
0
0
0
0
clip_hi_thresh_3(7:0)
0
0
0
0
0
0
BIT7
clip_hi_thresh_3(15:0)
0
BIT0
0
: The high threshold value for clip detection.
Register name: RAGC3_CLIP_LOTHRESH
Page: 0x1860
Address: 0x33
BIT15
BIT8
0
0
0
clip_lo_thresh_3(15:8)
0
0
0
0
0
clip_lo_thresh_3(7:0)
0
0
0
0
0
0
BIT7
clip_lo_thresh_3(15:0)
0
BIT0
0
: The low threshold value for clip detection.
Register name: RAGC3_CLIP_HITIMER
Page: 0x1860
Address: 0x34
BIT15
BIT8
0
0
0
clip_hi_timer_3(15:8)
0
0
0
0
0
clip_hi_timer_3(7:0)
0
0
0
0
0
0
BIT7
clip_hi_timer_3(15:0)
0
BIT0
0
: The clip high timer value in samples
Register name: RAGC3_CLIP_LOTIMER
Page: 0x1860
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Address: 0x35
BIT15
BIT8
0
0
0
clip_lo_timer_3(15:8)
0
0
0
0
0
clip_lo_timer_3(7:0)
0
0
0
0
0
0
BIT7
clip_lo_timer_3(15:0)
0
BIT0
0
: The clip low timer value in samples.
Register name: RAGC3_CLIP_SAMPLES
Page: 0x1860
Address: 0x36
BIT15
BIT8
0
0
0
clip_hi_samples_3(7:0)
0
0
0
0
0
clip_lo_samples_3(7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
clip_hi_samples_3(7:0) : Number of samples above the high threshold within the clip high time to enable a clip event.
clip_lo_samples_3(7:0) : Number of samples below the low threshold within the clip low time to disable a clip event.
Register name: RAGC3_CLIP_ERROR
Page: 0x1860
Address: 0x37
BIT15
BIT8
0
0
0
clip_error_3(15:8)
0
0
0
0
0
clip_error_3(7:0)
0
0
0
0
0
0
BIT7
clip_error_3(15:0)
0
BIT0
0
: Error value that is added into the loop accumulator when a clip is detected.
Register name: RAGC0_ACCUM_LSB
Page: 0x1860
Address: 0x38
READ ONLY
BIT15
BIT8
0
0
0
ragc0_accum(15:8)
0
0
0
0
0
ragc0_accum (7:0)
0
0
0
0
0
0
BIT7
ragc0_accum(15:0)
0
BIT0
0
: lower 16 bits of the ragc0 error accumulator.
Register name: RAGC0_ACCUM_MSB
Page: 0x1860
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Address: 0x39
READ ONLY
BIT15
BIT8
0
0
0
ragc0_accum(31:24)
0
0
0
0
0
ragc0_accum (23:16)
0
0
0
0
0
0
BIT7
ragc0_accum(31:16)
0
BIT0
0
: upper 16 bits of the ragc0 error accumulator.
Register name: RAGC1_ACCUM_LSB
Page: 0x1860
Address: 0x3A
READ ONLY
BIT15
BIT8
0
0
0
ragc1_accum(15:8)
0
0
0
0
0
ragc1_accum (7:0)
0
0
0
0
0
0
BIT7
ragc1_accum(15:0)
0
BIT0
0
: lower 16 bits of the ragc1 error accumulator.
Register name: RAGC1_ACCUM_MSB
Page: 0x1860
Addre ss: 0x3B
READ ONLY
BIT15
BIT8
0
0
0
ragc1_accum(31:24)
0
0
0
0
0
ragc1_accum (23:16)
0
0
0
0
0
0
BIT7
ragc1_accum(31:16)
0
BIT0
0
: upper 16 bits of the ragc1 error accumulator.
Register name: RAGC2_ACCUM_LSB
Page: 0x1860
Address: 0x3C
READ ONLY
BIT15
BIT8
0
0
0
ragc2_accum(15:8)
0
0
0
0
0
ragc2_accum (7:0)
0
0
0
0
0
0
BIT7
ragc2_accum(15:0)
0
BIT0
0
: lower 16 bits of the ragc2 error accumulator.
Register name: RAGC2_ACCUM_MSB
Page: 0x1860
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Address: 0x3D
READ ONLY
BIT15
BIT8
0
0
0
ragc2_accum(31:24)
0
0
0
0
0
ragc2_accum (23:16)
0
0
0
0
0
0
BIT7
ragc2_accum(31:16)
0
BIT0
0
: upper 16 bits of the ragc2 error accumulator.
Register name: RAGC3_ACCUM_LSB
Page: 0x1860
Address: 0x3E
READ ONLY
BIT15
BIT8
0
0
0
ragc3_accum(15:8)
0
0
0
0
0
ragc3_accum (7:0)
0
0
0
0
0
0
BIT7
ragc3_accum(15:0)
0
BIT0
0
: lower 16 bits of the ragc3 error accumulator.
Register name: RAGC3_ACCUM_MSB
Page: 0x1860
Address: 0x3F
READ ONLY
BIT15
BIT8
0
0
0
ragc3_accum(31:24)
0
0
0
0
0
ragc3_accum (23:16)
0
0
0
0
0
0
BIT7
ragc3_accum(31:16)
0
BIT0
0
: upper 16 bits of the ragc3 error accumulator.
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DDC Channel Controls (Pages 0x0%00 and 0x0%20, where % = 1 to F is the 2*(DDC channel #)+1)
Register name: FIR_MODE
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x0
BIT15
cdma_mode
0
BIT7
unused
0
unused
0
BIT8
0
0
0
crastarttap_cfir(4:0)
0
0
cdma_mode
crastarttap_pfir
crastarttap_cfir
0
crastarttap_pfir(4:0)
0
0
0
unused
0
unused
0
0
BIT0
unused
0
: When asserted the DDC block is in CDMA mode (2 streams per DDC block).
: These bits define the number of taps that PFIR will use for the filtering.
: These bits define the number of taps that CFIR will use for the filtering.
Formulas for the number of taps, in the different FIR’s, using the crastarttap word.
DDC PFIR: 4*(crastarttap_pfir+1)
DDC PFIR long mode: 8*(crastarttap_pfir+1)
DDC CFIR: 2*(crastarttap_cfir+1)
Register name: FIR_GAIN
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x1
BIT15
0
BIT7
unused
0
pfir_gain(2:0)
0
unused
0
pfir_gain(2:0)
cfir_gain
0
unused
0
unused
0
unused
0
unused
0
cfir_gain
0
unused
0
unused
0
unused
0
unused
0
BIT8
unused
0
BIT0
unused
0
: PFIR gain, from 2e-19 to 2e-12 for the receive PFIR. (“000” = 2e-19 and “111” = 2e-12)
: When ‘0’ then the gain of the CFIR is 2e-19, otherwise when set to ‘1’ the gain is 2e-18.
Register name: SQR_SUM
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x2
BIT15
BIT8
0
0
0
pmeter_sqr_sum_ddc(15:8)
0
0
0
0
0
pmeter_sqr_sum_ddc(7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
pmeter_sqr_sum _ddc(15:0): The sqr_sum register is the number of 4 sample sets to accumulate for a power measurement.
In CDMA mode, one sample set is the I & Q of the signal and diversity. Ia & Qa (signal) are
each squared and accumulated and Ib & Qb (diversity) are squared and accumulated. In UMTS
mode, each I and Q pair are squared and accumulated. 4 samples is equal to one SQR_SUM
count. The count is initiated when the sync is asserted or when the interval start time is
reached. When the SQR_NUM number is reached, the accumulated powers are made
available for MPU access and an interrupt is generated.
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Register name: STRT_INTRVL
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x3
BIT15
BIT8
0
0
0
pmeter_sync_delay_ddc(7:0)
0
0
0
0
0
pmeter_interval_ddc(7:0)
0
0
0
0
0
0
BIT7
0
BIT0
0
pmeter_sync_delay_ddc(7:0): The delay from selected sync source to when the power calculation starts. The actual value
is sync_delay + 1.
pmeter_interval_ddc(7:0)
: The start interval timer is the interval over which the SQR_SUM is restarted and must be
greater than the SQR_SUM. The actual interval is interval + 1, and must be greater than
the sqr_sum interval. The interval start counter and RMS power accumulation is started at
the sync pulse after the programmed delay and every time the interval counter reaches its
limit. This value is in 1024 sample units.
Register name: CIC_MODE1
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x4
BIT15
BIT8
0
0
BIT7
cic_scale_b(1:0)
0
0
cic_scale_a(4:0)
cic_scale_a(4:0)
0
cic_gain_
ddc
0
0
0
0
cic_scale_b(4:2)
0
0
BIT0
cic_decim(4:0)
0
0
0
0
0
: This sets the gain shift at the output of the A channel CIC. 0x00 is no shift, each increment by 1
increases the signal amplitude by 2X.
: This sets the gain shift at the output of the B channel CIC. 0x00 is no shift, each increment by 1
increases the signal amplitude by 2X.
: Adds a fixed gain of 12dB at the CIC output when asserted.
: Sets the CIC decimation rate, where decimation is cic_decim + 1.
cic_scale_b(4:0)
cic_gain_ddc
cic_decim(4:0)
Register name: CIC_MODE2
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x5
BIT15
0
0
cic_m2_ena_a(5:0)
0
0
0
0
unused
0
unused
0
BIT7
0
cic_m2_ena_b(3:0)
0
0
cic_m2_ena_a(5:0)
cic_m2_ena_b(5:0)
0
: Programs the A channel CIC fir sections M
cic_m2_ena_a(0) controls the M value for the first
the M value for the last comb section.
: Programs the B channel CIC fir sections M
cic_m2_ena_b(0) controls the M value for the first
the M value for the last comb section.
BIT8
cic_m2_ena_b(5:4)
0
0
BIT0
unused
unused
0
0
value to 2 when set, 1 when cleared.
comb section and cic_m2_ena_a(5) controls
value to 2 when set, 1 when cleared.
comb section and cic_m2_ena_b(5) controls
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Register name: TADJC
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x6
DOUBLE BUFFERED, REQUIRES SYNC FOR LOADING
BIT15
unused
0
BIT7
unused
0
unused
0
0
unused
0
tadj_offset_coarse_a(2:0)
0
0
0
tadj_offset_coarse_b(2:0)
0
0
unused
0
unused
0
unused
0
unused
0
BIT8
unused
0
BIT0
unused
0
tadj_offset_coarse_a(2:0) : This is the coarse time adjustment offset and acts as an offset from the write address in the
delay ram. This value affects the A data in the path if CDMA mode is being used. Each LSB is
one more offset between input to the course delay block and the output of the course block.
tadj_offset_coarse_b(2:0) : Effects the B channel in CDMA, just as the above effects the A channel.
Register name: TADJF
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x7
DOUBLE BUFFERED, REQUIRES SYNC FOR LOADING
BIT15
tadj_offset_fine_a(2:0)
0
0
0
BIT7
tadj_interp
(0)
0
tadj_offset_fine_b(2:0)
0
0
0
unused
unused
unused
unused
unused
0
0
0
0
0
tadj_offset_fine_a(2:0)
tadj_offset_fine_b(2:0)
tadj_interp(2:0)
BIT8
tadj_interp(2:1)
0
0
BIT0
unused
unused
0
0
: This is the fine adjust (zero stuff offset) value. It adjusts the time delay at the rxclk rate. This value
affects the A channel data in the path if CDMA mode is being used.
: Same as above except this value affects the B channel data in CDMA mode.
: This is the interpolation (zero stuff) value for the fine time adjust block. Interpolation can be from 1
to 8 (tadj_interp + 1). This value affects the A and B data in the path if CDMA mode is being
used.
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Register name: PHASEADD0A
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x8
DOUBLE BUFFERED, REQUIRES SYNC FOR LOADING
BIT15
BIT8
0
0
0
phase_add_a(15:8)
0
0
0
0
0
phase_add_a(7:0)
0
0
0
0
0
0
BIT7
phase_add_a(15:0)
0
BIT0
0
: This 32 bit word is used to control the frequency of the NCO. This value is added to the frequency
accumulator every clock cycle (UMTS mode and Main channel in CDMA mode).
Register name: PHASEADD1A
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x9
DOUBLE BUFFERED, REQUIRES SYNC FOR LOADING
BIT15
BIT8
0
0
0
phase_add_a(31:24)
0
0
0
0
0
phase_add_a(23:16)
0
0
0
0
0
0
BIT7
phase_add_a(31:16)
0
BIT0
0
: This 32 bit word is used to control the frequency of the NCO. This value is added to the frequency
accumulator every clock cycle (UMTS mode and A channel in CDMA mode).
Register name: PHASEADD0B
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0xA
DOUBLE BUFFERED, REQUIRES SYNC FOR LOADING
BIT15
BIT8
0
0
0
phase_add_b(15:8)
0
0
0
0
0
phase_add_b(7:0)
0
0
0
0
0
0
BIT7
phase_add_b(15:0)
:
0
BIT0
0
This 32 bit word is used to control the frequency of the NCO. This value is added to the frequency
accumulator every clock cycle (B channel in CDMA mode).
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Register name: PHASEADD1B
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0xB
DOUBLE BUFFERED, REQ UIRES SYNC FOR LOADING
BIT15
BIT8
0
0
0
phase_add_b(31:24)
0
0
0
0
0
phase_add_b(23:16)
0
0
0
0
0
0
BIT7
phase_add_b(31:16)
0
BIT0
0
: This 32 bit word is used to control the frequency of the NCO. This value is added to the frequency
accumulator every clock cycle (B channel in CDMA mode).
Register name: PHASE_OFFSETA
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0xC
DOUBLE BUFFERED, REQUIRES SYNC FOR LOADING
BIT15
BIT8
0
0
0
phase_offset_a(15:8)
0
0
0
0
0
phase_offset_a(7:0)
0
0
0
0
0
0
BIT7
phase_offset_a(15:0)
0
BIT0
0
: This is the fixed phase offset added to the output of the frequency accumulator for sinusoid
generation in the NCO. (UMTS mode and A channel in CDMA mode)
Register name: PHASE_OFFSETB
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0xD
DOUBLE BUFFERED, REQUIRES SYNC FOR LOADING
BIT15
BIT8
0
0
0
phase_offset_b(15:8)
0
0
0
0
0
phase_offset_b(7:0)
0
0
0
0
0
0
BIT7
phase_offset_b(15:0)
0
BIT0
0
: This is the fixed phase offset added to the output of the frequency accumulator for sinusoid
generation in the NCO. (B channel in CDMA mode)
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Register name: CONFIG1
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0xE
BIT15
dither_ena
0
BIT7
unused
0
dither_mask(1:0)
0
0
pmeter_
sync_
disable
0
unused
unused
unused
unused
0
0
0
0
dither_ena
dither_mask(1)
dither_mask(0)
pmeter_sync_disable
:
:
:
:
ddc_ena
:
muxed_data
:
mixer_gain
mpu_ram_read
:
:
zero_qsample
:
mux_pos
:
mux_factor
:
ddc_ena
BIT8
mpu_ram_
read
muxed
_data
mixer_gain
0
0
1
zero_
qsample
0
mux_pos
0
BIT0
mux_factor
0
0
This bit controls whether dither is turned on(1) or off(0).
This bit controls the MASKing of the dither word’s MSB. (1= MASKed, 0=used in dither word)
This bit controls the MASKing of the dither word’s MSB-1. (1= MASKed, 0=used in dither word)
Turns off the sync to the channel power meter. This can be used to individually turn off syncs to a
channels power meter while still having syncs to other power meters available.
When set this turns on the DDC. When cleared, the clocks to this block are turned off. For the
DDC blocks used as the second half in the long PFIR configuration, this bit should be cleared.
When asserted the DDC mux block assumes that multiple channels are muxed together on one
input data stream. For factory use only.
For a 2X muxed stream it would look like: Sa0, Sb0, Sa1, Sb1, Sa2, Sb2 …. etc...
Adds a fixed 6 dB of gain to the mixer output(before round and limiting) when asserted.
(TESTING PURPOSES) Allows the coefficient RAMs in the PFIR/CFIR to be read out the mpu
data bus. Unfortunately, this cannot be done during normal operation and must be done when the
state of the output data is not important. THIS BIT MUST ONLY BE SET DURING THE MPU
READ OPERATION AND MUST BE CLEARED FOR NORMAL DDC OPERATION.
When asserted, the Q sample into the mixer is held to zero. For UMTS mode at any input rate,
and CDMA mode with input rates of rxclk/2 or lower, this bit must be set for real only input data
mode (also for muxed input data stream modes). For real only inputs at the full rxclk rate in
CDMA mode, the remix_only bit must be set in the DDCCONFIG1 register.
These bits set the position for selection in the muxed data stream. This value must be less than
or equal to the mux_factor bits.
These two bits set the number of channels in the data stream. 0=1 stream, 1=2 streams. The
ch_rate_sel bits for the DDC should be programmed to rxclk/2 for the 2 streams mode.
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Register name: CONFIG2
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0xF
BIT15
unused
0
BIT7
unused
0
unused
0
unused
0
unused
0
unused
0
0
0
ddc_tst_sel(5:0)
unused
0
unused
0
ddc_tst_sel(5:0)
0
0
unused
0
BIT8
unused
0
BIT0
0
0
: This is the selection of which signal comes out the test bus. When a constant ‘0’ is selected this
also reduces power by preventing the data at the input of the tst_blk from changing. It does not
stop the clock however. The 36bits for the testbus are routed to the rxin_c, rxin_d, dvga_c and
dvga_d pins on the chip.
SYNC on dvga_c(0)
AFLAG on dvga_d(5)
N
Y
Y
N
N
N
N
Y
Y
ddc_tst_sel(5:0)
N
N
N
N
001001
001010
001011
001100
Data selected for output (36 bits total)
rxin_d(15:0), dvga_c(3:2), rxin_c(15:0), dvga_c(5:4)
cons tant 0
pfir output - (35:18) I and (17:0) Q
cfir output – (35:18) I and (17:0) Q
tadj A output - (35:18) I and (17:0) Q
tadj B output - (35:18) I and (17:0) Q
nco SINE output – (35:20) zeroed (19:0) SINE
nco COSINE output – (35:20) zeroed (19:0) COSINE
cic output - (35:18) I and (17:0) Q
agc output – (35:11) I and (10:0) Q
{full 25b I result and upper 11b Q result}
mix A output - (35:18) i*cos-q*sin and (17:0) i*sin+q*cos
mix B output - (35:18) i*cos -q*sin and (17:0) i*sin+q*cos
DDC MUX A output (35:18) I and (17:0) Q
DDC MUX B output (35:18) I and (17:0) Q
000000
000001
000010
000011
000100
000101
000110
000111
001000
Register name: AGC_CONFIG1
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x10
BIT15
BIT8
0
agc_dblw(3:0)
0
0
0
0
agc_dabv(3:0)
0
0
0
agc_dzro(3:0)
0
0
0
0
agc_dsat(3:0)
0
0
BIT7
0
BIT0
0
agc_dblw(3:0)
: The value to shift the gain that is then added to the accumulator when the value of the incoming
data * current gain value is below the Threshold.
agc_dabv(3:0)
: The value to shift the gain that is then subtracted from the accumulator when the value of the
incoming data * the current gain value is above the Threshold.
agc_dzro(3:0)
: The value to shift the gain that is then added to the accumulator when the value of the incoming
data * current gain values consistently equal to zero. (Usually a smaller number than
agc_dblw).
agc_dsat(3:0)
: The value to shift the gain that is then subtracted form the accumulator when the value of the
incoming data * the current gain value is consistently equal to maximum (saturation).
Note:
The larger the number in the above words, the smaller the step size. The above values control the AGC gain
shifting (range is from 3 to 18).
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Register name: AGC_CONFIG2
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x11
BIT15
BIT8
0
zero_msk(3:0)
0
0
0
0
0
agc_thresh(7:0)
0
0
0
agc_rnd(3:0)
0
0
BIT7
zero_msk(3:0)
agc_rnd(3:0)
0
0
0
0
BIT0
0
: Masks the lower 4 bits of the magnitude of the input signal so that they are counted as zeros.
: Determines where to round the output of the AGC; the number of bits output is (18 – agc_rnd).
For example, 0000 is 18 bits.
: Threshold for (input * gain) comparison. This value is compared to the magnitude of the upper
eight bits of the agc output.
agc_thresh(7:0)
Register name: AGC_CONFIG3
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x12
BIT15
unused
0
BIT7
unused
BIT8
unused
unused
0
0
unused
unused
0
0
0
agc_freeze
agc_
freeze
0
agc_
clear
0
agc_max_cnt(3:0)
0
0
0
0
BIT0
agc_zero_cnt(3:0)
0
0
0
0
: Freezes the agc when set. This should be asserted when the AGC algorithm is bypassed or held
constant.
: When the agc_output (input * gain) is at full scale for this number of samples, then the gain shift
value is changed to agc_dsat.
: Clears the AGC accumulator when set. Assert this when the AGC is in bypass mode.
: when the agc_output (input * gain) is zero value for this number of samples, then the gain shift
value is changed to agc_dzro.
agc_max_cnt(3:0)
agc_clear
agc_zero_cnt(3:0)
Register name: AGC_GAINMSB
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x13
DOUBLE BUFFERED, REQUIRES SYNC FOR LOADING
BIT15
BIT8
0
0
0
agc_gaina(23:16)
0
0
0
0
0
agc_gainb(23:16)
0
0
0
0
0
0
BIT7
agc_gaina(23:16)
agc_gainb(23:16)
0
BIT0
0
: MSBs of the agc_gaina word.
: MSBs of the agc_gainb word.
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Register name: AGC_GAINA
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x14
DOUBLE BUFFERED, REQUIRES SYNC FOR LOADING
BIT15
BIT8
0
0
0
agc_gaina(15:8)
0
0
0
0
0
agc_gaina(7:0)
0
0
0
0
0
0
BIT7
agc_gaina(15:0)
0
BIT0
0
: This is the lower 16 bits of the total 24 bits of programmable gain. The gain value is always
positive with the upper 12 bits being the integer value and the lower 12 bits being the fractional.
This gain value is used for all UMTS operations and for A channel data when in CDMA mode. A
24-bit value of 00000000001.000000000000 is unity gain.
Register name: AGC_GAINB
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x15
DOUBLE BUFFERED, REQUIRES SYNC FOR LOADING
BIT15
BIT8
0
0
0
agc_gainb(15:8)
0
0
0
0
0
agc_gainb(7:0)
0
0
0
0
0
0
BIT7
agc_gainb(15:0)
0
BIT0
0
: This is the lower 16 of the total of 24 bit of programmable gain. The gain value is always positive
with the upper 12 bits being the integer value and the lower 12 bits being the fractional. This gain
value is used for B channel data when in CDMA. A 24-bit value of 00000000001.000000000000
is unity gain.
Register name: AGC_AMAX
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x16
BIT15
BIT8
0
0
0
agc_amax(15:8)
0
0
0
0
0
agc_amax(7:0)
0
0
0
0
0
0
BIT7
agc_amax(15:0)
0
BIT0
0
: This is the maximum gaina or gainb can be adjusted up. The value programmed is a positive
value that is used to generate the most positive AGC gain adjust. For example, if 512 is
programmed, the maximum gain will be the programmed gain (AGC_GAINA/B) + 512.
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Register name: AGC_AMIN
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x17
BIT15
BIT8
0
0
0
agc_amin(15:8)
0
0
0
0
0
agc_amin(7:0)
0
0
0
0
0
0
BIT7
agc_amin(15:0)
0
BIT0
0
: This is the minimum gaina or gainb can be adjusted down. The value programmed is a positive
value that is inverted internally to generate the most negative AGC gain adjust. For example, if
512 is programmed, the minimum gain will be the programmed gain (AGC_GAINA/B) – 512.
Register name: PSER_CONFIG1
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x18
BIT15
unused
0
BIT8
0
0
BIT7
unused
0
unused
0
unused
0
0
pser_recv_fsinvl(6:0)
0
0
0
0
BIT0
pser_recv_fsinvl(6:0)
pser_recv_bits(4:0)
0
0
pser_recv_bits(4:0)
0
0
0
: Receive serial interface frame sync interval in bit clocks.
: Number of output bits per sample-1; for 18 bits, this is set to {10001}.
Register name: PSER_CONFIG2
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x19
BIT15
0
BIT7
pser_recv
_8pin
0
pser_recv_clkdiv(3:0)
0
0
pser_recv
_alt
0
pser_recv_clkdiv(3:0)
pser_recv_8pin
pser_recv_alt
pser_recv_fsdel(1:0)
0
unused
0
unused
0
unused
unused
unused
unused
0
0
0
0
BIT8
unused
0
BIT0
pser_recv_fsdel(1:0)
unused
0
0
0
: Receive serial interface clock divider rate-1; 0 is full rate and 15 divides the clock by 16. For
example, to run the receive serial interface at 1/4 the AFE8406 clock, set pser_recv_clkdiv(3:0) =
0011.
: When set, 4 pins are used for I and 4 pins for Q in UMTS mode. When cleared, 2 pins are used
for I and 2 pins for Q. This is used in combination with the pser_recv_alt bit. When this bit is set,
it would be set in 2 adjacent DDC channels; one would also set the pser_recv_alt bit in the
adjacent DDC. This will cause the I channel to be serialized on 4 pins and the Q channel to be
serialized on the adjacent channels 4 pins.
: When set, this channel's receive serial interface will output the Q data from the adjacent DDC
channel.
: Delay between the receive frame sync output and the MSB of serial data {3,2,1,0}. This number is
in serial output bit times, not rxclk periods.
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Register name: DDCCONFIG1
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x1A
BIT15
ddcmux_sel_a (3:0)
0
0
0
0
agc_rnd_
disable
0
gain_mon
remix_only
cic_
bypass
0
0
BIT7
ddcmux_sel_b(3:0)
0
0
ddcmux_sel_X(3:0)
0
0
0
BIT8
ch_rate_sel(1:0)
0
0
BIT0
double_tap(1:0)
0
0
: Controls which samples go to the mixer for I/Q. Since in CDMA mode there are two streams, an A
and B stream, two mux select values are used.
Select Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
I data from X input
RXINA
RXINB
RXINC
RXIND
RXINA
RXINA
RXIN A
RXINB
RXINB
RXINB
RXINC
RXINC
RXINC
RXIND
RXIND
RXIND
Q data from X input
RXINA
RXINB
RXINC
RXIND
RXINB
RXINC
RXIND
RXINA
RXINC
RXIND
RXINA
RXINB
RXIND
RXINA
RXINB
RXINC
RXINA = internal A-side ADC, RXINB = internal B-side ADC, RXINC = external input C, RXIND = external input D
agc_rnd_disable
gain_mon
OUTPUT
I
Q
ch_rate_sel(1:0)
: When set, the agc_rnd bits have no effect. The whole 29 bits are used in the rounding and the
round bit is bit4.
: Combines the gain with the I/Q output signals when asserted.
Bits(17:10)
Gained I value
Gained Q value
Bits(9:4)
Bits(3:2)
Gain(18:11)
Gain(10:5)
Shift status(1:0)
Bits(1:0)
“00”
“00”
: Sets the DDC channel input data rate. The value set here should match the value in the Receive
Input Interface rate select bits (rate_sel). MUST BE SET THE SAME AS REGISTER
rate_sel(1:0).
ch_rate_sel
00
01
10
11
Input data rate
rxclk
rxclk/2
rxclk/4
rxclk/8
When muxed_data is set (Factory Use Only) rate_sel should be set to rxclk “00” and ch_rate_sel
should be set to rxclk/2 “01”.
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: Assert this when real only, full rxclk rate input data is used in CDMA mode. The signal on the Q
bus selected by the ddcmux_sel_X(3:0) bits above is ignored (functions as if the Q data is 0).
: Factory Use Only. If asserted then the data from the rxin_a(15:0) and rxin_b(15:0) are fed directly
into the cfir input as I and Q respectively. rxin_a(0) also functions as the “sync_cfir” signal and
should rise at the beginning of input data.
cic_bypass
ONLY DDC0, DDC2 and DDC4 can be the UMTS double tap (64 to 128 tap) PFIR Mode. DDC1, DDC3 and DDC5
PFIRs are used to lengthen the DDC0, DDC2 and DDC4 PFIRs.
double_tap(1)
: When set, the DDC is in double length PFIR mode which sends the data out of the last PFIR
sample ram in this DDC (DDC0, DDC2, DDC4) to the adjacent secondary DDC (DDC1, DDC3,
DDC5) PFIR forming a 128-tap delay line. Output data received from the adjacent secondary
DDC PFIR summer is added into the Main DDC’s PFIR sum to form the final output.
double_tap(0)
: When set, the PFIR input comes from the adjacent(Main) PFIR. When cleared, PFIR input is
from the CFIR connected directly to this PFIR. Only valid in DDC1, DDC3 and DDC5. The
ddc_ena bit in the CONFIG1 register should be cleared for the DDC1, DDC3 and DDC5
when double_tap(0) is set.
Note: to put 2 DDCs in to 128 tap mode:
Program DDC0/DDC2/DDC4 double_tap(1:0) to “10” and ddc_ena to “1”.
Program DDC1/DDC3/DDC5 double_tap(1:0) to “01” and ddc_ena to “0”.
Register name: SYNC_0
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x1B
BIT15
unused
0
BIT7
unused
0
BIT8
0
ssel_cic(2:0)
0
1
ssel_agc_freeze(2:0)
1
ssel_cic(2:0)
ssel_pmeter(2:0)
ssel_agc_freeze(2:0)
ssel_serial(2:0)
0
unused
0
0
ssel_pmeter(2:0)
0
0
unused
0
0
ssel_serial(2:0)
0
0
BIT0
0
: Selects the sync source for the DDC CIC filter, thus setting the decimation moment.
: Selects the sync source for the channel power meter.
: Selects the sync that is used to hold the AGC in freeze mode. With this functionality the user can
program the AGC freeze control to look at the state of an input sync, or the one shots. It defaults
to being off or not looking at any syncs and not driving the freeze control. This way, upon startup,
the chip looks at the MPU register bit for AGC freezing and not the syncs.
: Selects the sync source for the DDC serial interface state machines.
Sync sources are contained in this and many of the following registers. For all sync source selections:
ssel_XXXX(2:0)
000
001
010
011
100
101
110
111
Selected sync source for DDC
rxsyncA
rxsyncB
rxsyncC
rxsyncD
DDC sync counter
one shot (register write triggered)
always 0
always 1
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Register name: SYNC_1
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x1C
BIT15
unused
0
BIT7
unused
0
BIT8
0
ssel_tadj_fine(2:0)
0
0
ssel_gain(2:0)
0
ssel_tadj_fine(2:0)
ssel_tadj_reg(2:0)
ssel_gain(2:0)
ssel_ddc_agc(2:0)
:
:
:
:
0
unused
0
0
ssel_tadj_reg(2:0)
0
0
unused
0
0
ssel_ddc_agc(2:0)
0
0
BIT0
0
Selects the sync source for the fine time adjust zero stuff moment.
Selects the sync source for the fine and coarse time adjust register updates.
Selects the sync source for the DDC AGC gain register.
Selects the sync source to initialize the AGC, primarily for test purposes.
Register name: SYNC_2
Page: 0x0%00, where % = 2*(DDC channel #)+1
Address: 0x1D
BIT15
unused
0
BIT7
unused
0
BIT8
0
ssel_nco(2:0)
0
0
ssel_freq(2:0)
0
ssel_nco
ssel_dither
ssel_freq
ssel_phase
:
:
:
:
0
unused
0
0
ssel_dither(2:0)
0
0
unused
0
0
ssel_phase (2:0)
0
0
BIT0
0
Selects the sync source for the NCO accumulator reset.
Selects the sync source for the NCO phase dither generator reset.
Selects the sync source for the NCO frequency register.
Selects the sync source for the NCO phase offset register.
Register name: DDC_CHK_SUM
Page: 0x0%20, where % = 2*(DDC channel #)+1
Address: 0x00
READ ONLY
BIT15
BIT8
0
0
0
ddc_chk_sum(15:0)
0
0
0
0
0
ddc_chk_sum(7:0)
0
0
0
0
0
0
BIT7
ddc_chk_sum
0
BIT0
0
: The DDC self test checksum value
Register name: PMETER_RESULT_A_LSB
Page: 0x0%20, where % = 2*(DDC channel #)+1
Address: 0x01
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READ ONLY
BIT15
0
BIT8
0
0
pmeter_result_a(15:8)
0
0
0
pmeter_result_a(7:0)
0
0
0
0
BIT7
0
BIT0
0
0
pmeter_result_a(15:0)
0
0
0
: Lower 16 bits of the UMTS mode or CDMA mode A channel power measurement.
Register name: PMETER_RESULT_A_MID
Page: 0x0%20, where % = 2*(DDC channel #)+1
Address: 0x02
READ ONLY
BIT15
0
BIT8
0
0
pmeter_result_a(31:24)
0
0
0
pmeter_result_a(23:16)
0
0
0
0
BIT7
0
BIT0
0
0
0
0
0
pmeter_result_a(31:16) : Mid 16 bits of the UMTS mode or CDMA mode A channel power measurement.
Register name: PMETER_RESULT_A_MSB
Page: 0x0%20, where % = 2*(DDC channel #)+1
Address: 0x03
READ ONLY
BIT15
0
BIT8
0
0
pmeter_result_a(47:40)
0
0
0
pmeter_result_a(39:32)
0
0
0
0
BIT7
0
BIT0
0
0
0
0
0
pmeter_result_a(47:32) : Upper mid 16 bits of the UMTS mode or CDMA mode A channel power measurement.
Register name: PMETER_RESULT_B_LSB
Page: 0x0%20, where % = 2*(DDC channel #)+1
Address: 0x04
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READ ONLY
BIT15
0
BIT8
0
0
pmeter_result_b(15:8)
0
0
0
pmeter_result_b(7:0)
0
0
0
0
BIT7
0
BIT0
0
0
pmeter_result_b(15:0)
0
0
0
: Lower 16 bits of the CDMA mode B channel power measurement.
Register name: PMETER_RESULT_B_MID
Page: 0x0%20, where % = 2*(DDC channel #)+1
Address: 0x05
READ ONLY
BIT15
0
BIT8
0
0
pmeter_result_b(31:24)
0
0
0
pmeter_result_b(23:16)
0
0
0
0
BIT7
0
BIT0
0
0
0
0
0
pmeter_result_b(31:16) : Mid 16 bits of the CDMA mode B channel power measurement.
Register name: PMETER_RESULT_B_MSB
Page: 0x0%20, where % = 2*(DDC channel #)+1
Address: 0x06
READ ONLY
BIT15
0
BIT8
0
0
pmeter_result_b(47:40)
0
0
0
pmeter_result_b(39:32)
0
0
0
0
BIT7
0
BIT0
0
0
0
0
0
pmeter_result_b(47:32) : Upper mid 16 bits of the CDMA mode B channel power measurement.
Register name: PMETER_RESULT_AB_UMSB
Page: 0x0%20, where % = 2*(DDC channel #)+1
Address: 0x07
READ ONLY
BIT15
0
0
pmeter_result_a(54:48)
0
0
0
0
pmeter_result_b(54:48)
0
0
0
0
0
BIT8
unused
0
0
BIT0
unused
0
BIT7
0
0
pmeter_result_a(54:48) : Most Significant 7 bits of the 55-bit UMTS or CDMA mode A channel power measurement.
pmeter_result_b(54:48) : Most Significant 7 bits of the 55-bit CDMA mode B channel power measurement.
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4
SLWS168 - OCTOBER 2005
AFE8406 Pins
4.1
Analog Section Signals
Signal Name
inpa
inma
inpb
inmb
Ball
F3
F4
V4
V3
Type
input
input
input
input
Description
ADCA analog positive input
ADCA analog negative input
ADCB analog positive input
ADCB analog negative input
clkpa
clkma
clkpb
clkmb
H1
J1
R1
T1
input
input
input
input
ADCA clock positive input
ADCA clock negative input
ADCB clock positive input
ADCB clock negative input
refpa
refma
refpb
refmb
L3
K3
P3
N3
input
input
input
input
ADCA positive reference input. connect 0.1uF to AVSS.
ADCA negative reference input; connect 0.1uF to AVSS.
ADCB positive reference input; connect 0.1uF to AVSS.
ADCB negative reference input; connect 0.1uF to AVSS.
cma
cmb
H3
T3
output
output
iref
M3
input
Current set; connect 56KΩ to AVSS.
oea
L9
input
oeb
N9
input
ovra
ovrb
da(13:0)
db(13:0)
clkouta
clkoutb
fuse_sel
G6
N8
N/A
N/A
N/A
N/A
H5
output
output
output
output
output
output
input
connect to AVDD
ADCA output enable; AVDD=enable, AVSS=disabled
connect to AVDD
ADCB output enable; AVDD=enable, AVSS=disabled
ADCA over range indicator bit
ADCB over range indicator bit
ADCA output data; internally connected to rxin_a_15:2
ADCB output data; internally connected to rxin_b_15:2
ADCA output clock; internally connected to adcclka
ADCB output clock; internally connected to adcclkb
connect to AVSS; fuse trim enable - factory use only
pin_configure
T5
input
ADCA common mode output reference
ADCB common mode output reference
connect to AVDD
Set mode of the following 3 pins
when pin_configure = AVSS (factory use only, customers should always tie to AVDD)
sdata
N10
input
serial interface data - factory use only
sclk
M9
input
serial interface clock - factory use only
sen
M10
input
serial interface enable - factory use only
when pin_configure = AVDD (normal operating mode)
dll_disable
N10
input
connect to AVDD
AVDD=disables DLL, AVSS=enables DLL
pwdn
M9
Input
connect to AVSS
AVDD=powered down, AVSS=powered up
ext_ref
M10
input
connect to AVSS
AVDD=External reference, AVSS=internal reference.
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SLWS168 - OCTOBER 2005
Digital Receive Section Signals
Signal Name
rxclk
Ball
R22
Type
input
Description
receive digital section clock input
adcclk_a
adcclk_b
adcclk_c
adcclk_d
N/A
N/A
AA11
AB11
input
input
input
input
rxin_a_x input clock; connected to ADCA output clock
rxin_b_x input clock; connected to ADCB output clock
rxin_c_x input clock
rxin_d_x input clock
rxin_a_ovr
rxin_b_ovr
rxin_c_ovr
rxin_d_ovr
G6
N8
AB6
V12
input/output
input/output
input
input
adc overflow/overrange bit for rxin_a; driven by ADC A
adc overflow/overrange bit for rxin_b; driven by ADC B
adc overflow/overrange bit for rxin_c
adc overflow/overrange bit for rxin_d
dvga_a_5
dvga_a_4
dvga_a_3
dvga_a_2
dvga_a_1
dvga_a_0
D7
D8
C7
B7
A7
C8
output
output
output
output
output
output
Digital VGA control output for ADC0 MSB
Digital VGA control output for ADC0
Digital VGA control output for ADC0
Digital VGA control output for ADC0
Digital VGA control output for ADC0
Digital VGA control output for ADC0 LSB
dvga_b_5
dvga_b_4
dvga_b_3
dvga_b_2
dvga_b_1
dvga_b_0
B8
A8
D9
D10
C9
B9
output
output
output
output
output
output
Digital VGA control output for ADC1 MSB
Digital VGA control output for ADC1
Digital VGA control output for ADC1
Digital VGA control output for ADC1
Digital VGA control output for ADC1
Digital VGA control output for ADC1 LSB
dvga_c_5
dvga_c_4
dvga_c_3
dvga_c_2
dvga_c_1
dvga_c_0
AA15
AB15
V16
W16
Y16
AA16
output
output
output
output
output
output
Digital VGA control output for rxin_c MSB, test bus bit 1
Digital VGA control output for rxin_c, test bus bit 0
Digital VGA control output for rxin_c, test bus bit 19
Digital VGA control output for rxin_c, test bus bit 18
Digital VGA control output for rxin_c, test bus CLK
Digital VGA control output for rxin_c LSB, test bus SYNC
dvga_d_5
dvga_d_4
dvga_d_3
dvga_d_2
dvga_d_1
dvga_d_0
AB16
V17
W17
AA17
AB17
V18
output
output
output
output
output
output
Digital VGA control output for rxin_d MSB, test bus AFLAG
Digital VGA control output for rxin_d
Digital VGA control output for rxin_d
Digital VGA control output for rxin_d
Digital VGA control output for rxin_d
Digital VGA control output for rxin_d LSB
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rxin_a_15
N/A
input
rxin_a_14
rxin_a_13
rxin_a_12
rxin_a_11
rxin_a_10
rxin_a_9
rxin_a_8
rxin_a_7
rxin_a_6
rxin_a_5
rxin_a_4
rxin_a_3
rxin_a_2
rxin_a_1
rxin_a_0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
rxin_b_15
N/A
input
rxin_b_14
rxin_b_13
rxin_b_12
rxin_b_11
rxin_b_10
rxin_b_9
rxin_b_8
rxin_b_7
rxin_b_6
rxin_b_5
rxin_b_4
rxin_b_3
rxin_b_2
rxin_b_1
rxin_b_0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
SLWS168 - OCTOBER 2005
receive input data bus a bit 15 (MSB);
connected to ADC A d(13)
receive input data bus a
receive input data bus a
receive input data bus a
receive input data bus a
receive input data bus a
receive input data bus a
receive input data bus a
receive input data bus a
receive input data bus a
receive input data bus a
receive input data bus a
receive input data bus a
receive input data bus a; connected to ADC A d(0)
receive input data bus a
receive input data bus a bit 0 (LSB)
receive input data bus b bit 15 (MSB);
connected to ADC B d(13)
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b
receive input data bus b; connected to ADC B d(0)
receive input data bus b
receive input data bus b bit 0 (LSB)
rxin_c_15
Y7
input/output
receive input data bus c bit 15 (MSB), test bus bit 17
rxin_c_14
AA7
input/output
receive input data bus c bit 14, test bus bit 16
rxin_c_13
AB7
input/output
receive input data bus c bit 13, test bus bit 15
rxin_c_12
Y8
input/output
receive input data bus c bit 12, test bus bit 14
rxin_c_11
V10
input/output
receive input data bus c bit 11, test bus bit 13
rxin_c_10
AA8
input/output
receive input data bus c bit 10, test bus bit 12
rxin_c_9
AB8
input/output
receive input data bus c bit 9, test bus bit 11
rxin_c_8
W9
input/output
receive input data bus c bit 8, test bus bit 10
rxin_c_7
Y9
input/output
receive input data bus c bit 7, test bus bit 9
rxin_c_6
AA9
input/output
receive input data bus c bit 6, test bus bit 8
rxin_c_5
AB9
input/output
receive input data bus c bit 5, test bus bit 7
rxin_c_4
W10
input/output
receive input data bus c bit 4, test bus bit 6
rxin_c_3
Y10
input/output
receive input data bus c bit 3, test bus bit 5
rxin_c_2
AA10
input/output
receive input data bus c bit 2, test bus bit 4
rxin_c_1
AB10
input/output
receive input data bus c bit 1, test bus bit 3
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rxin_c_0
W11
input/output
receive input data bus c bit 0 (LSB), test bus bit 2
rxin_d_15
rxin_d_14
rxin_d_13
rxin_d_12
rxin_d_11
rxin_d_10
rxin_d_9
rxin_d_8
rxin_d_7
rxin_d_6
rxin_d_5
rxin_d_4
rxin_d_3
rxin_d_2
rxin_d_1
rxin_d_0
W12
Y12
AA12
AB12
V13
W13
Y13
AA13
AB13
V14
W14
AA14
AB14
V15
W15
Y15
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
receive input data bus d bit 15 (MSB), test bus bit 35
receive input data bus d bit 14, test bus bit 34
receive input data bus d bit 13, test bus bit 33
receive input data bus d bit 12, test bus bit 32
receive input data bus d bit 11, test bus bit 31
receive input data bus d bit 10, test bus bit 30
receive input data bus d bit 9, test bus bit 29
receive input data bus d bit 8, test bus bit 28
receive input data bus d bit 7, test bus bit 27
receive input data bus d bit 6, test bus bit 26
receive input data bus d bit 5, test bus bit 25
receive input data bus d bit 4, test bus bit 24
receive input data bus d bit 3, test bus bit 23
receive input data bus d bit 2, test bus bit 22
receive input data bus d bit 1, test bus bit 21
receive input data bus d bit 0 (LSB), test bus bit 20
rx_synca
rx_syncb
rx_syncc
rx_syncd
P21
P22
N20
N21
input
input
input
input
rx_sync_out
rxclk_out
E22
E21
output
output
receive general purpose output sync
receive clock output
rx_sync_out_7
A20
output
rx_sync_out_6
C19
output
rx_sync_out_5
rx_sync_out_4
rx_sync_out_3
rx_sync_out_2
rx_sync_out_1
rx_sync_out_0
C17
C16
D15
B13
C12
A10
output
output
output
output
output
output
receive serial interface frame strobe for rxout_7_x,
output clock (rxout_clk) for parallel interface.
receive serial interface frame strobe for rxout_6_x,
frame strobe (rx_sync_out) for parallel interface.
receive serial interface frame strobe for rxout_5_x
receive serial interface frame strobe for rxout_4_x
receive serial interface frame strobe for rxout_3_x
receive serial interface frame strobe for rxout_2_x
receive serial interface frame strobe for rxout_1_x
receive serial interface frame strobe for rxout_0_x
receive sync input
receive sync input
receive sync input
receive sync input
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rxout_7_a
D20
output
rxout_7_b
C21
output
rxout_7_c
B20
output
rxout_7_d
C20
output
rxout_6_a
A19
output
rxout_6_b
B19
output
rxout_6_c
A18
output
rxout_6_d
B18
output
rxout_5_a
D18
output
rxout_5_b
B17
output
rxout_5_c
D17
output
rxout_5_d
A17
output
rxout_4_a
A16
output
rxout_4_b
B16
output
rxout_4_c
D16
output
rxout_4_d
A15
output
rxout_3_a
B15
output
rxout_3_b
C15
output
rxout_3_c
A14
output
rxout_3_d
B14
output
rxout_2_a
D14
output
rxout_2_b
A13
output
rxout_2_c
C13
output
rxout_2_d
D13
output
DDC 7 serial out data.
DDC Parallel Interface
DDC 7 serial out data.
DDC Parallel Interface
DDC 7 serial out data.
DDC Parallel Interface
DDC 7 serial out data.
DDC Parallel Interface
SLWS168 - OCTOBER 2005
CDMA A:
I(12)
CDMA B:
I(13)
CDMA A:
I(14)
CDMA B:
I(15)
I data
UMTS: I msb
I data
UMTS: I msb – 1
DDC 6 serial out data. CDMA A:
DDC Parallel Interface I(8)
DDC 6 serial out data. CDMA B:
DDC Parallel Interface I(9)
DDC 6 serial out data. CDMA A:
DDC Parallel Interface I(10)
DDC 6 serial out data. CDMA B:
DDC Parallel Interface I(11)
I data
UMTS: I msb
I data
UMTS: I msb – 1
Q data UMTS: Qmsb
Q data UMTS: Qmsb –1
Q data UMTS: Qmsb
Q data UMTS: Qmsb –1
DDC 5 serial out data.
Parallel Interface I(4)
DDC 5 serial out data.
Parallel Interface I(5)
DDC 5 serial out data.
Parallel Interface I(6)
DDC 5 serial out data.
Parallel Interface I(7)
CDMA A: I data
UMTS: I msb
CDMA B: I data
UMTS: I msb – 1
DDC 4 serial out data.
Parallel Interface I(0)
DDC 4 serial out data.
Parallel Interface I(1)
DDC 4 serial out data.
Parallel Interface I(2)
DDC 4 serial out data.
Parallel Interface I(3)
CDMA A: I data
UMTS: I msb
CDMA B: I data
UMTS: I msb – 1
CDMA A: Q data UMTS: Qmsb
CDMA B: Q data UMTS: Qmsb –1
CDMA A: Q data UMTS: Qmsb
CDMA B: Q data UMTS: Qmsb –1
DDC 3 serial out data. CDMA A:
Parallel Interface Q(12)
DDC 3 serial out data. CDMA B:
Parallel Interface Q(13)
DDC 3 serial out data. CDMA A:
Parallel Interface Q(14)
DDC 3 serial out data. CDMA B:
Parallel Interface Q(15)
DDC 2 serial out data. CDMA A:
Parallel Interface Q(8)
DDC 2 serial out data. CDMA B:
Parallel Interface Q(9)
DDC 2 serial out data. CDMA A:
Parallel Interface Q(10)
DDC 2 serial out data. CDMA B:
Parallel Interface Q(11)
I data
UMTS: I msb
I data
UMTS: I msb – 1
Q data UMTS: Qmsb
Q data UMTS: Qmsb –1
I data
UMTS: I msb
I data
UMTS: I msb – 1
Q data UMTS: Qmsb
Q data UMTS: Qmsb –1
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rxout_1_a
A12
output
rxout_1_b
B12
output
rxout_1_c
D12
output
rxout_1_d
A11
output
rxout_0_a
B11
output
rxout_0_b
C11
output
rxout_0_c
B10
output
rxout_0_d
A9
output
SLWS168 - OCTOBER 2005
DDC 1 serial out data.
Parallel Interface Q(4)
DDC 1 serial out data.
Parallel Interface Q(5)
DDC 1 serial out data.
Parallel Interface Q(6)
DDC 1 serial out data.
Parallel Interface Q(7)
CDMA A: I data
UMTS: I msb
CDMA B: I data
UMTS: I msb – 1
DDC 0 serial out data.
Parallel Interface Q(0)
DDC 0 serial out data.
Parallel Interface Q(1)
DDC 0 serial out data.
Parallel Interface Q(2)
DDC 0 serial out data.
Parallel Interface Q(3)
CDMA A: I data
UMTS: I msb
CDMA B: I data
UMTS: I msb – 1
CDMA A: Q data UMTS: Qmsb
CDMA B: Q data UMTS: Qmsb –1
CDMA A: Q data UMTS: Qmsb
CDMA B: Q data UMTS: Qmsb –1
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4.3
SLWS168 - OCTOBER 2005
Microprocessor Signals
Signal Name
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
Ball
Y22
Y21
AB20
AA20
Y20
W20
V20
AB19
AA19
Y19
W19
V19
AB18
AA18
Y18
W18
Type
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
Description
MPU register interface data bus bit 0 (LSB)
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus
MPU register interface data bus bit 15 (MSB)
a0
a1
a2
a3
a4
a5
T20
U22
U21
W22
V21
W21
input
input
input
input
input
input
MPU register interface address bus bit 0 (LSB)
MPU register interface address bus
MPU register interface address bus
MPU register interface address bus
MPU register interface address bus
MPU register interface address bus bit 5 (MSB)
rd_n
wr_n
ce_n
T22
R20
T21
input
input
input
MPU register interface read – active low
MPU register interface write – active low
MPU register interface chip enable – active low
reset_n
interrupt
R21
M21
input
output
chip reset – active low
chip interrupt
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specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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4.4
JTAG Signals
Signal Name
tdi
tms
trst_n
Ball
K22
K21
J22
Type
input
input
input
tck
tdo
L20
L21
input
output
4.5
SLWS168 - OCTOBER 2005
Description
JTAG test data in
JTAG test mode select
JTAG test reset (same as trst; the “_n” is for
consistency - being active low)
Note: the trst_n pin should be asserted low after
power up to insure the JTAG logic is properly
initialized.
JTAG test clock
JTAG test data out
Factory Test and No Connect Signals
Signal Name
testmode0
testmode1
scanen
fa002_scan
fa002_clk
fa002_out
zero
fuse_out
fuse_ena
fuse_bias
Ball
G21
G22
H21
J20
H22
J21
H20
F20
D21
F21
Type
input
input
input
input
input
output
input
output
input
input
Note
Do not connect; internal pull down
Do not connect; internal pull down
Do not connect; internal pull down
Do not connect; internal pull down
Do not connect; internal pull down
Do not connect
Do not connect; internal pull down
Do not connect
Do not connect; internal pull down
Do not connect; internal pull down
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4.6
Power and Ground Signals
Signal Name
AVDD
DRVDD
FUSE_AVDD
AVSS
DRVSS
VDDS
VDDS_VFUSE
DVDD
DVSS
4.7
SLWS168 - OCTOBER 2005
Ball
H4, J3, L1, L2, M2, N1, N2, R3, T4
H6, H7, J8, K8, L8, P8, R8, T6, T7
M1
A1, A2, A3, A4, A5, B1, B2, B3, B4, B5,
C1, C2, C3, C4, C5, D1, D2, D3, D4, D5,
E1, E2, E3, E4, E5, F1, F2, F5, F6, F7, F8, F9,
G1, G2, G3, G4, G5, G7, G8, G9, H2,
J2, J4, J5, J6, K1, K2, K4, K5, K6,
L4, L5, L6, L7, M4, M5, M6, M7,
N4, N5, N6, N7, P1, P2, P4, P5, P6,
R2, R4, R5, R6, T2,
U1, U2, U3, U4, U5, U6, U7, U8, U9,
V1, V2, V5, V6, V7, V8
W1, W2, W3, W4, W5, Y1, Y2, Y3, Y4,
AA1, AA2, AA3, AA4, AB1, AB2, AB3, AB4
H8, H9, J7, J9, K7, K9,
M8, P7, P9, R7, R9, T8, T9
B6, B21, D6, D11, D19,
E10, E11, E12, E13, E14, E15, E16, E17, E18, E19,
K20, M20, P20,
U11, U12, U13, U14, U15, U16, U17, U18, U19,
V11, W7, AA6, AA21
D22
F22, G10, G19, H10, H19, J10, J19, K10, K19, L10, L19,
M19, N19, P10, P19, R10, R19, V22
A6, A21, A22,
B22,
C6, C10, C14, C18, C22,
E6, E7, E8, E9, E20,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, G11,
G12, G13, G14, G15, G16, G17, G18, G20,
H11, H12, H13, H14, H15, H16, H17, H18,
J11, J12, J13, J14, J15, J16, J17, J18,
K11, K12, K13, K14, K15, K16, K17, K18,
L11, L12, L13, L14, L15, L16, L17, L18,
M11, M12, M13, M14, M15, M16, M17, M18,
N11, N12, N13, N14, N15, N16, N17, N18, N22,
P11, P12, P13, P14, P15, P16, P17, P18,
R11, R12, R13, R14, R15, R16, R17, R18,
T10, T11, T12, T13, T14, T15, T16, T17, T18, T19,
U10, U20, V9, W6, W8,
Y5, Y6, Y11, Y14, Y17,
AA5, AA22, AB5, AB21, AB22
Description
Analog Power (3.3V)
Analog I/O Power (3.3V)
Analog Power (3.3V)
Analog Ground
Analog I/O Ground
Digital I/O Power (3.3V) Also
called Vpad
Digital I/O Power (3.3V)
Digital Core Power (1.5V)
Also called Vcore
Digital Ground
Digital Supply Monitoring
Signal Name
dvddmon
Ball
L22
dvssmon
M22
Description
It is recommended that this pin be brought to a probe point for monitoring and
debugging purposes.
It is recommended that this pin be brought to a probe point for monitoring and
debugging purposes.
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4.8
SLWS168 - OCTOBER 2005
JTAG
The JTAG standard for boundary scan testing will be implemented for board testing purposes. Internal scan test
will not be supported. Five device pins are dedicated for JTAG support: tdi, tdo, tms, tck, and trst_n. The JTAG
bsdl configuration file will be available from TI at a later time.
Note: the trst_n pin should be asserted LOW after power up to insure the JTAG logic is properly initialized.
5
Specifications
NOTE: These numbers are engineering estimates prior to first silicon. They will change after we have
characterized the parts.
5.1
Absolute Maximum Ratings
Table 1.
Absolute Maximum Ratings
PARAMETER
Analog Chip, Analog Supply Voltage
Analog Chip, I/O Ring Supply Voltage
Analog Chip, Ground Difference DRVSS to AVSS
Digital Chip, Pad Ring Supply Voltage
Digital Chip, Core Supply Voltage
Analog Chip, Analog Input Voltage
Analog Chip, Digital Input Voltage
Digital Chip, Digital Input Voltage
Clamp current for an input or output
Storage Temperature
SYMBOL
AVDD
DRVDD
Junction Temperature
TJ
Theta Junction to Ambient (0 LFPM)
ΘJA
VDDS
DVDD
TSTG
MIN
-0.3
-0.3
-0.1
-0.3
-0.3
-0.15
-0.3
-0.3
-20
-65
MAX
3.7
3.7
0.1
3.7
1.8
2.5
DRVDD+0.3
VDDS+0.3
+20
140
105
Theta Junction to Ambient (100 LFPM)
Theta Junction to Ambient (250 LFPM)
Theta Junction to Ambient (500 LFPM)
Theta Junction to Case
Lead Soldering Temperature (10 seconds)
300
UNITS
V
V
V
V
V
V
V
V
mA
NOTES
°C
°C
°C
°C
°C
°C
°C
°C
ESD Classification
Class 2
Moisture Sensitivity
Class 2
CAUTION: Exceeding the absolute maximum ratings (min or max) may cause permanent damage to the part. These are
stress only ratings and are not intended for operation.
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5.2
SLWS168 - OCTOBER 2005
Recommended Operating Conditions
Table 2.
Recommended Operating Conditions
PARAMETER
Analog Chip, Analog Supply Voltage
Analog Chip, I/O Ring Supply Voltage
Analog Chip, Differential Input Range
Analog Chip, Input Common Mode
Analog Chip, Differential Clock Inputs
Analog Chip, Clock Input Duty Cycle
Digital Chip, I/O Ring Supply Voltage
Digital Chip, Core Supply Voltage
Digital Chip, Supply Voltage Difference, VDDS – DVDD
Temperature Ambient, no air flow
SYMBOL
AVDD
DRVDD
MIN
3.0
3.0
VCM
1.5
Junction Temperature
TJ
NOM
3.3
3.3
2.3
MAX
3.6
3.6
1.6
3
50
VDDS
DVDD
TA
3
1.425
3.6
1.575
2.0
+85
-40
105
UNITS
V
V
V
V
Vpp
%
V
V
V
°C
°C
NOTES
1
2
1. Chips specifications in Tables 6.4 and 6.5 are production tested to100C case temperature. QA tests are performed at 85C.
2. Thermal management will be required for full rate operation, See table below and Section 5.4. The circuit is designed for junction
temperatures up to 125C. Sustained operation at elevated temperatures will reduce long -term reliability. Lifetime calculations based on
maximum junction temperature of 105C. Thermal management mechanisms such as air flow, heat sinks or lower ambient temperature may
need to be employed to maintain a maximum junction temperature of 105C.
5.3
Thermal Characteristics
THERMAL CONDUCTIVITY
SYMBOL
TYP
UNITS
Theta Junction to Ambient (0 LFPM)
θJA
14
° C/W
° C/W
° C/W
° C/W
° C/W
Theta Junction to Ambient (100 LFPM)
13
Theta Junction to Ambient (250 LFPM)
12.2
Theta Junction to Ambient (500 LFPM)
11.6
θJC
Theta Junction to Case
2.8
Note: Air flow will reduce θja and is highly recommended.
5.4
Power Consumption
The maximum power consumption is largely a function of the operating mode of the chip. The Dual ADC
chip power dissipation is fairly constant over clock rate due to the constant biasing in the analog circuits.
The following equation estimates the typical power supply current for the digital chip The AC
Characteristics table provides maximum current in a maximum configuration used in production test.
IDVDD = proportional to filter lengths, supply, frequency, and number of channels active; separate
equations for CDMA and UMTS modes to be included after characterization.
Current consumption on the pad supply is primarily due to the external loads and follows C*V*F. Internal
loads are estimated at 2pF per pin. Data outputs have a transition density of going from a zero to a one
once per four clocks, while clock outputs transition every cycle. The rx_sync_out_X frame strobes
consume negligible power due to the low transition frequency. In general,
IVDDS = Σ DataPad/4*C*F*V + Σ ClockPad*C*F*V
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Analog Electrical Characteristics
Typ, min, and max values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, sampling rate = 80MSPS, 50%
clock duty cycle, AVDD = DRVDD = 3.3V, DLL OFF, -1dBFS differential input, internal reference, and 3VPP differential clock, unless
otherwise noted.
PARAMETER
Resolution
Analog Inputs
Differential input range
Differential input impedance
Differential input capacitance
Total analog input common-mode current
Analog input bandwidth
Conversion Characteristics
CONDITIONS
MIN
ADC clock rate, fadc
(fclkpa=fclkma=fclkpb=fclkmb= fadc )
frxclk = 1xf adc
ch_rate_sel = rate_sel =
00
85
frxclk = 2xf adc
ch_rate_sel = rate_sel =
01
80
frxclk = 4xf adc
ch_rate_sel = rate_sel =
10
40
frxclk = 8xf adc
ch_rate_sel = rate_sel =
11
20
2mA per input, 4mA total
Source impedance = 50?
Data Latency – ADC input to FIFO input
Internal Reference Voltages
Lower Reference Voltages, REFMA & REFMB
Upper Reference Voltages, REFPA & REFPB
Reference Error
Common Mode Voltage Outputs, CMA & CMB
Dynamic DC Characteristics and Accuracy
No missing codes
Differential Linearity Error, DNL
Integral Linearity Error, INL
Offset Error
Offset Temperature Coefficient
Gain Error
Gain Temperature Coefficient
Dynamic AC Characteristics
Signal to Noise Ratio, SNR
RMS Output Noise
TYP
14 tested
MAX
UNITS
Bits
2.3
Vpp
k?
4
750
mA
MHz
MSPS
16.5
Clock
Cycles
0.97
2.11
V
V
%
V
1.55 +/0.05
tested
Fin = 10MHz
Fin = 10MHz
Fin = 10MHz, 25 oC
Fin = 10MHz, -40 to 85 oC
Fin = 30MHz
Fin = 55MHz
Fin = 70MHz, 25 oC
Fin = 70MHz, -40 to 85 oC
Fin = 110MHz
Fin = 150MHz
Fin = 225MHz
INPA & INMA tied to C MA
INPB & INMB tied to CMB
LSBs
LSBs
mV
%/oC
%FS
∆%/oC
TBD
TBD
TBD
73.5
TBD
TBD
TBD
TBD
TBD
1.1
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
LSBs
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Spurious free dynamic range, SFDR
Fin = 10MHz, 25 oC
Fin = 10MHz, -40 to 85 oC
Fin = 30MHz
Fin = 55MHz
Fin = 70MHz, 25 oC
Fin = 70MHz, -40 to 85 oC
Fin = 110MHz
Fin = 150MHz
Fin = 225MHz
SLWS168 - OCTOBER 2005
TBD
TBD
TBD
84
TBD
TBD
TBD
TBD
TBD
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
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Analog Electrical Characteristics (Continued)
Typ, min, and max values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, sampling rate = 65MSPS, 50%
clock duty cycle, AVDD = DRVDD = 3.3V, DLL OFF, -1dBFS differential input, internal reference, and 3VPP differential clock, unless
otherwise noted.
PARAMETER
Second Harmonic, HD2
Third Harmonic, HD3
Worst harmonic/spur other than HD2 or HD3
Signal to Noise plus Distortion
Total Harmonic Distortion, THD
Channel to channel crosstalk
CONDITIONS
Fin = 10MHz, 25 oC
Fin = 10MHz, -40 to 85 oC
Fin = 30MHz
Fin = 55MHz
Fin = 70MHz, 25 oC
Fin = 70MHz, -40 to 85 oC
Fin = 110MHz
Fin = 150MHz
Fin = 225MHz
Fin = 10MHz, 25 oC
Fin = 10MHz, -40 to 85 oC
Fin = 30MHz
Fin = 55MHz
Fin = 70MHz, 25 oC
Fin = 70MHz, -40 to 85 oC
Fin = 110MHz
Fin = 150MHz
Fin = 225MHz
Fin = 10MHz, 25 oC
Fin = 70MHz, 25 oC
Fin = 10MHz, 25 oC
Fin = 10MHz, -40 to 85 oC
Fin = 30MHz
Fin = 55MHz
Fin = 70MHz, 25 oC
Fin = 70MHz, -40 to 85 oC
Fin = 110MHz
Fin = 150MHz
Fin = 225MHz
Fin = 10MHz, 25 oC
Fin = 10MHz, -40 to 85 oC
Fin = 30MHz
Fin = 55MHz
Fin = 70MHz, 25 oC
Fin = 70MHz, -40 to 85 oC
Fin = 110MHz
Fin = 150MHz
Fin = 225MHz
Fin = 225MHz
MIN
TBD
TBD
TYP
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
90
MAX
UNITS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
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Digital Chip DC Characteristics
Table 3.
PARAMETER
DC Operating Conditions (-40 to 85°C case unless noted)
SYMBOL
VDDS=3 to 3.6V
MIN
MAX
0.8
2.0
0.5
2.4
VDDS
5
35
UNITS
NOTES
Voltage input low
VIL
V
1
Voltage input high
VIH
V
1
Voltage output low (IOL = 2mA)
VOL
V
1
Voltage output high (IOH = -2mA)
VOH
V
1
Pullup current (VIN = 0V) (tdi, tms, trst_n, ce_n, wr_n,
| IPU |
uA
1
rd_n, reset_n ) (nominal 20uA)
Pulldown current (VIN = VDDS) (all other inputs and
| IPD |
5
35
uA
1
bidirs) (nominal 20uA)
Leakage current (VIN = 0V or VDDS)
| IIN |
20
uA
1
Outputs in tristate condition
Quiescent supply current, IDVDD or IVDDS
ICCQ
8
mA
1
(Vin = 0 for pads with pulldowns, Vin=VDDS for inputs
with pullups)
Capacitance for inputs
CIN
Typical 5
pF
2
Capacitance for bidirectionals
CBI
Typical 5
pF
2
Notes:
General: Voltages are measured at low speed. Output voltages are measured with the indicated current load.
General: Currents are measured at nominal voltages, high tem perature (TBDoC for production test, 85oC for QA).
1. Each part is tested at TBDoC case temperature for the given specification. Lots are sample tested at -40oC.
2. Controlled by design and process and not directly tested.
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Digital Chip AC Timing Characteristics
Table 4. AC Characteristics
(-40 TO +85 C Case, Supplies across recommended range unless noted)
o
PARAMETER
Clock Frequency (adcclk_c/d, rxclk)
Clock low period (Below VIL) (adcclk_c/d, rxclk)
Clock high period (Above VIH) (adcclk_c/d, rxclk)
Clock rise and fall times (VIL to VIH) (adcclk_c/d, rxclk)
SYMBOL
FCK
tCKL
tCKH
tRF
MIN
Input setup (rxsync_a/b/c/d) before rxclk rises
Input setup (rxin_c/d_[0-15] ) before rxclk rises
(adc fifo blocks bypassed)
Input setup (rxin_c/d_[0-15] ) before adcclk_c/d rises
(adc fifo blocks enabled)
Input hold (rxsync_a/b/c/d) after rxclk rises
Input hold (rxin_c/d_[0-15] ) after rxclk rises
(adc fifo blocks bypassed)
Input hold (rxin_c/d_[0-15] ) after adcclk_c/d rises
(adc fifo blocks enabled)
tSU
tSU
Data output delay (rx_sync_out_[0-7], rxout_[0-7]_a/b/c/d,
rxclk_out, rx_sync_out, dvga_[a-d]_[5-0]) after rxclk rises.
Data output hold (rx_sync_out_[0-7], rxout_[0-7]_a/b/c/d,
rxclk_out, rx_sync_out, dvga_[a-d]_[5-0]) after rxclk rises.
tDLY
tOHD
0.5
JTAG Clock Frequency (tck)
JTAG Clock low period (Below VIL) (tck)
JTAG Clock high period (Above VIH) (tck)
JTAG Input (tdi or tms) setup before tck goes high
JTAG Input (tdi or tms) hold time after tck goes high
JTAG output (tdo) delay from falling edge of tck.
FJCK
tJCKL
tJCKH
tJSU
tJHD
tJDLY
10
10
1
10
MAX
160
UNITS
MHz
ns
ns
ns
NOTES
1
1
1
3
2
2
ns
ns
1
1
tSU
2
ns
1
tHD
tHD
1
2
ns
ns
1
1
tHD
1
ns
1
ns
1
ns
1
MHz
ns
ns
ns
ns
ns
1
1
1
1
1
1
2
2
2
6.5
40
10
Control setup during reads or writes
tCSU
6
ns
1
3 pin mode: a[5:0] valid before rd_n, wr_n or ce_n falling edge
2 pin mode: a[5:0] and wr_n valid before ce_n falling edge
Control setup during writes
tEWCSU
10
ns
1
3 pin mode: d[15:0] valid before wr_n and ce_n rising edge
2 pin mode: d[15:0] valid before ce_n rising edge
Control hold during writes.
tCHD
6
ns
1
3 pin mode: a[5:0] and d[15:0] valid after wr_n and ce_n rise
2 pin mode: a[5:0], d[15:0] and wr_n valid after ce_n rise
Control strobe (ce_n and wr_n low) pulse width during write.
tCSPW
15
ns
1
Control output delay ce_n and rd_n low and a[5:0] stable to
tCDLY
25
ns
1
d[15:0] during read.
Control recovery time between reads or writes.
tREC
6
ns
1
Control end of read to Hi-Z.
tHIZ
10
ns
1
rd_n and ce_n rise to d[15:0] tristate
Control read d[15:0] output hold time
tCOH
3
ns
1
Core dynamic supply current ,nominal voltages, 160 MHz,
ICDYN
TBD
TBD
mA
1
(specific conditions, typical app with chip busy within capability
of the tester, high temperature.)
Notes:
General: Timing is measured from the respective clock at VDDS/2 to input or output at VDDS/2. Output loading is a 50
Ohm transmission line whose delay is calibrated out.
1. Each part is tested at TBDoC case temperature for the given specification. Lots are sample tested at -40oC.
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2. Controlled by design and process and not directly tested. Verified on initial part evaluation.
3. Recommended practice.
4. reset_n and interrupt have no timing specifications since they are asynchronous signals
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Package/Ordering Information
PRODUCT
AFE8406
PACKAGE-LEAD
Plastic BGA – 484
PACKAGE
DESIGNATOR
GDQ
SPECIFIED
TEMPERATURE
RANGE
-40°C to +85°C
PACKAGE
MARKING
TBD
ORDERING
NUMBER
TBD
TRANSPORT
MEDIA,
QUANTITY
Tray, TBD
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