Agere LUCL9215GAU-D Short-loop sine wave ringing slic Datasheet

Data Sheet
September 2001
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Introduction
Applications
The Agere Systems Inc. L9215 is a subscriber line
interface circuit that is optimized for short-loop,
power-sensitive applications. This device provides
the complete set of line interface functionality (including power ringing) needed to interface to a subscriber
loop. This device has the capability to operate with a
VCC supply of 3.3 V or 5 V and is designed to minimize external components required at all device
interfaces.
■
Voice over Internet Protocol (VoIP)
■
Cable Modems
■
Terminal Adapters (TA)
■
Wireless Local Loop (WLL)
■
Telcordia Technologies™ GR-909 Access
■
Network Termination (NT)
■
Key Systems
Features
■
Onboard ringing generation
■
Three ringing input options:
— Sine wave
— PWM
— Logic level square wave
■
Flexible VCC options:
— 5 V or 3.3 V VCC
— No –5 V required
■
Battery switch to minimize off-hook power
■
11 operating states:
— Scan mode for minimal power dissipation
— Forward and reverse battery active
— On-hook transmission states
— Meter pulse states
— Ring mode
— Disconnect mode
■
Ultralow on-hook power:
— 27 mW scan mode
— 42 mW active mode
■
Two SLIC gain options to minimal external components in codec interface
■
Loop start, ring trip, and ground key detectors
■
Software- or hardware-controllable current-limit
and overhead voltage
■
Meter pulse compatible
■
32-pin PLCC package
■
48-pin MLCC package
Description
This device is optimized to provide battery feed, ringing, and supervision on short-loop plain old telephone service (POTS) loops.
This device provides power ring to the subscriber
loop through amplification of a low-voltage input. It
provides forward and reverse battery feed states, onhook transmission, a low-power scan state, meter
pulse states, and a forward disconnect state.
The device requires a VCC and battery to operate.
VCC may be either a 5 V or a 3.3 V supply. The ringing signal is derived from the high-voltage battery. A
battery switch is included to allow for use of a lowervoltage battery in the off-hook mode, thus minimizing
short-loop off-hook power.
Loop closure, ring trip, and ground key detectors are
available. The loop closure detector has a fixed
threshold with hysteresis. The ring trip detector
requires a single-pole filter, thus minimizing external
components required.
This device supports meter pulse applications. Meter
pulse is injected into a dedicated meter pulse input.
Injection of meter pulse onto tip and ring is controlled
by the device’s logic input pin.
Both the dc current limit and overhead voltage are
programmable. Programming may be done by external resistors or an applied voltage source. If the voltage source is programmable, the current limit and
overhead may be set via software control.
The device is offered with two gain options. This
allows for an optimized codec interface, with minimal
external components regardless of whether a firstgeneration or a programmable third-generation
codec is used.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Table of Contents
Contents
Page
Introduction..................................................................1
Features ....................................................................1
Applications...............................................................1
Description ................................................................1
Features ......................................................................4
Description...................................................................4
Architecture Diagram...................................................7
Pin Information ............................................................8
Operating States........................................................11
State Definitions ........................................................12
Forward Active ........................................................12
Reverse Active........................................................12
Forward Active with PPM ........................................12
Reverse Active with PPM........................................12
Scan........................................................................12
On-Hook Transmission—Forward Battery ..............12
On-Hook Transmission with PPM—Forward
Battery ....................................................................13
On-Hook Transmission—Reverse Battery ..............13
On-Hook Transmission with PPM—Reverse
Battery ....................................................................13
Disconnect ..............................................................13
Ring.........................................................................13
Thermal Shutdown..................................................13
Absolute Maximum Ratings.......................................14
Electrical Characteristics ...........................................15
Test Configurations ...................................................22
Applications ...............................................................24
Power Control .........................................................24
dc Loop Current Limit..............................................24
Overhead Voltage ...................................................25
Active Mode .........................................................25
On-Hook Transmission Mode...............................26
Scan Mode ...........................................................26
Ring Mode............................................................26
2
Contents
Page
Loop Range ........................................................... 26
Battery Reversal Rate ............................................ 26
Supervision............................................................... 27
Loop Closure.......................................................... 27
Ring Trip ................................................................ 27
Tip or Ring Ground Detector .................................. 27
Power Ring ............................................................ 27
Sine Wave Input Signal and Sine Wave Power
Ring Signal Output............................................ 28
PWM Input Signal and Sine Wave Power
Ring Signal Output............................................ 30
5 V VCC Operation ............................................... 31
3.3 V VCC Operation ............................................ 32
Square Wave Input Signal and Trapezoidal
Power Ring Signal Output ................................ 32
Periodic Pulse Metering (PPM) ................................ 34
ac Applications ......................................................... 34
ac Parameters........................................................ 34
Codec Types .......................................................... 34
First-Generation Codecs ..................................... 34
Third-Generation Codecs .................................... 34
ac Interface Network .............................................. 34
Design Examples ................................................... 35
First-Generation Codec ac Interface
Network—Resistive Termination ...................... 35
Example 1, Real Termination .............................. 36
First-Generation Codec ac Interface
Network—Complex Termination ....................... 39
Complex Termination Impedance Design
Example............................................................ 39
ac Interface Using First-Generation Codec ......... 39
Set ZTG—Gain Shaping....................................... 39
Transmit Gain...................................................... 40
Receive Gain....................................................... 41
Hybrid Balance .................................................... 41
Blocking Capacitors............................................. 42
Third-Generation Codec ac Interface
Network—Complex Termination ....................... 45
Outline Diagrams...................................................... 47
32-Pin PLCC .......................................................... 47
48-Pin MLCC.......................................................... 48
48-Pin MLCC, JEDEC MO-220 VKKD-2................ 49
Ordering Information................................................. 50
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Table of Contents (continued)
Figures
Page
Figure 1. Architecture Diagram ...................................7
Figure 2. 32-Pin PLCC Diagram .................................8
Figure 3. 48-Pin MLCC Diagram .................................8
Figure 4. Basic Test Circuit ......................................22
Figure 5. Metallic PSRR ...........................................23
Figure 6. Longitudinal PSRR ....................................23
Figure 7. Longitudinal Balance .................................23
Figure 8. ac Gains ....................................................23
Figure 9. Ringing Waveform Crest Factor = 1.6 .......27
Figure 10. Ringing Waveform Crest Factor = 1.2 .....27
Figure 11. Ring Mode Typical Operation ...................28
Figure 12. RINGIN Operation ....................................29
Figure 13. L9215/16 Ringing Input Circuit Selection
Table for Square Wave and PWM
Inputs........................................................30
Figure 14. Modulation Waveforms ............................31
Figure 15. 5 V PWM Signal Amplitude ......................31
Figure 16. Ringing Output on RING, with
Vcc = 5 V..................................................31
Figure 17. 3.3 V PWM Signal Amplitude ...................32
Figure 18. Ringing Output on RING, with
Vcc = 3.1 V...............................................32
Figure 19. Square Wave Input Signal and Trapezoidal
Power Ring Signal Output ........................32
Figure 20. Crest Factor vs. Battery Voltage...............33
Figure 21. Crest Factor vs. R (kΩ) ............................33
Figure 22. ac Equivalent Circuit ................................36
Figure 23. Agere T7504 First-Generation Codec
Resistive Termination; Nonmeter Pulse
Application................................................37
Figure 24. Interface Circuit Using First-Generation
Codec (Blocking Capacitors
Not Shown) ..............................................40
Figure 25. ac Interface Using First-Generation
Codec (Including Blocking Capacitors)
for Complex Termination Impedance ......42
Figure 26. Agere T7504 First-Generation Codec
Complex Termination; Meter Pulse
Application................................................43
Figure 27. Third-Generation Codec ac Interface
Network; Complex Termination ...............45
Agere Systems Inc.
Tables
Page
Table 1. Pin Descriptions ........................................... 9
Table 2. Control States ............................................ 11
Table 3. Supervision Coding .................................... 11
Table 4. Recommended Operating
Characteristics ........................................... 14
Table 5. Thermal Characteristics.............................. 14
Table 6. Environmental Characteristics .................... 15
Table 7. 5 V Supply Currents ................................... 15
Table 8. 5 V Powering .............................................. 15
Table 9. 3.3 V Supply Currents................................. 16
Table 10. 3.3 V Powering ......................................... 16
Table 11. 2-Wire Port .............................................. 17
Table 12. Analog Pin Characteristics ...................... 18
Table 13. ac Feed Characteristics ........................... 19
Table 14. Logic Inputs and Outputs (VCC = 5 V) ...... 20
Table 15. Logic Inputs and Outputs (VCC = 3.3 V) ... 20
Table 16. Ringing Specifications ............................. 21
Table 17. Ring Trip .................................................. 21
Table 18. PPM ......................................................... 21
Table 19. Typical Active Mode On- to Off-Hook
Tip/Ring Current-Limit Transient
Response ................................................ 25
Table 20. FB1 and FB2 Values vs. Typical
Ramp Time .............................................. 26
Table 21. Onset of Power Ringing Clipping
VCC = 5 V, Cinput = 0.47 µF .................... 29
Table 22. Onset of Power Ringing Clipping
VCC = 3.1 V, Cinput = 0.47 µF ................. 29
Table 23. Signal and Component Selection Chart ... 30
Table 24. Parts List L9215; Agere T7504
First-Generation Codec Resistive Termination; Nonmeter Pulse Application ............ 38
Table 25. Parts List L9215; Agere T7504
First-Generation Codec Complex Termination; Meter Pulse Application ................... 44
Table 26. Parts List L9215; Agere T8536
Third-Generation Codec Meter Pulse
Application ac and dc Parameters;
Fully Programmable ................................ 46
3
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Features
■
■
■
Onboard balanced ringing generation:
— No ring relay
— No bulk ring generator required
— 15 Hz to 70 Hz ring frequency supported
— Sine wave input-sine wave output
— PWM input-sine wave output
— Square wave input-trapezoidal output
Power supplies requirements:
— VCC talk battery and ringing battery required
— No –5 V supply required
— No high-voltage positive supply required
Flexible Vcc options:
— 5 V or 3.3 V VCC operation
— 5 V or 3.3 V VCC interchangeable and transparent
to users
■
Logic-controlled battery switch:
— Minimize off-hook power dissipation
■
Minimal external components required
■
11 operating states:
— Forward active, VBAT2 applied
— Polarity reversal active, VBAT2 applied
— On-hook transmission, VBAT1 applied
— On-hook transmission polarity reversal, VBAT1
applied
— PPM active forward active, V BAT2 applied
— PPM active polarity reversal active, V BAT2 applied
— PPM active on-hook transmission, VBAT1 applied
— PPM active on-hook transmission polarity reversal, VBAT1 applied
— Scan
— Forward disconnect
— Ring mode
■
Unlatched parallel data control interface
■
Ultralow SLIC power:
— Scan 38 mW (VCC = 5 V)
— Forward/reverse active 57 mW (VCC = 5 V)
— Scan 27 mW (VCC = 3.3 V)
— Forward/reverse active 42 mW (VCC = 3.3 V)
■
Supervision:
— Loop start, fixed threshold with hysteresis
— Ring trip, single-pole ring trip filtering, fixed threshold as a function of battery voltage
— Common-mode current for ground key applications, user-adjustable threshold
Data Sheet
September 2001
■
Adjustable current limit:
— 10 mA to 70 mA programming range
■
Overhead voltage:
— Clamped typically <51 V differentially
— Clamped maximum <56.5 V single-ended
— Adjustable in active mode
■
Thermal shutdown protection with hysteresis
■
Longitudinal balance:
— ETSI/ITU-T balance
— Telcordia Technologies GR-909 balance
■
Meter pulse compatible:
— Dedicated meter pulse signal input
— On-hook transmission of PPM
■
ac interface:
— Two SLIC gain options to minimize external components required for interface to first- or third-generation codecs
— Sufficient dynamic range for direct coupling to
codec output
■
32-pin PLCC package/48-pin MLCC package
■
90 V CBIC-S technology
Description
The L9215 is designed to provide battery feed, ringing,
and supervision functions on short plain old telephone
service (POTS) loops. This device is designed for
ultralow power in all operating states.
The L9215 offers 11 operating states. The device
assumes use of a lower-voltage talk battery, a highervoltage ringing battery, and a VCC supply.
The L9215 requires only a positive VCC supply. No
–5 V supply is needed. The L9215 can operate with a
VCC of either 5 V or 3.3 V, allowing for greater user flexibility. The choice of VCC voltage is transparent to the
user; the device will function with either supply voltage
connected.
Two batteries are used:
1. A high-voltage ring battery (VBAT1).
VBAT1 is a maximum –75 V. VBAT1 is used for power
ring signal amplification and for scan and on-hook
transmission modes. This supply is current limited
to approximately the maximum power ringing current, typically 50 mA.
2. A lower-voltage talk battery (VBAT2).
VBAT2 is used for active mode powering.
4
Agere Systems Inc.
Data Sheet
September 2001
Description (continued)
Forward and reverse battery active modes are used for
off-hook conditions. Since this device is designed for
short-loop applications, the lower-voltage VBAT2 is
applied during the forward and reverse active states.
Battery reversal is quiet, without breaking the ac path.
Rate of battery reversal may be ramped to control
switching time.
The magnitude of the overhead voltage in the forward
and reverse active modes has a typical default value of
6.0 V, allowing for an undistorted signal of 3.14 dBm
into 900 Ω. This overhead can be increased to accommodate higher signal levels and/or PPM. The ring trip
detector is turned off during active modes to conserve
power.
Because on-hook transmission is not allowed in the
scan mode, an on-hook transmission mode is defined.
This mode is functionally similar to the active mode,
except the tip ring voltage is derived from the higher
VBAT1 rather than VBAT2.
In the on-hook transmission modes with a primary battery whose magnitude is greater than a nominal
51 V, the magnitude of the tip-to-ground and ring-toground voltage is clamped at less than 56.5 V.
To minimize on-hook power, a low-power scan mode is
available. In this mode, all functions except off-hook
supervision are turned off to conserve power. On-hook
transmission is not allowed in the scan mode.
In the scan mode with a primary battery whose magnitude is greater than a nominal 51 V, the magnitude of
the tip-to-ground and ring-to-ground voltage is clamped
at less than 56.5 V.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
This feature eliminates the need for a separate external
ring relay, associated external circuitry, and a bulk ringing generator. See the Applications section of this data
sheet for more information.
PPM is injected at the PPMIN pin (ac coupled). This is a
high-impedance input that controls the PPM differential
voltage on tip and ring. The PPM signal may be
present at this pin at all times; however, PPM will only
be transmitted to tip and ring during a PPM active
mode. There are forward and reverse active, and forward and reverse on-hook transmission modes with
PPM active.
No PPM shaping is done by the device. It is assumed
that a shaped PPM input is presented to PPMIN.
The maximum allowed PPM current at the 200 Ω ac
meter pulse load to avoid saturation of the device’s
internal AAC amplifier is 3 mArms. This signal level
is sufficient to provide a minimum 200 mVrms to the
200 Ω PPM load under maximum specified dc loop
conditions. Above 3 mArms PPM current, external
meter pulse rejection may be required. See the Applications section of this data sheet for more information if
on-hook transmission of PPM is required. Sufficient
overhead to accommodate on-hook transmission must
be programmed by the user at the OVH input.
Both the ring trip and loop closure supervision functions are included. The loop closure has a fixed typical
10.5 mA on- to off-hook threshold in the active mode
and a fixed 11.5 mA on- to off-hook threshold from the
scan mode. In either case, there is a 2 mA hysteresis.
The ring trip detector requires only a single-pole filter at
the input, minimizing external components. The ring
trip threshold at a given battery voltage is fixed. Typical
ring trip threshold is 42.5 mA for a –75 V VBAT1.
A forward disconnect mode is provided, where all circuits are turned off and power is denied to the loop.
The device offers a ring mode, in which a power ring
signal is provided to the tip/ring pair. During the ring
mode, a user-supplied, low-voltage ring signal (ac coupled) is input to the device’s RINGIN input. This signal is
amplified to produce the power ring signal. This signal
may be a sine wave or filtered square wave to produce
a sine wave on trapezoidal output. Ring trip detector
and common-mode current detector are active during
the ring mode.
Agere Systems Inc.
5
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Description (continued)
A common-mode current detector for tip or ring ground
detection is included for ground key applications. The
threshold is user programmable via external resistors.
See the Applications section of this data sheet for more
information on supervision functions.
Upon reaching the thermal shutdown temperature, the
device will enter an all off mode. Upon cooling, the
device will re-enter the state it was in prior to thermal
shutdown. Hysteresis is built in to prevent oscillation.
Longitudinal balance is consistent with European ETSI
and North American GR-909 requirements. Specifications are given in Table 6.
Data control is via a parallel unlatched control scheme.
The dc current limit is programmable in the active
modes via an applied voltage source. The voltage
source may be an external independent voltage
source. Also, the programming voltage may be derived
via a resistor divider network from the VREF SLIC output. A programmable external voltage source may be
used to provide software control of the loop closure
threshold. Design equations for this feature are given in
the dc Loop Current Limit section of the Applications
section of this data sheet.
Programming range is 10 mA to 70 mA with VCC =
5 V and 10 mA to 45 mA with VCC = 3.3 V. Programming accuracy is ±8% at 22 mA to 28 mA current limit.
Circuitry is added to the L9215 to minimize the inrush
of current from the VCC supply and to the battery supply
during an on- to off-hook transition, thus saving in
power supply design cost. See the Applications section
of this data sheet for more information.
Overhead is programmable in the active modes via an
applied voltage source. The voltage source may be an
external independent voltage source. Also the programming voltage may be derived via a resistor divider
network from the VREF SLIC output.
If the overhead is not programmed, a default overhead
of approximately 6.0 V is achieved. This is adequate
for a 3.14 dBm overload into 900 Ω. For the default
overhead, pin OVH is connected to ground. See the
Applications section of this data sheet for more information.
Data Sheet
September 2001
The L9215 uses a voltage feed-current sense architecture; thus, the transmit gain is a transconductance. The
L9215 transconductance is set via a single external
resistor, and this device is designed for optimal performance with a transconductance set at 300 V/A.
The L9215 offers an option for a single-ended to differential receive gain of either 8 or 2. These options are
mask programmable at the factory and are selected by
choice of code.
A receive gain of 8 is more appropriate when choosing
a first-generation type codec where termination impedance, hybrid balance, and overall gains are set by
external analog filters. The higher gain is typically
required for synthesization of complex termination
impedance.
A receive gain of 2 is more appropriate when choosing
a third-generation type codec. Third-generation codecs
will synthesize termination impedance and set hybrid
balance and overall gains. To accomplish these functions, third-generation codecs typically have both analog and digital gain filters. For optimal signal-to-noise
performance, it is best to operate the codec at a higher
gain level. If the SLIC then provides a high gain, the
SLIC output may be saturated causing clipping distortion of the signal at tip and ring. To avoid this situation,
with a higher gain SLIC, external resistor dividers are
used. These external components are not necessary
with the lower gain offered by the L9215. See the Applications section of this data sheet for more information.
The L9215 is internally referenced to 1.5 V. This reference voltage is output at the VREF output of the device.
The SLIC output VITR is also referenced to 1.5 V;
therefore, it must be ac coupled to the codec input.
However, the SLIC inputs RCVP/RCVN are floating
inputs. If there is not feedback from RCVP/RCVN to
VITR, RCVP/RCVN may be directly coupled to the
codec output. If there is feedback from RCVP/RCVN to
VITR, RCVP/RCVN must be ac coupled to the codec
output.
The L9215 is packaged in a 32-pin PLCC surfacemount package and a 48-pin MLCC ultrasmall surfacemount package. Use L9215A for gain of 8 applications
and L9215G for gain of 2 applications.
Transmit and receive gains have been chosen to minimize the number of external components required in
the SLIC-codec ac interface, regardless of the choice
of codec.
6
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Architecture Diagram
AGND
VCC
BGND VBAT2
VREF
VITR
POWER
B = 20
VBAT1
VPROG
NSTAT
RTFLT
CURRENT
LIMIT
AND
INRUSH
CONTROL
DCOUT
RING
TRIP
LOOP
CLOSURE
AAC
TXI
1.5 V
BAND-GAP
REFERENCE
VITR
ITR
COMMONMODE
CURRENT
DETECTOR
RECTIFIER
ICM
TRGDET
–
VTX
(ITR/306)
OUT
AX
+
X1
VREF
–
RFT
PT
ITR
18 Ω
CF2
OVH
+1
+
X1
TIP/RING
CURRENT
SENSE
ITR
PR
FB2
FB1
+
RFR
18 Ω
CF1
VREG
–1
ac INTERFACE
–
RCVN
GAIN
+
RCVP
–
9215A GAIN = 4
VREG
PPM
2x
9215G GAIN = 1
PARALLEL
DATA
INTERFACE
RINGING
27.5x
RINGIN
PPMIN
BR B0
B1
B2
12-3530.g (F)
Figure 1. Architecture Diagram
Agere Systems Inc.
7
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
RCVP
VITR
NC
NSTAT
TXI
VTX
ITR
Pin Information
4
3
2
1
32
31
30
RCVN
5
29
BR
RINGIN
6
28
B0
PPMIN
7
27
B1
OVH
8
26
B2
DCOUT
9
25
PR
L9215A/G
32-PIN PLCC
VPROG
10
24
PT
CF2
11
23
FB2
CF1
12
22
FB1
RTFLT
13
21
ICM
19
20
TRGDET
18
BGND
VCC
17
VBAT2
16
VBAT1
15
AGND
VREF
14
NC
ITR
NC
VTX
TXI
NC
NSTAT
NC
VITR
NC
RCVP
RCVN
Figure 2. 32-Pin PLCC Diagram
48 47 46 45 44 43 42 41 40 39 38 37
RINGINN
1
36
BR
PPMIN
2
35
B0
NC
3
34
B1
NC
4
33
B2
OVH
5
32
NC
DCOUT
6
31
PR
VPROG
7
30
NC
NC
8
29
PT
L9215A/G
48-PIN MLCC
CF2
9
28
NC
CF1
10
27
NC
NC
11
26
FB1
RTFLT
12
25
FB2
ICM
TRGDET
NC
BGND
VBAT2
NC
VBAT1
NC
Vcc
AGND
NC
VREF
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. 48-Pin MLCC Diagram
8
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Pin Information (continued)
Table 1. Pin Descriptions
32-Pin
PLCC
1
48-Pin
MLCC
43
Symbol
Type
Name/Function
NSTAT
O
2
NC
—
3
3, 4, 8, 11,
14, 17, 18,
21, 27, 28,
30, 32, 37,
39, 42, 44, 46
45
Loop Closure Detector Output—Ring Trip Detector Output. When
low, this logic output indicates that an off-hook condition exists or ringing is tripped.
No Connection.
VITR
O
4
47
RCVP
I
5
48
RCVN
I
6
1
RINGIN
I
7
2
PPMIN
I
8
5
OVH
I
9
6
DCOUT
O
10
7
VPROG
I
11
12
13
9
10
12
CF2
CF1
RTFLT
—
—
—
14
13
VREF
O
Agere Systems Inc.
Transmit ac Output Voltage. Output of internal AAC amplifier. This
output is a voltage that is directly proportional to the differential ac tip/
ring current.
Receive ac Signal Input (Noninverting). This high-impedance input
controls to ac differential voltage on tip and ring. This node is a floating
input.
Receive ac Signal Input (Inverting). This high-impedance input controls to ac differential voltage on tip and ring. This node is a floating
input.
Power Ring Signal Input. ac-couple to a sine wave or lower crest factor low-voltage ring signal. The input here is amplified to provide the
full-power ring signal at tip and ring. This signal may be applied continuously, even during nonringing states.
Receive PPM Signal Input. ac-couple to a 12 kHz or 16 kHz PPM signal. The input here is amplified to provide the differential PPM voltage
on tip and ring. This signal may be applied continuously, even during
non-PPM modes.
Overhead Voltage Program Input. Connect a voltage source to this
point to program the overhead voltage. Voltage source may be external
or derived via a resistor divider from V REF. A programmable external
voltage source may be used to provide software control of the overhead voltage. If a resistor or voltage source is not connected, the overhead voltage will default to a nominal 6.0 V. If the default overhead is
desired, connect this pin to ground.
dc Output Voltage. This output is a voltage that is directly proportional
to the absolute value of the differential tip/ring current. This is used to
set ring trip threshold.
Current-Limit Program Input. Connect a voltage source to this point
to program the dc current limit. Voltage source may be external or
derived via a resistor divider from VREF. A programmable external voltage source may be used to provide software control of the current limit.
Filter Capacitor. Connect a capacitor from this node to ground.
Filter Capacitor. Connect a capacitor from this node to CF2.
Ring Trip Filter. Connect this lead to DCOUT via a resistor and to
AGND with a capacitor to filter the ring trip circuit to prevent spurious
responses. A single-pole filter is needed.
SLIC Internal Reference Voltage. Output of internal 1.5 V reference
voltage.
9
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Pin Information (continued)
Table 1. Pin Descriptions (continued)
32-Pin
PLCC
15
16
48-Pin
MLCC
15
16
Symbol
17
18
19
20
19
20
22
23
VBAT1
VBAT2
BGND
TRGDET
21
24
ICM
22
25
FB2
23
26
FB1
24
29
PT
25
31
PR
26
27
28
29
30
33
34
35
36
38
B2
B1
B0
BR
ITR
31
40
VTX
O
32
41
TXI
I
10
AGND
VCC
Type
Name/Function
GND Analog Signal Ground.
PWR Analog Power Supply. User choice of 5 V or 3.3 V nominal power or supply.
PWR Battery Supply 1. High-voltage battery.
PWR Battery Supply 2. Lower-voltage battery.
GND Battery Ground. Ground return for the battery supplies.
O
Tip/Ring Ground Detect. When high, this open collector output indicates
the presence of a ring ground or a tip ground. This supervision output may
be used in ground key or common-mode fault detection applications.
I
Common-Mode Current Sense. To program tip or ring ground sense
threshold, connect a resistor to VCC and connect a capacitor to AGND to filter 50/60 Hz. If unused, the pin is connected to ground.
—
Polarity Reversal Slowdown Capacitor. Connect a capacitor from this
node for controlling rate of battery reversal. If ramped battery reversal is
not desired, this pin is left open.
—
Polarity Reversal Slowdown Capacitor. Connect a capacitor from this
node for controlling rate of battery reversal. If ramped battery reversal is
not desired, this pin is left open.
I/O Protected Tip. The output drive of the tip amplifier and input to the loop
sensing circuit. Connect to loop through overvoltage and overcurrent protection.
I/O Protected Ring. The output drive of the ring amplifier and input to the loop
sensing circuit. Connect to loop through overvoltage and overcurrent protection.
u
I
State Control Input. These pins have an internal 60 kΩ pull-up.
I
Transmit Gain. Input to AX amplifier. Connect a resistor from this node to
VTX to set transmit gain. Gain shaping for termination impedance with a
COMBO I codec is also achieved with a network from this node to VTX.
ac Output Voltage. Output of internal AX amplifier. The voltage at this pin
is directly proportional to the differential tip/ring current.
ac/dc Separation. Input to internal AAC amplifier. Connect a 0.1 µF capacitor from this pin to VTX.
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Operating States
Table 2. Control States
B0
1
1
1
1
1
1
1
1
0
0
0
B1
1
1
0
0
1
1
0
0
1
0
1
B2
0
0
0
0
1
1
1
1
1
0
1
BR
1
0
1
0
1
0
1
0
1
1
0
State
Forward active
Forward active with PPM
Reverse active
Reverse active with PPM
On-hook transmission forward battery (in this state, the device will power up)
On-hook transmission with PPM forward battery
On-hook transmission reverse battery
On-hook transmission with PPM reverse battery
Scan
Disconnect
Ring
Table 3. Supervision Coding
NSTAT
TRGDET
0 = off-hook or ring trip or TSD.
0 = no ring or tip ground
1 = on-hook and no ring trip and no 1 = ring or tip ground
TSD or DISCONNECT state.
Agere Systems Inc.
11
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
State Definitions
Reverse Active with PPM
Forward Active
■
Pin PR is positive with respect to PT.
■
VBAT2 is applied to tip/ring drive amplifiers.
■
Loop closure and common-mode detect are active.
■
Ring trip detector is turned off to conserve power.
■
PPM input is on.
■
Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900 Ω and may be
increased via OVH to accommodate higher-voltage
meter pulse signals.
■
Pin PT is positive with respect to PR.
■
VBAT2 is applied to tip/ring drive amplifiers.
■
Loop closure and common-mode detect are active.
■
Ring trip detector is turned off to conserve power.
■
PPM input is off.
■
Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900 Ω and may be
increased via OVH.
Scan
Reverse Active
■
Except for loop closure, all circuits (including ring trip
and common-mode detector) are powered down.
■
Pin PR is positive with respect to PT.
■
VBAT2 is applied to tip/ring drive amplifiers.
■
On-hook transmission is disabled.
■
Loop closure and common-mode detect are active.
■
■
Ring trip detector is turned off to conserve power.
Pin PT is positive with respect to PR and VBAT1 is
applied to tip/ring.
■
■
PPM input is off.
■
Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900 Ω and may be
increased via OVH.
The tip-to-ring on-hook differential voltage will be typically between –44 V and –51 V with a –70 V primary
battery.
Forward Active with PPM
On-Hook Transmission—Forward Battery
■
Pin PT is positive with respect to PR.
■
VBAT1 is applied to tip/ring drive amplifiers.
■
Supervision circuits, loop closure, and commonmode detect are active.
■
Pin PT is positive with respect to PR.
■
VBAT2 is applied to tip/ring drive amplifiers.
■
Loop closure and common-mode detect are active.
■
Ring trip detector is turned off to conserve power.
■
Ring trip detector is turned off to conserve power.
■
On-hook transmission is allowed.
■
PPM input is on.
■
■
Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900 Ω and may be
increased via OVH to accommodate higher-voltage
meter pulse signals.
The tip-to-ring on-hook differential voltage will be
between –41 V and –49 V with a –70 V primary battery.
■
PPM is off.
12
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
State Definitions (continued)
On-Hook Transmission with PPM—Forward
Battery
■
Pin PT is positive with respect to PR.
■
VBAT1 is applied to tip/ring drive amplifiers.
■
Supervision circuits, loop closure, and commonmode detect are active.
■
Ring trip detector is turned off to conserve power.
■
On-hook transmission is allowed.
■
The tip-to-ring on-hook differential voltage will be
between –41 V and –49 V with a –70 V primary battery.
■
■
Ring trip detector is turned off to conserve power.
■
On-hook transmission is allowed.
■
The tip-to-ring on-hook differential voltage will be
between –41 V and –49 V with a –70 V primary battery.
■
PPM is on.
Disconnect
■
The tip/ring amplifiers and all supervision are turned
off.
■
The SLIC goes into a high-impedance state.
■
NSTAT is forced high (on-hook).
PPM is on.
Ring
On-Hook Transmission—Reverse Battery
■
Pin PR is positive with respect to PT.
■
VBAT1 is applied to tip/ring drive amplifiers.
■
Supervision circuits, loop closure, and commonmode detect are active.
■
Ring trip detector is turned off to conserve power.
■
On-hook transmission is allowed.
■
The tip-to-ring on-hook differential voltage will be
between –41 V and –49 V with a –70 V primary battery.
■
PPM is off.
On-Hook Transmission with PPM—Reverse
Battery
■
Pin PR is positive with respect to PT.
■
VBAT1 is applied to tip/ring drive amplifiers.
■
Supervision circuits, loop closure, and commonmode detect are active.
Agere Systems Inc.
■
Power ring signal is applied to tip and ring.
■
Input waveform at RINGIN is amplified.
■
Ring trip supervision and common-mode current
supervision are active; loop closure is inactive.
■
Overhead voltage is reduced to typically 4 V, regardless of programming on OVH, and current limit set at
VPROG is disabled.
■
Current is limited by saturation current of the amplifiers themselves, typically 100 mA at 125 °C.
Thermal Shutdown
■
Not controlled via truth table inputs.
■
NSTAT is forced low (off-hook) during this state
■
This mode is caused by excessive heating of the
device, such as may be encountered in an extended
power cross situation.
13
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Absolute Maximum Ratings (@ TA = 25 °C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
dc Supply (VCC)
Battery Supply (VBAT1)
Battery Supply (VBAT2)
Logic Input Voltage
Logic Output Voltage
Operating Temperature Range
Storage Temperature Range
Relative Humidity Range
Ground Potential Difference (BGND to AGND)
PT or PR Fault Voltage (dc)
PT or PR Fault Voltage (10 x 1000 µs)
Symbol
—
—
—
—
—
—
—
—
—
VPT, VPR
VPT, VPR
Min
–0.5
—
—
–0.5
–0.5
–40
–40
5
—
VBAT – 5
VBAT – 15
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
7.0
–80
VBAT1
VCC + 0.5
VCC + 0.5
125
150
95
±1
3
15
Unit
V
V
V
V
V
°C
°C
%
V
V
V
Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when
powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the
device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage.
Table 4. Recommended Operating Characteristics
Parameter
5 V dc Supplies (VCC)
3 V dc Supplies (VCC)
High Office Battery Supply (VBAT1)
Auxiliary Office Battery Supply (VBAT2)
Operating Temperature Range
Min
—
3.13
–60
–12
–40
Typ
5.0
3.3
–70
—
25
Max
5.25
—
–75
VBAT1
85
Unit
V
V
V
V
°C
Table 5. Thermal Characteristics
Parameter
Thermal Protection Shutdown (Tjc)
Min
150
Typ
165
Max
—
Unit
°C
32-pin PLCC Thermal Resistance Junction to Ambient (θJA)1, 2:
Natural Convection 2S2P Board
Natural Convection 2S0P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board
—
—
—
—
35.5
50.5
31.5
42.5
—
—
—
—
°C/W
°C/W
°C/W
°C/W
48-pin MLCC Thermal Resistance Junction to Ambient (θJA)1, 2
—
38
—
°C/W
1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Airflow, PCB board layers, and other factors can greatly affect this parameter.
14
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics
Table 6. Environmental Characteristics
Parameter
Temperature Range
Humidity Range1
Min
–40
5
Typ
—
—
Max
85
951
Unit
°C
%RH
Min
Typ
Max
Unit
—
—
—
4.30
0.24
3
4.80
0.35
6
mA
mA
µA
—
—
—
5.95
25
1.2
7.0
85
1.40
mA
µA
mA
—
—
—
6.0
1.5
1.5
7.0
1.9
6
mA
mA
µA
—
—
—
2.7
15
3.5
3.75
110
25
mA
µA
µA
—
—
—
5.9
1.8
2
6.5
2.2
6
mA
mA
µA
Min
—
—
Typ
38
57
Max
46
64
Unit
mW
mW
—
—
—
135
14
156
165
23
184
mW
mW
mW
1. Not to exceed 26 grams of water per kilogram of dry air.
Table 7. 5 V Supply Currents
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 5 V.
Parameter
Supply Currents (scan state; no loop current):
IVCC
IVBAT1
IVBAT2
Supply Currents (forward/reverse active; no loop current, with or without PPM,
VBAT2 applied):
IVCC
IVBAT1
IVBAT2
Supply Currents (on-hook transmission mode; no loop current, with or without
PPM, VBAT1 applied):
IVCC
IVBAT1
IVBAT2
Supply Currents (disconnect mode):
IVCC
IVBAT1
IVBAT2
Supply Currents (ring mode; no load):
IVCC
IVBAT1
IVBAT2
Table 8. 5 V Powering
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 5 V.
Parameter
Power Dissipation (scan state; no loop current)
Power Dissipation (forward/reverse active; no loop current, with or without PPM)
Power Dissipation (on-hook transmission mode; no loop current, with or without
PPM, VBAT1 applied)
Power Dissipation (disconnect mode)
Power Dissipation (ring mode; no load)
Agere Systems Inc.
15
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics (continued)
Table 9. 3.3 V Supply Currents
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 3.3 V.
Parameter
Supply Currents (scan state; no loop current):
IVCC
IVBAT1
IVBAT2
Supply Currents (forward/reverse active; no loop current, with/without PPM,
VBAT2 applied):
IVCC
IVBAT1
IVBAT2
Supply Currents (on-hook transmission mode; no loop current, with/without
PPM, VBAT1 applied):
IVCC
IVBAT1
IVBAT2
Supply Currents (disconnect mode):
IVCC
IVBAT1
IVBAT2
Supply Currents (ring mode; no loop current):
IVCC
IVBAT1
IVBAT2
Min
Typ
Max
Unit
—
—
—
3.2
0.24
3
3.6
0.35
6
mA
mA
µA
—
—
—
4.8
25
1.2
5.7
85
1.4
mA
µA
mA
—
—
—
4.9
1.5
1.5
5.7
1.9
6
mA
mA
µA
—
—
—
1.8
8
2
2.5
110
25
mA
µA
µA
—
—
—
4.70
1.8
2
5.4
2.2
6
mA
mA
µA
Min
—
Typ
27
Max
36.5
Unit
mW
—
42
53
mW
—
121
151
mW
—
6.5
15
mW
—
141
172
mW
Table 10. 3.3 V Powering
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 3.3 V.
Parameter
Power Dissipation (scan state; no loop current)
Power Dissipation (forward/reverse active; no loop current, with/without PPM,
VBAT2 applied)
Power Dissipation (on-hook transmission mode; no loop current, with/without
PPM, VBAT1 applied)
Power Dissipation (disconnect mode)
Power Dissipation (ring mode; no loop current)
16
Agere Systems Inc.
Data Sheet
September 2001
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Electrical Characteristics (continued)
Table 11. 2-Wire Port
Parameter
Tip or Ring Drive Current = dc + Longitudinal + Signal Currents + PPM
Tip or Ring Drive Current = Ringing + Longitudinal
Signal Current
Longitudinal Current Capability per Wire (Longitudinal current is independent of dc loop current.)
PPM Signal Current = 1.25 VMAX into 200 Ω ac
Ringing Current (RLOAD = 1386 Ω + 40 µF)
Ringing Current Limit (RLOAD = 100 Ω)
dc Loop Current—ILIM (RLOOP = 100 Ω):
Programming Range (VCC = 5 V)
Programming Range (VCC = 3.3 V)
Voltage at VPROG
dc Current Variation (current limit 22 mA to 28 mA)
dc Current Variation (current limit 70 mA)
dc Feed Resistance (does not include protection resistors)
Open Loop Voltages:
Scan Mode:
|VBAT1| > 51 V |VTIP| – |VRING|
PR to Battery Ground
PT to Battery Ground
OHT Mode:
|VBAT1| > 51 V (VOH = 0 V) |VTIP| – |VRING|
PR to Battery Ground
PT to Battery Ground
Active Mode (VOH = 0 V):
|PT – PR| – |VBAT2|
Ring Mode:
|PT – PR| – |VBAT1|
Agere Systems Inc.
Min
105
65
10
8.5
Typ
—
—
—
15
Max
—
—
—
—
Unit
mAp
mAp
mArms
mArms
6.25
29
—
—
—
—
—
—
50
mArms
mArms
mAp
15
15
0.194
—
—
—
—
—
—
—
—
50
70
45
1.01
±8
±10
—
mA
mA
V
%
%
Ω
44
—
—
51
—
—
—
56.5
56.5
V
V
41
—
—
49
—
—
—
56.5
56.5
V
V
5.65
6.0
6.5
V
—
4.0
—
V
17
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics (continued)
Table 11. 2-Wire Port (continued)
Parameter
Loop Closure Threshold:
Active/On-hook Transmission Modes
Scan Mode
Loop Closure Threshold Hysteresis:
VCC = 5 V
VCC = 3.3 V
Ground Key:
Differential Detector Threshold
Detection
Longitudinal to Metallic Balance at PT/PR
Test Method: Q552 (11/96) Section 2.1.2 and IEEE® 455:
300 Hz to 600 Hz
600 Hz to 3.4 kHz
Metallic to Longitudinal (harm) Balance:
200 Hz to 1000 Hz
100 Hz to 4000 Hz
PSRR 500 Hz—3000 Hz:
VBAT1, VBAT2
VCC (5 V operation)
Min
Typ
Max
Unit
—
—
10.5
11.5
—
—
mA
mA
—
—
2
1
—
—
mA
mA
5
50
8
—
10
—
mA
ms
52
52
—
—
—
—
dB
dB
40
40
—
—
—
—
dB
dB
45
35
—
—
—
—
dB
dB
Table 12. Analog Pin Characteristics
Parameter
TXI (input impedance)
Output Offset (VTX)
Output Offset (VITR)
Output Drive Current (VTX)
Output Drive Current (VITR)
Output Voltage Swing:
Maximum (VTX, VITR)
Minimum (VTX)
Minimum (VITR)
Output Short-circuit Current
Output Load Resistance
Output Load Capacitance
RCVN and RCVP:
Input Voltage Range (VCC = 5 V)
Input Voltage Range (VCC = 3.3 V)
Input Bias Current
Differential PT/PR Current Sense (DCOUT):
Gain (PT/PR to DCOUT)
Offset Voltage at ILOOP = 0
18
Min
Typ
Max
Unit
—
—
—
±300
±10
100
—
—
—
—
—
±10
±100
—
—
kΩ
mV
mV
µA
µA
AGND
AGND + 0.25
AGND + 0.35
—
10
—
—
—
—
—
—
20
VCC
VCC – 0.5
VCC – 0.4
±50
—
—
V
V
V
mA
kΩ
pF
0
0
—
—
—
0.05
VCC – 0.5
VCC – 0.3
—
V
V
µA
—
–20
67
—
—
20
V/A
mV
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics (continued)
Table 13. ac Feed Characteristics
Parameter
Impedance1
ac Termination
Total Harmonic Distortion (200 Hz—4 kHz)2:
Off-hook
On-hook
Transmit Gain (f = 1004 Hz, 1020 Hz, current limit)3:
PT/PR Current to VITR
Receive Gain, f = 1004 Hz, 1020 Hz Open Loop:
RCVP or RCVN to PT—PR (gain of 8 option, L9215A)
RCVP or RCVN to PT—PR (gain of 2 option, L9215G)
Gain vs. Frequency (transmit and receive)2 600 Ω Termination,
1004 Hz, 1020 Hz Reference:
200 Hz—300 Hz
300 Hz—3.4 kHz
3.4 kHz—20 kHz
20 kHz—266 kHz
Gain vs. Level (transmit and receive)2 0 dBV Reference:
–55 dB to +3.0 dB
Idle-channel Noise (tip/ring) 600 Ω Termination:
Psophometric
C-Message
3 kHz Flat
Idle-channel Noise (VTX) 600 Ω Termination:
Psophometric
C-Message
3 kHz Flat
Min
Typ
Max
Unit
150
600
1400
Ω
—
—
—
—
0.3
1.0
%
%
300 – 3%
300
300 + 3%
V/A
7.76
1.94
8
2
8.24
2.06
—
—
–0.3
–0.05
–3.0
—
0
0
0
—
0.05
0.05
0.05
2.0
dB
dB
dB
dB
–0.05
0
0.05
dB
—
—
—
–82
8
—
–77
13
20
dBmp
dBrnC
dBrn
—
—
—
–82
8
—
–77
13
20
dBmp
dBrnC
dBrn
1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between
150 Ω and 1400 Ω can be synthesized.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 4750 Ω, the recommended value. Positive current is defined as the differential current flowing from PT to PR.
Agere Systems Inc.
19
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics (continued)
Table 14. Logic Inputs and Outputs (VCC = 5 V)
Parameter
Input Voltages:
Low Level
High Level
Input Current:
Low Level (VCC = 5.25 V, VI = 0.4 V)
High Level (VCC = 5.25 V, VI = 2.4 V)
Output Voltages (open collector with internal pull-up resistor):
Low Level (VCC = 4.75 V, IOL = 200 µA)
High Level (VCC = 4.75 V, IOH = –20 µA)
Symbol
Min
Typ
Max
Unit
VIL
VIH
–0.5
2.0
0.4
2.4
0.7
VCC
V
V
IIL
IIH
—
—
—
—
±50
±50
µA
µA
VOL
VOH
0
2.4
0.2
—
0.4
VCC
V
V
Symbol
Min
Typ
Max
Unit
VIL
VIH
–0.5
2.0
0.2
2.5
0.5
VCC
V
V
IIL
IIH
—
—
—
—
±50
±50
µA
µA
VOL
VOH
0
2.2
0.2
—
0.5
VCC
V
V
Table 15. Logic Inputs and Outputs (VCC = 3.3 V)
Parameter
Input Voltages:
Low Level
High Level
Input Current:
Low Level (VCC = 3.46 V, VI = 0.4 V)
High Level (VCC = 3.46 V, VI = 2.4 V)
Output Voltages (open collector with internal pull-up resistor):
Low Level (VCC = 3.13 V, IOL = 200 µA)
High Level (VCC = 3.13 V, IOH = –5 µA)
20
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Electrical Characteristics (continued)
Table 16. Ringing Specifications
Parameter
RINGIN (This input is ac coupled through 0.47 µF.):
Input Voltage Swing
Input Impedance
Ring Signal Isolation:
PT/PR to VITR
Ring Mode
Ring Signal Isolation:
RINGIN to PT/PR
Nonring Mode
Ringing Voltage (5 REN 1380 Ω + 40 µF load, 100 Ω loop, 2 x 50 Ω protection
resistors, –70 V battery)
Ringing Voltage (3 REN 2310 Ω + 24 µF load, 250 Ω loop, 2 x 50 Ω protection
resistors, –70 V battery)
Ring Signal Distortion:
5 REN 1380 Ω, 40 µF Load, 100 Ω Loop
3 REN 2310 Ω, 24 µF Load, 250 Ω Loop
Differential Gain:
RINGIN to PT/PR—No Load
Min
Typ
Max
Unit
0
—
—
—
100
60
VCC
—
—
V
kΩ
dB
—
80
—
dB
40
—
—
Vrms
40
—
—
Vrms
—
—
3
3
—
—
%
%
—
55
—
—
Table 17. Ring Trip
Parameter
Ring Trip (NSTAT = 0): Loop Resistance (total)
Ring Trip (NSTAT = 1): Loop Resistance (total)
Trip Time (f = 20 Hz)
Min
Typ
Max
Unit
100
—
—
—
—
—
600
10
100
Ω
kΩ
ms
Ringing will not be tripped by the following loads:
■
10 kΩ resistor in parallel with a 6 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
■
100 Ω resistor in series with a 2 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
Table 18. PPM
Parameter
PPM Source*:
Frequency (f1)
Frequency (f2)
Input Signal
Input Impedance
Signal Gain (2.2 Vrms maximum at PT/PR)
Isolation
Harmonic Distortion
Min
Typ
Max
Unit
11.88
15.80
0
—
5.5
—
—
12
16
1.1
50
6
60
—
12.12
16.20
1.25
—
6.5
—
5
kHz
kHz
Vrms
kΩ
dB
dB
%
* PPM signal should be ac coupled through 10 nF.
Agere Systems Inc.
21
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Test Configurations
RINGIN
RINGIN
RTFLT
0.1 µF
0.47 µF
383 kΩ
PPMIN
10 nF
DCOUT
30 Ω
RCVP
PR
TIP
PPMIN
26.7 kΩ
60.4 kΩ
69.8 kΩ
RCVN
RLOOP
100 Ω/600 Ω
RCV
RCV
0.1 µF
30 Ω
VITR
VITR
PT
RING
L9215
BASIC TEST
CIRCUIT
OVH
VPROG
0.1 µF
TXI
VTX
4750 Ω
VREF
ITR
FB2
FB1
CF1
0.1 µF
BR
BR
B0
B0
B1
B1
B2
B2
CF2
0.1 µF
VBAT2
VBAT1
BGND VCC
0.1 µF
AGND
0.1 µF
ICM TRGDET NSTAT
82.3 kΩ
0.1 µF
VBAT2
VBAT1
VCC
0.1 µF
VCC
12-3531.E (F)
Figure 4. Basic Test Circuit
22
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Test Configurations (continued)
100 µF
V BAT OR VCC
100 Ω
TIP
VS
DISCONNECT
BYPASS CAPACITOR
4.7 µF
368 Ω
+
VM
368 Ω
VS
BASIC
TEST CIRCUIT
–
RING
100 µF
VBAT OR
VCC
TIP
+
600 Ω
BASIC
TEST CIRCUIT
VT/R
VS
VM
LONGITUDINAL BALANCE = 20log
12-2584.c (F)
–
RING
Figure 7. Longitudinal Balance
PSRR = 20log
VS
VT/R
12-2582.c (F)
Figure 5. Metallic PSRR
VITR
PT
+
600 Ω
V BAT OR VCC
100 Ω
4.7 µF
DISCONNECT
BYPASS CAPACITOR
VT/R
–
BASIC
TEST CIRCUIT
PR
RCV
RCV
VS
VS
V BAT OR
V CC
GXMT =
VXMT
VT/R
GRCV =
VT/R
VRCV
67.5 Ω
TIP
10 µF
+
VM
–
BASIC
TEST CIRCUIT
12-2587.G (F)
67.5 Ω
56.3 Ω
Figure 8. ac Gains
RING
10 µF
PSRR = 20log
VS
VM
12-2583.b (F)
Figure 6. Longitudinal PSRR
Agere Systems Inc.
23
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Applications
Power Control
Under normal device operating conditions, power dissipation on the device must be controlled to prevent the
device temperature from rising above the thermal shutdown and causing the device to shut down. Power dissipation is highest with higher battery voltages, higher
current limit, and under shorter dc loop conditions.
Additionally, higher ambient temperature will also
reduce thermal margin.
To support required power ringing voltages, this device
is meant to operate with a high-voltage primary battery
(–65 V to –75 V typically). Thus, power control is normally achieved by use of the battery switch and an auxiliary lower absolute voltage battery. Operating
temperature range, maximum current limit, maximum
battery voltage, minimum dc loop length and protection
resistors values, airflow, and number of PC board layers will influence the overall thermal performance. The
following example illustrates typical thermal design
considerations.
The thermal resistance of the 32-pin PLCC package is
typically 50.5 °C/W, which is representative of the natural airflow as seen in a typical switch cabinet with a
two-layer board.
The L9215 will enter thermal shutdown at a minimum
temperature of 150 °C. The thermal design should
ensure that the SLIC does not reach this temperature
under normal operating conditions.
For this example, assume a maximum ambient operating temperature of 85 °C, a maximum current limit of
30 mA, a maximum battery of –70 V, and an auxiliary
battery of –21 V. Assume a (worst-case) minimum dc
loop of 20 Ω of wire resistance, 30 Ω protection resistors, and 200 Ω for the handset. Additionally, include
the effects of parameter tolerance.
1. TTSD – TAMBIENT(max) = allowed thermal rise.
150 °C – 85 °C = 65 °C.
2. Allowed thermal rise = package thermal
impedance • SLIC power dissipation.
65 °C = 50.5 °C/W • SLIC power dissipation
SLIC power dissipation (PD) = 1.29 W.
24
Data Sheet
September 2001
Thus, if the total power dissipated in the SLIC is less
than 1.29 W, it will not enter the thermal shutdown
state. Total SLIC power is calculated as:
Total PD = maximum battery • maximum current
limit + SLIC quiescent power.
For the L9215, the worst-case SLIC on-hook active
power is 76.4 mW. Thus,
Total off-hook power = (ILOOP)(current-limit
tolerance)*(VBATAPPLIED) + SLIC on-hook power
Total off-hook power = (0.030 A)(1.08) * (21) +
76.4 mW
Total off-hook power = 756.8 mW
The power dissipated in the SLIC is the total power dissipation less the power that is dissipated in the loop.
SLIC PD = total power – loop power
Loop off-hook power = (ILOOP * 1.08)2 • (RLOOP(dc)
min + 2RHANDSET)
Loop off-hook power = (0.030 A)(1.08)2 • (20 Ω +
60 Ω + 200 Ω)
Loop off-hook power = 293.9 mW
SLIC off-hook power = Total off-hook power – loop
off-hook power
SLIC off-hook power = 756.8 mW – 293.9 mW
SLIC off-hook power = 462.9 mW < 1.29 W
Thus, under the worst-case normal operating conditions of this example, the thermal design, using the
auxiliary, is adequate to ensure the device is not driven
into thermal shutdown under worst-case operating conditions.
dc Loop Current Limit
In the active modes, dc current limit is programmable
via an applied voltage source at the device’s VPROG
control input. The voltage source may be an external
voltage source or derived via a resistor divider network
from the VREF SLIC output or an external voltage
source. A programmable external voltage source may
be used to provide software control of the loop current
limit. The loop current limit (ILIM) is related to the VPROG
voltage at the onset of current limit by:
ILIM (mA) = 67 (mA/V) * VPROG (V)
Note that there is a 12.5 kΩ slope to the I/V characteristic in the current-limit region; thus, once in current
limit, the actual loop current will increase slightly, as
loop length decreases.
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Applications (continued)
Overhead Voltage
dc Loop Current Limit (continued)
Active Mode
Note that the overall current-limit accuracy achieved
will not only be affected by the specified accuracy of
the internal SLIC current-limit circuit (accuracy associated with the 67 term), but also by the accuracy of the
voltage source and the accuracy of any external resistor divider network used and voltage offsets due to the
specified input bias current. Tolerance of the current
limit is ±8%. If a resistor divider from VREF is used, it is
recommended that the sum of the two resistors be
greater than 100 kΩ.
Overhead is programmable in the active mode via an
applied voltage source at the device’s OVH control
input. The voltage source may be an external voltage
source or derived via a resistor divider network from
the VREF SLIC output or an external voltage source. A
programmable external voltage source may be used to
provide software control of the overhead voltage. The
overhead voltage (VOH) is related to the OVH voltage
by:
The above equations describe the active mode steadystate current-limit response. There will be a transient
response of the current-limit circuit upon an on- to offhook transition. Typical active mode transient currentlimit response is given in Table 19.
Overall accuracy is determined by the accuracy of the
voltage source and the accuracy of any external resistor divider network used and voltage offsets due to the
specified input bias current. If a resistor divider from
VREF is used, a lower magnitude resistor will give a
more accurate result due to a lower offset associated
with the input bias current; however, lower value resistors will also draw more power from VREF.
Table 19. Typical Active Mode On- to Off-Hook Tip/
Ring Current-Limit Transient Response
Parameter
dc Loop Current:
Active Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 5 ms
dc Loop Current:
Active Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 50 ms
dc Loop Current:
Active Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 300 ms
Value
Unit
ILIM + 60
mA
VOH = 6.0 V + 5 * VOVH (V)
Note that a default overhead voltage of 6.0 V is
achieved by shorting input pin OVH to analog ground.
The default overhead provides sufficient headroom for
an on-hook transmission of a 3.14 dBm signal into
900 Ω .
ILIM + 20
mA
ILIM
mA
Overhead voltage may need to be increased to accommodate on-hook transmission of higher-voltage signals, such as meter pulse. The following example is
meant to illustrate the design procedure that can be followed.
Assume we need on-hook transmission of a 1.0 Vrms
meter pulse into 200 Ω. Further, assume 50 Ω protection resistors are used.
VOH = 6.0 V + (1+ [2 * Rp]/200) * Vpeak
VOH = 6.0 + (1+ [2 * 50]/200) * 1 (1.414)
VOH = 8.121 V
Agere Systems Inc.
25
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Applications (continued)
Overhead Voltage (continued)
Data Sheet
September 2001
transmit direction at VITR is deactivated. However, if
the AX amplifier at VTX is active during the ring mode,
differential ring current may be sensed at VTX during
the ring mode.
Active Mode (continued)
Adding 0.5 V for tolerance, the overhead needs to be
increased to (8.121 V + 0.5 V) = 8.621 V to allow for an
undistorted on-hook transmission of a 1 Vrms meter
pulse into 200 Ω. This is done by applying voltage to
pin VOH.
VOH (V) = 6.0 V + 5 * VOVH (V)
8.621 V = 6 V + 5 * VOVH
VOVH = 0.5242 V
Thus, a nominal 0.5242 V is applied to pin VOVH to
increase the overhead.
Scan Mode
If the magnitude of the primary battery is greater than
51 V, the magnitude of the open loop tip-to-ring open
loop voltage is clamped typically between 44 V and
51 V. If the magnitude of the primary battery is less
than a nominal 51 V, the overhead voltage will track the
magnitude of the battery voltage, i.e., the magnitude of
the open circuit tip-to-ring voltage will be 4 V to 6 V less
than battery. In the scan mode, overhead is unaffected
by VOVH.
On-Hook Transmission Mode
If the magnitude of the primary battery is greater than
51 V, the magnitude of the open loop tip-to-ring open
loop voltage is clamped typically between 41 V and
49 V. If the magnitude of the primary battery is less
than a nominal 51 V, the overhead voltage will track the
magnitude of the battery voltage, i.e., the magnitude of
the open circuit tip-to-ring voltage will be 6 V to 8 V less
than battery. In the scan mode, overhead is unaffected
by VOVH.
Loop Range
The dc loop range is calculated using:
V BAT2 – V OH
- – 2RP – RDC
RL = -----------------------------------I LIMIT
VBAT2 is typically applied under off-hook conditions for
power conservation and SLIC thermal considerations.
The L9215 is intended for short-loop applications and,
therefore, will always be in current limit during off-hook
conditions. However, note that the ringing loop length
rather than the dc loop length, will be the factor to
determine operating loop length.
Battery Reversal Rate
The rate of battery reverse is controlled or ramped by
capacitors FB1 and FB2. A chart showing FB1 and FB2
values versus typical ramp time is given below. Leave
FB1 and FB2 open if it is not desired to ramp the rate of
battery reversal.
Table 20. FB1 and FB2 Values vs. Typical Ramp
Time
CFB1 and CFB2
Transition Time
0.01 µF
0.1 µF
0.22 µF
0.47 µF
1.0 µF
1.22 µF
1.3 µF
1.4 µF
1.6 µF
20 ms
220 ms
440 ms
900 ms
1.8 s
2.25 s
2.5 s
2.7 s
3.2 s
Ring Mode
In the ring mode, to maximize ringing loop length, the
overhead is decreased to the saturation of the tip ring
drive amplifiers, a nominal 4 V. The tip-to-ground voltage is 1 V, and the ring to VBAT1 voltage is 3 V. In the
ring mode, overhead is unaffected by VOVH.
During the ring mode, to conserve power the receive
input at RCVN/RCVP is deactivated. During the ring
mode, to conserve power, the ACC amplifier in the
26
Agere Systems Inc.
Data Sheet
September 2001
Supervision
The L9215 offers the loop closure and ring trip supervision functions. Internal to the device, the outputs of
these detectors are multiplexed into a single package
output, NSTAT. Additionally, a common-mode current
detector for tip or ring ground detection is included for
ground key applications.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
is input to the device’s RINGIN input. This signal is
amplified to produce the balanced power ring signal.
The user may supply a sine wave input, PWM input, or
a square wave to produce sinusoidal or trapezoidal
ringing at tip and ring.
Various crest factors are shown below for illustrative
purposes.
80
Loop Closure
VOLTS (V)
The loop closure has a fixed typical 10.5 mA on- to offhook threshold in the active mode and a fixed 11.5 mA
on- to off-hook threshold from the scan mode. In either
case, there is a 2 mA hysteresis with VCC = 5 V and a
1 mA hysteresis with VCC = 3.3 V.
60
20
0
–20
–40
–60
–80
0.00 0.04 0.08 0.12 0.16 0.20
0.02 0.06 0.10 0.14 0.18
TIME (s)
Ring Trip
The ring trip detector requires only a single-pole filter at
the input, minimizing external components. An R/C
combination of 383 kΩ and 0.1 µF, for a filter pole at
5.15 Hz, is recommended.
40
12-3346a (F)
Note: Slew rate = 5.65 V/ms; trise = tfall = 23 ms; pwidth = 2 ms;
period = 50 ms.
Figure 9. Ringing Waveform Crest Factor = 1.6
The ring trip threshold is internally fixed as a function of
battery voltage and is given by:
80
RT (mA) = 67 * {(0.0045 * VBAT1) + 0.317}
60
RT is ring trip current in mA.
VBAT1 is the magnitude of the ring battery in V.
There is a 6 mA to 8 mA hysteresis.
VOLTS (V)
where:
40
20
0
–20
–40
Tip or Ring Ground Detector
In the ground key or ground start applications, a common-mode current detector is used to indicate either a
tip- or ring-ground has occurred (ground key) or an offhook has occurred (ground start). The detection threshold is set by connecting a resistor from ICM to VCC.
170 x VCC/RICM (kΩ) = ITH (mA)
Additionally, a filter capacitor across RICM will set the
time constant of the detector. No hysteresis is associated with this detector.
–60
–80
0.00 0.04 0.08 0.12 0.16 0.20
0.02 0.06 0.10 0.14 0.18
TIME (s)
12-3347a (F)
Note: Slew rate = 10.83 V/ms; trise = tfall = 12 ms; pwidth = 13 ms;
period = 50 ms.
Figure 10. Ringing Waveform Crest Factor = 1.2
Voltage applied to the load may be increased by using
a filtered square wave input to produce a lower crest
factor trapezoidal power ring signal at tip and ring.
Power Ring
The device offers a ring mode, in which a balanced
power ring signal is provided to the tip/ring pair. During
the ring mode, a user-supplied low-voltage ring signal
Agere Systems Inc.
27
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring
Signal Output
The low-voltage sine wave input is applied to the L9215
at pin RINGIN. This signal should be ac-coupled
through 0.47 µF. During the ring mode, the signal at
RINGIN is amplified and presented to the subscriber
loop. The differential gain from RINGIN to tip and ring is
a nominal 55.
When the device enters the ring mode, the tip/ring
overhead set at OVH and the scan clamp circuit is disabled, allowing the voltage magnitude of the power ring
signal to be maximized. Additionally, in the ring mode,
the loop current limit is increased 2.5X the value set by
the VPROG voltage.
The magnitude of the power ring voltage will be a function of the gain of the ring amplifier, the high-voltage
battery, and the input signal at RING IN. The input range
of the signal at RINGIN is 0 V to Vcc. As the input voltage at RINGIN is increased, the magnitude of the power
ring voltage at tip and ring will increase linearly, per the
differential gain of 55, until the tip and ring drive amplifiers begin to saturate. Once the tip and ring amplifiers
reach saturation, further increases of the input signal
will cause clipping distortion of the power ring signal at
tip and ring. The ring signal will appear balanced on tip
and ring. That is, the power ring signal is applied to
both tip and ring, with the signal on tip 180° out of
phase from the signal on ring.
Data Sheet
September 2001
11. Thus, the total voltage swing is 52 V (60 V to 8 V)
for a 1 V input, which is approximately the differential
gain of the device. Note that the tip and ring power ring
signals will swing around VBATTERY divided by two. In
this case, there is a –70 V battery so tip and ring swing
around –34 V.
0
VRING
VTIP
–20
–40
–60
0.60 0.62
0.64
0.66
0.68
0.70
0.72
0.74
0.76
0.78 0.80
TIME
12-3573F
1.0
VRINGIN
0.5
0.0
–0.5
–1.0
0.60 0.62
0.64
0.66
0.68
0.70
0.72
0.74
0.76
0.78
0.80
TIME
12-3574F
Figure 11. Ring Mode Typical Operation
Figure 11 shows typical operation of the ring mode,
prior to saturation of the tip and ring drive amplifiers. A
–70 V battery is used with a 100 Ω loop and a 1 REN
load. The input signal is 1 V through a 0.47 µF capacitor at RINGIN, (the input circuit is shown in Figure 12).
This produces a voltage swing from –34 V to –60 V on
ring and from –8 V to –34 V on tip, as shown in Figure
28
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued)
It is recommended that the input level at RINGIN be adjusted so that the power ring signal at tip and ring is just at
the edge or slightly clipping. This gives maximum power transfer with minimal distortion of the sine wave. The tip
side will saturate at a nominal 1 V above ground. The ring side will saturate at a nominal 3 V above battery. The
input circuit for a sine wave along with waveforms to illustrate the tip and ring saturation is shown in Figure 12.
L9215
PT
GND
+1
RINGIN
1V
0.47 µF
VTIP
71 V
INPUT
27.5x
VRING
3V
VBAT
TR
–1
100 kΩ
VBAT = –75 V
12-3532.H(F)
Figure 12. RINGIN Operation
The point at which clipping of the power ring signal begins at tip and ring is a function of the battery voltage, the
input capacitor at RINGIN, and the input signal at RINGIN and Vcc. Typical characteristic conditions showing the
onset of clipping are given below.
Table 21. Onset of Power Ringing Clipping VCC = 5 V, Cinput = 0.47 µF
Input
VBAT1 (V)
–70.15
–68.06
–66.00
–64.08
–62.04
–60.05
T/R
Vrms (mV)
891
858
833
814
789
747
Vrms (V)
46.88
45.11
43.69
42.57
41.21
39.11
Gain
52.62
52.58
52.45
52.30
52.23
52.36
Table 22. Onset of Power Ringing Clipping VCC = 3.1 V, Cinput = 0.47 µF
Input
VBAT1 (V)
–70.12
–68.07
–66.06
–64.01
–62.00
–60.00
Agere Systems Inc.
T/R
Vrms (mV)
894
855
824
799
780
749
Vrms (V)
47.15
45.11
43.38
41.95
40.79
39.09
Gain
52.74
52.76
52.65
52.5
52.29
52.19
29
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued)
During nonring modes, the sinusoidal ringing waveform may be left on at RINGIN. Via the state table, the ring signal
will be removed from tip and ring even if the low-voltage input is still present at RINGIN. There are certain timing
considerations that should be made with respect to state changes which are detailed in the Switching Behavior of
L9215 Ringing SLIC Application Note.
PWM Input Signal and Sine Wave Power Ring Signal Output
A pulse-width modulated (PWM) signal may be used to provide the ringing input to RINGIN. The signal is applied
through a low-pass filter and ac-coupled into RINGIN as shown below. This approach gives a sine wave output at
tip and ring.
L9215/16
C2
R1
INPUT
RINGIN
C1
12-3578bF
Figure 13. L9215/16 Ringing Input Circuit Selection Table for Square Wave and PWM Inputs
Table 23. Signal and Component Selection Chart
VBAT
70 V
70 V
70 V
70 V
70 V
70 V
85 V
85 V
85 V
85 V
85 V
85 V
30
VCC
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
Input
5 V Square
3 V Square
10 kHz PWM 5 V
10 kHz PWM 3 V
90 kHz PWM 5 V
90 kHz PWM 3 V
5 V Square
3 V Square
10 kHz PWM 5 V
10 kHz PWM 3 V
90 kHz PWM 5 V
90 kHz PWM 3 V
R1
12 kΩ
7 kΩ
10 kΩ
10 kΩ
7 kΩ
7 kΩ
10 kΩ
7 kΩ
10 kΩ
4 kΩ
4 kΩ
4 kΩ
C1
1 µF
1 µF
0.22 µF
0.22 µF
0.1 µF
0.1 µF
1 µF
1 µF
0.22 µF
0.22 µF
0.1 µF
0.1 µF
C2
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
CF
1.3
1.3
sine
sine
sine
sine
1.3
1.3
sine
sine
sine
sine
Typical 5 REN Ringing Voltage RMS
48 V
49 V
42 V
42 V
42 V
42 V
59 V
51 V
51 V
47 V
51 V
49 V
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Supervision (continued)
5 V VCC Operation
Power Ring (continued)
A PWM signal was generated with an HP™ 8116
Function Generator modulated with a 20 Hz signal. The
optimal frequency used was 10 kHz. THE PWM signal
amplitude was 5.0 V (0 V to 5 V). This signal is shown
in Figure 15.
PWM Input Signal and Sine Wave Power Ring Signal Output (continued)
Modulation waveforms showing PWM are in Figure 14
below.
12-3575F
Figure 15. 5 V PWM Signal Amplitude
12-3381(F)
A. Upper = Pwm Signal Centered at 10 kHz
Lower = Modulation Signal
This input produced 44.96 Vrms ringing signal on
tip/ring under open loop conditions and 42.0 Vrms was
delivered to 5 REN load. The ringing output on ring,
with VCC = 5 V, is shown in Figure 16.
12-3380(F)
B. Same as A but Expanded
Figure 14. Modulation Waveforms
1660
Notes:
The modulating 20 Hz signal THD was measured at 1.3 %.
The tip/ring 20 Hz signal THD was measured at 1 %.
VBAT1 = –70.6 V, VBAT2 = –26.5 V, VCC = 5.019 V.
PWM input 10 kHz, 5.0 Vp-p.
R1 = 10 kΩ, C1 = 0.22 µF, C2 = 0.47 µF.
Figure 16. Ringing Output on RING, with VCC = 5 V
Agere Systems Inc.
31
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Supervision (continued)
Power Ring (continued)
3.3 V VCC Operation
A PWM signal was generated with an HP 8116 Function Generator modulated with a 20 Hz signal. The optimal frequency used was 10 kHz. The PWM signal
amplitude was 3.10 V (0 V to 3.10 V). This input signal
is shown in Figure 17.
12-3571F
Figure 17. 3.3 V PWM Signal Amplitude
This produced 44.96 Vrms ringing signal on tip/ring
under open-loop conditions and 42.0 Vrms was delivered to 5 REN load. The ringing output on ring, with
VCC = 3.1 V is shown in Figure 18.
During nonring modes, the PWM waveform may be left
on at RINGIN. Via the state table, the ring signal will be
removed from tip and ring even if the low-voltage input
is still present at RINGIN. There are certain timing consideration that should be made with respect to state
changes which are detailed in the Switching Behavior
of L9215 Ringing SLIC Application Note.
Square Wave Input Signal and Trapezoidal Power
Ring Signal Output
A low-voltage square wave signal may be used to provide the ringing input to RINGIN. The signal is applied
through a low-pass filter and ac-coupled into RING IN as
shown in Figure 13 and Table 23. This approach gives
a trapezoidal wave output at tip and ring.
Using this approach, a trapezoidal waveform can be
achieved at tip and ring. This has the advantage of
increasing the power transfer to the load for a given
battery voltage, thus increasing the effective ringing
loop length as compared to a sine wave. The actual
crest factor achieved is a function of the magnitude of
the battery, the magnitude of the input voltage, frequency, and R1.
CH1
CH2
CH3
CH4
1660
Notes:
The modulating 20 Hz signal THD was measured at 1.3 %.
12-3572F
Notes:
CH1 = CMOS Input (5 V) at RINGIN.
The tip/ring 20 Hz signal THD was measured at 1 %.
CH2 = Filtered input at RINGIN.
VBAT1 = –70.6 V, VBAT2 = –26.5 V, VCC = 3.10 V.
CH3 = Tip.
PWM input 10 kHz, 3.1 Vp-p.
CH4 = Ring.
R1 = 10 kΩ, C1 = 0.22 µF, C2 = 0.47 µF.
R1 = 14 kΩ, C1 = 1.0 µF, C2 = 0.47 µF.
Figure 18. Ringing Output on RING, with VCC = 3.1 V
VBAT1 = –70 V, Vrms = 51 V, Vp-p = 67 V, frequency = 20 Hz, crest
factor = 1.3.
Figure 19. Square Wave Input Signal and Trapezoidal Power Ring Signal Output
32
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Supervision (continued)
Power Ring (continued)
Square Wave Input Signal and Trapezoidal Power Ring Signal Output (continued)
The following charts are meant to give some guidance to the relationship between crest factor, battery voltage, and
R1 value.
1.36
1.35
1.34
1.33
CF
1.32
1.31
1.3
1.29
1.28
1.27
1.26
58
60
62
64
66
68
70
72
BAT V
12-3576F
Figure 20. Crest Factor vs. Battery Voltage
1.5
1.45
CF
1.4
1.35
1.3
1.25
10
10.5
11
11.5
12
R (kΩ)
12.5
13
13.5
14
12-3577F
Figure 21. Crest Factor vs. R (kΩ)
During nonring modes, the square wave input may be left on or removed from RINGIN. Via the state table, the ring
signal will be removed from tip and ring even if the low-voltage input is still present at RINGIN. However, removing
the waveform has certain advantages in terms of the timing of state. These advantages are detailed in the Switching Behavior of L9215 Ringing SLIC Application Note.
Agere Systems Inc.
33
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Periodic Pulse Metering (PPM)
Codec Types
Periodic pulse metering (PPM), also referred to as teletax (TTX), is input to the PPMIN input of the L9215.
Upon application of appropriate logic control, this signal is presented to the tip/ring subscriber loop. The
state of the L9215 should be changed while applying
PPM signals during the quiet interval of the PPM
cadence. The L9215 assumes that a shaped PPM signal is applied to the PPMIN input.
At this point in the design, the codec needs to be
selected. The interface network between the SLIC and
codec can then be designed. Below is a brief codec
feature summary.
PPM input signals may be a maximum 1.25 V at
PPMIN. The gain from PPMIN to tip/ring is 6 dB. Thus,
for 1.0 Vrms at tip and ring, apply a 0.50 Vrms signal at
PPMIN. The PPM signal should be ac coupled to
PPMIN through a 10 nF capacitor.
When applied to tip and ring, the PPM signal will also
be returned through the SLIC and will appear at the
SLIC VITR output. The concern is that this high-voltage
signal can overload an internal SLIC amplifier or the
codec input and cause distortion of the (desired) ac
signal. Because the L9215 is intended for short dc
loops, the assumption is that low meter pulse signals
are sufficient. The maximum allowed PPM current at
the 200 Ω ac meter pulse load to avoid saturation of the
device’s internal AAC amplifier is 3 mArms. This signal
level is sufficient to provide a minimum 200 mVrms to
the 200 Ω PPM load under maximum specified dc loop
conditions. Above 3 mArms PPM current, external
meter pulse rejection may be required. If on-hook
transmission of PPM is required, sufficient overhead to
accommodate on-hook transmission must be programmed by the user at the OVH input.
ac Applications
ac Parameters
There are four key ac design parameters. Termination
impedance is the impedance looking into the 2-wire
port of the line card. It is set to match the impedance of
the telephone loop in order to minimize echo return to
the telephone set. Transmit gain is measured from the
2-wire port to the PCM highway, while receive gain is
done from the PCM highway to the transmit port.
Transmit and receive gains may be specified in terms
of an actual gain, or in terms of a transmission level
point (TLP), that is the actual ac transmission level in
dBm. Finally, the hybrid balance network cancels the
unwanted amount of the receive signal that appears at
the transmit port.
34
First-Generation Codecs
These perform the basic filtering, A/D (transmit), D/A
(receive), and µ-law/A-law companding. They all have
an op amp in front of the A/D converter for transmit
gain setting and hybrid balance (cancellation at the
summing node). Depending on the type, some have
differential analog input stages, differential analog output stages, 5 V only or ±5 V operation, and µ-law/A-law
selectability. These are available in single and quad
designs. This type of codec requires continuous time
analog filtering via external resistor/capacitor networks
to set the ac design parameters. An example of this
type of codec is the Agere T7504 quad 5 V only codec.
This type of codec tends to be the most economical in
terms of piece part price, but tends to require more
external components than a third-generation codec.
Further ac parameters are fixed by the external R/C
network so software control of ac parameters is difficult.
Third-Generation Codecs
This class of devices includes all ac parameters set
digitally under microprocessor control. Depending on
the device, it may or may not have data control latches.
Additional functionality sometimes offered includes
tone plant generation and reception, PPM generation,
test algorithms, and echo cancellation. Again, this type
of codec may be 3.3 V, 5 V only, or ±5 V operation, single quad or 16 channel, and µ-law/A-law or 16-bit linear
coding selectable. Examples of this type of codec are
the Agere T8535/6 (5 V only, quad, standard features),
T8537/8 (3.3 V only, quad, standard features), T8533/4
(5 V only, quad with echo cancellation), and the
T8531/32 (5 V only 16 channel).
ac Interface Network
The ac interface network between the L9215 and the
codec will vary depending on the codec selected. With
a first-generation codec, the interface between the
L9215 and codec actually sets the ac parameters. With
a third-generation codec, all ac parameters are set digitally, internal to the codec; thus, the interface between
Agere Systems Inc.
Data Sheet
September 2001
ac Applications (continued)
ac Interface Network (continued)
the L9215 and this type of codec is designed to avoid
overload at the codec input in the transmit direction
and to optimize signal to noise ratio (S/N) in the receive
direction.
Because the design requirements are very different
with a first- or third-generation codec, the L9215 is
offered with two different receive gains. Each receive
gain was chosen to optimize, in terms of external components required, the ac interface between the L9215
and codec.
With a first-generation codec, the termination impedance is set by providing gain shaping through a feedback network from the SLIC VITR output to the SLIC
RCVN/RCVP inputs. The L9215 provides a transconductance from T/R to VITR in the transmit direction and
a single-ended to differential gain from either RCVN or
RCVP to T/R in the receive direction. Assuming a short
from VITR to RCVN or RCVP, the maximum impedance that is seen looking into the SLIC is the product of
the SLIC transconductance times the SLIC receive
gain, plus the protection resistors. The various specified termination impedance can range over the voiceband as low as 300 Ω up to over 1000 Ω. Thus, if the
SLIC gains are too low, it will be impossible to synthesize the higher termination impedances. Further, the
termination that is achieved will be far less than what is
calculated by assuming a short for SLIC output to SLIC
input. In the receive direction, in order to control echo,
the gain is typically a loss, which requires a loss network at the SLIC RCVN/RCVP inputs, which will
reduce the amount of gain that is available for termination impedance. For this reason, a high-gain SLIC is
required with a first-generation codec.
With a third-generation codec, the line card designer
has different concerns. To design the ac interface, the
designer must first decide upon all termination impedance, hybrid balances, and transmission-level point
(TLP) requirements that the line card must meet. In the
transmit direction, the only concern is that the SLIC
does not provide a signal that is too hot and overloads
the codec input. Thus, for the highest TLP that is being
designed to, given the SLIC gain, the designer, as a
function of voiceband frequency, must ensure the
codec is not overloaded. With a given TLP and a given
SLIC gain, if the signal will cause a codec overload, the
designer must insert some sort of loss, typically a resistor divider, between the SLIC output and codec input.
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Note also that some third-generation codecs require
the designer to provide an inherent resistive termination via external networks. The codec will then provide
gain shaping, as a function of frequency, to meet the
return loss requirements. This feedback will increase
the signal at the codec input and increase the likelihood that a resistor divider is needed in the transmit
direction. Further stability issues may add external
components or excessive ground plane requirements
to the design.
In the receive direction, the issue is to optimize the
S/N. Again, the designer must consider all the considered TLPs. The idea is, for all desired TLPs, to run the
codec at or as close as possible to its maximum output
signal, to optimize the S/N. Remember, noise floor is
constant, so the hotter the signal from the codec, the
better the S/N. The problem is if the codec is feeding a
high-gain SLIC, either an external resistor divider is
needed to knock the gain down to meet the TLP
requirements, or the codec is not operated near maximum signal levels, thus compromising the S/N.
Thus, it appears that the solution is to have a SLIC with
a low gain, especially in the receive direction. This will
allow the codec to operate near its maximum output
signal (to optimize S/N), without an external resistor
divider (to minimize cost).
To meet the unique requirements of both type of
codecs, the L9215 offers two receive gain choices.
These receive gains are mask-programmable at the
factory and are offered as two different code variations.
For interface with a first-generation codec, the L9215 is
offered with a receive gain of 8. For interface with a
third-generation codec, the L9215 is offered with a
receive gain of 2. In either case, the transconductance
in the transmit direction or the transmit gain is 300 Ω.
This selection of receive gain gives the designer the
flexibility to maximize performance and minimize external components, regardless of the type of codec chosen.
Design Examples
First-Generation Codec ac Interface Network—
Resistive Termination
The following reference circuit shows the complete
SLIC schematic for interface to the Agere T7504 firstgeneration codec for a resistive termination impedance. For this example, the ac interface was designed
for a 600 Ω resistive termination and hybrid balance
with transmit gain and receive gain set to 0 dBm. For
illustration purposes, no PPM injection was assumed in
this example. This implies use of the default overhead
voltage and no components for meter pulse rejection.
35
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Receive Gain:
Design Examples (continued)
V T/R
g rcv = -----------V FR
First-Generation Codec ac Interface Network—
Resistive Termination (continued)
g rcv =
8
-----------------------------------------------------------------R CV
R R C V 
ZT 
1 + R
 ----------- + ------------  1 + ---------
R T1
This is a lower feature application example and uses
single battery operation, fixed overhead, current limit,
and loop closure threshold.
RGP
Z T/R
Transmit Gain:
Resistor RGN is optional. It compensates for any mismatch of input bias voltage at the RCVN/RCVP inputs.
If it is not used, there may be a slight offset at tip and
ring due to mismatch of input bias voltage at the
RCVN/RCVP inputs. It is very common to simply tie
RCVN directly to ground in this particular mode of operation. If used, to calculate RGN, the impedance from
RCVN to ac ground should equal the impedance from
RCVP to ac ground.
g tx =
gtx =
V GSX
----------V T/R
–-------R X 300
- × --------R T2
Z T/R
Hybrid Balance:
RX
hbal = 20log  ------------ – g tx × g rcv
R HB
Example 1, Real Termination
The following design equations refer to the circuit in
Figure 22. Use these to synthesize real termination
impedance.
Termination Impedance:
V GSX
hbal = 20log  ---------------
V FR
To optimize the hybrid balance, the sum of the currents
at the VFX input of the codec op amp should be set to
0. The expression for ZHB becomes the following:
V T/R
zT = -----------– I T/R
zT
R H B ( kΩ ) =
2400
= 50 Ω + 2 R P + ----------------------------------RT1
R T1
1 + --------- + -----------R G P R R CV
RX
-----------------g tx × g rcv
RX
VGSX
–0.300 V/mA
RT2
VFXIN
VITR
ZT/R
VS
ZT
RP TIP
IT/R
+
VT/R
–
RP
RING
18 Ω
–
–
AV = 1
+
AV = 4
+
CURRENT
SENSE
RT1
RHB1
RCVN
RRCV
RCVP
VFXIP
–
+
+2.4 V
VFR
RGP
+
AV = –1
18 Ω
–
L9215
1/4 T7504 CODEC
12-2554.V (F)
Figure 22. ac Equivalent Circuit
36
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued)
VBAT1
DBAT1
VBAT2 VCC
CBAT1
CBAT2
CCC
0.1 µF
0.1 µF
0.1 µF
VBAT1
BGND VBAT2 VCC
AGND
CRT
0.1 µF
RRT
383 kΩ
FUSIBLE OR PTC
30 Ω
VBAT1
RTFLT
ICM TRGDET
ITR
ground key
not used
RGX
4750 Ω
RX
VTX
DCOUT
CTX
0.1 µF
PR
FUSIBLE OR PTC
GSX
TXI
RT6
49.9 kΩ
AGERE
L7591
30 Ω
100 kΩ
VITR
L9215A
PT
RT3
69.8 kΩ
OVH (DEFAULT OVERHEAD)
RRCV
60.4 kΩ
RCVP
RVPROG
23.7 kΩ
RGP
26.7 kΩ
VPROG (ILIMIT = 25 mA)
RVREF
80.6 kΩ
rate of battery
reversal not
ramped
RCVN
not
used
CF2 FB1 FB2 NSTAT BR B2 B1 B0 RINGIN PPMIN
VREF
CF1
CF1
0.22 µF
CF2
0.1 µF
C2
0.47 µF
C1
1.0 µF
VREF
CC1
0.1 µF
RHB1 VFXIN
100 kΩ
CC2
0.1 µF
–
DX
+
PCM
HIGHWAY
+2.4 V
VFRO
DR
FSE
FSEP
MCLK
SYNC
AND
CLOCK
ASEL
CONTROL
INPUTS
RN2
17.65 kΩ
VREF
1/4 T7504
CODEC
R1
12 kΩ
Figure 23. Agere T7504 First-Generation Codec Resistive Termination; Nonmeter Pulse Application
Agere Systems Inc.
37
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued)
Table 24. Parts List L9215; Agere T7504 First-Generation Codec Resistive Termination; Nonmeter Pulse
Application
Name
Value
Fault Protection
RPT
30 Ω
RPR
30 Ω
Protector
Agere L7591
Power Supply
CBAT1
0.1 µF
CBAT2
0.1 µF
DBAT1
1N4004
CCC
0.1 µF
CF1
0.22 µF
CF2
0.1 µF
dc Profile
RVPROG
23.7 kΩ
RVREF
80.6 kΩ
Ring/Ring Trip
C1
1.0 µF
C2
0.47 µF
R1
12 kΩ
CRT
0.1 µF
RRT
383 kΩ
ac Interface
RGX
4750 Ω
CTX
0.1 µF
CC1
0.1 µF
CC2
0.1 µF
RT3
69.8 kΩ
Tolerance
1%
1%
—
Rating
Function
Fusible or PTC Protection resistor.
Fusible or PTC Protection resistor.
—
Secondary protection.
20%
20%
—
20%
20%
20%
100 V
50 V
—
10 V
100 V
100 V
VBAT filter capacitor.
VBAT filter capacitor. |VBAT2| < |VBAT1|.
Reverse current.
VCC filter capacitor.
Filter capacitor.
Filter capacitor.
1%
1%
1/16 W
1/16 W
With RVREF fixes dc current limit.
With RVPROG fixes dc current limit.
20%
20%
1%
20%
1%
10 V
10 V
1/16 W
10 V
1/16 W
Ring filter for square wave.
ac-couple input ring signal.
Ring filter for square wave.
Ring trip filter capacitor.
Ring trip filter resistor.
1%
20%
20%
20%
1%
1/16 W
10 V
10 V
10 V
1/16 W
Sets T/R to VITR transconductance.
ac/dc separation.
dc blocking capacitor.
dc blocking capacitor.
With RGP and RRCV, sets termination
impedance and receive gain.
With RX, sets transmit gain.
With RT6, sets transmit gain.
With RX, sets hybrid balance.
With RGP and RT3, sets termination
impedance and receive gain.
With RRCV and RT3, sets termination
impedance and receive gain.
Optional. Compensates for input offset at RCVN/RCVP.
RT6
RX
RHB1
RRCV
49.9 kΩ
100 kΩ
100 kΩ
60.4 kΩ
1%
1%
1%
1%
1/16 W
1/16 W
1/16 W
1/16 W
RGP
26.7 kΩ
1%
1/16 W
RGN Optional
17.6 kΩ
1%
1/16 W
Notes:
Termination impedance = 600 Ω.
Hybrid balance = 600 Ω.
T x = 0 dBm Rx = 0 dBm.
38
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
ac Interface Using First-Generation Codec
Design Examples (continued)
RGX/RTGS/CGS (ZTG): these components give gain shaping to get good gain flatness. These components are a
scaled version of the specified complex termination
impedance.
First-Generation Codec ac Interface Network—
Complex Termination
The following reference circuit shows the complete
SLIC schematic for interface to the Agere T7504 firstgeneration codec for the German complex termination
impedance. For this example, the ac interface was
designed for a 220 Ω + (820 Ω || 115 nF) complex termination and hybrid balance with transmit gain and
receive gain set to 0 dBm. For illustration purposes,
1 Vrms PPM injection was assumed in this example.
This implies the overhead voltage is increased to
7.24 V and no meter pulse rejection is required. Also,
this example illustrates the device using fixed overhead
and current limit.
Complex Termination Impedance Design Example
The gain shaping necessary for a complex termination
impedance may be done by shaping across the AX
amplifier at nodes ITR and VTX.
Complex termination is specified in the form:
Note for pure (600 Ω) resistive terminations, components RTGS and CGS are not used. Resistor RGX is used
and is still 4750 Ω.
RX/RT6: with other components set, the transmit gain
(for complex and resistive terminations) RX and RT6 are
varied to give specified transmit gain.
RT3/RRCV/RGP: for both complex and resistive terminations, the ratio of these resistors sets the receive gain.
For resistive terminations, the ratio of these resistors
sets the return loss characteristic. For complex terminations, the ratio of these resistors sets the low-frequency return loss characteristic.
CN/RN1/RN2: for complex terminations, these components provide high-frequency compensation to the
return loss characteristic.
For resistive terminations, these components are not
used and RCVN is connected to ground via a resistor.
RHB: sets hybrid balance for all terminations.
R2
Set ZTG—Gain Shaping
R1
C
5-6396(F)
To work with this application, convert termination to the
form:
R1´
ZTG = RGX || RTGS + CGS which is a scaled version of
ZT/R (the specified termination resistance) in the
R1´ || R2´ + C´ form.
RGX must be 4750 Ω to set SLIC transconductance to
300 V/A.
RGX = 4750 Ω
At dc, CGS and C´ are open.
R 2´
RGX = M x R1´
C´
5-6398(F)
where:
R1´ = R1 + R2
R1
R2´ = ------- (R1 + R2)
R2
2
R2
C´ =  --------------------- C
R1 + R2
Agere Systems Inc.
where M is the scale factor.
4750
M = -------------R1′
It can be shown:
RTGS = M x R2´
and
CTGS =
C′
-----M
39
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Set ZTG—Gain Shaping (continued)
RTGS
CGS
Rx
–IT/R
318.25
RGX = 4750 Ω
0.1 µF
RT6
–
+
20
VTX
TXI
VITR
CODEC
OP AMP
CN
RT3
RN1
RHB
RCVN
CODEC
OUTPUT
DRIVE
AMP
RRCV
RCVP
RN2
RGP
5-6400.P (F)
Figure 24. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown)
TX (specified[dB]) is the specified transmit gain. 600 Ω is the
impedance at the PCM, and R EQ is the impedance at
Transmit Gain
Transmit gain will be specified as a gain from T/R to
PCM, TX (dB). Since PCM is referenced to 600 Ω and
assumed to be 0 dB, and in the case of T/R being referenced to some complex impedance other than 600 Ω
resistive, the effects of the impedance transformation
must be taken into account.
Again, specified complex termination impedance at T/R
is of the form:
600
tip and ring. 20log ----------- represents the power
R EQ
loss/gain due to the impedance transformation.
Note in the case of a 600 Ω pure resistive termination
600
600
at T/R 20log ----------- = 20log ---------- = 0.
R EQ
600
Thus, there is no power loss/gain due to impedance
transformation and TX (dB) = TX (specified[dB]).
R2
Finally, convert TX (dB) to a ratio, gTX:
R1
TX (dB) = 20log gTX
C
5-6396(F)
First, calculate the equivalent resistance of this network
at the midband frequency of 1000 Hz.
REQ =
2
( 2 πf ) 2 C 1 2 R 1 R 2 2 + R 1 + R 2 2 
2 πf R 2 2 C 1
 ---------------------------------------------------------------------------- + ---------------------------------------------------
2
2




2
2
2
2
1 + ( 2 πf ) R 2 C 1
1 + ( 2 πf ) R 2 C 1
The ratio of RX/RT6 is used to set the transmit gain:
RX
R T6
318.25
20
---------- = gTX • ------------------
1
• ---- with a quad Agere codec
M
such as T7504:
RX < 200 kΩ
Using REQ, calculate the desired transmit gain, taking
into account the impedance transformation:
TX (dB) = TX (specified[dB]) + 20log
40
600
----------R EQ
Agere Systems Inc.
Data Sheet
September 2001
L9215A/G
Short-Loop Sine Wave Ringing SLIC
ac Applications (continued)
Hybrid Balance
Design Examples (continued)
Set the hybrid cancellation via RHB.
Receive Gain
RX
RHB = ------------------------------g RCV × g TX
Ratios of RRCV, RT3, and RGP will set both the low-frequency termination and receive gain for the complex
case. In the complex case, additional high-frequency
compensation, via CN, RN1, and RN2, is needed for the
return loss characteristic. For resistive termination, CN,
RN1, and RN2 are not used and RCVN is tied to ground
via a resistor.
Determine the receive gain, gRCV, taking into account
the impedance transformation in a manner similar to
transmit gain.
R EQ
RX (dB) = RX (specified[dB]) + 20log ----------600
RX (dB) = 20log gRCV
Then:
4
gRCV = -----------------------------------------------R
RCV R RCV
1 + --------------- + --------------R T3
R GP
and low-frequency termination
2400
ZTER(low) = -------------------------------------------- + 2RP + 50 Ω
R T3 R T3
1 + ------------ + --------------R GP R RCV
If a 5 V only codec such as the Agere T7504 is used,
dc blocking capacitors must be added as shown in
Figure 25. This is because the codec is referenced to
2.5 V and the SLIC to ground—with the ac coupling, a
dc bias at T/R is eliminated and power associated with
this bias is not consumed.
Typically, values of 0.1 µF to 0.47 µF capacitors are
used for dc blocking. The addition of blocking capacitors will cause a shift in the return loss and hybrid balance frequency response toward higher frequencies,
degrading the lower-frequency response. The lower
the value of the blocking capacitor, the more pronounced the effect is, but the cost of the capacitor is
lower. It may be necessary to scale resistor values
higher to compensate for the low-frequency response.
This effect is best evaluated via simulation. A PSPICE®
model for the L9215 is available.
Design equation calculations seldom yield standard
component values. Conversion from the calculated
value to standard value may have an effect on the ac
parameters. This effect should be evaluated and optimized via simulation.
ZTER(low) is the specified termination impedance assuming low frequency (C or C´ is open).
RP is the series protection resistor.
50 Ω is the typical internal feed resistance.
These two equations are best solved using a computer
spreadsheet.
Next, solve for the high-frequency return loss compensation circuit, CN, RN1, and RN2:
2R P
CNRN2 = ------------- CG RTGP
2400
2400 R TGS
RN1 = RN2 -------------  -------------- – 1
2R P  R TGP
There is an input offset voltage associated with nodes
RCVN and RCVP. To minimize the effect of mismatch
of this voltage at T/R, the equivalent resistance to ac
ground at RCVN should be approximately equal to that
at RCVP. Refer to Figure 25 (with dc blocking capacitors). To meet this requirement, RN2 = RGP || RT3.
Agere Systems Inc.
41
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Blocking Capacitors
RTGS
CGS
Rx
–IT/R
318.25
RGX = 4750 Ω
0.1 µF
RT6
CB1
20
VTX
TXI
VITR
–
+
CODEC
OP AMP
CN
RN1
RT3
RCVN
RHB
CB2
RCVP
RN2
RRCV
RGP
CODEC
OUTPUT
DRIVE
AMP
2.5 V
5-6401.M (F)
Figure 25. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex Termination Impedance
42
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Blocking Capacitors (continued)
VBAT2 VCC
VBAT1
DBAT1
CBAT1
CBAT2
CCC
0.1 µF
0.1 µF
0.1 µF
VBAT1
BGND
VBAT2 VCC
AGND
CRT
0.1 µF
RRT
383 kΩ
FUSIBLE
OR PTC
TRGDET
ITR
ground key
not used
RTFLT
RGX
4750 Ω
RTGS 1.74 kΩ
CGS 12 nF
VTX
DCOUT
CTX
0.1 µF
PR
30 Ω
VBAT1
ICM
RX
115 kΩ
TXI
GSX
AGERE
L7591
30 Ω
CC1
RT6
40.6 kΩ 0.1 µF
VITR
L9215A
PT
FUSIBLE
OR PTC
CN
120 pF
RT3
R HB1
49.9 kΩ 113 kΩ
RRCV
RVREF
80.6 kΩ
OVH
RCVP
ROVH
10 kΩ
rate of battery
reversal not
ramped
VREF
CF1
CF2 FB1 FB2 NSTAT BR B2 B1 B0 RINGIN
CF1
0.22 µF
CF2
0.1 µF
FROM/TO CONTROL
RING
59.0 kΩ
RCVN
RN1
127
kΩ
PPMIN
RN2 VREF
47.5 kΩ
VPROG (ILIMIT = 25 mA)
RVPROG
20 kΩ
VFXIN
CRING
0.47 µF
CPPM
10 nF
RGP
54.9 kΩ
CC2
0.1 µF
–
DX
+
VFRO
DR
FSE
FSEP
MCLK
SYNC
AND
CLOCK
ASEL
CONTRO
INPUTS
VREF
PPM
0.5 VRMS
PCM
HIGHWAY
+2.4 V
1/4 T7504
CODEC
Figure 26. Agere T7504 First-Generation Codec Complex Termination; Meter Pulse Application
Agere Systems Inc.
43
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Applications (continued)
Design Examples (continued)
Blocking Capacitors (continued)
Table 25. Parts List L9215; Agere T7504 First-Generation Codec Complex Termination; Meter Pulse
Application
Termination impedance = 220 Ω + (820 Ω || 115 nF), hybrid balance = 220 Ω + (820 Ω || 115 nF) Tx = 0 dBm,
Rx = 0 dBm.
Name
Value Tolerance
Rating
Fault Protection
RPT
30 Ω
1%
Fusible or PTC
RPR
30 Ω
1%
Fusible or PTC
Protector
Agere
—
—
L7591
Power Supply
CBAT1
0.1 µF
20%
100 V
CBAT2
0.1 µF
20%
50 V
DBAT1
1N4004
—
—
CCC
0.1 µF
20%
10 V
CF1
0.22 µF
20%
100 V
CF2
0.1 µF
20%
100 V
dc Profile
RVPROG
20 kΩ
1%
1/16 W
RVOVH
10 kΩ
1%
1/16 W
RVREF
80.6 kΩ
1%
1/16 W
Ring/Ring Trip
CRING
0.47 µF
20%
10 V
CRT
0.1 µF
20%
10 V
RRT
383 kΩ
1%
1/16 W
PPM
CPPM
10 nF
20%
10 V
ac Interface
RGX
4750 Ω
1%
1/16 W
RTGS
1.74 kΩ
1%
1/16 W
CGS
12 nF
5%
10 V
CTX
0.1 µF
20%
10 V
CC1
0.1 µF
20%
10 V
CC2
0.1 µF
20%
10 V
RT3
49.9 kΩ
1%
1/16 W
RT6
RX
RHB1
RRCV
RGP
40.2 kΩ
115 kΩ
113 kΩ
59.0 kΩ
54.9 kΩ
1%
1%
1%
1%
1%
1/16 W
1/16 W
1/16 W
1/16 W
1/16 W
CN
RN1
RN2
120 pF
127 kΩ
47.5 kΩ
20%
1%
1%
10 V
1/16 W
1/16 W
44
Function
Protection resistor.
Protection resistor.
Secondary protection.
VBAT filter capacitor.
VBAT filter capacitor. |VBAT2| < |VBAT1|.
Reverse current.
VCC filter capacitor.
Filter capacitor.
Filter capacitor.
With RVREF fixes dc current limit.
With RVREF fixes overhead voltage.
With RVPROG fixes dc current limit/overhead.
ac-couple input ring signal.
Ring trip filter capacitor.
Ring trip filter resistor.
ac-couple PPM input.
Sets T/R to VITR transconductance.
Gain shaping for complex termination.
Gain shaping for complex termination.
ac/dc separation.
dc blocking capacitor.
dc blocking capacitor.
With RGP and RRCV, sets termination impedance and receive
gain.
With RX, sets transmit gain.
With RT6, sets transmit gain.
With RX, sets hybrid balance.
With RGP and RT3, sets termination impedance and receive gain.
With RRCV and RT3, sets termination impedance and receive
gain.
High frequency compensation.
High frequency compensation.
High frequency compensation, compensate for dc offset at
RCVP/RCVN.
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network—Complex Termination
The following reference circuit shows the complete SLIC schematic for interface to the Agere T8536 third-generation codec. All ac parameters are programmed by the T8536. Note this codec differentiates itself in that no external
components are required in the ac interface to provide a dc termination impedance or for stability. For illustration
purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used. Also, this
example illustrates the device using programmable overhead and current limit. Please see the T8535/6 data sheet
for information on coefficient programming.
VBAT1
DBAT1
0.1 µF
RRT
383 kΩ
CBAT2
CCC
0.1 µF
0.1 µF
0.1 µF
BGND
VBAT2 VCC
AGND
ITR
RTFLT
RGX
4750 Ω
VTX
DCOUT
FUSIBLE OR PTC
CTX
0.1 µF
PR
50 Ω
VBAT2
CBAT1
VBAT1
CRT
VBAT2 VCC
TXI
CC1
0.1 µF
AGERE
L7591
50 Ω
VFXI
VITR
PT
DX0
RCIN
L9215G
20 MΩ
DR0
FUSIBLE OR PTC
RCVP
VFROP
RCVN
VFRON
OVH
CONTROL
VOLTAGE
DX1
DR1
VPROG
1/4
T8536/8
FS
VREF
CF1
CF2
NSTAT BR B2 B1 B0
RINGIN
PPMIN
CF1
0.22 µF
CF2
0.1 µF
FROM/TO T8536
CONTROL LATCHES
CRING
0.47 µF
CPPM
10 nF
PPM
0.5 Vrms
PCM
HIGHWAY
B2
SLIC4a
B1
SLIC3a
B0
SLIC2a
BR
SLIC1a
NSTAT
SLIC0a
BCLK
SYNC
AND
CLOCK
DGND
VDD
VDD
Figure 27. Third-Generation Codec ac Interface Network; Complex Termination
Agere Systems Inc.
45
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network—Complex Termination (continued)
Table 26. Parts List L9215; Agere T8536 Third-Generation Codec Meter Pulse Application ac and dc
Parameters; Fully Programmable
Name
Value
Fault Protection
RPT
50 Ω
RPR
50 Ω
Protector
Agere L7591
Power Supply
CBAT1
0.1 µF
CBAT2
0.1 µF
DBAT1
1N4004
CCC
0.1 µF
CF1
0.22 µF
CF2
0.1 µF
Ring/Ring Trip
CRING
0.47 µF
CRT
0.1 µF
RRT
383 kΩ
PPM
CPPM
10 nF
ac Interface
RGX
4750 Ω
RCIN
20 MΩ
CTX
0.1 µF
CC1
0.1 µF
Tolerance
1%
1%
—
Rating
Function
Fusible or PTC Protection resistor*.
Fusible or PTC Protection resistor*.
—
Secondary protection.
20%
20%
—
20%
20%
20%
100 V
50 V
—
10 V
100 V
100 V
VBAT filter capacitor.
VBAT filter capacitor. |VBAT2| < |VBAT1|.
Reverse current.
VCC filter capacitor.
Filter capacitor.
Filter capacitor.
20%
20%
1%
10 V
10 V
1/16 W
ac-couple input ring signal.
Ring trip filter capacitor.
Ring trip filter resistor.
20%
10 V
1%
5%
20%
20%
1/16 W
1/16 W
10 V
10 V
ac-couple PPM input.
Sets T/R to VITR transconductance.
dc Bias
ac/dc separation.
dc blocking capacitor.
* For loop stability, increase to 50 Ω minimum if synthesizing 900 Ω or 900 Ω + 2.16 µF termination impedance.
46
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Outline Diagrams
32-Pin PLCC
Dimensions are in millimeters.
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Sales Representative.
12.446 ± 0.127
11.430 ± 0.076
4
PIN #1 IDENTIFIER
ZONE
1
30
5
29
13.970
± 0.076
14.986
± 0.127
13
21
14
20
3.175/3.556
1.27 TYP
0.38 MIN
TYP
SEATING PLANE
0.10
0.330/0.533
5-3813F
Agere Systems Inc.
47
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Outline Diagrams (continued)
48-Pin MLCC
Dimensions are in millimeters.
Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Sales Representative.
The exposed pad on the bottom of the package will be at VBAT1 potential.
C
7.00
C
CL
3.50
6.75
3.375
0.50 BSC
1
2
3
DETAIL A
VIEW FOR EVEN TERMINAL/SIDE
6.75
PIN #1
IDENTIFIER ZONE
7.00
0.18/0.30
0.00/0.05
SECTION C–C
DETAIL A
0.65/0.80
1.00 MAX
12°
SEATING PLANE
0.20 REF
0.08
0.01/0.05
11 SPACES @
0.50 = 5.50
0.24/0.60
0.18/0.30
0.24/0.60
5.10
± 0.15
3
2
1
0.30/0.45
EXPOSED PAD
0.50 BSC
0195mod
48
Agere Systems Inc.
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Outline Diagrams (continued)
48-Pin MLCC, JEDEC MO-220 VKKD-2
Dimensions are in millimeters.
Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Sales Representative.
The exposed pad on the bottom of the package will be at VBAT1 potential.
7.00
CL
3.50
PIN #1
IDENTIFIER ZONE
0.50 BSC
3.50
DETAIL A
VIEW FOR EVEN TERMINAL/SIDE
INDEX AREA
(7.00/2 x 7.00/2)
7.00
0.18
0.23
0.18
TOP VIEW
0.23
1.00 MAX
SEATING PLANE
0.20 REF
SIDE VIEW
0.08
DETAIL B
0.02/0.05
11 SPACES @
0.50 = 5.50
DETAIL A
0.18/0.30
0.30/0.50
2.50/2.625
5.00/5.25
3
2
1
EXPOSED PAD
0.50 BSC
DETAIL B
BOTTOM VIEW
Agere Systems Inc.
49
L9215A/G
Short-Loop Sine Wave Ringing SLIC
Data Sheet
September 2001
Ordering Information
Device Part No.
LUCL9215AAU-D
LUCL9215AAU-DT
LUCL9215GAU-D
LUCL9215GAU-DT
LUCL9215ARG-D
LUCL9215GRG-D
Description
SLIC Gain = 8
SLIC Gain = 8
SLIC Gain = 2
SLIC Gain = 2
SLIC Gain = 8
SLIC Gain = 2
Package
32-Pin PLCC Dry Bag
32-Pin PLCC Tape & Reel
32-Pin PLCC Dry Bag
32-Pin PLCC Tape & Reel
48-Pin MLCC Dry Bag
48-Pin MLCC Dry Bag
Comcode
108327214
108327222
108417932
108417940
108955451
108955444
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
PSPICE is a registered trademark of MicroSim Corporation.
Telcordia Technologies is a trademark of Bell Communications Research, Inc.
HP is a trademark of Hewlett-Packard Company.
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
[email protected]
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA:
Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)
EUROPE:
Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liab ility is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
September 2001
DS01-299ALC (Replaces DS01-104ALC)