Catalyst CAT24FC65JI-1.8TE13 64k-bit i2c serial cmos eeprom with partial array write protection Datasheet

CAT24FC65, CAT24FC66
64K-Bit I2C Serial CMOS EEPROM with Partial Array Write Protection
FEATURES
■ Fast mode I2C bus compatible*
■ 5 ms max write cycle time
■ Max clock frequency:
■ Write protect feature
- 400KHz for VCC=2.5V to 5.5V
– Bottom 1/4 array protected when WP at VIH
(CAT24FC65)
– Top 1/4 array protected when WP at VIH
(CAT24FC66)
■ Schmitt trigger filtered inputs for
noise suppression
■ Low power CMOS technology
■ 1,000,000 program/erase cycles
■ 64-byte page write buffer
■ 100 year data retention
■ Self-timed write cycle with auto-clear
■ 8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC
■ Industrial and automotive temperature ranges
(EIAJ), 8-pin TSSOP and TDFN packages
DESCRIPTION
The CAT24FC65/66 is a 64k-bit Serial CMOS EEPROM
internally organized as 8,192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements.
PIN CONFIGURATION
DIP Package (P, L, GL)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
A1
A2
VSS
BLOCK DIAGRAM
TDFN Package (RD2, ZD2)
VCC
WP
SCL
SDA
A0 1
8 VCC
A1 2
7 WP
A2 3
6 SCL
VSS 4
5 SDA
EXTERNAL LOAD
1
2
3
8
7
6
VCC
WORD ADDRESS
BUFFERS
(Top View)
4
5
SDA
A0
SCL
SDA
A2
VSS
A1
1
2
3
4
8
7
6
5
COLUMN
DECODERS
512
TSSOP Package (U, Y, GY)
VCC
WP
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VSS
SOIC Package
(J, W, K, X, GW, GX)
A0
The CAT24FC65/66 features a 64-byte page write
buffer. The device operates via the I2C bus serial
interface and is available in 8-pin DIP, SOIC, TSSOP
and TDFN packages.
VCC
WP
SCL
SDA
START/STOP
LOGIC
XDEC
128
EEPROM
128X512
CONTROL
LOGIC
WP
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
+2.5V to +5.5V Power Supply
VSS
Ground
A0
A1
NC
No Connect
A2
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
SCL
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1047, Rev. H
CAT24FC65/66
ABSOLUTE MAXIMUM RATINGS*
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Temperature Under Bias ................. –55°C to +125°C
Lead Soldering Temperature (10 secs) ............ 300°C
Storage Temperature ....................... –65°C to +150°C
Output Short Circuit Current(2) ........................ 100mA
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
VCC with Respect to Ground ............... –2.0V to +7.0V
RELIABILITY CHARACTERISTICS (3)
Symbol
Parameter
Min
NEND
Endurance
1,000,000
Cycles/Byte
TDR
Data Retention
100
Years
VZAP
ESD Susceptibility
4000
Volts
Latch-up
100
mA
ILTH
(4)
Typ
Max
Units
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +5.5V, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC1
Power Supply Current - Read
ICC2
Power Supply Current - Write
ISB(5)
Max
Units
fSCL = 400 KHz
VCC=5V
400
µA
fSCL = 400KHz
VCC=5V
3
mA
Standby Current
VIN = GND or VCC
VCC=5V
1
µA
ILI
Input Leakage Current
VIN = GND to VCC
1
µA
ILO
Output Leakage Current
VOUT = GND to VCC
1
µA
VIL
Input Low Voltage
-0.5
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
0.4
V
Max
Units
VOL1
Output Low Voltage (VCC = +3.0V)
CIN
(3)
Typ
IOL = 3.0 mA
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
CI/O(3)
Min
Conditions
Min
Typ
Input/Output Capacitance (SDA)
VI/O = 0V
8
pF
Input Capacitance (SCL, WP, A0, A1)
VIN = 0V
6
pF
70
kΩ
ZWPL
WP Input Impedance
VIN ≤ 0.5V
5
ZWPH
WP Input Impedance
VIN>0.7VxVCC
500
kΩ
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby current (ISB ) = 10 µA max at extended temperature range.
Doc. No. 1047, Rev. H
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC65/66
A.C. CHARACTERISTICS
VCC = +2.5V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
VCC=2.5V - 5.5V
Min
FSCL
tAA
Clock Frequency
SCL Low to SDA Data Out and ACK Out
50
Max
Units
400
kHz
900
ns
tBUF(2)
Time the Bus Must be Free Before a New Transmission
Can Start
1300
ns
tHD:STA
Start Condition Hold Time
600
ns
tLOW
Clock Low Period
1300
ns
tHIGH
Clock High Period
600
ns
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
600
ns
tHD:DAT
Data In Hold Time
0
ns
tSU:DAT
Data In Setup Time
100
ns
tR(2)
SDA and SCL Rise Time
300
ns
tF(2)
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
600
ns
tDH
Data Out Hold Time
50
ns
tWR
Write Cycle Time
5
ms
tSP
Input Suppresssion (SDA, SCL)
50
ns
tSU;WP
WP Setup Time
600
ns
tHD;WP
WP Hold Time
1300
ns
Power-Up Timing (2)(3)
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power-Up to Read Operation
1
ms
tPUW
Power-Up to Write Operation
1
ms
Note:
(1) AC measurement conditions:
RL (connects to VCC): 0.3VCC to 0.7 VCC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 VCC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1047, Rev. H
CAT24FC65/66
SDA: Serial Data/Address
FUNCTIONAL DESCRIPTION
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
The CAT24FC65/66 supports the I 2 C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24FC65/66
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or receiver,
but the Master device controls which mode is activated.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
bottom/top (CAT24FC65/CAT24FC66)1/4 of memory
is write protected. When left floating, memory is
unprotected.
PIN DESCRIPTIONS
A0, A1, A2: Device Address Inputs
SCL: Serial Clock
These pins are hardwired or left connected. When
hardwired, up to eight CAT24FC65/66's may be
addressed on a single bus system. When the pins are
left unconnected, the default values are zero.
The serial clock input clocks all data transferred into or
out of the device.
Figure 1. Bus Timing
tF
tHIGH
tLOW
tR
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
ACK
BYTE n
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1047, Rev. H
STOP BIT
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC65/66
I2C BUS PROTOCOL
allow as many as eight devices on the same bus. These
bits must compare to their hardwired input pins. The last
bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT24FC65/66 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC65/66 then performs a Read or Write operation
depending on the state of the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC65/66 monitors
the SDA and SCL lines and will not respond until this
condition is met.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
The CAT24FC65/66 responds with an acknowledge
after receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after receiving
each 8-bit byte.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The CAT24FC65/66 uses the next three
bits as address bits. The address bits A2, A1 and A0
When the CAT24FC65/66 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24FC65/66 will continue to
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 5. Slave Address Bits
1
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
0
1
0
A2
5
A1
A0
R/W
Doc No. 1047, Rev. H
CAT24FC65/66
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
WRITE OPERATIONS
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24FC65/66 in a single write cycle.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24FC65/66. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24FC65/66 acknowledges
once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24FC65/66 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing the start condition followed by the slave address for
a write operation. If CAT24FC65/66 is still busy with the
write operation, no ACK will be returned. If
CAT24FC65/66 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Page Write
WRITE PROTECTION
The CAT24FC65/66 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24FC65/66 will respond with an
acknowledge, and internally increment the six low order
address bits by one. The high order bits remain unchanged.
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24FC65/66
will accept both slave and byte addresses, but the
memory location accessed is protected from programming by the device’s failure to send an acknowledge
after the first byte of data is received.
Figure 6. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8
A7–A0
S
A
C
K
* **
S
T
O
P
DATA
P
A
C
K
A
C
K
A
C
K
*=Don't Care Bit
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8
A7–A0
S
DATA
DATA n
S
T
O
P
DATA n+63
P
***
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
*=Don't Care Bit
Doc. No. 1047, Rev. H
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC65/66
The READ operation for the CAT24FC65/66 is initiated
in the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
slave address and byte addresses of the location it
wishes to read. After CAT24FC65/66 acknowledges,
the Master device sends the START condition and the
slave address again, this time with the R/W bit set to one.
The CAT24FC65/66 then responds with its acknowledge
and sends the 8-bit byte requested. The master device
does not send an acknowledge but will generate a STOP
condition.
Immediate/Current Address Read
Sequential Read
The CAT24FC65/66’s address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E=8,191),
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT24FC65/66
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24FC65/66 sends the initial 8bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC65/66 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
READ OPERATIONS
The data being transmitted from CAT24FC65/66 is
outputted sequentially with data from address N followed
by data from address N+1. The READ operation address
counter increments all of the CAT24FC65/66 address
bits so that the entire memory array can be read during
one operation. If more than E (where E=8,191) bytes are
read out, the counter will ‘wrap around’ and continue to
clock out data bytes.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
Figure 8. Immediate Address Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
DATA
S
P
A
C
K
SCL
SDA
8
N
O
A
C
K
9
8TH BIT
DATA OUT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
S
T
O
P
NO ACK
7
STOP
Doc No. 1047, Rev. H
CAT24FC65/66
Figure 9. Selective Read Timing
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
ADDRESS
S
T
A
R
T
BYTE ADDRESS
A15–A8
A7–A0
***
S
SLAVE
ADDRESS
S
T
O
P
DATA
S
A
C
K
A
C
K
P
A
C
K
A
C
K
N
O
A
C
K
*=Don't Care Bit
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 1047, Rev. H
8
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC65/66
ORDERING INFORMATION
Prefix
CAT
Optional
Company ID
Device #
24FC66
Product
Number
24FC65
24FC66
Suffix
J
I
Temperature Range
I = Industrial (-40˚C to 85˚C)
A = Automotive (-40˚C to 105˚C)
E = Extended (-40˚C to 125˚C)
Package
P: PDIP
K: SOIC, EIAJ
J: SOIC, JEDEC
U: TSSOP
RD2: TDFN
L: PDIP (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
X: SOIC, EIAJ (Lead-free, Halogen-free)
ZD2: TDFN (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GX: SOIC, EIAJ (Lead-free, Halogen-free, NiPdAu lead plating)
-1.8
REV-D
TE13
Tape & Reel
Die Revision
Operating Voltage
Blank: 2.5 to 5.5V
Notes:
(1) The device used in the above example is a 24FC66JI-TE13 REV-D (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc No. 1047, Rev. H
REVISION HISTORY
Date
07/28/03
Revision Comments
A
Initial Issue
02/26/04
B
Added 8-pin TSSOP package (updated in all areas)
04/02/04
C
Eliminated data sheet designation
05/16/04
D
Update D.C. Operating Characteristics
Update Read & Write Cycle Limits
Update Ordering Information
Update Revision History
Update Rev Number
06/07/04
E
Update Read & Write Cycle Limits
08/25/04
F
Update Ordering Information and notes
03/24/05
G
Update
Update
Update
Update
Update
Update
Update
08/03/05
H
Update Pin Configuration
Update Ordering Information
Features
Description
Pin Functions
Reliability Characteristics
D.C. Operating Characteristics
A.C. Characteristics
Ordering Information
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Publication #:
Revison:
Issue date:
1047
H
08/03/05
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