LTC3548-1 Dual Synchronous, Fixed Output 2.25MHz Step-Down DC/DC Regulator DESCRIPTION FEATURES n n n n n n n n n n n n High Efficiency: Up to 95% 1.8V at 800mA/1.575V at 400mA Very Low Quiescent Current: Only 40μA 2.25MHz Constant Frequency Operation High Switch Current: 1.2A and 0.7A No Schottky Diodes Required VIN: 2.5V to 5.5V Current Mode Operation for Excellent Line and Load Transient Response Short-Circuit Protected Low Dropout Operation: 100% Duty Cycle Ultralow Shutdown Current: IQ < 1μA Small Thermally Enhanced 3mm × 3mm DFN Packages The LTC®3548-1 is a dual, fixed output, constant frequency, synchronous step-down DC/DC converter. Intended for low power applications, it operates from 2.5V to 5.5V input voltage range and has a constant 2.25MHz switching frequency, allowing the use of tiny, low cost capacitors and inductors with a profile ≤1mm. The output voltage for channel 1 is fixed at 1.8V and for channel 2 is fixed at 1.575V. Internal synchronous 0.35Ω, 1.2A/0.7A power switches provide high efficiency without the need for external Schottky diodes. Burst Mode® operation provides high efficiency at light loads. To further maximize battery runtime, the P-channel MOSFETs are turned on continuously in dropout (100% duty cycle), and both channels draw a total quiescent current of only 40μA. In shutdown, the device draws <1μA. APPLICATIONS n n n n n n The LTC3548-1 is available in both thin (0.75mm) and ultra-thin (0.55mm) 3mm × 3mm DFN packages. PDAs/Palmtop PCs Digital Cameras Cellular Phones Portable Media Players PC Cards Wireless and DSL Modems L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131. TYPICAL APPLICATION LTC3548-1 Efficiency Curve/Power Loss CIN 10μF CER RUN1 RUN2 CFF2 330pF 2.2μH SW2 SW1 VOUT2 VOUT1 VFB2 VFB1 GND VOUT1 1.8V 800mA CFF1 330pF COUT1 10μF CER VOUT1 = 1.8V 85 80 10 VOUT2 = 1.575V 75 POWER LOSS (mW) 4.7μH VOUT2 1.575V 400mA 100 90 LTC3548-1 COUT2 10μF CER 1000 95 VIN EFFICIENCY (%) VIN 2.7V TO 5.5V 100 1 70 3548-1 F01 65 CHANNEL 1 CHANNEL 2 60 Figure 1. 1.8V/1.575V at 800mA/400mA Step-Down Regulators 1 10 100 LOAD CURRENT (mA) 0.1 1000 35481 F01b 35481fb 1 LTC3548-1 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN Voltages .................................................– 0.3V to 6V VFB1, VFB2, VOUT1, VOUT2, RUN1, RUN2 Voltages ..................... –0.3V to VIN + 0.3V SW1, SW2 Voltage ........................... –0.3V to VIN + 0.3V Ambient Operating Temperature Range (Note 2)....................................................– 40°C to 85°C Junction Temperature (Note 5) ............................. 125°C Storage Temperature Range...................– 65°C to 125°C PIN CONFIGURATION TOP VIEW VFB1 VOUT1 VIN SW1 GND TOP VIEW 10 VFB2 9 VOUT2 1 2 4 8 RUN1 7 SW2 5 6 RUN2 3 11 10 VFB2 VFB1 1 VOUT1 2 VIN 3 SW1 4 7 SW2 GND 5 6 RUN2 9 VOUT2 11 8 RUN1 DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN KD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC UTDFN TJMAX = 125°C, θJA = 40°C/W, θJC = 3°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND (SOLDERED TO A 4-LAYER BOARD) TJMAX = 125°C, θJA = 43°C/W, θJC = 10°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND (SOLDERED TO A 4-LAYER BOARD) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3548EDD-1#PBF LTC3548EDD-1#TRPBF LBZC 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC3548EKD-1#PBF LTC3548EKD-1#TRPBF CXVT 10-Lead (3mm × 3mm) Plastic UTDFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 35481fb 2 LTC3548-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2) SYMBOL PARAMETER CONDITIONS VIN Operating Voltage Range VOUT1 Output Voltage VOUT2 Output Voltage ΔVLINE REG Reference Voltage Line Regulation ΔVLOAD REG IS MIN ● 2.5 0°C ≤ TA ≤ 85°C (Note 3) –40°C ≤ TA ≤ 85°C (Note 3) ● 1.764 1.755 0°C ≤ TA ≤ 85°C (Note 3) –40°C ≤ TA ≤ 85°C (Note 3) ● 1.544 1.536 TYP MAX UNITS 5.5 V 1.8 1.8 1.836 1.836 V V 1.575 1.575 1.607 1.607 V V VIN = 2.5V to 5.5V (Note 3) 0.3 0.5 Output Voltage Load Regulation (Note 3) 0.5 Input DC Supply Current Active Mode Sleep Mode Shutdown VOUT1 = 1.5V, VOUT2 = 1.3V VOUT1 = 1.9V, VOUT2 = 1.65V RUN = 0V, VIN = 5.5V 700 40 0.1 950 60 1 μA μA μA fOSC Oscillator Frequency VOUT1 = 1.8V, VOUT2 = 1.575V 1.8 2.25 2.7 MHz ILIM Peak Switch Current Limit Channel 1 Peak Switch Current Limit Channel 2 VIN = 3V, Duty Cycle <35% VIN = 3V, Duty Cycle <35% 0.95 0.6 1.2 0.7 1.6 0.9 A A RDS(ON) Top Switch On-Resistance Bottom Switch On-Resistance (Note 6) (Note 6) 0.35 0.30 0.45 0.45 Ω Ω ISW(LKG) Switch Leakage Current VIN = 5V, VRUN = 0V, VOUT1 = VOUT2 = 0 0.01 1 μA VRUN RUN Threshold ● 1 1.5 V IRUN RUN Leakage Current ● 0.01 1 μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3548-1 is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the – 40°C and 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. 0.3 % Note 3: The LTC3548-1 is tested in a proprietary test mode that connects the output of the error amplifier to an outside servo-loop. Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: TJ is calculated from the ambient TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA). Note 6: The DFN switch on-resistance is guaranteed by correlation to wafer level measurements. TYPICAL PERFORMANCE CHARACTERISTICS Burst Mode Operation ● %/V TA = 25°C unless otherwise specified. Load Step Load Step VOUT2 200mV/DIV SW 5V/DIV VOUT1 200mV/DIV IL 200mA/DIV IL 200mA/DIV IL 500mA/DIV ILOAD 40mA TO 400mA 200mA/DIV VOUT1 20mV/DIV VIN = 3.6V 2μs/DIV VOUT1 = 1.8V ILOAD = 60mA CHANNEL 1; CIRCUIT OF FIGURE 3 3548-1 G01 ILOAD 80mA TO 800mA 500mA/DIV 20μs/DIV VIN = 3.6V VOUT2 = 1.575V ILOAD = 40mA TO 400mA CHANNEL 2; CIRCUIT OF FIGURE 3 3548-1 G03 VIN = 3.6V 20μs/DIV VOUT1 = 1.8V ILOAD = 80mA TO 800mA CHANNEL 1; CIRCUIT OF FIGURE 3 3548-1 G02 35481fb 3 LTC3548-1 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified. Oscillator Frequency vs Temperature Efficiency vs Input Voltage 2.5 100 Oscillator Frequency vs Input Voltage 10 VIN = 3.6V 8 95 IOUT = 100mA FREQUENCY (MHz) EFFICIENCY (%) 90 85 80 IOUT = 800mA IOUT = 10mA 75 IOUT = 1mA 70 6 FREQUENCY DEVIATION (%) 2.4 2.3 2.2 2.1 4 2 0 –2 –4 –6 65 60 –8 2 2.5 3 3.5 4 4.5 5 INPUT VOLTAGE (V) 5.5 2.0 –50 –25 6 50 25 75 0 TEMPERATURE (°C) 100 RDS(ON) vs Input Voltage VIN = 3.6V VIN = 4.2V 450 0 –0.2 –0.4 –0.6 400 MAIN SWITCH 350 300 350 300 250 SYNCHRONOUS SWITCH 250 200 150 –0.8 –1 –50 200 –25 50 25 0 75 TEMPERATURE (°C) 100 1 125 2 3 5 4 INPUT VOLTAGE (V) 6 100 –50 –25 7 Efficiency vs Load Current Load Regulation Line Regulation 2.0 0.5 95 1.5 0.4 90 1.0 80 75 0.3 VOUT1 = 1.8V VOUT ERROR (%) VOUT ERROR (%) VOUT2 = 1.575V 25 50 75 100 125 150 0 JUNCTION TEMPERATURE (°C) 3548-1 G09 100 85 MAIN SWITCH SYNCHRONOUS SWITCH 3548-1 G08 3548-1 G07 VOUT1 = 1.8V VIN = 3.6V 400 RDS(ON) (mΩ) 0.4 6 VIN = 2.7V 450 0.2 5 RDS(ON) vs Junction Temperature 550 500 0.6 EFFICIENCY (%) 4 3 3548-1 G06 500 RDS(ON) (mΩ) OUTPUT VOLTAGE ERROR (%) 2 3548-1 G05 Output Voltage Error vs Temperature 0.8 125 INPUT VOLTAGE (V) 3548-1 G04 1 –10 0.5 0 VOUT2 = 1.575V –1.0 65 –1.5 0.1 VOUT2 = 1.575V 0 –0.1 –0.5 70 VOUT1 = 1.8V 0.2 –0.2 –0.3 60 1 10 100 LOAD CURRENT (mA) 1000 3548-1 G11 –0.4 –2.0 –0.5 1 10 100 LOAD CURRENT (mA) 1000 3548-1 G12 2.5 3 4 4.5 3.5 LOAD CURRENT (mA) 5 5.5 3548-1 G15 35481fb 4 LTC3548-1 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current Efficiency vs Load Current 100 100 95 95 VIN = 3.6V VIN = 2.7V 85 VIN = 4.2V 80 VIN = 2.7V 90 EFFICIENCY (%) VIN = 3.6V 90 EFFICIENCY (%) TA = 25°C unless otherwise specified. 75 85 VIN = 4.2V 80 75 70 70 VOUT1 = 1.8V NO LOAD ON OTHER CHANNEL CIRCUIT OF FIGURE 3 65 60 1 10 100 LOAD CURRENT (mA) 1000 3548-1 G16 VOUT2 = 1.575V NO LOAD ON OTHER CHANNEL CIRCUIT OF FIGURE 3 65 60 1 10 100 LOAD CURRENT (mA) 1000 3548-1 G17 PIN FUNCTIONS VFB1 (Pin 1): Output Feedback for Channel 1. Receives the feedback voltage from internal resistive divider across the output. Normal voltage for this pin is 0.6V. VOUT1 (Pin 2): Output Voltage Feedback Pin for Channel 1. An internal resistive divider divides the output voltage down for comparison to the internal reference voltage. VIN (Pin 3): Input Power Supply. Must be closely decoupled to GND. SW1 (Pin 4): Regulator 1 Switch Node Connection to the Inductor. This pin swings from VIN to GND. GND (Pin 5): Ground. Connect to the (–) terminal of COUT and (–) terminal of CIN (see Figure 4). RUN2 (Pin 6): Regulator 2 Enable. Forcing this pin to VIN enables regulator 2, while forcing it to GND causes regulator 2 to shut down. This pin must be driven; do not float. SW2 (Pin 7): Regulator 2 Switch Node Connection to the Inductor. This pin swings from VIN to GND. RUN1 (Pin 8): Regulator 1 Enable. Forcing this pin to VIN enables regulator 1, while forcing it to GND causes regulator 1 to shut down. This pin must be driven; do not float. VOUT2 (Pin 9): Output Voltage Feedback Pin for Channel 2. An internal resistive divider divides the output voltage down for comparison to the internal reference voltage. VFB2 (Pin 10): Output Feedback for Channel 2. Receives the feedback voltage from internal resistive divider across the output. Normal voltage for this pin is 0.6V. Exposed Pad (GND) (Pin 11): Ground. Connect to the (–) terminal of COUT, and (–) terminal of CIN. Must be connected to electrical ground on PCB (see Figure 4). 35481fb 5 LTC3548-1 BLOCK DIAGRAM REGULATOR 1 VIN BURST CLAMP VIN SLOPE COMP EN – + 0.6V EA ITH BURST – + 5Ω ICOMP + 0.35V – SLEEP VOUT1 2 R1 S VFB VFB1 1 R3 0.55V R – UVDET + OVDET Q SWITCHING LOGIC AND BLANKING CIRCUIT UV + ANTI SHOOTTHRU 4 SW1 OV – + 0.65V Q RS LATCH IRCMP SHUTDOWN – 11 GND VIN 3 VIN RUN1 8 0.6V REF OSC RUN2 6 VOUT2 9 OSC 5 GND REGULATOR 2 (IDENTICAL TO REGULATOR 1) R1 = 240k, R3 = 120k FOR REGULATOR 1 R1 = 195k, R3 = 120k FOR REGULATOR 2 7 SW2 VFB2 10 3548-1 BD 35481fb 6 LTC3548-1 OPERATION The LTC3548-1 uses a constant frequency, current mode architecture. The operating frequency is set at 2.25MHz. Both channels share the same clock and run in-phase. The output voltage is set by an internal divider. An error amplfier compares the divided output voltage with a reference voltage of 0.6V and adjusts the peak inductor current accordingly. Main Control Loop During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle when the VOUT voltage is below the regulated voltage. The current flows into the inductor and the load increases until current limit is reached. The switch turns off and energy stored in the inductor flows through the bottom switch (N-channel MOSFET) into the load until the next clock cycle. The peak inductor current is controlled by the internally compensated ITH voltage, which is the output of the error amplifier. This amplifier compares the feedback voltage VFB to the 0.6V reference (see Block Diagram). When the load current increases, the VFB voltage decreases slightly below the reference. This decrease causes the error amplifier to increase the ITH voltage until the average inductor current matches the new load current. The main control loop is shut down by pulling the RUN pin to ground. Low Current Operation When the load is relatively light, the LTC3548-1 automatically switches into Burst Mode operation, in which the PMOS switch operates intermittently based on load demand with a fixed peak inductor current. By running cycles periodically, the switching losses which are dominated by the gate charge losses of the power MOSFETs are minimized. The main control loop is interrupted when the output voltage reaches the desired regulated value. A voltage comparator trips when ITH is below 0.35V, shutting off the switch and reducing the power. The output capacitor and the inductor supply the power to the load until ITH exceeds 0.65V, turning on the switch and the main control loop which starts another cycle. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. In dropout, the PMOS switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel MOSFET and the inductor. An important design consideration is that the RDS(ON) of the P-channel switch increases with decreasing input supply voltage (see Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the LTC3548-1 is used at 100% duty cycle with low input voltage (see Thermal Considerations in the Applications Information section). Low Supply Operation To prevent unstable operation, the LTC3548-1 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 1.65V. 35481fb 7 LTC3548-1 APPLICATIONS INFORMATION A general LTC3548-1 application circuit is shown in Figure 2. External component selection is driven by the load requirement, and begins with the selection of the inductor L. Once the inductor is chosen, CIN and COUT can be selected. VIN 2.7V TO 5.5V Inductor Core Selection CIN 10μF CER VIN RUN1 RUN2 LTC3548-1 4.7μH VOUT2 1.575V 400mA COUT2 10μF CER CFF2 330pF 2.2μH SW2 SW1 VOUT2 VOUT1 VFB2 VFB1 VOUT1 1.8V 800mA CFF1 330pF GND COUT1 10μF CER 3548-1 F01 Figure 2. LTC3548-1 General Schematic Inductor Selection Although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple current. The inductor ripple current ΔIL decreases with higher inductance and increases with higher VIN or VOUT: IL = higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. VOUT VOUT • 1– fO • L VIN Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. A reasonable starting point for setting ripple current is ΔIL = 0.3 • IOUT(MAX), where IOUT(MAX) is 0.8A for channel 1 and 400mA for channel 2. The largest ripple current ΔIL occurs at the maximum input voltage. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: V V L = OUT • 1– OUT fO • IL VIN(MAX) The inductor value will also have an effect on Burst Mode operation. The transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characterisitics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the LTC3548-1 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3548-1 applications. Table 1. Representative Surface Mount Inductors PART NUMBER VALUE (μH) DCR (Ω MAX) MAX DC SIZE CURRENT (A) W × L × H (mm3) Sumida CDRH3D16 2.2 3.3 4.7 0.075 0.110 0.162 1.20 1.10 0.90 3.8 × 3.8 × 1.8 Sumida CMD4D06 2.2 4.7 0.089 0.166 0.95 0.75 4.1 × 3.2 × 0.8 Sumida CMD4D11 2.2 3.3 0.116 0.174 0.950 0.770 4.4 × 5.8 × 1.2 Murata LQH32CN 1.0 2.2 0.060 0.097 1.00 0.79 2.5 × 3.2 × 2.0 Toko D312F 2.2 3.3 0.060 0.260 1.08 0.92 2.5 × 3.2 × 2.0 Panasonic ELT5KT 3.3 4.7 0.17 0.20 1.00 0.95 4.5 × 5.4 × 1.2 Input Capacitor (CIN) Selection In continuous mode, the input current of the converter is a square wave with a duty cycle of approximately VOUT/VIN. To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IRMS ≈IMAX VOUT ( VIN – VOUT ) VIN 35481fb 8 LTC3548-1 APPLICATIONS INFORMATION where the maximum average output current IMAX equals the peak current minus half the peak-to-peak ripple current, IMAX = ILIM – ΔIL/2. This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case is commonly used to design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of the design. An additional 0.1μF to 1μF ceramic capacitor is also recommended on VIN for high frequency decoupling, when not using an all ceramic capacitor solution. Output Capacitor (COUT) Selection The selection of COUT is driven by the required ESR to minimize voltage ripple and load step transients. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (ΔVOUT) is determined by: 1 VOUT IL ESR + 8fO COUT where fO = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. With ΔIL = 0.3 • IOUT(MAX) the output ripple will be less than 100mV at maximum VIN and fO = 2.25MHz with: ESRCOUT < 150mΩ Once the ESR requirements for COUT have been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement, except for an all ceramic solution. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantulum capacitors are all available in surface mount packages. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any aluminum electrolytic at a somewhat higher price. Special polymer capacitors, such as Sanyo POSCAP, Panasonic Special Polymer (SP), and Kemet A700, offer very low ESR, but have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but they have a larger ESR and it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and are often used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have the lowest ESR and cost, but also have the lowest capacitance density, a high voltage and temperature coefficient, and exhibit audible piezoelectric effects. In addition, the high Q of ceramic capacitors along with trace inductance can lead to significant ringing. In most cases, 0.1μF to 1μF of ceramic capacitors should also be placed close to the LTC3548-1 in parallel with the main capacitors for high frequency decoupling. Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low ESR. Unfortunately, the ESR is so low that it can cause loop stability problems. Solid tantalum capacitor ESR generates a loop “zero” at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually resonate with their ESL before ESR becomes effective. Also, ceramic caps are prone to temperature effects which requires the designer to check loop stability over the operating temperature range. To minimize their large temperature and voltage coefficients, only X5R or X7R ceramic capacitors should be used. A good selection of ceramic capacitors is available from Taiyo Yuden, AVX, Kemet, TDK, and Murata. Great care must be taken when using only ceramic input and output capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output 35481fb 9 LTC3548-1 APPLICATIONS INFORMATION can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, the ringing at the input can be large enough to damage the part. margin. In addition, a feed-forward capacitor, CFF, is added externally to improve the high frequency response. Capacitor CFF provides phase lead by creating a high frequency zero with R1, which improves the phase margin. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. Typically, 3-4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 2-3 times the linear drop of the first cycle. Thus, a good place to start is with the output capacitor size of approximately: ΔIOUT COUT ≈ 2.5 fO • VDROOP The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 10μF ceramic capacitor is usually enough for these conditions. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT, generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second-order overshoot/DC ratio cannot be used to determine phase In some applications, a more severe transient can be caused by switching loads with large (>1μF) load input capacitors. The discharged load input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot Swap™ controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3548-1 circuits: 1)VIN quiescent current, 2) switching losses, 3) I2R losses, 4) other losses. 1) The VIN current is the DC supply current given in the Electrical Characteristics which excludes MOSFET driver and control currents. VIN current results in a small (<0.1%) loss that increases with VIN, even at no load. Hot Swap is a trademark of Linear Technology Corporation. 35481fb 10 LTC3548-1 APPLICATIONS INFORMATION 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB are the gate charges of the internal top and bottom MOSFET switches. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 3) I2R losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flows through inductor L, but is “chopped” between the internal top and bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (D) as follows: RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT 2(RSW + RL) duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will turn off and the SW node will become high impedance. To prevent the LTC3548-1 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD • θJA where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT As an example, consider the case when the LTC3548-1 is at an input voltage of 2.7V with a load current of 400mA and 800mA and an ambient temperature of 70°C. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the main switch is 0.425Ω. Therefore, power dissipated by each channel is: PD = I2 • RDS(ON) = 272mW and 68mW 4) Other “hidden” losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. The DFN package junction-to-ambient thermal resistance, θJA, is 40°C/W. Therefore, the junction temperature of the regulator operating in a 70°C ambient temperature is approximately: Thermal Considerations As a design example, consider using the LTC3548-1 in an portable application with a Li-Ion battery. The battery provides a VIN = 2.8V to 4.2V. The load requires a maximum of 800mA in active mode and 2mA in standby mode. The output voltage is VOUT = 1.8V. In a majority of applications, the LTC3548-1 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3548-1 is running at high ambient temperature with low supply voltage and high TJ = (0.272 + 0.068) • 40 + 70 = 83.6°C which is below the absolute maximum junction temperature of 125°C. Design Example 35481fb 11 LTC3548-1 APPLICATIONS INFORMATION First, calculate the inductor value for about 30% ripple current at maximum VIN: L= Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3548-1. These items are also illustrated graphically in the layout diagram of Figure 4. Check the following in your layout: 1.8V 1.8V • 1– = 1.9μH 2.25MHz • 240mA 4.2V Choosing a vendor’s closest inductor value of 2.2μH, results in a maximum ripple current of: 1.8V 1.8V • 1 = 207mA 2.25MHz • 2.2μ 4.2V 1. Does the capacitor CIN connect to the power VIN (Pin 3) and GND (exposed pad) as close as possible? This capacitor provides the AC current to the internal power MOSFETs and their drivers. For cost reasons, a ceramic capacitor will be used. COUT selection is then based on load step droop instead of ESR requirements. For a 5% output droop: 2. The feedback lines from VOUT should be routed away from noisy traces such as the SW line and its trace should be minimized. IL = COUT ≈ 1.8 800mA = 7.1μF 2.25MHz • (5% • 1.8V) 3. Are the COUT and L1 closely connected? The (–) plate of COUT returns current to GND and the (–) plate of CIN. 4. Keep sensitive components away from the SW pins. The input capacitor CIN should be routed away from the SW traces and the inductors. A good standard value is 10μF. Since the output impedance of a Li-lon battery is very low, CIN is typically 10μF. Figure 3 shows the complete schematic for this design example. 5. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the GND pin at one point and should not share the high current path of CIN or COUT. 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to VIN or GND. VIN 2.7V TO 5.5V CIN 10μF CER VIN RUN1 RUN2 LTC3548-1 4.7μH VOUT2 1.575V 400mA COUT2 10μF CER CFF2 330pF 2.2μH SW2 SW1 VOUT2 VOUT1 VFB2 VFB1 VOUT1 1.8V 800mA CFF1 330pF GND COUT1 10μF CER 3548-1 F01 Figure 3. LTC3548-1 Typical Application 35481fb 12 LTC3548-1 APPLICATIONS INFORMATION VOUT2 L2 6 RUN2 7 SW2 9 VOUT2 8 RUN1 COUT2 11 GND 10 VFB2 CFF GND 3 4 VIN SW1 5 2 CFF GND 1 VFB1 VOUT1 GND CIN COUT1 VIA TO VOUT1 L1 VOUT1 VIN 3548-1 F04 GND Figure 4. LTC3548-1 Layout Diagram Efficiency vs Load Current 100 95 EFFICIENCY (%) 90 VOUT1 = 1.8V 85 VOUT2 = 1.575V 80 75 70 65 60 1 10 100 LOAD CURRENT (mA) 1000 3548-1 G11 35481fb 13 LTC3548-1 TYPICAL APPLICATIONS 1mm Profile Core and I/O Supplies VIN 2.7V TO 5.5V C1 10μF CER VIN L2 4.7μH VOUT2 1.575V 400mA C3 10μF CER CFF2 330pF RUN1 RUN2 L1 2.2μH LTC3548-1 SW2 SW1 VOUT2 VOUT1 VFB2 VOUT1 1.8V 800mA CFF1 330pF VFB1 C2 10μF CER 3548-1 TA07 GND C1, C2: MURATA GRM219R60J106KE19 C3: MURATA GRM219R60J475KE19 L1: COILTRONICS LPO3310-222MX L2: COILTRONICS LPO3310-472MX *IF C1 IS GREATER THAN 3" FROM POWER SOURCE, ADDITIONAL CAPACITANCE MAY BE REQUIRED. Efficiency vs Load Current 100 95 EFFICIENCY (%) 90 VOUT1 = 1.8V 85 VOUT2 = 1.575V 80 75 70 65 60 1 10 100 LOAD CURRENT (mA) 1000 3548-1 G11 35481fb 14 LTC3548-1 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) R = 0.115 TYP 6 0.38 ± 0.10 10 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 1.65 ± 0.10 (2 SIDES) 3.00 ±0.10 (4 SIDES) PACKAGE OUTLINE PIN 1 TOP MARK (SEE NOTE 6) (DD) DFN 1103 5 0.25 ± 0.05 0.50 BSC 0.75 ±0.05 0.200 REF 0.25 ± 0.05 1 0.50 BSC 2.38 ±0.05 (2 SIDES) 2.38 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE KD Package 10-Lead Plastic UTDFN (3mm × 3mm) (Reference LTC DWG # 05-08-1739 Rev Ø) 2.00 REF 2.38 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 10 2.38 ±0.10 3.00 ±0.10 1.65 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 6 R = 0.05 TYP 0.675 ±0.05 3.50 ±0.05 2.15 ±0.05 0.40 ± 0.10 2.00 REF 3.00 ±0.10 1.65 ± 0.10 PIN 1 TOP MARK (SEE NOTE 6) 0.125 REF 0.55 ±0.05 0.00 – 0.05 5 R = 0.115 TYP 1 (KD10) UTDFN 1106 REV Ø 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE VARIATION OF (TBI). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 35481fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC3548-1 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1878 600mA (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.7V to 6V, VOUT(MIN) = 0.8V, IQ = 10μA, ISD <1μA, MSOP-8 Package LT1940 Dual Output 1.4A(IOUT), Constant 1.1MHz, High Efficiency Step-Down DC/DC Converter VIN: 3V to 25V, VOUT(MIN) = 1.2V, IQ = 2.5mA, ISD = <1μA, TSSOP-16E Package LTC3252 Dual 250mA (IOUT), 1MHz, Spread Spectrum Inductorless Step-Down DC/DC Converter 88% Efficiency, VIN: 2.7V to 5.5V, VOUT(MIN) = 0.9V to 1.6V, IQ = 60μA, ISD < 1μA, DFN-12 Package LTC3405/LTC3405A 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20μA, ISD <1μA, ThinSOT Package LTC3406/LTC3406B 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA, ISD <1μA, ThinSOT Package LT3407/LT3407-2 600mA/1.5MHz, 800mA/2.25MHz Dual Synchronous Step-Down DC/DC Converter 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD <1μA, MSE, DFN Package LTC3410/LTC3410B 300mA, 2.25MHz Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 26μA, ISD <1μA, SC70 Package LTC3411 1.25A (IOUT), 4MHz, Synchronous Step Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD <1μA, MSOP-10 Package LTC3412 2.5A (IOUT), 4MHz, Synchronous Step Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD <1μA, TSSOP-16E Package LTC3414 4A (IOUT), 4MHz, Synchronous Step Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA, ISD <1μA, TSSOP-28E Package LTC3440 600mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 2.5V, IQ = 25μA, ISD <1μA, MSOP-10 Package LTC3548 400mA/800mA (IOUT), 2.25MHz, Dual Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD <1μA, MSE, DFN-10 Packages 35481fb 16 Linear Technology Corporation LT 0608 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006