Very Low Power CMOS SRAM 128K X 8 bit BS62LV1027 Pb-Free and Green package materials are compliant to RoHS n FEATURES n DESCRIPTION Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V Ÿ Very low power consumption : VCC = 3.0V Operation current : 18mA (Max.) at 55ns 2mA (Max.) at 1MHz Standby current : 0.02uA (Typ.) at 25 OC VCC = 5.0V Operation current : 47mA (Max.) at 55ns 10mA (Max.) at 1MHz Standby current : 0.4uA (Typ.) at 25OC Ÿ High speed access time : -55 55ns (Max.) at VCC : 3.0~5.5V -70 70ns (Max.) at VCC : 2.7~5.5V Ÿ Automatic power down when chip is deselected Ÿ Easy expansion with CE2, CE1 and OE options Ÿ Three state outputs and TTL compatible Ÿ Fully static operation Ÿ Data retention supply voltage as low as 1.5V The BS62LV1027 is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 by 8 bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.02uA at 3.0V/25OC and maximum access time of 55ns at 3.0V/85OC. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV1027 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV1027 is available in DICE form, JEDEC standard 32 pin 450mil Plastic SOP, 600mil Plastic DIP, 8mmx13.4mm STSOP, 8mmx20mm TSOP and 36-ball BGA package. n POWER CONSUMPTION POWER DISSIPATION PRODUCT FAMILY STANDBY OPERATING TEMPERATURE VCC=5.0V BS62LV1027DC BS62LV1027HC BS62LV1027PC BS62LV1027SC BS62LV1027STC BS62LV1027TC BS62LV1027HI BS62LV1027PI BS62LV1027SI BS62LV1027STI BS62LV1027TI Operating (ICCSB1, Max.) 1MHz fMax. 1MHz 9mA 29mA 46mA 1.5mA 9mA 17mA Industrial -40OC to +85OC 5.0uA 1.5uA 10mA 30mA 47mA 2mA 10mA 18mA • BS62LV1027PC BS62LV1027PI BS62LV1027SC BS62LV1027SI 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BS62LV1027STC BS62LV1027STI BS62LV1027TC BS62LV1027TI VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 DICE BGA-36-0608 PDIP-32 SOP-32 STSOP-32 TSOP-32 BGA-36-0608 PDIP-32 SOP-32 STSOP-32 TSOP-32 n BLOCK DIAGRAM OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 A6 A7 A12 A14 A16 A15 A13 A8 A9 A11 Address 10 Input 2 3 4 1024 Row Decoder Memory Array 1024 x 1024 Buffer 1024 DQ0 8 DQ1 DQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 fMax. 1.0uA 1 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND VCC=3.0V 10MHz 3.0uA • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC=5.0V 10MHz Commercial +0OC to +70OC n PIN CONFIGURATIONS A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 PKG TYPE (ICC, Max.) VCC=3.0V 5 DQ3 DQ4 6 A A0 A1 CE2 A3 A6 A8 B DQ4 A2 WE A4 A7 DQ0 C DQ5 NC A5 D VSS E VCC F DQ6 G DQ7 H A9 8 DQ5 DQ6 Data Input Buffer Data Output Buffer 8 Column I/O Write Driver Sense Amp 8 128 Column Decoder DQ7 DQ1 CE2 CE1 WE OE VCC GND VCC VSS NC NC DQ2 OE CE1 A16 A15 DQ3 A10 A11 A12 A13 A14 7 Control Address Input Buffer A5 A10 A4 A3 A2 A1 A0 36-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. R0201-BS62LV1027 1 Revision 2.3 May. 2006 BS62LV1027 n PIN DESCRIPTIONS Name Function A0-A16 Address Input These 17 address inputs select one of the 131,072 x 8-bit in the RAM CE1 Chip Enable 1 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read form or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. CE2 Chip Enable 2 Input WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. DQ0-DQ7 Data Input/Output There 8 bi-directional ports are used to read data from or write data into the RAM. Ports VCC Power Supply GND Ground n TRUTH TABLE MODE CE1 CE2 WE OE Not selected (Power Down) H X X X X L X X Output Disabled L H H Read L H Write L H n ABSOLUTE MAXIMUM RATINGS TBIAS TSTG VCC CURRENT High Z ICCSB, ICCSB1 H High Z ICC H L DOUT ICC L X DIN ICC (1) n OPERATING RANGE RATING UNITS RANG AMBIENT TEMPERATURE VCC Terminal Voltage with Respect to GND Temperature Under Bias -0.5(2) to 7.0 V Commercial 0OC to + 70OC 2.4V ~ 5.5V -40 to +125 O C Industrial -40OC to + 85OC 2.4V ~ 5.5V Storage Temperature -60 to +150 O C SYMBOL VTERM I/O OPERATION PARAMETER PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA n CAPACITANCE O (TA = 25 C, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns. R0201-BS62LV1027 (1) CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V 6 pF VI/O = 0V 8 pF 1. This parameter is guaranteed and not 100% tested. 2 Revision 2.3 May. 2006 BS62LV1027 O O n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNITS 2.4 -- 5.5 V VCC Power Supply VIL Input Low Voltage -0.5(2) -- 0.8 V VIH Input High Voltage 2.2 -- VCC+0.3(3) V IIL Input Leakage Current VCC = Max, VIN = 0V to VCC -- -- 1 uA ILO Output Leakage Current V CC = Max, CE1= VIH, CE2= VIL, or OE = VIH, V I/O = 0V to V CC -- -- 1 uA VOL Output Low Voltage V CC = Max, IOL = 2.0mA -- -- 0.4 V 2.4 -- -- V VOH ICC(5) ICC1 ICCSB ICCSB1(6) Output High Voltage VCC=3.0V VCC=5.0V VCC=3.0V V CC = Min, IOH = -1.0mA VCC=5.0V Operating Power Supply Current CE1 = VIL, CE2 = VIH, IDQ = 0mA, f = fMax(4) VCC=3.0V -- -- 18 VCC=5.0V -- -- 47 Operating Power Supply Current CE1 = VIL, CE2 = VIH, IDQ = 0mA, f = 1MHz VCC=3.0V 2 VCC=5.0V 10 Standby Current – TTL CE1 = VIH, or CE2 = VIL, IDQ = 0mA VCC=3.0V -- -- 0.5 VCC=5.0V -- -- 1.0 CE1≧VCC-0.2V or CE2≦0.2V, VCC=3.0V -- 0.02 1.5 VCC=5.0V -- 0.4 5.0 MIN. TYP. (1) MAX. UNITS 1.5 -- -- V -- 0.02 0.5 uA 0 -- -- ns tRC (2) -- -- ns Standby Current – CMOS VIN≧V CC-0.2V or VIN≦0.2V 1. Typical characteristics are at TA=25OC and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. fMax.=1/tRC. 5. ICC (MAX.) is 17mA/46mA at VCC=3.0V/5.0V and TA=70OC. 6. ICCSB1(MAX.) is 1.3uA/4.0uA at VCC=3.0V/5.0V and TA=70OC. O mA mA mA uA O n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C) SYMBOL PARAMETER VDR VCC for Data Retention ICCDR(3) Data Retention Current tCDR Chip Deselect to Data Retention Time tR TEST CONDITIONS CE1≧VCC-0.2V or CE2≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V CE1≧VCC-0.2V or CE2≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V See Retention Waveform Operation Recovery Time O 1. VCC=1.5V, TA=25 C and not 100% tested. 2. tRC = Read Cycle Time. 3. ICCRD(Max.) is0.3uA at TA=70OC. n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled) Data Retention Mode VCC VCC VDR≧1.5V tCDR CE1 R0201-BS62LV1027 VIH VCC tR CE1≧VCC - 0.2V 3 VIH Revision 2.3 May. 2006 BS62LV1027 n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled) Data Retention Mode VDR≧1.5V VCC VCC VCC tCDR tR CE2≦0.2V CE2 VIL VIL n AC TEST CONDITIONS n KEY TO SWITCHING WAVEFORMS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load WAVEFORM tCLZ, tOLZ, tCHZ, tOHZ, tWHZ CL = 5pF+1TTL Others CL = 30pF+1TTL ALL INPUT PULSES VCC 1 TTL Output GND CL(1) 90% 90% 10% 10% → ← Rise Time : 1V/ns → ← Fall Time : 1V/ns INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” WILL BE CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED CHANGE : STATE UNKNOW DOES NOT APPLY CENTER LINE IS HIGH INPEDANCE “OFF” STATE 1. Including jig and scope capacitance. O O n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE CYCLE TIME : 55ns (VCC = 3.0~5.5V) MIN. TYP. MAX. CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. TYP. MAX. JEDEC PARAMETER NAME PARAMETER NAME tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns tAVQX tAA Address Access Time -- -- 55 -- -- 70 ns tE1LQV tACS1 Chip Select Access Time (CE1) -- -- 55 -- -- 70 ns tE2HQV tACS2 Chip Select Access Time (CE2) -- -- 55 -- -- 70 ns tGLQV tOE Output Enable to Output Valid -- -- 30 -- -- 35 ns tE1LQX tCLZ1 Chip Select to Output in Low Z (CE1) 10 -- -- 10 -- -- ns tE2HQX tCLZ2 Chip Select to Output in Low Z (CE2) 10 -- -- 10 -- -- ns tGLQX tOLZ Output Enable to Output in Low Z 5 -- -- 5 -- -- ns tE1HQZ tCHZ1 Chip Deselect to Output in High Z (CE1) -- -- 30 -- -- 35 ns tE2LQZ tCHZ2 Chip Deselect to Output in High Z (CE2) -- -- 30 -- -- 35 ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns tAVQX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns R0201-BS62LV1027 DESCRIPTION 4 UNITS Revision 2.3 May. 2006 BS62LV1027 n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tAA tOH tOH DOUT READ CYCLE 2 (1,3,4) CE1 tACS1 CE2 tACS2 tCLZ tCHZ1, tCHZ2 (5) (5) DOUT READ CYCLE 3 (1, 4) tRC ADDRESS tAA OE tOH tOE tOLZ CE1 (5) tACS1 tCLZ1 CE2 tOHZ (5) tCHZ1 (1,5) tCHZ2 (2,5) tACS2 (5) tCLZ2 DOUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. R0201-BS62LV1027 5 Revision 2.3 May. 2006 BS62LV1027 O O n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE CYCLE TIME : 55ns (VCC = 3.0~5.5V) CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. TYP. MAX. MIN. TYP. MAX. Write Cycle Time 55 -- -- 70 -- -- ns tCW Chip Select to End of Write 55 -- -- 70 -- -- ns tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns tAVWH tAW Address Valid to End of Write 55 -- -- 70 -- -- ns tWLWH tWP Write Pulse Width 30 -- -- 35 -- -- ns tWHAX tWR1 Write Recovery Time (CE1, WE) 0 -- -- 0 -- -- ns tE2LAX tWR2 Write Recovery Time (CE2) 0 -- -- 0 -- -- ns tWLQZ tWHZ Write to Output in High Z -- -- 25 -- -- 30 ns tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns tWHQX tOW End of Write to Output Active 5 -- -- 5 -- -- ns JEDEC PARAMETER NAME PARAMETER NAME tAVAX tWC tE1LWH DESCRIPTION UNITS n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS tWR1 (3) tWR2 (3) OE CE1 (5) CE2 (5) tAW WE (11) tCW (11) tWP tAS tOHZ tCW (2) (4,10) DOUT tDH tDW DIN R0201-BS62LV1027 6 Revision 2.3 May. 2006 BS62LV1027 WRITE CYCLE 2 (1,6) tWC ADDRESS (5) CE1 CE2 tCW (11) tCW (11) (5) tAW tWP WE tAS tWHZ tWR2 (2) (4,10) (3) tOW (7) (8) DOUT tDW tDH (8,9) DIN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write. R0201-BS62LV1027 7 Revision 2.3 May. 2006 BS62LV1027 n ORDERING INFORMATION BS62LV1027 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE D: DICE H: BGA-36-0608 P: PDIP S: SOP T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. n PACKAGE DIMENSIONS WITH PLATING c b c1 BASE METAL b1 SECTION A-A SOP -32 R0201-BS62LV1027 8 Revision 2.3 May. 2006 BS62LV1027 n PACKAGE DIMENSIONS (continued) n STSOP - 32 TSOP - 32 R0201-BS62LV1027 9 Revision 2.3 May. 2006 BS62LV1027 PACKAGE DIMENSIONS (continued) PDIP - 32 NOTES : 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.2 Max. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. BALL PITCH e = 0.75 D E N D1 E1 8.0 6.0 48 5.25 3.75 E1 e D1 VIEW A 36 mini-BGA (6 x 8mm) R0201-BS62LV1027 10 Revision 2.3 May. 2006 BS62LV1027 n Revision History Revision No. History Draft Date 2.2 Add Icc1 characteristic parameter Improve Iccsb1 spec. I-grade from 20uA to 5.0uA at 5.0V 2.5uA to 1.5uA at 3.0V C-grade from 8.0uA to 3.0uA at 5.0V 1.3uA to 1.0uA at 3.0V Jan. 13, 2006 2.3 Change I-grade operation temperature range - from –25OC to –40OC May. 25, 2006 R0201-BS62LV1027 11 Remark Revision 2.3 May. 2006