TI BQ294704DSGT Overvoltage protection for 2-series to 4-series cell li-ion batteries with external delay capacitor Datasheet

bq294700, bq294701, bq294702
bq294703, bq294704, bq294705
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SLUSB15 – SEPTEMBER 2012
Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries
with External Delay Capacitor
Check for Samples: bq294700, bq294701, bq294702, bq294703, bq294704, bq294705
FEATURES
APPLICATIONS
•
•
•
•
•
1
•
•
•
•
•
2-, 3-, and 4-Series Cell Overvoltage Protection
External Capacitor-Programmed Delay Timer
Factory Programmed OVP Threshold
(Threshold Range 3.85 V to 4.6 V)
Output Options: Active High or Open Drain
Active Low
High-Accuracy Overvoltage Protection:
±10 mV
Low Power Consumption ICC ≈ 1 µA
(VCELL(ALL) < VPROTECT)
Low Leakage Current Per Cell Input < 100 nA
Small Package Footprint
– 8-Pin SON (2 mm x 2 mm)
Notebook
UPS Battery Backup
DESCRIPTION
The bq2947xy family of products is an overvoltage monitor and protector for Li-Ion battery pack systems. Each
cell is monitored independently for an overvoltage condition.
In the bq2947xy device, an external delay timer is initiated upon detection of an overvoltage condition on any
cell. Upon expiration of the delay timer, the output is triggered into its active state (either high or low, depending
on the configuration). The external delay timer feature also includes the ability to detect an open or shorted delay
capacitor on the CD pin, which will similarly trigger the output driver in an overvoltage condition.
For quicker production-line testing, the bq2947xy device provides a Customer Test Mode with reduced delay
time.
1 VDD
OUT 8
2 V4
CD 7
3 V3
VSS 6
4 V2
V1 5
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
bq294700, bq294701, bq294702
bq294703, bq294704, bq294705
SLUSB15 – SEPTEMBER 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
–40°C to
110°C
OVP (V)
OV Hysteresis
(V)
Output Drive
Tape and Reel
(Large)
bq294700
4.350
0.300
CMOS Active High
bq294700DSGR
bq294701
4.250
0.300
CMOS Active High
bq294701DSGR
bq294702
4.300
0.300
CMOS Active High
bq294702DSGR
bq294703
4.325
0.300
CMOS Active High
bq294703DSGR
4.400
0.300
CMOS Active High
bq294704DSGR
4.450
0.300
CMOS Active High
bq294705DSGR
0–0.300
CMOS Active High
or Open Drain
Active Low
bq2947xyTBD
Part Number
Package
Package
Designator
8-pin
SON
bq294704
DSG
bq294705
bq2947xy (1)
(1)
3.850–4.600
Future option, contact TI.
THERMAL INFORMATION
bq2947xy
THERMAL METRIC (1)
SON
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance
θJC(top)
Junction-to-case(top) thermal resistance
θJB
Junction-to-board thermal resistance
32.5
ψJT
Junction-to-top characterization parameter
1.6
ψJB
Junction-to-board characterization parameter
33
θJC(bottom)
Junction-to-case(bottom) thermal resistance
10
(1)
2
62
72
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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bq294700, bq294701, bq294702
bq294703, bq294704, bq294705
www.ti.com
SLUSB15 – SEPTEMBER 2012
PIN FUNCTIONS
bq2947xy
Pin Name
Type I/O
1
VDD
P
Power supply input
Description
2
V4
IA
Sense input for positive voltage of the fourth cell from the bottom of the stack
3
V3
IA
Sense input for positive voltage of the third cell from the bottom of the stack
4
V2
IA
Sense input for positive voltage of the second cell from the bottom of the stack
5
V1
IA
Sense input for positive voltage of the lowest cell in the stack
6
VSS
P
Electrically connected to IC ground and negative terminal of the lowest cell in the stack
7
CD
OA
External capacitor connection for delay timer
8
OUT
OA
Analog Output drive for overvoltage fault signal. Active High or Open Drain Active Low
9
PWPD
P
TI recommends connecting the exposed pad to VSS on PCB.
PIN DETAILS
In the bq2947xy device, each cell is monitored independently. Overvoltage is detected by comparing the actual
cell voltage to a protection voltage reference, VOV. If any cell voltage exceeds the programmed OV value, a timer
circuit is activated. This timer circuit charges the CD pin to a nominal value, then slowly discharges it with a fixed
current back down to VSS. When the CD pin falls below a nominal threshold near VSS, the OUT terminal goes
from inactive to active state. Additionally, a timeout detection circuit checks to ensure that the CD pin
successfully begins charging to above VSS and subsequently drops back down to VSS, and if a timeout error is
detected in either direction, it will similarly trigger the OUT pin to become active. See Figure 2 for details on CD
and OUT pin behavior during an overvoltage event.
Cell Voltage (V)
(V4–V3, V3
3 –V2, V2 – V1, V1–VSS)
For an NCH Open Drain Active Low configuration, the OUT pin pulls down to VSS when active (OV present) and
is high impedance when inactive (no OV).
VOV
VOV –VHYS
tCD
OUT (V)
Figure 1. Timing for Overvoltage Sensing
Copyright © 2012, Texas Instruments Incorporated
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Figure 2 shows the behavior of CD pin during an OV sequence.
Fault condition
present
Fault response
becomes active
VCD
V(CD)
tCHGDELAY
tCD
VOUT1
V(OUT)
Note: Active High OUT version shown
Figure 2. CD Pin Mechanism
NOTE
In the case of an Open Drain Active Low version, the VOUT signal will be high and
transition to low state when the voltage on the VCD capacitor discharges to the set level
based on the tCD timer.
Input Sense Voltage, Vx
These inputs sense each battery cell voltage. A series resistor and a capacitor across the cell for each input is
required for noise filtering and stable voltage monitoring.
Output Drive, OUT
This terminal serves as the fault signal output, and may be ordered in either Active High or Open Drain Active
Low options.
Supply Input, VDD
This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current,
and a capacitor is connected to ground for noise filtering.
External Delay Capacitor, CD
This terminal is connected to an external capacitor that sets the delay timer during an overvoltage fault event.
The CD pin includes a timeout detection circuit to ensure that the output drives active even with a shorted or
open capacitor during an overvoltage event.
The capacitor connected on the CD pin rapidly charges to a voltage if any one of the cell inputs exceeds the OV
threshold. Then the delay circuit gradually discharges the capacitor on the CD pin. Once this capacitor
discharges below a set voltage, the OUT transitions from an inactive to active state.
4
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bq294700, bq294701, bq294702
bq294703, bq294704, bq294705
www.ti.com
SLUSB15 – SEPTEMBER 2012
To calculate the delay, use the following equation:
tCD (sec) = K * CCD (µF), where K = 10 to 20 range.
(1)
Example: If CCD= 0.1 µF (typical), then the delay timer range is
tCD (sec) = 10 * 0.1 = 1 s (Minimum)
tCD (sec) = 20 * 0.1 = 2 s (Maximum)
NOTE
The tolerance on the capacitor used for CCD increases the range of the tCD timer.
FUNCTIONAL BLOCK DIAGRAM
Figure 3 shows a CMOS Active High configuration.
PACK+
RVD
CVD
VDD
1
RIN
V4
2
RIN
V3
3
CIN
RIN
V2
4
Sensing Circuit
CIN
VOV
Enable
OUT
Active
Delay Charge/
Discharge Circuit
CIN
RIN
V1
8
5
CIN
VSS
6
PWPD
9
7
CD
CCD
PACK–
Figure 3. Block Diagram
NOTE
In the case of an Open Drain Active Low configuration, an external pull-up resistor is
required on the OUT terminal.
Copyright © 2012, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
CONDITION
VALUE/UNIT
VDD–VSS
–0.3 to 30 V
V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS
–0.3 to 30 V
Supply voltage range
Input voltage range
Output voltage range
OUT–VSS
–0.3 to 30 V
Continuous total power dissipation, PTOT
See package dissipation rating.
Storage temperature range, TSTG
–65 to 150°C
Lead temperature (soldering, 10 s),
TSOLDER
(1)
300°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted)
MAX
UNIT
Supply voltage, VDD (1)
PARAMETER
MIN
3
20
V
Input voltage
range
0
5
V
–40
110
°C
V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS
Operating ambient temperature range, TA
(1)
NOM
See APPLICATION SCHEMATIC.
DC CHARACTERISTICS
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to 110°C and VDD = 3 V
to 20 V (unless otherwise noted).
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Voltage Protection Thresholds
VOV
V(PROTECT) Overvoltage
Detection
VHYS
OV Detection Hysteresis
VOA
OV Detection Accuracy
VOADRIFT
bq294700, RIN = 1 kΩ
4.350
V
bq294701, RIN = 1 kΩ
4.250
V
bq294702, RIN = 1 kΩ
4.300
V
bq294703, RIN = 1 kΩ
4.325
V
bq294704, RIN = 1 kΩ
4.400
V
bq294705, RIN = 1 kΩ
4.450
V
bq2947xy
OV Detection Accuracy
Across Temperature
(1)
400
mV
TA = 25°C
250
–10
300
10
mV
TA = –40°C
–40
40
mV
TA = 0°C
–20
20
mV
TA = 60°C
–24
24
mV
TA = 110°C
–54
54
mV
2
µA
0.1
µA
Supply and Leakage Current
IDD
Supply Current
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
at TA = 25°C (See Figure 14.)
IIN
Input Current at Vx Pins
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
at TA = 25°C (See Figure 14.)
Input Current (ALL Vx
and VDD Input Pins)
Current Consumption at Power down, (V4–V3) =
(V3–V2) = (V2–V1) = (V1–VSS) = 2.30 V at TA =
25°C
ICELL
1
–0.1
1.1
µA
Output Drive OUT, CMOS Active High Versions Only
(1)
6
Future option, contact TI.
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SLUSB15 – SEPTEMBER 2012
DC CHARACTERISTICS (continued)
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to 110°C and VDD = 3 V
to 20 V (unless otherwise noted).
SYMBOL
PARAMETER
CONDITION
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV,
VDD = 14.4 V, IOH = 100 µA
VOUT
Output Drive Voltage,
Active High
MIN
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV,
VDD = 14.4 V,
OUT = 0 V, measured out of OUT pin.
IOUTL
OUT Sink Current (no
OV)
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V,
OUT = VDD, measured into OUT pin .Pull resistor
RPU = 5 kΩ to VDD = 14.4 V
UNIT
V
VDD –
0.3
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V, IOL = 100 µA measured into OUT
pin.
OUT Source Current
(during OV)
MAX
6
If three of four cells are short circuited, only one
cell remains powered and > VOV, VDD = Vx (cell
voltage), IOH = 100 µA
IOUTH
TYP
250
0.5
V
400
mV
4.5
mA
14
mA
400
mV
14
mA
100
nA
2
s
170
ms
Output Drive OUT, CMOS Open Drain Active Low Versions Only
VOUT
Output Drive Voltage,
Active High
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V, IOL = 100 µA measured into OUT
pin.
IOUTL
OUT Sink Current (no
OV)
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V,
OUT = VDD, measured into OUT pin. Pull resistor
RPU = 5 kΩ to VDD = 14.4 V
IOUTLK
OUT pin leakage
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V,
OUT = VDD, measured into OUT pin.
OV Delay Time
CCD = 0.1 µF (see Equation 1)
1
OV Delay Time with CD
pin = 0 V
Delay due to CCD capacitor shorted to ground for
Customer Test Mode
20
250
0.5
Delay Timer
tCD
tCD_GND
Copyright © 2012, Texas Instruments Incorporated
1.5
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TYPICAL CHARACTERISTICS
4.40
0.316
Mean
Min
Max
4.39
4.38
0.315
4.36
VHYS (V)
VOUT (V)
4.37
4.35
4.34
4.33
0.314
0.313
4.32
4.31
4.30
−50
−25
0
25
50
Temperature (°C)
75
100
125
0.312
−50
−25
0
G001
Figure 4. Overvoltage Threshold (OVT) vs.
Temperature
25
50
Temperature (°C)
75
100
125
G002
Figure 5. Hysteresis VHYS vs. Temperature
1.6
1.8
1.5
1.6
1.4
1.4
1.2
ICELL (µA)
IDD (µA)
1.3
1.1
1.0
1.2
1.0
0.9
0.8
0.8
0.7
0.6
−50
−25
0
25
50
Temperature (°C)
75
100
125
0.6
−50
Figure 6. IDD Current Consumption vs.
Temperature at VDD = 16 V
−3.68
8
−3.70
7
25
50
Temperature (°C)
75
100
125
G004
6
−3.74
−3.76
VOUT (V)
IOUT (mA)
0
Figure 7. ICELL vs. Temperature
at VCELL= 9.2 V
−3.72
−3.78
−3.80
−3.82
5
4
3
2
−3.84
1
−3.86
−3.88
−50
−25
0
25
50
Temperature (°C)
75
100
Figure 8. Output Current IOUT vs.
Temperature
8
−25
G003
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125
G005
0
0
5
10
15
VDD (V)
20
25
30
G006
Figure 9. VOUT vs. VDD
Copyright © 2012, Texas Instruments Incorporated
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SLUSB15 – SEPTEMBER 2012
APPLICATION INFORMATION
Figure 10 shows the recommended reference design components.
Pack+
100 Ω
VCELL4
VCELL3
VCELL2
1k
0.1µF
1k
0.1µF
1k
OUT
VDD
1k
0.1µF
V4
CD
V3
VSS
V2
V1
PWPD
0.1 µF
VCELL1
0.1 µF
0.1µF
Pack–
Figure 10. Application Configuration for Active High
NOTE
In the case of an Open Drain Active Low configuration, an external pull-up resistor is
required on the OUT terminal.
Changes to the ranges stated in Table 1 will impact the accuracy of the cell
measurements.
Table 1. Parameters
PARAMETER
EXTERNAL COMPONENT
MIN
NOM
MAX
Voltage monitor filter resistance
RIN
900
1000
4700
UNIT
Ω
Voltage monitor filter capacitance
CIN
0.01
0.1
1.0
µF
Supply voltage filter resistance
RVD
100
1
KΩ
Supply voltage filter capacitance
CVD
0.1
1.0
µF
CD external delay capacitance
CCD
0.1
1.0
µF
NOTE
The device is calibrated using an RIN value = 1 kΩ. Using a value other than this
recommended value changes the accuracy of the cell voltage measurements and VOV
trigger level.
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APPLICATION SCHEMATIC
Pack+
Pack+
100 Ω
100 Ω
VDD
1k
VCELL2
1k
0.1µF
0.1µF
OUT
V4
CD
V3
VSS
V2
V1
CD
V3
VSS
1k
VCELL3
1k
VCELL2
1k
0.1µF
V2
PWPD
VCELL1
OUT
VDD
V4
0.1µF
0.1µF
V1
PWPD
0.1µF
VCELL1
0.1µF
0.1µF
0.1µF
0.1µF
Pack–
Pack–
Figure 11. 2-Series Cell Configuration Active High
with Capacitor-Programmed Delay
Figure 12. 3-Series Cell Configuration Active High
with Capacitor-Programmed Delay
NOTE
In these application examples of 2s and 3s, an external pull-up resistor is required on the
OUT terminal to configure for an Open Drain Active Low operation.
10
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SLUSB15 – SEPTEMBER 2012
CUSTOMER TEST MODE
It is possible to reduce test time for checking the overvoltage function by simply shorting the external CD
capacitor to VSS. In this case, the OV delay would be reduced to the t(CD_GND) value, which has a maximum of
170 ms.
Figure 13 shows the timing for the Customer Test Mode.
OV Condition
V(VCELL)
≤ 170 ms
V(OUT)
CD pin held low
V(CD)
Figure 13. Timing for Customer Test Mode
Figure 14 shows the measurement for current consumption of the product for both VDD and Vx.
IDD
1 VDD
IIN4
I IN3
OUT 8
2 V4
CD 7
3 V3
VSS 6
4 V2
V1 5
ICELL
IIN2
IIN1
ICELL = IDD + IIN1 + I IN2 + IIN3 + I IN4
Figure 14. Configuration for IC Current Consumption Test
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
BQ294700DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
700
BQ294700DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
700
BQ294701DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
701
BQ294701DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
701
BQ294702DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
702
BQ294702DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
702
BQ294703DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
703
BQ294703DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
703
BQ294704DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
704
BQ294704DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
704
BQ294705DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
705
BQ294705DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
705
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
BQ294700DSGR
WSON
DSG
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294700DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294701DSGR
WSON
DSG
8
3000
330.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294701DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294702DSGR
WSON
DSG
8
3000
330.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294702DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294703DSGR
WSON
DSG
8
3000
330.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294703DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294704DSGR
WSON
DSG
8
3000
330.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294704DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294705DSGR
WSON
DSG
8
3000
330.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294705DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ294700DSGR
WSON
DSG
8
3000
367.0
367.0
35.0
BQ294700DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294701DSGR
WSON
DSG
8
3000
367.0
367.0
35.0
BQ294701DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294702DSGR
WSON
DSG
8
3000
367.0
367.0
35.0
BQ294702DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294703DSGR
WSON
DSG
8
3000
367.0
367.0
35.0
BQ294703DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294704DSGR
WSON
DSG
8
3000
367.0
367.0
35.0
BQ294704DSGT
WSON
DSG
8
250
210.0
185.0
35.0
BQ294705DSGR
WSON
DSG
8
3000
367.0
367.0
35.0
BQ294705DSGT
WSON
DSG
8
250
210.0
185.0
35.0
Pack Materials-Page 2
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