Cypress CY25562 Spread spectrum clock generator Datasheet

CY25562
Spread Spectrum Clock Generator
Features
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Applications
• High-resolution VGA controllers
• LCD panels and monitors
• Workstations and servers
50- to 200-MHz operating frequency range
Wide range of spread selections (9)
Accepts clock and crystal inputs
Low power dissipation
3.3V = 70 mw. (Fin = 65 MHz)
Frequency spread disable function
Center spread modulation
Low cycle-to-cycle jitter
Eight-pin SOIC package
Benefits
• Peak EMI reduction by 8 to 16 dB
• Fast time to market
• Cost reduction
Pin Configuration
Block Diagram
300K
Xin/
CLK
XIN/CLK 1
REFERENCE
DIVIDER
1
PD
8 XOUT
Loop
Filter
CP
VDD 2
7 S0
CY25562
Xout 8
MODULATION
CONTROL
FEEDBACK
DIVIDER
vco
VSS 3
SSCLK 4
VDD 2
INPUT
DECODER
LOGIC
VSS 3
DIVIDER
&
MUX
VDD
6 S1
5 SSCC
4 SSCLK
VDD
20 K
20 K
20 K
20 K
VSS
VSS
5
6
7
SSCC
S1
S0
Cypress Semiconductor Corporation
Document #: 38-07392 Rev. *B
•
3901 North First Street
•
San Jose
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CA 95134 • 408-943-2600
Revised December 28, 2002
CY25562
Pin Description
Pin #
Pin Name
Type
Pin Description
1
2
Xin/CLK
I
Clock or Crystal connection input. Refer to Table 1 for input frequency range selection.
VDD
P
Positive power supply.
3
GND
P
Power supply ground.
4
SSCLK
O
SSCG Modulated clock output.
5
SSCC
I
Spread Spectrum Clock Control (Enable/Disable) function. SSCG function is enabled
when input is high and disabled when input is low. This pin is pulled high internally.
6
S1
I
Tri-level Logic input control pin used to select frequency and bandwidth.
Frequency/bandwidth selection and tri-level logic programming. See Figure 1. Pin 6 has
internal resistor divider network to VDD and VSS. Refer to Block Diagram on page 1.
7
S0
I
Tri-level Logic input control pin used to select Frequency and Bandwidth.
Frequency/bandwidth selection and Tri-level Logic programming. See Figure 1. Pin 7 has
internal resistor divider network to VDD and VSS. Refer to Block Diagram on page 1.
8
Xout
O
Oscillator output pin connected to crystal. Leave this pin unconnected If an external
clock drives Xin/CLK.
General Description
The Cypress CY25562 is a Spread Spectrum Clock Generator
(SSCG) IC used for the purpose of reducing electromagnetic
interference (EMI) found in today’s high-speed digital
electronic systems.
select one of the nine available Spread % ranges. Refer
toTable 1 for programming details.
The CY25562 uses a Cypress-proprietary phase-locked loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and frequency modulate the input frequency of the
reference clock. By frequency modulating the clock, the
measured EMI at the fundamental and harmonic frequencies
of clock (SSCLK) is greatly reduced.
A wide range of digitally selectable spread percentages is
made possible by using tri-level (High, Low, and Middle) logic
at the S0 and S1 digital control inputs.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading system performance.
Spread Spectrum Clock Control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
The CY25562 is a very simple and versatile device to use. The
frequency and spread % range is selected by programming S0
and S1 digital inputs. These inputs use three (3) logic states
including High (H), Low (L), and Middle (M) logic levels to
The CY25562 is available in an eight-pin SOIC package with
a 0-to-70°C operating temperature range.
Document #: 38-07392 Rev. *B
The CY25562 is intended for applications with a reference
frequency in the range of 50 to 200 MHz.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Refer to the CY25561 for applications with lower drive requirements and the CY25560 with lower drive and frequency
requirements.
Page 2 of 8
CY25562
Table 1. Frequency and Spread % Selection (Center Spread)
5 0 – 1 0 0 M H z (L o w R a n g e )
In p u t
F re q u e n c y
(M H z )
50 - 60
60 - 70
70 - 80
80 - 100
S1=M
S0=M
(% )
4 .3
4 .0
3 .8
3 .5
S1=M
S0=0
(% )
3 .9
3 .6
3 .4
3 .1
S1=1
S0=0
(% )
3 .3
3 .1
2 .9
2 .7
S1=0
S0=0
(% )
2 .9
2 .6
2 .5
2 .2
S1=0
S0=M
(% )
2 .7
2 .5
2 .4
2 .1
S e le c t th e
F re q u e n c y a n d
C e n te r S p re a d %
d e s ir e d a n d th e n
set S1, S0 as
in d ic a te d .
1 0 0 – 2 0 0 M H z ( H ig h R a n g e )
In p u t
F re q u e n c y
(M H z )
100 – 120
1 2 0 -1 3 0
130 - 140
140 - 150
150 - 160
160 - 170
170 - 180
180 - 190
190 - 200
S1=1
S0=M
(% )
3 .0
2 .7
2 .6
2 .6
2 .5
2 .4
2 .4
2 .3
2 .3
S1=0
S0=1
(% )
2 .4
2 .1
2 .0
2 .0
1 .8
1 .8
1 .8
1 .7
1 .6
S1=1
S0=1
(% )
1 .6
1 .4
1 .3
1 .3
1 .2
1 .2
1 .2
1 .1
1 .1
S1=M
S0=1
(% )
1 .3
1 .1
1 .1
1 .1
1 .0
1 .0
1 .0
0 .9
0 .9
S e le c t th e
F re q u e n c y a n d
C e n te r S p re a d %
d e s ir e d a n d th e n
set S1, S0 as
in d ic a te d .
Tri-level Logic
With binary logic, four states can be programmed with two
control lines, whereas tri-level logic can program nine logic
states using two control lines. Tri-level logic in the CY25562 is
implemented by defining a third logic state in addition to the
standard logic “1” and “0.” Pins 6 and 7 of the CY25562
recognize a logic state by the voltage applied to the respective
pin. These states are defined as “0” (Low), “M” (Middle), and
“1” (One). Each of these states have a defined voltage range
that is interpreted by the CY25562 as “0”, “M,” or “1” logic state.
Refer to Table 2 for voltage ranges for each logic state. The
CY25562 has two equal value resistors connected internally
to pin 6 and pin 7, which produce the default “M” state. Pins 6
and/or 7 can be tied directly to ground or VDD to program a
logic “0” or “1” state, respectively. See examples below.
VDD
CY25562
CY25562
S0
S0 = "M" (N/C)
7
S1 = "0" (GND)
6
SSCC = "1"
5
VDD
CY25562
S0
S0 = "1"
7
S1
S0
S0 = "1"
7
S1 = "1"
6
SSCC = "1"
5
S1
S1 = "0" (GND)
6
SSCC = "1"
5
VDD
S1
VDD
Figure 1. Tri-level Logic Examples
SSCG Theory of Operation
The CY25562 is a PLL-type clock generator using a proprietary Cypress design to modulate the reference clock. By
precisely controlling the bandwidth of the output clock, the
CY25562 becomes a low-EMI clock generator. The theory and
detailed operation of the CY25562 will be discussed in the
following sections.
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of this 50/50-duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics, i.e.; third, fifth, seventh, etc. It is possible to
reduce the amount of energy contained in the fundamental
Document #: 38-07392 Rev. *B
and odd harmonics by increasing the bandwidth of the fundamental clock frequency. Conventional digital clocks have a
very high Q factor, which means that all of the energy at that
frequency is concentrated in a very narrow bandwidth, consequently, higher energy peaks. Regulatory agencies test
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the fundamental and harmonic frequencies, the equipment under test is
able to satisfy agency requirements for EMI. Conventional
methods of reducing EMI use shielding, filtering, multi-layer
PCBs, etc. The CY25562 reduces the peak energy in the clock
by increasing the clock bandwidth, thus lowering the Q.
SSCG
SSCG uses a patented technology of modulating the clock
over a very narrow bandwidth and controlled rate of change,
Page 3 of 8
CY25562
both peak and cycle to cycle. The CY25562 takes a narrow
band digital reference clock in the range of 50–200 MHz and
produces a clock that sweeps between a controlled start (F1)
and stop (F2) frequency at a precise rate of change. To understand what happens to a clock when SSCG is applied,
consider a 200 MHz clock with a 50 % duty cycle. From a
200-MHz clock we know the following:
50 %
Modulation Rate
50 %
Tc = 5.0 ns
Clock Frequency = fc = 200 MHz
Clock Period = Tc = 1/200 MHz.
If this clock is applied to the Xin/CLK pin of the CY25562, the
output clock at pin 4 (SSCLK) will be sweeping back and forth
between two frequencies. These two frequencies, F1 and F2,
are used to calculate to total amount of spread or bandwidth
applied to the reference clock at pin 1. As the clock is making
the transition, sweep, from F1 to F2, the amount of time and
sweep waveform become a very important factor in the
amount of EMI reduction realized from an SSCG clock.
Device
CY25562
The modulation domain analyzer is used to visualize the
sweep waveform and sweep period. Figure 2 shows the
modulation profile of a 200-MHz SSCG clock. Notice that the
actual sweep waveform is not a simple sine or sawtooth
waveform. Figure 2 also shows a scan of the same SSCG
clock using a spectrum analyzer. The spectrum analyzer scan
shows a 10-dB reduction in the peak RF energy when using
the CY25562 SSCG clock.
Cdiv
2332
Spread Spectrum clock generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (Fmax) and
minimum frequency of the clock (Fmin) determine this band of
frequencies. The time required to transition from Fmin to Fmax
and back to Fmin is the period of the Modulation Rate, Tmod.
Modulation Rates of SSCG clocks are generally referred to in
terms of frequency or Fmod = 1/Tmod.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the Modulation Rate. In some SSCG clock
generators, the selected range determines the internal divider
count. In other SSCG clocks, the internal divider count is fixed
over the operating range of the part. The CY25562 has a fixed
divider count of 2332.
(All Ranges)
Example:
Device =
CY25562
Fin
=
200 MHz
Range =
S1 = 1, S0 = 1
Then;
Modulation Rate = Fmod = 200 MHz/2332 = 85.7 kHz.
Modulation Profile
Spectrum Analyzer
Figure 2. SSCG Clock, CY25562, Fin = 200 MHz
Document #: 38-07392 Rev. *B
Page 4 of 8
CY25562
CY25562 Application Schematic
VDD
C3
0.1 uF
2
1
200 MHz Reference Clock
8
VDD
XIN/CLK
4
SSCLK
XOUT
CY25562
6
S1
VDD
5
VDD
SSCC
S0
7
VSS
3
Figure 3. Application Schematic
The schematic in Figure 3 above demonstrates how the
CY25562 is configured in a typical application. This application
is using a 200-MHz reference clock connected to pin 1.
Because an external reference clock is used, pin 8 (Xout) is
left unconnected.
Document #: 38-07392 Rev. *B
This configuration depicts the profile and spectrum scans
shown in Figure 2. Note that S0 = S1 = 1, for a spread of
approximately 1.1%.
Page 5 of 8
CY25562
Absolute Maximum Ratings[1, 2]
Supply Voltage (VDD): .................................... –0.5V to +6.0V
Operating Temperature:...................................... 0°C to 70°C
DC Input Voltage:...................................–0.5V to VDD + 0.5V
Storage Temperature .................................. –65°C to +150°C
Junction Temperature .................................–40°C to +140°C
Static Discharge Voltage(ESD)........................... 2,000V–Min
Table 2. DC Electrical Characteristics VDD = 3.3V, Temp. = 25°C, and CL (Pin 4) = 15 pF unless otherwise noted
Parameter
Description
Conditions
VDD
Power Supply Range
±10%
Min.
Typ.
Max.
Unit
2.97
3.3
3.63
V
VINH
Input High Voltage
S0 and S1 only.
0.85VDD
VDD
VDD
V
VINM
Input Middle Voltage
S0 and S1 only.
0.40VDD
0.50VDD
0.60VDD
V
VINL
Input Low Voltage
S0 and S1 only.
0.0
0.0
0.15VDD
V
VOH1
Output High Voltage
IOH = 6 ma
2.4
VOH2
Output High Voltage
IOH = 20 ma
2.0
VOL1
Output Low Voltage
IOH = 6 ma
VOL2
Output Low Voltage
IOH = 20 ma
1.2
V
Cin1
Input Capacitance
Xin/CLK (Pin 1)
3
4
5
pF
Cin2
Input Capacitance
Xout (Pin 8)
6
8
10
pF
Cin2
Input Capacitance
S0, S1, SSCC (Pins 7,6,5)
3
4
5
pF
IDD1
Power Supply Current
FIN = 65 MHz, CL = 15 pF
23
30
mA
IDD2
Power Supply Current
FIN = 200 MHz, CL =15 pF
53
66
mA
IDD3
Power Supply Current
FIN = 200 MHz, No Load
48
60
mA
V
V
0.4
V
Table 3. Electrical Timing Characteristics VDD = 3.3V, T = 25°C, and CL = 15 pF unless otherwise noted. Rise/Fall @ 0.4 – 2.4V,
Duty @ 1.5V
Parameter
Description
Conditions
ICLKFR
Input Clock Frequency Range Pk–pK = 3.3 Volts
Min
Typ
50
Max
Unit
200
MHz
tRISE
Clock Rise Time (Pin 4)
SSCLK, CL = 15 pF, 200 MHz
0.8
0.9
1.0
ns
tFALL
Clock Fall Time (Pin 4)
SSCLK, CL = 15 pF, 200 MHz
0.8
0.9
1.0
ns
tRISE
Clock Rise Time (Pin 4)
SSCLK, CL = 33 pF, 200 MHz
1.1
1.45
1.8
ns
tFALL
Clock Fall Time (Pin 4)
SSCLK, CL = 33 pF, 200 MHz
1.1
1.5
1.9
ns
DTYin
Input Clock Duty Cycle
XIN/CLK (Pin 1)
30
50
70
%
DTYout
Output Clock Duty Cycle
SSCLK1 (Pin 4)
45
50
55
%
FM1
Frequency Modulation
Fin = 70 MHz
29.5
30.0
30.5
kHz
FM2
Frequency Modulation
Fin = 200 MHz
85.0
85.4
86
kHz
CCJ1
Cycle-to-Cycle Jitter
Fin = 50 MHz, Mod ON
150
175
ps
CCJ2
Cycle-to-Cycle Jitter
Fin = 120 MHz, Mod ON
175
200
ps
CCJ3
Cycle-to-Cycle Jitter
Fin = 200 MHz, Mod ON
250
300
ps
Ordering Information
Part Number
Package Type
Product Flow
CY25562SC
8-pin SOIC
Commercial, 0° to 70°C
CY25562SCT
8-pin SOIC–Tape and Reel
Commercial, 0° to 70°C
Note:
1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Operation at any Absolute Maximum Rating is not implied.
Document #: 38-07392 Rev. *B
Page 6 of 8
CY25562
Package Drawing and Dimensions
8-lead (150-mil) SOIC S8
51-85066-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07392 Rev. *B
Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY25562
Document History Page
Document Title: CY25562 Spread Spectrum Clock Generator
Document Number: 38-07392
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
115526
07/08/02
OXC
New Data Sheet
*A
119444
10/17/02
RGL
Corrected the values in the Absolute Maximum Ratings to match the device.
*B
122703
12/28/02
RBI
Added power up requirements to maximum ratings information.
Document #: 38-07392 Rev. *B
Page 8 of 8
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