TI1 MSP430FR6047IPZ Ultrasonic sensing msp430 microcontrollers for waterâ metering application Datasheet

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MSP430FR6047
SLASEB7 – JUNE 2017
MSP430FR6047 Ultrasonic Sensing MSP430™ Microcontrollers
for Water‑‑Metering Applications
1 Device Overview
1.1
Features
• Best-in-Class Ultrasonic Water-Flow Measurement
With Ultra-Low Power Consumption
– <25-ps Differential Time Of Flight (dTOF)
Accuracy
– High-Precision Time Measurement Resolution of
<5 ps
– Ability to Detect Low Flow Rates (<1 Liter per
Hour)
– Approximately 3-µA Overall Current
Consumption With One Measurement per
Second
• Compliant to and Exceeds ISO4064, OIML R49,
and EN 1434 Accuracy Standards
• Ability to Directly Interface Standard Ultrasonic
Sensors (up to 2 MHz)
• Integrated Analog Front End – Ultrasonic Sensing
Solution (USS) That Includes
– Programmable Pulse Generation (PPG) to
Generate Pulses at Different Frequencies
– Integrated PHY With Low-Impedance Output
Driver (4 Ω) to Control Input and Output
Channels
– High-Performance High-Speed 12-Bit SigmaDelta Analog-to-Digital Converter (ADC) (SDHS)
With Output Data Rates up to 8 MSPS
– Programmable Gain Amplifier (PGA) With
–6.5 dB to 30.8 dB
– High-Performance PLL With Output Range of
68 MHz to 80 MHz
• Metering Test Interface (MTIF)
– Pulse Generator + Pulse Counter
– Pulse Rates up to 1016 Pulses per Second (p/s)
– Count Capacity up to 65525 (16 Bit)
– Operates in LPM3.5 With 200 nA (Typical)
• Low-Energy Accelerator (LEA)
– Operation Independent of CPU
– 4KB of RAM Shared With CPU
– Efficient 256-Point Complex FFT:
Up to 40× Faster Than ARM® Cortex®-M0+
Core
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16‑MHz Clock
– Wide Supply Voltage Range:
1.8 V to 3.6 V (1)
• Optimized Ultra-Low-Power Modes
– Active Mode: Approximately 120 µA/MHz
– Standby Mode With Real-Time Clock (RTC)
(LPM3.5): 450 nA (2)
– Shutdown (LPM4.5): 30 nA
• Ferroelectric Random Access Memory (FRAM)
– Up to 256KB of Nonvolatile Memory
– Ultra-Low-Power Writes
– Fast Write at 125 ns Per Word (64KB in 4 ms)
– Unified Memory = Program + Data + Storage in
One Space
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– 32-Bit Hardware Multiplier (MPY)
– 6-Channel Internal DMA
– RTC With Calendar and Alarm Functions
– Six 16-Bit Timers With up to Seven
Capture/Compare Registers Each
– 32-Bit and 16-Bit Cyclic Redundancy Check
(CRC)
• High-Performance Analog
– 16-Channel Analog Comparator
– 12-Bit SAR ADC Featuring Window Comparator,
Internal Reference, and Sample-and-Hold, up to
20 External Input Channels
– Integrated LCD Driver With Contrast Control for
up to 264 Segments
• Multifunction Input/Output Ports
– All Pins Support Capacitive-Touch Capability
With No Need for External Components
– Accessible Bit-, Byte-, and Word-Wise (in Pairs)
– Edge-Selectable Wake From LPM on All Ports
– Programmable Pullup and Pulldown on All Ports
• Code Security and Encryption
– 128- or 256-Bit AES Security Encryption and
Decryption Coprocessor
– Random Number Seed for Random Number
Generation Algorithms
– IP Encapsulation Protects Memory From
External Access
– FRAM Provides Inherent Security Advantages
(1)
(2)
1
Minimum supply voltage is restricted by SVS levels.
The RTC is clocked by a 3.7-pF crystal.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1
MSP430FR6047
SLASEB7 – JUNE 2017
www.ti.com
• Enhanced Serial Communication
– Up to Four eUSCI_A Serial Communication
Ports
– UART With Automatic Baud-Rate Detection
– IrDA Encode and Decode
– Up to Two eUSCI_B Serial Communication
Ports
– I2C With Multiple-Slave Addressing
– Hardware UART or I2C Bootloader (BSL)
• Flexible Clock System
– Fixed-Frequency DCO With 10 Selectable
Factory-Trimmed Frequencies
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– 32-kHz Crystals (LFXT)
– High-Frequency Crystals (HFXT)
ADVANCE INFORMATION
1.2
•
•
Applications
Ultrasonic Smart Water Meters
Ultrasonic Smart Heat Meters
1.3
• Development Tools and Software (Also See Tools
and Software)
– Ultrasonic Sensing Design Center Graphical
User Interface
– Ultrasonic Sensing Software Library
– EVM430-FR6047 Water Meter Evaluation
Module Board
– MSP-TS430PZ100E Target Socket Board for
100-Pin Package
– Free Professional Development Environments
With EnergyTrace++ Technology
– MSP430Ware™ for MSP430™ Microcontrollers
• Device Comparison Summarizes the Available
Device Variants and Package Options
• For Complete Module Descriptions, See the
MSP430FR58xx, MSP430FR59xx,
MSP430FR68xx, and MSP430FR69xx Family
User's Guide
•
•
Liquid Level Sensing
Water Leak Detection
Description
The Texas Instruments MSP430FR6047 family of ultrasonic sensing and measurement SoCs are
powerful, highly integrated microcontrollers (MCUs) that are optimized for water and heat meters. These
MCUs offer an integrated Ultrasonic Sensing Solution (USS) module, which provides high accuracy for a
wide range of flow rates. The ultrasonic sensing module helps achieve ultra-low-power metering combined
with lower system cost due to maximum integration requiring very few external components.
MSP430FR6047 MCUs implements a high-speed ADC-based signal acquisition followed by optimized
digital signal processing using the integrated Low-Energy Accelerator (LEA) module to deliver a highaccuracy metering solution with ultra-low power optimum for battery-powered metering applications.
The ultrasonic sensing module includes a programmable pulse generator (PPG) and a physical interface
(PHY) with a low-impedance output driver for optimum sensor excitation and accurate impendence
matching to deliver best results for zero-flow drift (ZFD). The module also includes a programmable gain
amplifier (PGA) and a high-speed 12-bit 8-MSPS sigma-delta ADC (SDHS) for accurate signal acquisition
from industry-standard ultrasonic transducers.
Additionally, MSP430FR6047 MCUs integrate other peripherals to improve system integration for
metering. The devices have a metering test interface (MTIF) module to implement pulse generation to
indicate flow measured by the meter. The MSP430FR6047 MCUs also have an on-chip 8-mux LCD driver,
RTC, 12-bit SAR ADC, analog comparator, advanced encryption (AES256), and cyclic redundancy check
(CRC) modules.
MSP430FR6047 MCUs are supported by an extensive hardware and software ecosystem with reference
designs and code examples to get your design started quickly. Development kits for the MSP430FR6047
include the MSP-TS430PZ100E 100-pin target development board and EVM430-FR6047 ultrasonic water
flow meter EVM. TI also provides free software including the ultrasonic sensing design center, ultrasonic
sensing software library and MSP430Ware software.
TI's MSP430 ultra-low-power (ULP) FRAM microcontroller platform combines uniquely embedded FRAM
and a holistic ultra-low-power system architecture, allowing system designers to increase performance
while lowering energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and
endurance of RAM with the nonvolatility of Flash.
2
Device Overview
Copyright © 2017, Texas Instruments Incorporated
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MSP430FR6047
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SLASEB7 – JUNE 2017
Device Information (1) (2)
(1)
(2)
(3)
1.4
PART NUMBER
PACKAGE
BODY SIZE (3)
MSP430FR6047IPZ
LQFP (100)
14 mm × 14 mm
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 9, or see the TI website at www.ti.com.
For a comparison of all available device variants, see Section 3.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Functional Block Diagram
Figure 1-1 shows the functional block diagram of the devices.
P1.x, P2.x P3.x, P4.x
LFXIN,
HFXIN
LFXOUT,
HFXOUT
P5.x, P6.x
2x8
2x8
2x8
PJ.x
P9.x
P7.x, P8.x
2x8
1x8
1x8
Capacitive Touch IO 0/1
MCLK
Comp_E
ACLK
Clock
System
(up to 16
inputs)
SMCLK
DMA
Controller
6 Channel
(up to 16
standard
inputs,
up to 8
differential
inputs)
REF_A
Voltage
Reference
I/O Ports
P1, P2
2x8 I/Os
I/O Ports
P3, P4
2x8 I/Os
I/O Ports
P5, P6
2x8 I/Os
I/O Ports
P7, P8
2x8 I/Os
I/O Ports
P9
1x8 I/Os
PA
1x16 I/Os
PB
1x16 I/Os
PC
1x16 I/Os
PD
1x16 I/Os
PD
1x8 I/Os
I/O Port
PJ
1x8 I/Os
ADVANCE INFORMATION
ADC12_B
MAB
Bus
Control
Logic
MAB
MDB
CPUXV2
incl. 16
Registers
MPU
IP Encap
MDB
FRCTL_A
256KB
128KB
EEM
(S: 3+1)
CRC16
RAM
Power
Mgmt
4KB + 4KB
Tiny RAM
22B
LDO
SVS
Brownout
CRC-16CCITT
AES256
MPY32
CRC32
CRC-32ISO-3309
Security
Encryption,
Decryption
(128, 256)
Watchdog
TA2
TA3
Timer_A
2 CC
Registers
(int)
Timer_A
2 CC
Registers
(int)
LCD_C
(up to
264 Seg:
static,
2 to 8 mux)
MDB
JTAG
Interface
MAB
Spy-Bi-Wire
USS
LEA
Subsystem
Subsystem
TB0
TA0
TA1
TA4
Timer_B
7 CC
Registers
(int, ext)
Timer_A
3 CC
Registers
(int, ext)
Timer_A
3 CC
Registers
(int, ext)
Timer_A
2 CC
Registers
(int, ext)
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
(UART,
IrDA,
SPI)
eUSCI_B0
eUSCI_B1
2
(I C,
SPI)
RTC_C
RTC_A
MTIF
LPM3.5 Domain
CHx_IN, CHx_OUT
MTIF_PIN_EN
USSXTIN, USSXTOUT, USSXT_BOUT
MTIF_OUT_IN
Copyright © 2017, Texas Instruments Incorporated
A.
The device has 8KB of RAM, and 4KB of the RAM is shared with the LEA subsystem.
Figure 1-1. Functional Block Diagram
Device Overview
Copyright © 2017, Texas Instruments Incorporated
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3
MSP430FR6047
SLASEB7 – JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
Device Overview ......................................... 1
Detailed Description ................................... 69
Features .............................................. 1
6.1
Overview
1.2
Applications ........................................... 2
6.2
CPU
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 3
6.3
6.4
Revision History ......................................... 4
Device Comparison ..................................... 5
Terminal Configuration and Functions .............. 6
.......................................... 6
4.2
Pin Attributes ......................................... 7
4.3
Signal Descriptions .................................. 15
4.4
Pin Multiplexing ..................................... 25
4.5
Buffer Type .......................................... 25
4.6
Connection of Unused Pins ......................... 25
Specifications ........................................... 26
5.1
Absolute Maximum Ratings ........................ 26
5.2
ESD Ratings ........................................ 26
5.3
Recommended Operating Conditions ............... 27
4.1
5
6
1.1
Pin Diagram
ADVANCE INFORMATION
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
Active Mode Supply Current Into VCC Excluding
External Current ....................................
Typical Characteristics, Active Mode Supply
Currents .............................................
Low-Power Mode (LPM0, LPM1) Supply Currents
Into VCC Excluding External Current ................
Low-Power Mode (LPM2, LPM3, LPM4) Supply
Currents (Into VCC) Excluding External Current ....
Low-Power Mode With LCD Supply Currents (Into
VCC) Excluding External Current ....................
Low-Power Mode (LPMx.5) Supply Currents (Into
VCC) Excluding External Current ....................
Typical Characteristics, Low-Power Mode Supply
Currents .............................................
Typical Characteristics, Current Consumption per
Module ..............................................
Thermal Resistance Characteristics, LQFP-100
(PZ) .................................................
28
7
29
Interrupt Vector Table and Signatures .............. 74
6.7
Bootloader (BSL) .................................... 77
6.8
JTAG Operation ..................................... 78
6.9
FRAM Controller A (FRCTL_A) ..................... 79
6.10
RAM
6.11
6.12
Tiny RAM ............................................ 79
Memory Protection Unit (MPU) Including IP
Encapsulation ....................................... 79
6.13
Peripherals
6.14
Input/Output Diagrams .............................. 92
6.15
Device Descriptors (TLV) .......................... 136
6.16
Memory Map ....................................... 139
6.17
Identification........................................ 159
8.4
8.5
8.6
8.7
35
35
Timing and Switching Characteristics ............... 36
8.8
9
..........................................
79
80
Device Connection and Layout Fundamentals .... 160
Peripheral- and Interface-Specific Design
Information ......................................... 166
Device and Documentation Support .............. 169
8.3
34
................................................
Applications, Implementation, and Layout ...... 160
8.2
33
Low-Energy Accelerator (LEA) for Signal
Processing .......................................... 70
Operating Modes .................................... 71
8.1
32
69
69
6.6
29
8
69
6.5
7.1
7.2
30
............................................
.................................................
Ultrasonic Sensing Solution (USS) Module .........
...................
Device and Development Tool Nomenclature .....
Tools and Software ................................
Documentation Support ............................
Trademarks ........................................
Electrostatic Discharge Caution ...................
Export Control Notice ..............................
Glossary............................................
Getting Started and Next Steps
169
169
171
172
173
173
173
174
Mechanical, Packaging, and Orderable
Information ............................................. 174
2 Revision History
4
DATE
REVISION
NOTES
June 2017
*
Initial release
Revision History
Copyright © 2017, Texas Instruments Incorporated
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3 Device Comparison
Table 3-1 summarizes the available family members.
DEVICE
FRAM
(KB)
SRAM
(KB)
CLOCK
SYSTEM
LEA
USS
USSXT
MTIF
ADC12_B
Comp_E
MSP430FR6047
256
8
DCO
HFXT
LFXT
Yes
Yes
Yes
16 ext, 2 int ch.
16 ch.
3, 3 (7)
2, 2,2 (8)
MSP430FR60471
256
8
DCO
HFXT
LFXT
Yes
Yes
Yes
16 ext, 2 int ch.
16 ch.
MSP430FR6037
256
8
DCO
HFXT
LFXT
Yes
No
Yes
16 ext, 2 int ch.
MSP430FR60371
256
8
DCO
HFXT
LFXT
Yes
No
Yes
MSP430FR6045
128
8
DCO
HFXT
LFXT
Yes
Yes
MSP430FR6035
128
8
DCO
HFXT
LFXT
Yes
No
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Timer_A (3) Timer_B (4)
eUSCI
AES
BSL
I/Os
PACKAGE
2
Yes
UART
76
100 PZ (LQFP)
4
2
Yes
I2C
76
100 PZ (LQFP)
7
4
2
Yes
UART
76
100 PZ (LQFP)
3, 3 (7)
2, 2,2 (8)
7
4
2
Yes
I2C
76
100 PZ (LQFP)
16 ch.
3, 3 (7)
2, 2,2 (8)
7
4
2
Yes
UART
76
100 PZ (LQFP)
16 ch.
3, 3 (7)
2, 2,2 (8)
7
4
2
Yes
UART
76
100 PZ (LQFP)
A (5)
B (6)
7
4
3, 3 (7)
2, 2,2 (8)
7
16 ch.
3, 3 (7)
2, 2,2 (8)
16 ext, 2 int ch.
16 ch.
Yes
16 ext, 2 int ch.
Yes
16 ext, 2 int ch.
ADVANCE INFORMATION
Table 3-1. Device Comparison (1) (2)
For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having three capture/compare registers and PWM output generators and the second
instantiation having five capture/compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having three capture/compare registers and PWM output generators and the second
instantiation having five capture/compare registers and PWM output generators, respectively.
eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
eUSCI_B supports I2C with multiple slave addresses and SPI.
Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any) whereas Timer TA4 provides internal, external capture/compare inputs and
internal, external PWM outputs.
Device Comparison
Copyright © 2017, Texas Instruments Incorporated
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4 Terminal Configuration and Functions
4.1
Pin Diagram
DVCC3
P7.4/TA0.1/MTIF_OUT_IN
P7.5/TA1.1/MTIF_PIN_EN
P8.0/UCA3STE/TB0.2/DMAE0
P8.1/UCA3CLK/TB0.3/TB0OUTH
P8.2/UCA3SOMI/UCA3RXD/MCLK
P8.3/UCA3SIMO/UCA3TXD/RTCCLK
P7.6/TA4.1/DMAE0/COUT
P7.7/TA0.2/TB0OUTH/COUT
CH1_IN
CH1_OUT
PVSS
PVCC
PVSS
CH0_OUT
CH0_IN
P8.4/UCB1CLK/TA1.2/A10
P8.5/UCB1SIMO/UCB1SDA/A11
P8.6/UCB1SOMI/UCB1SCL/A12
P8.7/UCB1STE/USSXT_BOUT/A13
AVSS5
USSXTIN
USSXTOUT
AVSS1
AVCC1
Figure 4-1 shows the pinout of the 100-pin PZ package.
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
DVSS3
P2.3/TA0.0/UCA0STE/A15/C15
2
74
R33/LCDCAP
P1.0/UCA1CLK/TA1.0/A0/C0/VREF-/VeREF-
3
73
P6.3/R23
P1.1/UCA1STE/TA4.0/A1/C1/VREF+/VeREF+
4
72
P6.2/R13/LCDREF
AVSS2
5
71
P6.1/R03
PJ.4/LFXIN
6
70
P7.3/UCA2STE/TB0.1/COM7/LCDS33
PJ.5/LFXOUT
7
69
P7.2/UCA2CLK/TB0.0/COM6/LCDS34
AVSS3
8
68
P7.1/UCA2SOMI/UCA2RXD/SMCLK/COM5/LCDS35
PJ.6/HFXIN
9
67
P7.0/UCA2SIMO/UCA2TXD/ACLK/COM4/LCDS36
PJ.7/HFXOUT
10
66
P6.7/COM3/LCDS37
AVSS4
11
65
P6.6/COM2/LCDS38
P1.4/TB0.4/UCB0STE/A2/C2
12
64
P6.5/COM1
P1.5/TB0.5/UCB0CLK/A3/C3
13
63
P6.4/COM0
P1.6/UCB0SIMO/UCB0SDA/A4/C4
14
62
P6.0/COUT/LCDS0
P1.7/USSTRG/UCB0SOMI/UCB0SCL/A5/C5
15
61
P5.7/UCB1STE/LCDS1
P2.0/UCA0SIMO/UCA0TXD/A6/C6
16
60
P5.6/UCB1SOMI/UCB1SCL/LCDS2
P2.1/UCA0SOMI/UCA0RXD/A7/C7
17
59
P5.5/TA0CLK/UCB1SIMO/UCB1SDA/LCDS3
P1.2/UCA1SIMO/UCA1TXD/A8/C8
18
58
P5.4/UCB1CLK/LCDS4
P1.3/UCA1SOMI/UCA1RXD/A9/C9
19
57
P5.3/UCA2STE/LCDS5
TEST/SBWTCK
20
56
P5.2/UCA2CLK/LCDS6
RST /NMI/SBWTDIO
21
55
P5.1/UCA2SOMI/UCA2RXD/LCDS7
PJ.0/TDO/ACLK/SRSCG1/DMAE0/C10
22
54
P5.0/UCA2SIMO/UCA2TXD/LCDS8
PJ.1/TDI/TCLK/SMCLK/SRSCG0/TA4CLK/C11
23
53
P4.7/DMAE0/LCDS9
PJ.2/TMS/MCLK/SROSCOFF/TB0OUTH/C12
24
52
DVCC2
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DVSS2
P4.6/TB0CLK/TA4CLK/LCDS10
P4.5/TA0CLK/TA1CLK/LCDS11
P4.4/UCA0SOMI/UCA0RXD/LCDS12
P4.3/UCA0SIMO/UCA0TXD/LCDS13
P4.2/UCA0STE/LCDS14
P4.1/UCA0CLK/LCDS15
P4.0/RTCCLK/LCDS16
P9.3/ACLK/LCDS17
P9.2/MCLK/LCDS18
P9.1/SMCLK/LCDS19
P9.0/TA1.0/LCDS20
P2.7/TA0.0/LCDS21
P3.7/TB0.6/LCDS22
P3.6/TB0.5/LCDS23
P3.5/TB0.4/LCDS24
P3.4/TB0OUTH/LCDS25
P3.3/TB0.3/LCDS26
P3.2/TB0.2/LCDS27
P3.1/TB0.1/LCDS28
P3.0/TB0.0/LCDS29
P2.6/TA4.1/LCDS30
P2.5/TA4.0/LCDS31
P2.4/TA0CLK/TB0CLK/TA1CLK/LCDS32
DVSS1
PJ.3/TCK/RTCCLK/SRCPUOFF/TB0.6/C13
MSP430FR60xxPZ
DVCC1
ADVANCE INFORMATION
P2.2/COUT/UCA0CLK/A14/C14
On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 4-1. MSP430FR604x 100-Pin PZ Package
6
Terminal Configuration and Functions
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4.2
SLASEB7 – JUNE 2017
Pin Attributes
Table 4-1 lists the attributes of each pin.
PIN NUMBER
SIGNAL TYPE (3)
BUFFER TYPE (4)
POWER SOURCE (5)
RESET STATE
AFTER BOR (6)
I/O
LVCMOS
DVCC
OFF
COUT
O
LVCMOS
DVCC
–
UCA0CLK
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
SIGNAL NAME (1)
(2)
P2.2
1
A14
2
3
4
5
6
7
8
9
10
11
(1)
(2)
(3)
(4)
(5)
(6)
C14
I
Analog
DVCC
–
P2.3
I/O
LVCMOS
DVCC
OFF
TA0.0
I/O
LVCMOS
DVCC
–
UCA0STE
I/O
LVCMOS
DVCC
–
A15
I
Analog
DVCC
–
C15
I
Analog
DVCC
–
P1.0
I/O
LVCMOS
DVCC
OFF
UCA1CLK
I/O
LVCMOS
DVCC
–
TA1.0
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
C0
I
Analog
DVCC
–
VREF-
O
Analog
DVCC
–
VeREF-
I
Analog
DVCC
–
P1.1
I/O
LVCMOS
DVCC
OFF
UCA1STE
I/O
LVCMOS
DVCC
–
TA4.0
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
C1
I
Analog
DVCC
–
VREF+
O
Analog
DVCC
–
VeREF+
I
Analog
DVCC
–
A0
A1
AVSS2
PJ.4
LFXIN
P
Power
–
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
–
PJ.5
I/O
LVCMOS
DVCC
OFF
LFXOUT
O
Analog
DVCC
–
AVSS3
P
Power
–
N/A
I/O
LVCMOS
DVCC
–
PJ.6
HFXIN
I
Analog
DVCC
–
PJ.7
I/O
LVCMOS
DVCC
OFF
HFXOUT
O
Analog
DVCC
–
AVSS4
P
Power
–
N/A
ADVANCE INFORMATION
Table 4-1. Pin Attributes
The signal that is listed first for each pin is the reset default pin name.
To determine the pin mux encodings for each pin, see Section 6.14.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)
The power source shown in this table is the I/O power source, which may differ from the module power source.
Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
PIN NUMBER
12
13
14
SIGNAL TYPE (3)
BUFFER TYPE (4)
POWER SOURCE (5)
RESET STATE
AFTER BOR (6)
P1.4
I/O
LVCMOS
DVCC
OFF
TB0.4
I/O
LVCMOS
DVCC
–
UCB0STE
I/O
LVCMOS
DVCC
–
A2
I
Analog
DVCC
–
C2
I
Analog
DVCC
–
P1.5
I/O
LVCMOS
DVCC
OFF
TB0.5
I/O
LVCMOS
DVCC
–
UCB0CLK
SIGNAL NAME (1)
(2)
ADVANCE INFORMATION
I/O
LVCMOS
DVCC
–
A3
I
Analog
DVCC
–
C3
I
Analog
DVCC
–
P1.6
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
–
UCB0SDA
I/O
LVCMOS
DVCC
–
A4
I
Analog
DVCC
–
C4
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
–
UCB0SOMI
I/O
LVCMOS
DVCC
–
UCB0SCL
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
P1.7
USSTRG
15
A5
C5
16
I
Analog
DVCC
–
P2.0
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
–
UCA0SIMO
I/O
LVCMOS
DVCC
–
A6
I
Analog
DVCC
–
C6
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
–
UCA0SOMI
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
P2.1
17
A7
C7
18
I
Analog
DVCC
–
P1.2
I/O
LVCMOS
DVCC
OFF
UCA1TXD
O
LVCMOS
DVCC
–
UCA1SIMO
I/O
LVCMOS
DVCC
–
A8
I
Analog
DVCC
–
C8
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
UCA1RXD
I
LVCMOS
DVCC
–
UCA1SOMI
I/O
LVCMOS
DVCC
–
A9
I
Analog
DVCC
–
C9
I
Analog
DVCC
–
TEST
I
LVCMOS
DVCC
PD
SBWTCK
I
LVCMOS
DVCC
–
RST
I/O
LVCMOS
DVCC
PU
NMI
I
LVCMOS
DVCC
–
I/O
LVCMOS
DVCC
–
P1.3
19
20
21
SBWTDIO
8
Terminal Configuration and Functions
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PIN NUMBER
22
23
24
25
SIGNAL TYPE (3)
BUFFER TYPE (4)
POWER SOURCE (5)
RESET STATE
AFTER BOR (6)
PJ.0
I/O
LVCMOS
DVCC
OFF
TDO
O
LVCMOS
DVCC
–
ACLK
O
LVCMOS
DVCC
–
SRSCG1
O
LVCMOS
DVCC
–
DMAE0
I
LVCMOS
DVCC
–
C10
I
Analog
DVCC
–
PJ.1
I/O
LVCMOS
DVCC
OFF
TDI
I
LVCMOS
DVCC
–
TCLK
I
LVCMOS
DVCC
–
SMCLK
O
LVCMOS
DVCC
–
SRSCG0
O
LVCMOS
DVCC
–
TA4CLK
I
LVCMOS
DVCC
–
C11
I
Analog
DVCC
–
PJ.2
I/O
LVCMOS
DVCC
OFF
TMS
I
LVCMOS
DVCC
–
MCLK
O
LVCMOS
DVCC
–
SROSCOFF
O
LVCMOS
DVCC
–
TB0OUTH
I
LVCMOS
DVCC
–
C12
I
Analog
DVCC
–
PJ.3
I/O
LVCMOS
DVCC
OFF
TCK
I
LVCMOS
DVCC
–
RTCCLK
O
LVCMOS
DVCC
–
SRCPUOFF
O
LVCMOS
DVCC
–
TB0.6
–
SIGNAL NAME (1)
(2)
I/O
LVCMOS
DVCC
C13
I
Analog
DVCC
–
26
DVSS1
P
Power
–
N/A
27
DVCC1
P
Power
–
N/A
P2.4
28
29
30
31
32
33
I/O
LVCMOS
DVCC
OFF
TA0CLK
I
LVCMOS
DVCC
–
TB0CLK
I
LVCMOS
DVCC
–
TA1CLK
I
LVCMOS
DVCC
–
S32
O
Analog
DVCC
–
P2.5
I/O
LVCMOS
DVCC
OFF
TA4.0
I/O
LVCMOS
DVCC
–
S31
O
Analog
DVCC
–
P2.6
I/O
LVCMOS
DVCC
OFF
TA4.1
I/O
LVCMOS
DVCC
–
S30
O
Analog
DVCC
–
P3.0
I/O
LVCMOS
DVCC
OFF
TB0.0
I/O
LVCMOS
DVCC
–
S29
O
Analog
DVCC
–
P3.1
I/O
LVCMOS
DVCC
OFF
TB0.1
O
LVCMOS
DVCC
–
S28
O
Analog
DVCC
–
P3.2
I/O
LVCMOS
DVCC
OFF
TB0.2
O
LVCMOS
DVCC
–
S27
O
Analog
DVCC
–
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
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Table 4-1. Pin Attributes (continued)
PIN NUMBER
34
35
36
37
ADVANCE INFORMATION
38
39
40
41
42
43
44
45
46
47
48
10
SIGNAL TYPE (3)
BUFFER TYPE (4)
POWER SOURCE (5)
RESET STATE
AFTER BOR (6)
P3.3
I/O
LVCMOS
DVCC
OFF
TB0.3
I/O
LVCMOS
DVCC
–
S26
O
Analog
DVCC
–
P3.4
SIGNAL NAME (1)
(2)
I/O
LVCMOS
DVCC
OFF
TB0OUTH
I
LVCMOS
DVCC
–
S25
O
Analog
DVCC
–
P3.5
I/O
LVCMOS
DVCC
OFF
TB0.4
I/O
LVCMOS
DVCC
–
S24
O
Analog
DVCC
–
P3.6
I/O
LVCMOS
DVCC
OFF
TB0.5
I/O
LVCMOS
DVCC
–
S23
O
Analog
DVCC
–
P3.7
I/O
LVCMOS
DVCC
OFF
TB0.6
I/O
LVCMOS
DVCC
–
S22
O
Analog
DVCC
–
P2.7
I/O
LVCMOS
DVCC
OFF
TA0.0
I/O
LVCMOS
DVCC
–
S21
O
Analog
DVCC
–
P9.0
I/O
LVCMOS
DVCC
OFF
TA1.0
I/O
LVCMOS
DVCC
–
S20
O
Analog
DVCC
–
P9.1
I/O
LVCMOS
DVCC
OFF
SMCLK
O
LVCMOS
DVCC
–
S19
O
Analog
DVCC
–
P9.2
I/O
LVCMOS
DVCC
OFF
MCLK
O
LVCMOS
DVCC
–
S18
O
Analog
DVCC
–
P9.3
I/O
LVCMOS
DVCC
OFF
ACLK
O
LVCMOS
DVCC
–
S17
O
Analog
DVCC
–
P4.0
I/O
LVCMOS
DVCC
OFF
RTCCLK
O
LVCMOS
DVCC
–
S16
O
Analog
DVCC
–
P4.1
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
–
S15
O
Analog
DVCC
–
P4.2
I/O
LVCMOS
DVCC
OFF
UCA0STE
I/O
LVCMOS
DVCC
–
S14
O
Analog
DVCC
–
P4.3
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
–
UCA0SIMO
I/O
LVCMOS
DVCC
–
S13
O
Analog
DVCC
–
P4.4
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
–
UCA0SOMI
I/O
LVCMOS
DVCC
–
S12
O
Analog
DVCC
–
Terminal Configuration and Functions
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SLASEB7 – JUNE 2017
PIN NUMBER
SIGNAL NAME (1)
(2)
P4.5
49
50
SIGNAL TYPE (3)
BUFFER TYPE (4)
POWER SOURCE (5)
RESET STATE
AFTER BOR (6)
I/O
LVCMOS
DVCC
OFF
TA0CLK
I
LVCMOS
DVCC
–
TA1CLK
I
LVCMOS
DVCC
–
S11
O
Analog
DVCC
–
P4.6
I/O
LVCMOS
DVCC
OFF
TB0CLK
I
LVCMOS
DVCC
–
TA4CLK
I
LVCMOS
DVCC
–
S10
O
Analog
DVCC
–
51
DVSS2
P
Power
–
N/A
52
DVCC2
P
Power
–
N/A
P4.7
53
54
55
56
57
58
I/O
LVCMOS
DVCC
OFF
DMAE0
I
LVCMOS
DVCC
–
S9
O
Analog
DVCC
–
P5.0
I/O
LVCMOS
DVCC
OFF
UCA2TXD
O
LVCMOS
DVCC
–
UCA2SIMO
I/O
LVCMOS
DVCC
–
S8
O
Analog
DVCC
–
P5.1
I/O
LVCMOS
DVCC
OFF
UCA2RXD
I
LVCMOS
DVCC
–
UCA2SOMI
I/O
LVCMOS
DVCC
–
S7
O
Analog
DVCC
–
P5.2
I/O
LVCMOS
DVCC
OFF
UCA2CLK
I/O
LVCMOS
DVCC
–
S6
O
Analog
DVCC
–
P5.3
I/O
LVCMOS
DVCC
OFF
UCA2STE
I/O
LVCMOS
DVCC
–
S5
O
Analog
DVCC
–
P5.4
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
–
S4
O
Analog
DVCC
–
P5.5
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
–
UCB1SIMO
I/O
LVCMOS
DVCC
–
UCB1SDA
I/O
LVCMOS
DVCC
–
S3
O
Analog
DVCC
–
P5.6
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
–
UCB1SCL
I/O
LVCMOS
DVCC
–
S2
O
Analog
DVCC
–
P5.7
I/O
LVCMOS
DVCC
OFF
UCB1STE
I/O
LVCMOS
DVCC
–
S1
O
Analog
DVCC
–
P6.0
I/O
LVCMOS
DVCC
OFF
COUT
I
LVCMOS
DVCC
–
S0
O
Analog
DVCC
–
P6.4
I/O
LVCMOS
DVCC
OFF
COM0
O
Analog
DVCC
–
TA0CLK
59
60
61
62
63
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
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Table 4-1. Pin Attributes (continued)
PIN NUMBER
64
65
66
67
ADVANCE INFORMATION
68
69
70
71
72
SIGNAL TYPE (3)
BUFFER TYPE (4)
POWER SOURCE (5)
RESET STATE
AFTER BOR (6)
P6.5
I/O
LVCMOS
DVCC
OFF
COM1
O
Analog
DVCC
–
P6.6
I/O
LVCMOS
DVCC
OFF
COM2
O
Analog
DVCC
–
S38
O
Analog
DVCC
–
P6.7
I/O
LVCMOS
DVCC
OFF
COM3
O
Analog
DVCC
–
SIGNAL NAME (1)
(2)
S37
O
Analog
DVCC
–
P7.0
I/O
LVCMOS
DVCC
OFF
UCA2TXD
O
LVCMOS
DVCC
–
UCA2SIMO
I/O
LVCMOS
DVCC
–
ACLK
O
LVCMOS
DVCC
–
COM4
O
Analog
DVCC
–
S36
O
Analog
DVCC
–
P7.1
I/O
LVCMOS
DVCC
OFF
UCA2RXD
I
LVCMOS
DVCC
–
UCA2SOMI
I/O
LVCMOS
DVCC
–
SMCLK
O
LVCMOS
DVCC
–
COM5
O
Analog
DVCC
–
S35
O
Analog
DVCC
–
P7.2
I/O
LVCMOS
DVCC
OFF
UCA2CLK
I/O
LVCMOS
DVCC
–
TB0.0
I/O
LVCMOS
DVCC
–
COM6
O
Analog
DVCC
–
S34
O
Analog
DVCC
–
P7.3
I/O
LVCMOS
DVCC
OFF
UCA2STE
I/O
LVCMOS
DVCC
–
TB0.1
I/O
LVCMOS
DVCC
–
COM7
O
Analog
DVCC
–
S33
O
Analog
DVCC
–
P6.1
I/O
LVCMOS
DVCC
OFF
R03
I/O
Analog
DVCC
–
P6.2
I/O
LVCMOS
DVCC
OFF
R13
I/O
Analog
DVCC
–
I
Analog
-
–
P6.3
I/O
LVCMOS
DVCC
OFF
R23
I/O
Analog
DVCC
–
R33
I/O
Analog
DVCC
-
LCDCAP
I/O
Analog
DVCC
–
P
Power
–
N/A
LCDREF
73
74
75
DVSS3
76
DVCC3
77
78
P
Power
–
N/A
P7.4
I/O
LVCMOS
DVCC
OFF
TA0.1
I/O
LVCMOS
DVCC
–
MTIF_OUT_IN
I/O
LVCMOS
DVCC
–
P7.5
I/O
LVCMOS
DVCC
OFF
TA1.1
I/O
LVCMOS
DVCC
–
I
LVCMOS
DVCC
–
MTIF_PIN_EN
12
Terminal Configuration and Functions
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PIN NUMBER
79
SIGNAL TYPE (3)
BUFFER TYPE (4)
POWER SOURCE (5)
RESET STATE
AFTER BOR (6)
P8.0
I/O
LVCMOS
DVCC
OFF
UCA3STE
I/O
LVCMOS
DVCC
–
TB0.2
I/O
LVCMOS
DVCC
–
SIGNAL NAME (1)
(2)
DMAE0
80
I
LVCMOS
DVCC
–
P8.1
I/O
LVCMOS
DVCC
OFF
UCA3CLK
I/O
LVCMOS
DVCC
–
TB0.3
I/O
LVCMOS
DVCC
–
TB0OUTH
81
82
83
84
I
LVCMOS
DVCC
–
P8.2
I/O
LVCMOS
DVCC
OFF
UCA3RXD
O
LVCMOS
DVCC
–
UCA3SOMI
I/O
LVCMOS
DVCC
–
MCLK
O
LVCMOS
DVCC
–
P8.3
I/O
LVCMOS
DVCC
OFF
UCA3TXD
O
LVCMOS
DVCC
–
UCA3SIMO
I/O
LVCMOS
DVCC
–
RTCCLK
O
LVCMOS
DVCC
–
P7.6
I/O
LVCMOS
DVCC
OFF
TA4.1
I/O
LVCMOS
DVCC
–
DMAE0
I
LVCMOS
DVCC
–
COUT
O
LVCMOS
DVCC
–
P7.7
I/O
LVCMOS
DVCC
OFF
TA0.2
I/O
LVCMOS
DVCC
–
TB0OUTH
I
LVCMOS
DVCC
–
COUT
O
LVCMOS
DVCC
–
85
CH1_IN
I
Analog
PVCC
–
86
CH1_OUT
O
Analog
PVCC
–
87
PVSS
P
Power
–
N/A
88
PVCC
P
Power
–
N/A
89
PVSS
P
Power
–
N/A
90
CH0_OUT
O
Analog
PVCC
–
91
CH0_IN
92
93
94
95
I
Analog
PVCC
–
P8.4
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
–
TA1.2
–
I/O
LVCMOS
DVCC
A10
I
Analog
DVCC
–
P8.5
I/O
LVCMOS
DVCC
OFF
UCB1SIMO
I/O
LVCMOS
DVCC
–
UCB1SDA
–
I/O
LVCMOS
DVCC
A11
I
Analog
DVCC
–
P8.6
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
–
UCB1SCL
I/O
LVCMOS
DVCC
–
A12
I
Analog
DVCC
–
P8.7
I/O
LVCMOS
DVCC
OFF
UCB1STE
I/O
LVCMOS
DVCC
–
USSXT_BOUT
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
A13
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
PIN NUMBER
(7)
SIGNAL NAME (1)
(2)
SIGNAL TYPE (3)
BUFFER TYPE (4)
POWER SOURCE (5)
RESET STATE
AFTER BOR (6)
96
AVSS5
P
Power
–
N/A
97
USSXTIN (7)
I
Analog
1.5V
–
98
USSXTOUT (7)
O
Analog
1.5V
–
99
AVSS1
P
Power
–
N/A
100
AVCC1
P
Power
–
N/A
Do not connect USSXTIN and USSXTOUT pins to AVCC nor to DVCC. USSXTIN does not support bypass mode, so do not drive an
external clock on the USSXTIN pin.
ADVANCE INFORMATION
14
Terminal Configuration and Functions
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4.3
SLASEB7 – JUNE 2017
Signal Descriptions
Table 4-2 describes the signals.
Table 4-2. Signal Descriptions
FUNCTION
PIN
NO.
SIGNAL NAME
PIN TYPE (1)
DESCRIPTION
ADC
A0
3
I
ADC analog input A0
A1
4
I
ADC analog input A1
A2
12
I
ADC analog input A2
A3
13
I
ADC analog input A3
A4
14
I
ADC analog input A4
A5
15
I
ADC analog input A5
A6
16
I
ADC analog input A6
A7
17
I
ADC analog input A7
A8
18
I
ADC analog input A8
A9
19
I
ADC analog input A9
A10
92
I
ADC analog input A10
A11
93
I
ADC analog input A11
A12
94
I
ADC analog input A12
A13
95
I
ADC analog input A13
A14
1
I
ADC analog input A14
A15
2
I
ADC analog input A15
VREF+
4
O
Output of positive reference voltage
VREF-
3
O
Output of negative reference voltage
VeREF+
4
I
Input for an external positive reference voltage to the ADC
3
I
Input for an external negative reference voltage to the ADC
22, 43,
67
O
ACLK output
VeREFACLK
Clock
(1)
HFXIN
9
I
Input for high-frequency crystal oscillator HFXT
HFXOUT
10
O
Output for high-frequency crystal oscillator HFXT
LFXIN
6
I
Input for low-frequency crystal oscillator LFXT
LFXOUT
7
O
Output of low-frequency crystal oscillator LFXT
MCLK
24, 42,
81
O
MCLK output
SMCLK
23, 41,
68
O
SMCLK output
ADVANCE INFORMATION
PZ
I = input, O = output, P = power
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
PIN
NO.
PIN TYPE (1)
DESCRIPTION
PZ
Comparator
ADVANCE INFORMATION
DMA
Debug
C0
3
I
Comparator input C0
C1
4
I
Comparator input C1
C2
12
I
Comparator input C2
C3
13
I
Comparator input C3
C4
14
I
Comparator input C4
C5
15
I
Comparator input C5
C6
16
I
Comparator input C6
C7
17
I
Comparator input C7
C8
18
I
Comparator input C8
C9
19
I
Comparator input C9
C10
22
I
Comparator input C10
C11
23
I
Comparator input C11
C12
24
I
Comparator input C12
C13
25
I
Comparator input C13
C14
1
I
Comparator input C14
C15
2
I
Comparator input C15
COUT
1, 83,
84
O
Comparator output
DMAE0
22, 79,
83
I
External DMA trigger
Spy-Bi-Wire input clock
SBWTCK
20
I
SBWTDIO
21
I/O
Spy-Bi-Wire data input/output
SRCPUOFF
25
O
Low-power debug: CPU Status register bit CPUOFF
SROSCOFF
24
O
Low-power debug: CPU Status register bit OSCOFF
SRSCG0
23
O
Low-power debug: CPU Status register bit SCG0
SRSCG1
22
O
Low-power debug: CPU Status register bit SCG1
TCK
25
I
Test clock
TCLK
23
I
Test clock input
TDI
23
I
Test data input
TDO
22
O
Test data output port
TEST
20
I
Test mode pin, selects digital I/O on JTAG pins
TMS
24
I
Test mode select
P1.0
3
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P1.1
4
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P1.2
18
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P1.3
19
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P1.4
12
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P1.5
13
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P1.6
14
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P1.7
15
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
GPIO
16
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
PIN
NO.
PIN TYPE (1)
DESCRIPTION
P2.0
16
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P2.1
17
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P2.2
1
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P2.3
2
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P2.4
28
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P2.5
29
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P2.6
30
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P2.7
39
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P3.0
31
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P3.1
32
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P3.2
33
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P3.3
34
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P3.4
35
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P3.5
36
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P3.6
37
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P3.7
38
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P4.0
44
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P4.1
45
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P4.2
46
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P4.3
47
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P4.4
48
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P4.5
49
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P4.6
50
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P4.7
53
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
GPIO
GPIO
GPIO
Terminal Configuration and Functions
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ADVANCE INFORMATION
PZ
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Table 4-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
PIN
NO.
PIN TYPE (1)
DESCRIPTION
PZ
P5.0
54
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P5.1
55
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P5.2
56
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P5.3
57
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P5.4
58
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P5.5
59
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P5.6
60
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P5.7
61
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P6.0
62
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P6.1
71
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P6.2
72
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P6.3
73
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P6.4
63
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P6.5
64
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P6.6
65
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P6.7
66
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P7.0
67
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P7.1
68
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P7.2
69
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P7.3
70
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P7.4
77
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P7.5
78
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P7.6
83
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P7.7
84
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
GPIO
ADVANCE INFORMATION
GPIO
GPIO
18
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
PIN
NO.
SIGNAL NAME
PIN TYPE (1)
DESCRIPTION
P8.0
79
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P8.1
80
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P8.2
81
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P8.3
82
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P8.4
92
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P8.5
93
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P8.6
94
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P8.7
95
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P9.0
40
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P9.1
41
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P9.2
42
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
P9.3
43
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
PJ.0
22
I/O
General-purpose digital I/O
PJ.1
23
I/O
General-purpose digital I/O
PJ.2
24
I/O
General-purpose digital I/O
PJ.3
25
I/O
General-purpose digital I/O
PJ.4
6
I/O
General-purpose digital I/O
PJ.5
7
I/O
General-purpose digital I/O
PJ.6
9
I/O
General-purpose digital I/O
PJ.7
10
I/O
General-purpose digital I/O
UCB0SCL
15
I/O
I2C clock for eUSCI_B0 I2C mode
UCB0SDA
14
I/O
I2C data for eUSCI_B0 I2C mode
UCB1SCL
94, 60
I/O
I2C clock for eUSCI_B1 I2C mode
UCB1SDA
93, 59
I/O
I2C data for eUSCI_B1 I2C mode
GPIO
GPIO
GPIO
I2C
Terminal Configuration and Functions
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ADVANCE INFORMATION
PZ
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Table 4-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
PIN
NO.
PIN TYPE (1)
DESCRIPTION
PZ
LCD
ADVANCE INFORMATION
20
COM0
63
O
LCD common output COM0 for LCD backplane
COM1
64
O
LCD common output COM1 for LCD backplane
COM2
65
O
LCD common output COM2 for LCD backplane
COM3
66
O
LCD common output COM3 for LCD backplane
COM4
67
O
LCD common output COM4 for LCD backplane
COM5
68
O
LCD common output COM5 for LCD backplane
COM6
69
O
LCD common output COM6 for LCD backplane
COM7
70
O
LCD common output COM7 for LCD backplane
LCDCAP
74
I/O
LCD capacitor connection
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
LCDREF
72
I
R03
71
I/O
Input/output port of lowest analog LCD voltage (V5)
R13
72
I/O
Input/output port of third most positive analog LCD voltage (V3 or V4)
R23
73
I/O
Input/output port of second most positive analog LCD voltage (V2)
R33
74
I/O
Input/output port of most positive analog LCD voltage (V1)
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
External reference voltage input for regulated LCD voltage
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
PIN
NO.
PIN TYPE (1)
DESCRIPTION
PZ
MTIF
28
O
LCD segment output
S31
29
O
LCD segment output
S30
30
O
LCD segment output
S29
31
O
LCD segment output
S28
32
O
LCD segment output
S27
33
O
LCD segment output
S26
34
O
LCD segment output
S25
35
O
LCD segment output
S24
36
O
LCD segment output
S23
37
O
LCD segment output
S22
38
O
LCD segment output
S21
39
O
LCD segment output
S20
40
O
LCD segment output
S19
41
O
LCD segment output
S18
42
O
LCD segment output
S17
43
O
LCD segment output
S16
44
O
LCD segment output
S15
45
O
LCD segment output
S14
46
O
LCD segment output
S13
47
O
LCD segment output
S12
48
O
LCD segment output
S11
49
O
LCD segment output
S10
50
O
LCD segment output
S9
53
O
LCD segment output
S8
54
O
LCD segment output
S7
55
O
LCD segment output
S6
56
O
LCD segment output
S5
57
O
LCD segment output
S4
58
O
LCD segment output
S3
59
O
LCD segment output
S2
60
O
LCD segment output
S1
61
O
LCD segment output
S0
62
O
LCD segment output
S38
65
O
LCD segment output
S37
66
O
LCD segment output
S36
67
O
LCD segment output
S35
68
O
LCD segment output
S34
69
O
LCD segment output
S33
70
O
LCD segment output
MTIF_PIN_EN
78
I
Meter test interface pin enable
MTIF_OUT_IN
77
I/O
ADVANCE INFORMATION
LCD
S32
Meter test interface input and output
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
PIN
NO.
PIN TYPE (1)
DESCRIPTION
PZ
Power
ADVANCE INFORMATION
RTC
SPI
System
22
AVCC1
100
P
Analog power supply
AVSS1
99
P
Analog ground supply
AVSS2
5
P
Analog ground supply
AVSS3
8
P
Analog ground supply
AVSS4
11
P
Analog ground supply
AVSS5
96
P
Analog ground supply
DVCC1
27
P
Digital power supply
DVCC2
52
P
Digital power supply
DVCC3
76
P
Digital power supply
DVSS1
26
P
Digital ground supply
DVSS2
51
P
Digital ground supply
DVSS3
75
P
Digital ground supply
PVCC
88
P
USS power supply
PVSS
87, 89
P
USS ground supply
RTCCLK
25, 44,
82
O
RTC clock calibration output
UCA0CLK
1, 45
I/O
Clock signal input for eUSCI_A0 SPI slave mode
Clock signal output for eUSCI_A0 SPI master mode
UCA0SIMO
16, 47
I/O
Slave in/master out for eUSCI_A0 SPI mode
UCA0SOMI
17, 48
I/O
Slave out/master in for eUSCI_A0 SPI mode
UCA0STE
2, 46
I/O
Slave transmit enable for eUSCI_A0 SPI mode
UCA1CLK
3
I/O
Clock signal input for eUSCI_A1 SPI slave mode
Clock signal output for eUSCI_A1 SPI master mode
UCA1SIMO
18
I/O
Slave in/master out for eUSCI_A1 SPI mode
UCA1SOMI
19
I/O
Slave out/master in for eUSCI_A1 SPI mode
UCA1STE
4
I/O
Slave transmit enable for eUSCI_A1 SPI mode
UCA2CLK
69, 56
I/O
Clock signal input for eUSCI_A2 SPI slave mode
Clock signal output for eUSCI_A2 SPI master mode
UCA2SIMO
67, 54
I/O
Slave in/master out for eUSCI_A2 SPI mode
UCA2SOMI
68, 55
I/O
Slave out/master in for eUSCI_A2 SPI mode
UCA2STE
70, 57
I/O
Slave transmit enable for eUSCI_A2 SPI mode
UCA3CLK
80
I/O
Clock signal input for eUSCI_A3 SPI slave mode
Clock signal output for eUSCI_A3 SPI master mode
UCA3SIMO
82
I/O
Slave in/master out for eUSCI_A3 SPI mode
UCA3SOMI
81
I/O
Slave out/master in for eUSCI_A3 SPI mode
UCA3STE
79
I/O
Slave transmit enable for eUSCI_A3 SPI mode
UCB0CLK
13
I/O
Clock signal input for eUSCI_B0 SPI slave mode
Clock signal output for eUSCI_B0 SPI master mode
UCB0SIMO
14
I/O
Slave in/master out for eUSCI_B0 SPI mode
UCB0SOMI
15
I/O
Slave out/master in for eUSCI_B0 SPI mode
UCB0STE
12
I/O
Slave transmit enable for eUSCI_B0 SPI mode
UCB1CLK
92, 58
I/O
Clock signal input for eUSCI_B1 SPI slave mode
Clock signal output for eUSCI_B1 SPI master mode
UCB1SIMO
93, 59
I/O
Slave in/master out for eUSCI_B1 SPI mode
UCB1SOMI
94, 60
I/O
Slave out/master in for eUSCI_B1 SPI mode
UCB1STE
95, 61
I/O
Slave transmit enable for eUSCI_B1 SPI mode
NMI
21
I
RST
21
I/O
Nonmaskable interrupt input
Reset input active low
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
PIN
NO.
SIGNAL NAME
PIN TYPE (1)
DESCRIPTION
PZ
TA0.0
2
I/O
TA0 CCR0 capture: CCI0A input, compare: Out0
TA0.0
39
I/O
TA0 CCR0 capture: CCI0B input, compare: Out0
TA0.1
77
I/O
TA0 CCR1 capture: CCI1A input, compare: Out1
TA0.2
84
I/O
TA0 CCR2 capture: CCI2A input, compare: Out2
28, 49,
59
I
TA1.0
3
I/O
TA1 CCR0 capture: CCI0A input, compare: Out0
TA1.0
40
I/O
TA1 CCR0 capture: CCI0B input, compare: Out0
TA1.1
78
I/O
TA1 CCR1 capture: CCI1A input, compare: Out1
TA1 CCR2 capture: CCI2A input, compare: Out2
TA1.2
92
I/O
28, 49
I
TA4.0
4
I/O
TA4 CCR0 capture: CCI0A input, compare: Out0
TA4.0
29
I/O
TA4 CCR0 capture: CCI0B input, compare: Out0
TA4.1
30
I/O
TA4CCR1 capture: CCI1B input, compare: Out1
TA4.1
83
I/O
TA4 CCR1 capture: CCI1A input, compare: Out1
23, 50
I
TB0.0
31
I/O
TB0 CCR0 capture: CCI0B input, compare: Out0
TB0.0
69
I/O
TB0 CCR0 capture: CCI0A input, compare: Out0
TB0.1
32
I/O
TB0 CCR1 capture: CCI1A input, compare: Out1
TB0.1
70
O
TB0 CCR1 compare: Out1
TB0.2
33
I/O
TB0 CCR2 capture: CCI2A input, compare: Out2
TB0.2
79
O
TB0 CCR2 compare: Out2
TB0.3
34
I/O
TB0 CCR3 capture: CCI3A input, compare: Out3
TB0.3
80
I/O
TB0 CCR3 capture: CCI3B input, compare: Out3
TB0.4
12
I/O
TB0 CCR4 capture: CCI4A input, compare: Out4
TB0.4
36
I/O
TB0 CCR4 capture: CCI4B input, compare: Out4
TB0.5
13
I/O
TB0 CCR5 capture: CCI5A input, compare: Out5
TB0.5
37
I/O
TB0CCR5 capture: CCI5B input, compare: Out5
TB0.6
25
I/O
TB0 CCR6 capture: CCI6B input, compare: Out6
TB0 CCR6 capture: CCI6A input, compare: Out6
TA1CLK
TA4CLK
Timer
TB0.6
UART
TA0 input clock
TA1 input clock
ADVANCE INFORMATION
TA0CLK
TA4 input clock
38
I/O
TB0CLK
28, 50
I
TB0 clock input
TB0OUTH
24, 35,
80, 84
I
Switch all PWM outputs high impedance input – TB0
UCA0RXD
17, 48
I
Receive data for eUSCI_A0 UART mode
UCA0TXD
16, 47
O
Transmit data for eUSCI_A0 UART mode
UCA1RXD
19
I
Receive data for eUSCI_A1 UART mode
UCA1TXD
18
O
Transmit data for eUSCI_A1 UART mode
UCA2RXD
68, 55
I
Receive data for eUSCI_A2 UART mode
UCA2TXD
67, 54
O
Transmit data for eUSCI_A2 UART mode
UCA3RXD
81
I
Receive data for eUSCI_A3 UART mode
UCA3TXD
82
O
Transmit data for eUSCI_A3 UART mode
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
PIN
NO.
PIN TYPE (1)
DESCRIPTION
PZ
USS
USSTRG
15
I
USS trigger
USSXTIN
97
I
Input for an oscillator USSXTT
USSXTOUT
98
O
Output for an oscillator USSXT
USSXT_BOUT
95
O
Buffered output clock of USSXT
CH0_IN
91
I
USS channel 0 RX
CH0_OUT
90
I/O
USS channel 0 TX
CH1_IN
85
I
USS channel 1 RX
CH1_OUT
86
I/O
USS channel 1 TX
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Terminal Configuration and Functions
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SLASEB7 – JUNE 2017
Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and diagrams of the
multiplexed ports, see Section 6.14.
4.5
Buffer Type
Table 4-3 describes the buffer types that are referenced in Table 4-1.
Table 4-3. Buffer Type
HYSTERESIS
PULLUP (PU)
OR
PULLDOWN (PD)
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
Analog (1)
3.0 V
N
N/A
N/A
N/A
LVCMOS
3.0 V
Y (2)
Programmable
See GeneralPurpose I/Os
See Typical
Characteristics
– Outputs
Power
(DVCC) (3)
3.0 V
N
N/A
N/A
N/A
Power
(AVCC) (3)
3.0 V
N
N/A
N/A
N/A
Power
(PVCC) (3)
3.0 V
N
N/A
N/A
N/A
0V
N
N/A
N/A
N/A
Power (DVSS
and AVSS) (3)
(1)
(2)
(3)
OTHER
CHARACTERISTICS
See analog modules in
Specifications for details
SVS enables hysteresis on
DVCC
This is a switch, not a buffer.
Only for input pins
This is supply input, not a buffer.
4.6
Connection of Unused Pins
Table 4-4 lists the correct termination of all unused pins.
Table 4-4. Connection of Unused Pins (1)
PIN
POTENTIAL
AVCC
DVCC
PVCC
DVCC
AVSS
DVSS
PVSS
DVSS
USS_CHx_IN,
USS_CHx_OUT
DVSS
USSXTIN
DVSS
USSXTOUT
Open
Px.0 to Px.7
Open
Switched to port function, output direction (PxDIR.n = 1)
RST/NMI
DVCC or VCC
47-kΩ pullup or internal pullup selected with 10-nF (2.2-nF (2)) pulldown
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If these pins are not used,
these should be switched to port function, output direction. When used as JTAG pins, these pins
should remain open.
TEST
Open
This pin always has an internal pulldown enabled.
(1)
(2)
COMMENT
Must not be connected to DVCC, AVCC, or PVCC.
For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.
The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools like FET interfaces or GANG programmers.
Terminal Configuration and Functions
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NOMINAL
VOLTAGE
BUFFER TYPE
(STANDARD)
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5 Specifications
5.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Voltage applied at DVCC and AVCC pins to VSS
–0.3
4.1
UNIT
V
Voltage applied at DVCC, AVCC, and PVCC pins to VSS
–0.3
4.1
V
Voltage difference between DVCC and AVCC pins (2)
±0.3
V
Voltage difference between DVCC, AVCC, and PVCC pins (2)
±0.3
V
Voltage applied to CHx_IN (USS SAPH module)
–0.3
1.65
V
Voltage applied to CHx_IN (duty cycle of 10% over 1 ms) (USS SAPH module)
–0.3
1.8
V
Voltage applied to USSXTIN (USSXTOUT)
–0.3
1.5
V
–0.3
VCC + 0.3 V
(4.1 V Max)
V
±2
mA
–40
125
°C
Voltage applied to any other pin
(3)
Diode current at any device pin
Storage temperature, Tstg
ADVANCE INFORMATION
(1)
(2)
(3)
(4)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
26
Electrostatic
discharge
All terminals
except CHx_OUT
On CHx_OUT
terminals
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
Specifications
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SLASEB7 – JUNE 2017
Recommended Operating Conditions
TYP data are based on VCC = 3.0 V and TA = 25°C (unless otherwise noted)
MIN
(1) (2) (3) (4)
VCC
Supply voltage range applied at all DVCC and AVCC pins
VCC
Supply voltage range applied at PVCC pin (1)
VSS
Supply voltage applied at all DVSS, AVSS, and PVSS pins.
TA
Operating free-air temperature
CDVCC
Capacitor value at DVCC (6)
fSYSTEM
LEA processor frequency
fACLK
Maximum ACLK frequency
fSMCLK
MAX
3.6
V
3.6
V
85
°C
0
V
1 – 20%
µF
No FRAM wait states
(NWAITSx = 0)
0
8
With FRAM wait states
(NWAITSx = 1) (9)
0
16 (10)
0
16 (10)
Maximum SMCLK frequency
UNIT
2.2
1.8
–40
Processor frequency (maximum MCLK frequency) (7)
fLEA
NOM
(5)
16
(8)
MHz
50
kHz
(10)
MHz
TI recommends powering the AVCC, DVCC, and PVCC pins from the same source. At a minimum, during power up, power down, and
device operation, the voltage difference among AVCC, DVCC, PVCC must not exceed the limits specified under Absolute Maximum
Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
(2) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
(3) Modules may have a different supply voltage range specification. See the specification of the respective modules in this data sheet.
(4) The USS module must be disabled if AVCC and DVCC are lower than 2.2 V.
(5) The minimum supply voltage is defined by the supervisor SVS levels. See the PMM SVS threshold parameters for the exact values.
(6) As a decoupling capacitor for each supply pin pair (DVCC and DVSS, AVCC and AVSS), place a low-ESR ceramic 100-nF (minimum)
capacitor as close as possible to the respective pin pairs (within a few millimeters). For the PVCC and PVSS pair, place a low-ESR
ceramic 22-µF (minimum) capacitor as close as possible to the pin pair (within a few millimeters).
(7) Modules may have a different maximum input clock specification. See the specification of each module in this data sheet.
(8) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted.
(9) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always excecuted
without wait states.
(10) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted. If a clock source with a
higher typical value is used, the clock must be divided in the clock system.
Specifications
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Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
1 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
IAM, FRAM_UNI
(Unified memory) (3)
(4) (5)
MAX
4 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
1970
µA
FRAM
0% cache hit
ratio
3.0 V
420
1455
2850
2330
3000
µA
ADVANCE INFORMATION
3.0 V
275
855
IAM,
FRAM(66%)
(4) (5)
FRAM
66% cache hit
ratio
3.0 V
220
IAM,
FRAM(75%)
(4) (5)
FRAM
75% cache hit
ratio
3.0 V
192
IAM,
FRAM(100%
FRAM
100% cache hit
ratio
3.0 V
125
IAM,
RAM
RAM
3.0 V
140
RAM
3.0 V
90
(5)
(6)
(7)
28
MAX
1550
FRAM
50% cache hit
ratio
(3)
(4)
TYP
1275
(4) (5)
(1)
(2)
MAX
665
FRAM(50%)
(7) (5)
TYP
UNIT
225
IAM,
(6) (5)
MAX
16 MHz
1 WAIT STATE
(NWAITSx = 1)
3.0 V
FRAM(0%)
IAM, RAM only
TYP
12 MHz
1 WAIT STATE
(NWAITSx = 1)
FRAM
IAM,
(4) (5)
MAX
8 MHz
0 WAIT
STATES
(NWAITSx = 0)
261
182
1022
1650
1888
1770
2041
2265
2606
µA
650
1240
1443
1490
1735
1880
2197
µA
535
1015
1170
1290
1490
1620
1870
µA
237
450
670
790
323
590
880
1070
292
540
830
1020
µA
µA
1313
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO = 24 MHz and
fMCLK = fSMCLK = fDCO / 2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio, fMCKL,eff = fMCLK / [1 × (1 – 0.75) + 1] = fMCLK / 1.25.
Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents the number of cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three
of every four accesses is from cache, and the remaining are FRAM accesses.
See for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best linear fit
using the typical data shown in Section 5.4.
Program and data reside entirely in RAM. All execution is from RAM.
Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Specifications
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Typical Characteristics, Active Mode Supply Currents
3000
I(AM,0%)
I(AM,50%)
2500
I(AM,66%)
Active Mode Current (µA)
I(AM,75%)
2000
I(AM,100%)
I(AM,75%)[µA] = 103 × f[MHz] + 68
I(AM,RAMonly)
1500
1000
500
0
1
2
3
4
5
6
7
8
9
MCLK Frequency (MHz)
A.
B.
I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hitto-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of FRAM
accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are FRAM
accesses.
I(AM, RAM only): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Figure 5-1. Typical Active Mode Supply Currents, No Wait States
5.6
Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
ILPM1
(1)
(2)
2.2 V
80
3.0 V
95
2.2 V
40
3.0 V
40
4 MHz
MAX
TYP
8 MHz
MAX
115
135
70
125
TYP
12 MHz
MAX
180
170
190
TYP
16 MHz
MAX
276
245
286
TYP
UNIT
MAX
250
340
265
70
136
230
205
70
136
235
210
316
250
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The current for the watchdog timer clocked by SMCLK is included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO = 24 MHz and
fMCLK = fSMCLK = fDCO / 2.
Specifications
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Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEMPERATURE
PARAMETER
VCC
–40°C
TYP
25°C
MAX
TYP
60°C
MAX
TYP
85°C
MAX
TYP
UNIT
MAX
ADVANCE INFORMATION
ILPM2,XT12
Low-power mode 2, 12-pF
crystal (1) (2) (3)
2.2 V
0.8
1.3
4.1
10.8
3V
0.8
1.3
4.1
10.8
ILPM2,XT3.7
Low-power mode 2, 3.7-pF
crystal (1) (4) (3)
2.2 V
0.6
1.2
4.0
10.7
3V
0.6
1.2
4.0
10.7
ILPM2,VLO
Low-power mode 2, VLO,
includes SVS (5)
2.2 V
0.5
1.0
3.8
10.5
3V
0.5
1.0
3.8
10.5
Low-power mode 3, 12-pF
crystal, includes SVS (1) (2)
2.2 V
0.8
1.0
2.2
4.5
ILPM3,XT12
3V
0.8
1.0
2.2
4.5
Low-power mode 3, 3.7-pF
crystal, excludes SVS (1) (4)
2.2 V
0.5
0.7
2.1
4.4
7.4
ILPM3,XT3.7
3V
0.5
0.7
2.1
4.4
7.4
ILPM3,VLO
Low-power mode 3,
VLO, excludes SVS (8)
2.2 V
0.4
0.5
1.9
4.2
9.5
3V
0.4
0.5
1.9
4.2
Low-power mode 3,
VLO, excludes SVS, RAM
powered-down
completely (8)
2.2 V
0.36
0.47
ILPM3,VLO,
3V
0.36
0.47
Low-power mode 4,
includes SVS (9)
2.2 V
0.5
3V
0.5
RAMoff
ILPM4,SVS
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
30
(6)
(7)
1.0
0.6
0.8
1.2
1.1
1.2
0.6
1.4
2.9
2.6
1.4
2.6
1.9
4.3
1.9
4.3
µA
µA
µA
9.9
µA
µA
µA
7.9
µA
9.5
µA
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2), fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2), fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Low-power mode 3, 12-pF crystal including SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and additional idle current.
See the idle currents specified for the respective peripheral groups.
Low-power mode 3, 3.7-pF crystal excluding SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and additional idle current.
See the idle currents specified for the respective peripheral groups.
Low-power mode 3, VLO excluding SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). RAM disabled (RCCTL0 = 5A55h). Current for
brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and additional idle current.
See the idle currents specified for the respective peripheral groups.
Low-power mode 4 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and additional idle current.
See the idle currents specified for the respective peripheral groups.
Specifications
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Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEMPERATURE
VCC
–40°C
TYP
25°C
MAX
60°C
TYP
MAX
TYP
1.1
85°C
MAX
UNIT
TYP
MAX
1.7
4.0
9.3
1.7
4.0
ILPM4
Low-power mode 4,
excludes SVS (10)
2.2 V
0.3
0.4
3V
0.3
0.4
Low-power mode 4,
excludes SVS, RAM
powered-down
completely (10)
2.2 V
0.3
0.37
ILPM4,RAMoff
3V
0.3
0.37
IIDLE,GroupA
Additional idle current if
one or more modules from
Group A (see Table 6-3)
are activated in LPM3 or
LPM4
3V
0.02
0.3
µA
IIDLE,GroupB
Additional idle current if
one or more modules from
Group B (see Table 6-3)
are activated in LPM3 or
LPM4
3V
0.02
0.35
µA
IIDLE,GroupC
Additional idle current if
one or more modules from
Group C (see Table 6-3)
are activated in LPM3 or
LPM4
3V
0.02
0.38
µA
1.0
1.2
1.2
2.8
2.5
µA
7.8
2.5
µA
(10) Low-power mode 4 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and additional idle current.
See the idle currents specified for the respective peripheral groups.
Specifications
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Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEMPERATURE (TA)
PARAMETER
VCC
–40°C
TYP
25°C
MAX
TYP
60°C
MAX
TYP
85°C
MAX
TYP
ILPM3,XT12
LCD,
ext. bias
LPM3 current, 12-pF
crystal, LCD 4-mux mode,
external biasing, excludes
SVS (1) (2)
3.0 V
0.9
1.1
ILPM3,XT12
LCD,
int. bias
LPM3 current, 12-pF
crystal, LCD 4-mux mode,
internal biasing, charge
pump disabled, excludes
SVS (1) (3)
3.0 V
2.6
2.8
2.2 V
6.3
6.5
8.0
10.0
ILPM3,XT12
LCD,CP
LPM3 current, 12-pF
crystal, LCD 4-mux mode,
internal biasing, charge
pump enabled, 1/3 bias,
excludes SVS (1) (4)
3.0 V
5.9
6.1
7.8
9.5
(1)
ADVANCE INFORMATION
(2)
(3)
(4)
32
2.5
3.8
3.8
UNIT
MAX
5.1
5.6
6.4
µA
12.8
µA
µA
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and additional idle current
(the idle current of the group containing LCD module already included). See the idle currents specified for the respective peripheral
groups.
LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
Specifications
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5.9
SLASEB7 – JUNE 2017
Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEMPERTURE (TA)
VCC
–40°C
TYP
25°C
MAX
TYP
ILPM3.5,XT12
LPM3.5, 12-pF crystal
including SVS (1) (2) (3)
2.2 V
0.45
0.5
3.0 V
0.45
0.5
ILPM3.5,XT3.7
LPM3.5, 3.7-pF crystal
excluding SVS (1) (4) (5)
2.2 V
0.3
3.0 V
0.3
ILPM4.5,SVS
LPM4.5, including SVS (6)
2.2 V
ILPM4.5
LPM4.5, excluding SVS (7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
60°C
MAX
TYP
85°C
MAX
TYP
0.55
0.75
0.55
0.75
0.35
0.4
0.65
0.35
0.4
0.65
0.23
0.2
0.28
0.4
3.0 V
0.23
0.2
0.28
0.4
2.2 V
0.035
0.045
0.075
0.15
3.0 V
0.035
0.045
0.075
0.15
2
UNIT
MAX
μA
μA
μA
μA
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
LPM3.5, 1-pF crystal including SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
LPM3.5, 3.7-pF crystal excluding SVS test conditions:
Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
LPM4.5 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
LPM4.5 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Specifications
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5.10 Typical Characteristics, Low-Power Mode Supply Currents
3
3
3.0 V, SVS off
3.0 V, SVS off
2.2 V, SVS off
2.2 V, SVS off
3.0 V, SVS on
2.5
3.0 V, SVS on
2.5
2.2 V, SVS on
LPM4 Supply Current (µA)
LPM3 Supply Current (µA)
2.2 V, SVS on
2
1.5
1
0.5
2
1.5
1
0.5
0
0
-25
0
25
50
75
100
-50
-25
0
25
Temperature (°C)
50
75
100
Temperature (°C)
Figure 5-2. LPM3 Supply Current vs Temperature (LPM3,XT3.7)
Figure 5-3. LPM4 Supply Current vs Temperature (LPM4,SVS)
0.7
0.7
3.0 V, SVS off
3.0 V, SVS off
2.2 V, SVS off
0.6
2.2 V, SVS off
0.6
LPM4.5 Supply Current (µA)
3.0 V, SVS on
LPM3.5 Supply Current (µA)
ADVANCE INFORMATION
-50
0.5
0.4
0.3
0.2
0.1
2.2 V, SVS on
0.5
0.4
0.3
0.2
0.1
0
0
-50
-25
0
25
50
75
100
-50
-25
Temperature (°C)
25
50
75
100
Temperature (°C)
Figure 5-4. LPM3.5 Supply Current vs Temperature
(LPM3.5,XT3.7)
34
0
Figure 5-5. LPM4.5 Supply Current vs Temperature (LPM4.5)
Specifications
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5.11 Typical Characteristics, Current Consumption per Module (1)
MODULE
TEST CONDITIONS
Timer_A
Timer_B
eUSCI_A
eUSCI_B
UART mode
REFERENCE CLOCK
MIN
TYP
Module input clock
2.5
Module input clock
3.8
Module input clock
SPI mode
SPI mode
RTC_C
32 kHz
μA/MHz
7.0
4.4
4.8
4.4
UNIT
μA/MHz
6.3
4.4
Module input clock
I2C mode, 100 kbaud
MAX
μA/MHz
μA/MHz
100
nA
MPY
Only from start to end of operation
MCLK
28
μA/MHz
CRC16
Only from start to end of operation
MCLK
3.3
μA/MHz
CRC32
Only from start to end of operation
MCLK
3.3
μA/MHz
LEA
MTIF
256-point complex FFT, data = zero
Generator and counter are enabled at 256 Hz,
no terminal activity
MCLK
LFXT
78
86
66
μA/MHz
0.20
uA
For other module currents not listed here, see the module-specific parameter sections.
ADVANCE INFORMATION
(1)
256-point complex FFT, data = nonzero
5.12 Thermal Resistance Characteristics, LQFP-100 (PZ) (1)
THERMAL METRIC (2)
VALUE (3)
UNIT
RθJA
Junction-to-ambient thermal resistance, still air
49.8
°C/W
RθJC(TOP)
Junction-to-case (top) thermal resistance
9.7
°C/W
RθJB
Junction-to-board thermal resistance
26.0
°C/W
ΨJB
Junction-to-board thermal characterization parameter
25.7
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.2
°C/W
(1)
(2)
(3)
N/A = not applicable
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Specifications
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5.13 Timing and Switching Characteristics
5.13.1 Power Supply Sequencing
TI recommends powering the AVCC, DVCC, and PVCC pins from the same source. At a minimum, during
power up, power down, and device operation, the voltage difference among AVCC, DVCC, and PVCC
must not exceed the limits specified in Absolute Maximum Ratings. Exceeding the specified limits may
cause malfunction of the device including erroneous writes to RAM and FRAM.
Table 5-1 lists the power ramp requirements for brownout and power up.
Table 5-1. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VVCC_BOR–
Brownout power-down level
VVCC_BOR+
Brownout power-up level (1)
(1)
ADVANCE INFORMATION
(2)
TEST CONDITIONS
(1)
| dDVCC/dt | < 3 V/s
| dDVCC/dt | < 3 V/s (2)
MIN
MAX
UNIT
0.7
1.66
V
0.79
1.68
V
Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
The brownout levels are measured with a slowly changing supply.
Table 5-2 lists the characteristics of the SVS.
Table 5-2. SVS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISVSH,LPM
SVSH current consumption, low-power modes
170
300
nA
VSVSH–
SVSH power-down level
1.75
1.80
1.85
V
VSVSH+
SVSH power-up level
1.77
1.88
1.99
V
VSVSH_hys
SVSH hysteresis
120
mV
tPD,SVSH, AM
SVSH propagation delay, active mode
10
µs
36
40
dVVcc/dt = –10 mV/µs
Specifications
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5.13.2 Reset Timing
Table 5-3 lists the requirements for the reset input.
Table 5-3. Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(RST)
(1)
External reset pulse duration on RST
VCC
(1)
MIN
2.2 V, 3.0 V
TYP
MAX
2
UNIT
µs
Not applicable if the RST/NMI pin is configured as NMI.
5.13.3 Clock Specifications
Table 5-4 lists the characteristics of the low-frequency oscillator.
Table 5-4. Low-Frequency Crystal Oscillator, LFXT
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
IVCC.LFXT
Current consumption
TEST CONDITIONS
VCC
MIN
180
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
TA = 25°C, CL,eff = 6 pF, ESR ≈ 40 kΩ
185
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
TA = 25°C, CL,eff = 9 pF, ESR ≈ 40 kΩ
fLFXT
LFXT oscillator crystal
frequency
LFXTBYPASS = 0
DCLFXT
LFXT oscillator duty cycle
Measured at ACLK,
fLFXT = 32768 Hz
fLFXT,SW
LFXT oscillator logic-level
square-wave input frequency
LFXTBYPASS = 1 (2)
DCLFXT, SW
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
OALFXT
Oscillation allowance for
LF crystals (4)
(2)
(3)
(4)
MAX
3.0 V
225
330
32768
30%
(3)
UNIT
nA
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF, ESR ≈ 40 kΩ
(1)
TYP
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF, ESR ≈ 44 kΩ
10.5
Hz
70%
32.768
30%
50
kHz
70%
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32768 Hz, CL,eff = 6 pF
210
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
300
kΩ
To improve EMI on the LFXT oscillator, observe the following guidelines:
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
• Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF
• For LFXTDRIVE = {1}, CL,eff = 6 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 9 pF
• For LFXTDRIVE = {3}, 9 pF ≤ CL,eff ≤ 12.5 pF
Specifications
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Table 5-4. Low-Frequency Crystal Oscillator, LFXT (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
CLFXIN
Integrated load capacitance at
LFXIN terminal (5) (6)
2
pF
CLFXOUT
Integrated load capacitance at
LFXOUT terminal (5) (6)
2
pF
tSTART,LFXT
fFault,LFXT
(5)
(6)
ADVANCE INFORMATION
(7)
(8)
(9)
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF
Start-up time (7)
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
800
3.0 V
ms
1000
Oscillator fault frequency (8) (9)
0
3500
Hz
This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT is the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications may set the
flag. A static condition or stuck at fault condition will set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-5 lists the characteristics of the high-frequency oscillator.
Table 5-5. High-Frequency Crystal Oscillator, HFXT
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
IDVCC.HFXT
HFXT oscillator crystal current
HF mode at typical ESR
TEST CONDITIONS
VCC
MIN
75
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1,
TA = 25°C, CL,eff = 18 pF, typical ESR, Cshunt
120
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2,
HFFREQ = 2,
TA = 25°C, CL,eff = 18 pF, typical ESR, Cshunt
HFXTBYPASS = 0, HFFREQ = 1 (2)
fHFXT
DCHFXT
(1)
(2)
(3)
38
HFXT oscillator duty cycle
(3)
MAX
3.0 V
190
250
4
8
(3)
8.01
16
HFXTBYPASS = 0, HFFREQ = 3 (3)
16.01
24
HFXTBYPASS = 0, HFFREQ = 2
Measured at SMCLK, fHFXT = 16 MHz
UNIT
μA
fOSC = 24 MHz
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3,
TA = 25°C, CL,eff = 18 pF, typical ESR, Cshunt
HFXT oscillator crystal
frequency, crystal mode
TYP
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1 (2),
TA = 25°C, CL,eff = 18 pF, typical ESR, Cshunt
40%
50%
MHz
60%
To improve EMI on the HFXT oscillator, observed the following guidelines:
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
• Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
HFFREQ = {0} is not supported for HFXT crystal mode of operation.
Maximum frequency of operation of the entire device cannot be exceeded.
Specifications
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Table 5-5. High-Frequency Crystal Oscillator, HFXT (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
fHFXT,SW
TEST CONDITIONS
HFXT oscillator logic-level
square-wave input frequency,
bypass mode
SW
OAHFXT
HFXT oscillator logic-level
square-wave input duty cycle
Oscillation allowance for
HFXT crystals (5)
tSTART,HFXT Start-up time (6)
MIN
TYP
MAX
(3)
0.9
4
HFXTBYPASS = 1, HFFREQ = 1 (4)
(3)
4.01
8
(4) (3)
8.01
16
16.01
24
40%
60%
HFXTBYPASS = 1, HFFREQ = 2
HFXTBYPASS = 1, HFFREQ = 3 (4)
DCHFXT,
VCC
HFXTBYPASS = 1, HFFREQ = 0 (4)
(3)
HFXTBYPASS = 1
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1 (2),
fHFXT,HF = 4 MHz, CL,eff = 16 pF
450
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1,
fHFXT,HF = 8 MHz, CL,eff = 16 pF
320
HFXTBYPASS = 0, HFXTDRIVE = 2,
HFFREQ = 2,
fHFXT,HF = 16 MHz, CL,eff = 16 pF
200
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3,
fHFXT,HF = 24 MHz, CL,eff = 16 pF
200
UNIT
MHz
Ω
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1,
TA = 25°C, CL,eff = 16 pF
3.0 V
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3,
TA = 25°C, CL,eff = 16 pF
3.0 V
1.6
ms
0.6
CHFXIN
Integrated load capacitance at
HFXIN terminaI (7) (8)
2
pF
CHFXOUT
Integrated load capacitance at
HFXOUT terminaI (7) (8)
2
pF
fFault,HFXT
Oscillator fault frequency
(9)
0
(10)
800
kHz
(4)
When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DCHFXT, SW.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes start-up counter of 1024 clock cycles.
(7) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT is the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
(8) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the
flag. A static condition or stuck at fault condition will set the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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Table 5-6 lists the characteristics of the DCO.
Table 5-6. DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1
±3.5%
MHz
ADVANCE INFORMATION
fDCO1
DCO frequency range
1 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0,
DCORSEL = 1, DCOFSEL = 0
fDCO2.7
DCO frequency range
2.7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1
2.667
±3.5%
MHz
fDCO3.5
DCO frequency range
3.5 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2
3.5
±3.5%
MHz
fDCO4
DCO frequency range
4 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 3
4
±3.5%
MHz
fDCO5.3
DCO frequency range
5.3 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4,
DCORSEL = 1, DCOFSEL = 1
5.333
±3.5%
MHz
fDCO7
DCO frequency range
7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5,
DCORSEL = 1, DCOFSEL = 2
7
±3.5%
MHz
fDCO8
DCO frequency range
8 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6,
DCORSEL = 1, DCOFSEL = 3
8
±3.5%
MHz
fDCO16
DCO frequency range
16 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4
16
±3.5% (1)
MHz
fDCO21
DCO frequency range
21 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5
21
±3.5% (1)
MHz
fDCO24
DCO frequency range
24 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6
24
±3.5% (1)
MHz
fDCO,DC
Duty cycle
Measured at SMCLK, divide by 1,
No external divide, all DCORSEL and
DCOFSEL settings except DCORSEL = 1,
DCOFSEL = 5 and DCORSEL = 1,
DCOFSEL = 6
50%
52%
tDCO,
DCO jitter
Based on fsignal = 10 kHz and DCO used
for 12-bit SAR ADC sampling source. This
achieves >74-dB SNR due to jitter; that is,
limited by ADC performance.
2
3
JITTER
dfDCO/dT
(1)
(2)
40
DCO temperature drift (2)
48%
3.0 V
0.01
ns
%/ºC
After a wakeup from LPM1, LPM2, LPM3, or LPM4, the DCO frequency fDCO might exceed the specified frequency range for a few clock
cycles by up to 5% before settling to the specified steady state frequency range.
Calculated using the box method: (MAX(–40°C to 85ºC) – MIN(–40°C to 85ºC)) / MIN(–40°C to 85ºC) / (85ºC – (–40ºC))
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Table 5-7 lists the characteristics of the VLO.
Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IVLO
Current consumption
fVLO
VLO frequency
Measured at ACLK
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
dfVLO/dVCC
VLO frequency supply voltage drift
Measured at ACLK (2)
fVLO,DC
Duty cycle
Measured at ACLK
(1)
(2)
MIN
TYP
MAX
100
6
9.4
nA
14
0.2
50%
kHz
%/°C
0.7
40%
UNIT
%/V
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-8 lists the characteristics of the MODOSC.
Table 5-8. Module Oscillator (MODOSC)
PARAMETER
TEST CONDITIONS
IMODOSC
Current consumption
fMODOSC
MODOSC frequency
fMODOSC/dT
MODOSC frequency temperature drift (1)
TYP
4.0
4.8
Enabled
fMODOSC/dVCC
MODOSC frequency supply voltage drift
DCMODOSC
Duty cycle
(1)
(2)
MIN
MAX
UNIT
5.4
MHz
25
μA
0.08
(2)
%/℃
1.4
Measured at SMCLK, divide by 1
40%
50%
%/V
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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5.13.4 Wake-up Characteristics
Table 5-9 lists the times required to wake up from LPM or reset.
Table 5-9. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
6
10
μs
400 +
1.5 / fDCO
ns
ADVANCE INFORMATION
tWAKE-UP FRAM
(Additional) wake-up time to activate the
FRAM in AM if previously disabled by the
FRAM controller or from an LPM if immediate
activation is selected for wake up
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode (1)
2.2 V, 3.0 V
tWAKE-UP LPM1
Wake-up time from LPM1 to active mode (1)
2.2 V, 3.0 V
tWAKE-UP LPM2
Wake-up time from LPM2 to active mode
(1)
2.2 V, 3.0 V
6
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode
(1)
2.2 V, 3.0 V
6.6 +
2.0 / fDCO
9.6 +
2.5 / fDCO
μs
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode (1)
2.2 V, 3.0 V
6.6 +
2.0 / fDCO
9.6 +
2.5 / fDCO
μs
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode
(2)
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode (2)
tWAKE-UP-RST
tWAKE-UP-BOR
(1)
(2)
6
μs
μs
2.2 V, 3.0 V
350
450
μs
SVSHE = 1
2.2 V, 3.0 V
350
450
μs
SVSHE = 0
2.2 V, 3.0 V
0.4
0.8
ms
2.2 V, 3.0 V
480
583
μs
2.2 V, 3.0 V
0.5
1
ms
Wake-up time from a RST pin triggered reset
to active mode (2)
Wake-up time from power-up to active mode
(2)
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge with MCLKREQEN = 1. This time includes the activation of the FRAM during wake up. With
MCLKREQEN = 0, the externally observable MCLK clock is gated one additional cycle.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Table 5-10 lists the typical charges used during wakeup.
Table 5-10. Typical Wake-up Charges
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
TEST
CONDITIONS
PARAMETER
QWAKE-UP FRAM
Charge used for activating the FRAM in AM or during wakeup
from LPM0 if previously disabled by the FRAM controller.
QWAKE-UP LPM0
MIN
TYP
MAX
UNIT
16.5
nAs
Charge used to wake up from LPM0 to active mode (with
FRAM active)
3.8
nAs
QWAKE-UP LPM1
Charge used to wake up from LPM1 to active mode (with
FRAM active)
21
nAs
QWAKE-UP LPM2
Charge used to wake up from LPM2 to active mode (with
FRAM active)
22
nAs
QWAKE-UP LPM3
Charge used to wake up from LPM3 to active mode (with
FRAM active)
28
nAs
QWAKE-UP LPM4
Charge used to wake up from LPM4 to active mode (with
FRAM active)
28
nAs
170
nAs
(2)
QWAKE-UP LPM3.5
Charge used to wake up from LPM3.5 to active mode
QWAKE-UP LPM4.5
Charge used to wake up from LPM4.5 to active mode (2)
QWAKE-UP-RESET
Charge used for reset from RST or BOR event to active
mode (2)
(1)
(2)
42
SVSHE = 1
173
SVSHE = 0
171
148
nAs
nAs
Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active
mode (for example, for an interrupt service routine).
Charge required until start of user code. This does not include the energy required to reconfigure the device.
Specifications
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5.13.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
10000.00
LPM0
LPM1
Average Wake-up Current (µA)
1000.00
LPM2,XT12
LPM3,XT12
LPM3.5,XT12
100.00
10.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-6. Average LPM Currents vs Wake-up Frequency at 25°C
10000.00
LPM0
LPM1
Average Wake-up Current (µA)
1000.00
LPM2,XT12
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-7. Average LPM Currents vs Wake-up Frequency at 85°C
Specifications
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5.13.5 Digital I/Os
Table 5-11 lists the characteristics of the digital inputs.
Table 5-11. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
2.2 V
1.2
1.65
3.0 V
1.65
2.25
2.2 V
0.55
1.00
3.0 V
0.75
1.35
2.2 V
0.44
0.98
3.0 V
0.60
1.30
UNIT
ADVANCE INFORMATION
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared
analog functions (1)
VIN = VSS or VCC
5
pF
Ilkg(Px.y)
High-impedance input leakage current
See
t(int)
External interrupt timing (external trigger
pulse duration to set interrupt flag) (4)
Ports with interrupt capability (see
Section 1.4 and Section 4.3)
t(RST)
External reset pulse duration on RST
(1)
(2)
(3)
(4)
(5)
44
(2) (3)
(5)
20
35
50
V
V
V
kΩ
2.2 V,
3.0 V
–20
2.2 V,
3.0 V
20
ns
2.2 V,
3.0 V
2
µs
+20
nA
If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in
series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and/or
PJ.5/LFXOUT.
The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Not applicable if RST/NMI pin configured as NMI .
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Table 5-12 lists the characteristics of the digital outputs.
Table 5-12. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
I(OHmax) = –1 mA (1)
VOH
High-level output voltage
I(OHmax) = –3 mA (2)
I(OHmax) = –2 mA (1)
I(OHmax) = –6 mA (2)
I(OLmax) = 1 mA (1)
VOL
Low-level output voltage
I(OLmax) = 3 mA (2)
I(OLmax) = 2 mA (1)
I(OLmax) = 6 mA (2)
fPx.y
Port output frequency
(with load) (3)
CL = 20 pF, RL
fPort_CLK
Clock output frequency (3)
ACLK, MCLK, or SMCLK at
configured output port,
CL = 20 pF (5)
trise,dig
Port output rise time, digital only
port pins
CL = 20 pF
tfall,dig
Port output fall time, digital only
port pins
CL = 20 pF
trise,ana
Port output rise time, port pins
with shared analog functions
CL = 20 pF
tfall,ana
Port output fall time, port pins with
shared analog functions
CL = 20 pF
(1)
(2)
(3)
(4)
(5)
(4) (5)
VCC
2.2 V
3.0 V
2.2 V
3.0 V
MIN
TYP
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
2.2 V
16
3.0 V
16
2.2 V
16
3.0 V
16
UNIT
V
V
MHz
MHz
2.2 V
4
15
3.0 V
3
15
2.2 V
4
15
3.0 V
3
15
2.2 V
6
15
3.0 V
4
15
2.2 V
6
15
3.0 V
4
15
ns
ns
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit, and the port might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected from the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
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PARAMETER
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5.13.5.1 Typical Characteristics, Digital Outputs
30
25°C
85°C
Low-Level Output Current (mA)
Low-Level Output Current (mA)
15
10
5
25°C
85°C
20
10
P1.1
P1.1
0
0
ADVANCE INFORMATION
0
0.5
1
1.5
2
0
0.5
Low-Level Output Voltage (V)
1
1.5
2
2.5
3
Low-Level Output Voltage (V)
C001
C001
VCC = 2.2 V
VCC = 3.0 V
Figure 5-8. Typical Low-Level Output Current vs
Low-Level Output Voltage
0
25°C
85°C
High-Level Output Current (mA)
High-Level Output Current (mA)
0
Figure 5-9. Typical Low-Level Output Current vs
Low-Level Output Voltage
-5
-10
25°C
85°C
-10
-20
P1.1
P1.1
-15
-30
0
0.5
1
1.5
2
0
0.5
High-Level Output Voltage (V)
1
1.5
2
2.5
C001
VCC = 2.2 V
C001
VCC = 3.0 V
Figure 5-10. Typical High-Level Output Current vs
High-Level Output Voltage
46
3
High-Level Output Voltage (V)
Figure 5-11. Typical High-Level Output Current vs
High-Level Output Voltage
Specifications
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Table 5-13 lists the supported pin oscillator frequencies.
Table 5-13. Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
foPx.y
(1)
TEST CONDITIONS
Pin-oscillator frequency
VCC
MIN
TYP
Px.y, CL = 10 pF (1)
3.0 V
1200
Px.y, CL = 20 pF (1)
3.0 V
650
MAX
UNIT
kHz
CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
Fitted
25°C
25°C
85°C
100
1000
85°C
100
10
100
10
External Load Capacitance (pF) (Including Board)
100
External Load Capacitance (pF) (Including Board)
C002
VCC = 2.2 V
One output active at a time.
Figure 5-12. Typical Oscillation Frequency vs
Load Capacitance
C002
VCC = 3.0 V
One output active at a time.
Figure 5-13. Typical Oscillation Frequency vs
Load Capacitance
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1000
Fitted
Pin Oscillator Frequency (kHz)
Pin Oscillator Frequency (kHz)
5.13.5.2 Typical Characteristics, Pin-Oscillator Frequency
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5.13.6 LEA
Table 5-14 lists the characteristics of the LEA.
Table 5-14. Low-Energy Accelerator (LEA) Performance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLEA
Frequency for specified
performance
MCLK
W_LEA_FFT
LEA subsystem energy on fast
fourier transform
Complex FFT 128-point Q.15 with
random data in LEA RAM
W_LEA_FIR
LEA subsystem energy on finite Real FIR on random Q.31 data with
impulse response
128 taps on 24 points
W_LEA_ADD
LEA subsystem energy on
additions
On 32 Q.31 elements with random
value out of LEA RAM with linear
address increment
MIN
TYP
MAX
UNIT
16
MHz
VCORE = 3 V,
MCLK = 16 MHz
350
nJ
VCORE = 3 V,
MCLK = 16 MHz
2.6
µJ
VCORE = 3 V,
MCLK = 16 MHz
6.6
nJ
5.13.7 Timer_A and Timer_B
ADVANCE INFORMATION
Table 5-15 lists the characteristics of Timer_A.
Table 5-15. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
2.2 V, 3.0 V
tTA,cap
Timer_A capture timing
All capture inputs, minimum pulse
duration required for capture
2.2 V, 3.0 V
MIN
TYP
MAX
UNIT
16
MHz
20
ns
Table 5-16 lists the characteristics of Timer_B.
Table 5-16. Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTB
Timer_B input clock frequency
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
2.2 V, 3.0 V
tTB,cap
Timer_B capture timing
All capture inputs, minimum pulse
duration required for capture
2.2 V, 3.0 V
48
Specifications
MIN
20
TYP
MAX
UNIT
16
MHz
ns
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5.13.8 eUSCI
Table 5-17 lists the supported clock frequencies of the eUSCI in UART mode.
Table 5-17. eUSCI (UART Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
MIN
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency (equals baud rate in MBaud)
MAX
UNIT
16
MHz
4
MHz
Table 5-18 lists the switching characteristics of the eUSCI in UART mode.
Table 5-18. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
VCC
UCGLITx = 0
UART receive deglitch time (1)
tt
TYP
MAX
5
UCGLITx = 1
2.2 V, 3.0 V
UCGLITx = 2
UCGLITx = 3
(1)
MIN
UNIT
30
20
90
35
160
50
220
ns
ADVANCE INFORMATION
PARAMETER
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch
time can limit the maximum useable baud rate. To ensure that pulses are correctly recognized, their duration should exceed the
maximum specification of the deglitch time.
Table 5-19 lists the supported clock frequency of the eUSCI in SPI master mode.
Table 5-19. eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
feUSCI
eUSCI input clock frequency
TEST CONDITIONS
Internal: SMCLK or ACLK, duty cycle = 50% ±10%
MIN
MAX
UNIT
16
MHz
Specifications
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Table 5-20 lists the switching characteristics of the eUSCI in SPI master mode.
Table 5-20. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP MAX
UNIT
ADVANCE INFORMATION
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
1
tSTE,LAG
STE lag time, Last clock to STE inactive
UCSTEM = 1, UCMODEx = 01 or 10
1
tSTE,ACC
STE access time, STE active to SIMO
data out
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
60
ns
tSTE,DIS
STE disable time, STE inactive to SOMI
high impedance
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
80
ns
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid, CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
50
2.2 V
40
3.0 V
40
2.2 V
0
3.0 V
0
UCxCLK
cycles
ns
ns
2.2 V
11
3.0 V
10
2.2 V
0
3.0 V
0
ns
ns
fUCxCLK = 1/2 tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-14 and Figure 5-15.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Specifies
the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in
Figure 5-14 and Figure 5-15.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,DIS
tVALID,MO
ADVANCE INFORMATION
tSTE,ACC
SIMO
Figure 5-14. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tVALID,MO
tSTE,DIS
SIMO
Figure 5-15. SPI Master Mode, CKPH = 1
Specifications
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Table 5-21 lists the switching characteristics of the eUSCI in SPI slave mode.
Table 5-21. eUSCI (SPI Slave Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
ADVANCE INFORMATION
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
52
MIN
2.2 V
45
3.0 V
40
2.2 V
2
3.0 V
3
MAX
ns
ns
2.2 V
45
3.0 V
40
2.2 V
50
3.0 V
45
2.2 V
4
3.0 V
4
2.2 V
7
3.0 V
7
35
35
3.0 V
0
ns
ns
3.0 V
0
ns
ns
2.2 V
2.2 V
UNIT
ns
ns
fUCxCLK = 1/2 tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-16 and Figure 5-17.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams inFigure 5-16
and Figure 5-17.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SI
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tSTE,DIS
tVALID,SO
ADVANCE INFORMATION
tSTE,ACC
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 5-17. SPI Slave Mode, CKPH = 1
Specifications
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Table 5-22 lists the switching characteristics of the eUSCI in I2C mode.
Table 5-22. eUSCI (I2C Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
2.2 V, 3.0 V
fSCL = 100 kHz
UNIT
16
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3.0 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3.0 V
100
ns
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
ADVANCE INFORMATION
tSU,STO
Setup time for STOP
tBUF
Bus free time between STOP and START
conditions
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
2.2 V, 3.0 V
0
MAX
2.2 V, 3.0 V
2.2 V, 3.0 V
4.7
4.0
4.7
1.3
UCGLITx = 0
50
2.2 V, 3.0 V
UCGLITx = 3
µs
0.6
fSCL > 100 kHz
UCGLITx = 2
µs
0.6
fSCL = 100 kHz
UCGLITx = 1
µs
0.6
µs
250
25
125
12.5
62.5
6.3
31.5
UCCLTOx = 1
tTIMEOUT
Clock low time-out
UCCLTOx = 2
27
2.2 V, 3.0 V
30
UCCLTOx = 3
tSU,STA
tHD,STA
ns
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-18. I2C Mode Timing
54
Specifications
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5.13.9 Segment LCD Controller
Table 5-23 lists the recommended operating conditions for the LCD controller.
Table 5-23. LCD_C Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
CONDITIONS
MIN
NOM
MAX
UNIT
VCC,LCD_C,CP en,3.6
Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V
LCDCPEN = 1, 0000b < VLCDx ≤ 1111b
(charge pump enabled, VLCD ≤ 3.6 V)
2.2
3.6
V
VCC,LCD_C,CP en,3.3
Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V
LCDCPEN = 1, 0000b < VLCDx ≤ 1100b
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
3.6
V
VCC,LCD_C,int.
bias
Supply voltage range, internal
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,ext.
bias
Supply voltage range, external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,VLCDEXT
Supply voltage range, external
LCD voltage, internal or external LCDCPEN = 0, VLCDEXT = 1
biasing, charge pump disabled
2.0
3.6
V
VLCDCAP
External LCD voltage at
LCDCAP, internal or external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
V
CLCDCAP
Capacitor value on LCDCAP
when charge pump enabled
LCDCPEN = 1, VLCDx > 0000b (charge
pump enabled)
fACLK,in
ACLK input frequency range
fLCD
LCD frequency range
fFRAME = (1 / (2 × mux)) × fLCD with
mux = 1 (static) to 8
fFRAME,4mux
LCD frame frequency range
fFRAME,4mux(MAX) = (1 / (2 × 4)) ×
fLCD(MAX) = (1 / (2 × 4)) × 1024 Hz
CPanel
Panel capacitance
fLCD = 1024 Hz, all common lines equally
loaded
VR33
Analog input voltage at R33
LCDCPEN = 0, VLCDEXT = 1
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
4.7–20%
4.7
10+20%
µF
30
32.768
40
kHz
1024
Hz
128
Hz
10000
pF
0
2.4
VCC + 0.2
V
VR13
VR03 +
2/3 ×
(VR33 –
VR03)
VR33
V
VR03
VR03 +
1/3 ×
(VR33 –
VR03)
VR23
V
VR03
VR03 +
1/2 ×
(VR33 –
VR03)
VR33
V
VR23,1/3bias
Analog input voltage at R23
VR13,1/3bias
Analog input voltage at R13 with LCDREXT = 1, LCDEXTBIAS = 1,
1/3 biasing
LCD2B = 0
VR13,1/2bias
Analog input voltage at R13 with LCDREXT = 1, LCDEXTBIAS = 1,
1/2 biasing
LCD2B = 1
VR03
Analog input voltage at R03
R0EXT = 1
VSS
VLCD – VR03
Voltage difference between
VLCD and R03
LCDCPEN = 0, R0EXT = 1
2.4
VLCDREF
External LCD reference voltage
applied at LCDREF
VLCDREFx = 01
0.8
V
1.0
VCC + 0.2
V
1.2
V
Specifications
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ADVANCE INFORMATION
PARAMETER
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Table 5-24 lists the electrical characteristics the LCD controller.
Table 5-24. LCD_C Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VLCDx = 0000, VLCDEXT = 0
VLCD,1
LCDCPEN = 1, VLCDx = 0001b
2 V to 3.6 V
VLCD,2
LCDCPEN = 1, VLCDx = 0010b
2 V to 3.6 V
2.66
VLCD,3
LCDCPEN = 1, VLCDx = 0011b
2 V to 3.6 V
2.72
VLCD,4
LCDCPEN = 1, VLCDx = 0100b
2 V to 3.6 V
2.78
VLCD,5
LCDCPEN = 1, VLCDx = 0101b
2 V to 3.6 V
2.84
VLCD,6
LCDCPEN = 1, VLCDx = 0110b
2 V to 3.6 V
2.90
VLCD,7
LCDCPEN = 1, VLCDx = 0111b
2 V to 3.6 V
2.96
LCDCPEN = 1, VLCDx = 1000b
2 V to 3.6 V
3.02
VLCD,9
LCDCPEN = 1, VLCDx = 1001b
2 V to 3.6 V
3.08
VLCD,10
LCDCPEN = 1, VLCDx = 1010b
2 V to 3.6 V
3.14
VLCD,11
LCDCPEN = 1, VLCDx = 1011b
2 V to 3.6 V
3.20
VLCD,12
LCDCPEN = 1, VLCDx = 1100b
2 V to 3.6 V
3.26
VLCD,13
LCDCPEN = 1, VLCDx = 1101b
2.2 V to 3.6 V
3.32
VLCD,14
LCDCPEN = 1, VLCDx = 1110b
2.2 V to 3.6 V
3.38
LCDCPEN = 1, VLCDx = 1111b
2.2 V to 3.6 V
LCD voltage
VLCD,8
ADVANCE INFORMATION
VLCD,15
2.4 V to 3.6 V
TYP
VLCD,0
MAX
UNIT
VCC
2.49
3.32
2.60
3.44
2.72
V
3.6
VLCD,7,0.8
LCD voltage with external
reference of 0.8 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b, VLCDREF = 0.8 V
2 V to 3.6 V
2.96 ×
0.8 V
V
VLCD,7,1.0
LCD voltage with external
reference of 1.0 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b, VLCDREF = 1.0 V
2 V to 3.6 V
2.96 ×
1.0 V
V
VLCD,7,1.2
LCD voltage with external
reference of 1.2 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b, VLCDREF = 1.2 V
2.2 V to 3.6 V
2.96 ×
1.2 V
V
ΔVLCD
Voltage difference between
consecutive VLCDx settings
ΔVLCD = VLCD,x – VLCD,x–1
with x = 0010b to 1111b
Peak supply currents due to
charge pump activities
LCDCPEN = 1, VLCDx = 1111b
external, with decoupling capacitor on
DVCC supply ≥1 µF
2.2 V
ICC,Peak,CP
tLCD,CP,on
Time to charge CLCD when
discharged
CLCD = 4.7 µF, LCDCPEN = 0→1,
VLCDx = 1111b
2.2 V
ICP,Load
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111b
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN = 0, ILOAD = ±10 µA
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN = 0, ILOAD = ±10 µA
56
Specifications
40
60
80
600
2.2 V
2.2 V
2.2 V
100
mV
µA
500
50
ms
µA
10
kΩ
10
kΩ
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5.13.10 ADC12_B
Table 5-25 lists the power and input requirements of the ADC.
Table 5-25. 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
V(Ax)
I(ADC12_B)
single-ended
mode
I(ADC12_B)
differential
mode
I(ADC12_B)
single-ended
low-power
mode
I(ADC12_B)
differential
low-power
mode
CI
RI
(1)
(2)
(3)
Analog input voltage
range (1)
Operating supply current
into AVCC and DVCC
terminals (2) (3)
Operating supply current
into AVCC and DVCC
terminals (2) (3)
Operating supply current
into AVCC and DVCC
terminals (2) (3)
TEST CONDITIONS
VCC
All ADC12 analog input pins Ax
MIN
NOM
0
MAX
UNIT
AVCC
V
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 0,
REFON = 0, ADC12SHTx = 0, ADC12DIV = 0
3.0 V
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 0,
REFON = 0, ADC12SHTx = 0, ADC12DIV = 0
2.2 V
140
190
3.0 V
175
245
2.2 V
170
230
fADC12CLK = MODCLK/4, ADC12ON = 1,
ADC12PWRMD = 1, ADC12DIF = 0,
REFON = 0, ADC12SHTx = 0, ADC12DIV = 0
3.0 V
85
125
fADC12CLK = MODCLK/4, ADC12ON = 1,
ADC12PWRMD = 1, ADC12DIF = 0,
REFON = 0, ADC12SHTx = 0, ADC12DIV = 0
2.2 V
83
120
3.0 V
110
165
2.2 V
109
160
2.2 V
10
15
>2 V
0.5
4
<2 V
1
10
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 1,
REFON = 0, ADC12SHTx = 0, ADC12DIV = 0
Operating supply current
into AVCC and DVCC
terminals (2) (3)
fADC12CLK = MODCLK/4, ADC12ON = 1,
ADC12PWRMD = 1, ADC12DIF = 1,
REFON = 0, ADC12SHTx= 0, ADC12DIV = 0
Input capacitance
Only one terminal Ax can be selected at one time
Input MUX ON resistance 0 V ≤ V(Ax) ≤ AVCC
145
199
µA
µA
ADVANCE INFORMATION
PARAMETER
µA
µA
pF
kΩ
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter I(ADC12_B).
Approximately 60% (typical) of the total current into the AVCC and DVCC terminals is from AVCC.
Specifications
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Table 5-26 lists the timing requirements of the ADC.
Table 5-26. 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
fADC12CLK
Frequency for
specified
performance
For specified performance of ADC12 linearity parameters with
ADC12PWRMD = 0. If ADC12PWRMD = 1, the maximum is 1/4
of the value shown here.
0.45
fADC12CLK
Frequency for
reduced performance
Linearity parameters have reduced performance
fADC12OSC
Internal oscillator (1)
ADC12DIV = 0, fADC12CLK = fADC12OSC from MODCLK
tCONVERT
Conversion time
4
REFON = 0, Internal oscillator, fADC12CLK = fADC12OSC from
MODCLK, ADC12WINC = 0
ADVANCE INFORMATION
Time ADC must be
off before can be
turned on again
Note: tADC12OFF must be met to make sure that tADC12ON time
holds
(3)
58
MHz
kHz
5.4
RS = 400 Ω, RI = 4 kΩ,
CI = 15 pF, Cpext= 8 pF (4)
MHz
(2)
100
100
All pulse sample mode
(ADC12SHP = 1) and extended
sample mode (ADC12SHP = 0) with
buffered reference
(ADC12VRSEL = 0x1, 0x3, 0x5,
0x7, 0x9, 0xB, 0xD, 0xF)
Extended sample mode
(ADC12SHP = 0) with unbuffered
reference (ADC12VRSEL= 0x0,
0x2, 0x4, 0x6, 0xC, 0xE)
(5)
5.4
3.5
See
tADC12OFF
(4)
UNIT
µs
External fADC12CLK from ACLK, MCLK, or SMCLK,
ADC12SSEL ≠ 0
See
(1)
(2)
(3)
4.8
2.6
Turnon settling time
of the ADC
Sampling time
MAX
32.768
tADC12ON
tSample
TYP
ns
ns
1
µs
See
(5)
The ADC12OSC is sourced directly from MODOSC in the UCS.
14 × 1 / fADC12CLK. If ADC12WINC = 1 then 15 × 1 / fADC12CLK.
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB: tsample = ln(2n+2) × (RS + RI) × (CI + Cpext), where n = ADC
resolution = 12, RS= external source resistance, Cpext = external parasitic capacitance.
6 × 1 / fADC12CLK
Specifications
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Table 5-27 lists the linearity parameters of the ADC.
Table 5-27. 12-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
Integral linearity error (INL) for
differential input
With external voltage reference
(ADC12VRSEL = 0x2,0x3, 0x4, 0x14, 0x15),
1.2 V ≤ VR+ – VR–≤ AVCC
±1.8
Integral linearity error (INL) for
single-ended inputs
With external voltage reference
(ADC12VRSEL = 0x2,0x3, 0x4, 0x14, 0x15),
1.2 V ≤ VR+ – VR–≤ AVCC
±2.2
ED
Differential linearity error (DNL)
With external voltage reference
(ADC12VRSEL = 0x2,0x3, 0x4, 0x14, 0x15),
EO
Offset error (1)
ADC12VRSEL = 0x1 without TLV calibration,
TLV calibration data can be used to improve the
parameter (3)
EI
EG
ET
(1)
(2)
(3)
(2)
Gain error
Total unadjusted error
UNIT
LSB
–0.99
+1.0
LSB
±0.5
±1.5
mV
With internal voltage reference VREF = 2.5 V
(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)
±0.2%
±1.7%
With internal voltage reference VREF = 1.2 V
(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)
±0.2%
±2.5%
With external voltage reference without internal
buffer (ADC12VRSEL = 0x2 or 0x4) without TLV
calibration, VR+ = 2.5 V, VR– = AVSS
±1
±3
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3), VR+ = 2.5 V, VR– = AVSS
±2
±27
With internal voltage reference VREF = 2.5 V
(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)
±0.2%
±1.8%
With internal voltage reference VREF = 1.2 V
(ADC12VRSEL = 0x1, 0x7, 0x9, 0xB, or 0xD)
±0.2%
±2.6%
With external voltage reference without internal
buffer (ADC12VRSEL = 0x2 or 0x4) without TLV
calibration, VR+ = 2.5 V, VR– = AVSS
±1
±5
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3), VR+ = 2.5 V, VR– = AVSS
±1
ADVANCE INFORMATION
PARAMETER
LSB
LSB
±28
Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.
Offset increases as IR drop increases when VR– is AVSS.
For details, see the Device Descriptor Table section in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx
Family User's Guide.
Specifications
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Table 5-28 lists the dynamic performance characteristics of the ADC with an external reference.
Table 5-28. 12-Bit ADC, Dynamic Performance With External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Resolution
SNR
ENOB
(1)
TEST CONDITIONS
MIN
Number of no missing code output-code bits
TYP
MAX
12
UNIT
bits
Signal-to-noise with differential inputs
VR+ = 2.5 V, VR– = AVSS
71
Signal-to-noise with single-ended inputs
VR+ = 2.5 V, VR– = AVSS
70
Effective number of bits with differential
inputs (1)
VR+ = 2.5 V, VR– = AVSS
11.4
Effective number of bits with single-ended
inputs (1)
VR+ = 2.5 V, VR– = AVSS
11.1
Effective number of bits with 32.768-kHz
clock (reduced performance) (1)
Reduced performance with fADC12CLK
from ACLK LFXT 32.768 kHz,
VR+ = 2.5 V, VR– = AVSS
10.9
dB
bits
ENOB = (SINAD – 1.76) / 6.02
Table 5-29 lists the dynamic performance characteristics of the ADC with an internal reference.
ADVANCE INFORMATION
Table 5-29. 12-Bit ADC, Dynamic Performance With Internal Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Resolution
SNR
ENOB
(1)
TEST CONDITIONS
MIN
Number of no missing code output-code bits
TYP
MAX
12
UNIT
bits
Signal-to-noise with differential inputs
VR+ = 2.5 V, VR– = AVSS
70
Signal-to-noise with single-ended inputs
VR+ = 2.5 V, VR– = AVSS
69
Effective number of bits with differential
inputs (1)
VR+ = 2.5 V, VR– = AVSS
11.4
Effective number of bits with single-ended
inputs (1)
VR+ = 2.5 V, VR– = AVSS
11.0
Effective number of bits with 32.768-kHz
clock (reduced performance) (1)
Reduced performance with fADC12CLK
from ACLK LFXT 32.768 kHz,
VR+ = 2.5 V, VR– = AVSS
10.9
dB
bits
ENOB = (SINAD – 1.76) / 6.02
Table 5-30 lists the characteristics of the temperature sensor and the V1/2.
Table 5-30. 12-Bit ADC, Temperature Sensor and Built-In V1/2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1) (2)
MIN
ADC12ON = 1, ADC12TCMAP = 1
2.5
mV/°C
TCSENSOR
See
tSENSOR(sample)
Sample time required if ADCTCMAP = 1 and
channel (MAX – 1) is selected (3)
ADC12ON = 1, ADC12TCMAP = 1,
Error of conversion result ≤1 LSB
V1/2
AVCC voltage divider for ADC12BATMAP = 1
on MAX input channel
ADC12ON = 1, ADC12BATMAP = 1
IV1/2
Current for battery monitor during sample time ADC12ON = 1, ADC12BATMAP = 1
tV1/2 (sample)
Sample time required if ADC12BATMAP = 1
and channel MAX is selected (4)
(2)
(3)
(4)
60
UNIT
mV
Temperature sensor voltage
(1)
MAX
700
VSENSOR
(2)
TYP
ADC12ON = 1, ADC12TCMAP = 1,
TA = 0°C
ADC12ON = 1, ADC12BATMAP = 1
30
47.5%
µs
50% 52.5%
38
1.7
72
µA
µs
The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can
be computed from the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor-on time, tSENSOR(on).
The on-time tV1/2(on) is included in the sampling time tV1/2(sample); no additional on time is needed.
Specifications
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Table 5-31 lists the characteristics of the external reference for the ADC.
Table 5-31. 12-Bit ADC, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
TEST CONDITIONS
MAX
UNIT
1.2
AVCC
V
VR+ > VR–
0
1.2
V
VR+ > VR–
1.2
AVCC
V
VR+
VR+ > VR–
VR–
Negative external reference voltage input
VeREF+ or VeREF- based on
ADC12VRSEL bit
VR+ –
VR–
Differential external reference voltage input
IVeREF+,
IVeREF-
IVeREF+,
IVeREF-
Static input current singled-ended input
mode
Static input current differential input mode
MIN
TYP
1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 0, ADC12PWRMD = 0
±10
1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 0, ADC12PWRMD = 01
±2.5
1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 1, ADC12PWRMD = 0
±20
1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 1, ADC12PWRMD = 1
±5
µA
µA
IVeREF+
Peak input current with single-ended input
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 0
1.5
mA
IVeREF+
Peak input current with differential input
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 1
3
mA
CVeREF+/-
Capacitance at VeREF+ or VeREFterminal
See
(1)
(2)
(2)
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance (CI) is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
Connect two decoupling capacitors, 10 µF and 470 nF, to VeREF to decouple the dynamic current required for an external reference
source if it is used for the ADC12_B. Also see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family
User's Guide.
Typical Temperature Sensor Voltage (mV)
950
900
850
800
750
700
650
600
550
500
–40
–20
0
20
40
60
80
Ambient Temperature (°C)
Figure 5-19. Typical Temperature Sensor Voltage
Specifications
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ADVANCE INFORMATION
PARAMETER
Positive external reference voltage input
VeREF+ or VeREF- based on
ADC12VRSEL bit
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5.13.11 Reference
Table 5-32 lists the characteristics of the internal reference.
Table 5-32. REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Positive built-in reference
voltage output
VREF+
RMS noise at VREF
(1)
VCC
MIN
TYP
MAX
UNIT
REFVSEL = {2} for 2.5 V, REFON = 1
2.7 V
2.5
±1.5%
REFVSEL = {1} for 2.0 V, REFON = 1
2.2 V
2.0
±1.5%
REFVSEL = {0} for 1.2 V, REFON = 1
1.8 V
1.2
±1.8%
30
130
µV
From 0.1 Hz to 10 Hz, REFVSEL = {0}
V
VOS_BUF_INT
VREF ADC BUF_INT
buffer offset (2)
TA = 25°C, ADC on, REFVSEL = {0},
REFON = 1, REFOUT = 0
–16
+16
mV
VOS_BUF_EXT
VREF ADC BUF_EXT
buffer offset (3)
TA = 25°C, REFVSEL = {0} , REFOUT = 1,
REFON = 1 or ADC on
–16
+16
mV
AVCC minimum voltage,
Positive built-in reference
active
REFVSEL = {0} for 1.2 V
1.8
AVCC(min)
REFVSEL = {1} for 2.0 V
2.2
REFVSEL = {2} for 2.5 V
2.7
ADVANCE INFORMATION
Operating supply current
into AVCC terminal (4)
IREF+
REFON = 1
3V
ADC ON, REFOUT = 0,
REFVSEL = {0, 1, or 2},
ADC12PWRMD = 0
ADC ON, REFOUT = 1,
REFVSEL = {0, 1, 2}, ADC12PWRMD = 0
IREF+_ADC_BUF
Operating supply current
into AVCC terminal (4)
ADC ON, REFOUT = 0,
REFVSEL = {0, 1, 2}, ADC12PWRMD = 1
3V
ADC ON, REFOUT = 1,
REFVSEL = {0, 1, 2}, ADC12PWRMD = 1
ADC OFF, REFON = 1, REFOUT = 1,
REFVSEL = {0, 1, 2}
IO(VREF+)
VREF maximum load
current, VREF+ terminal
REFVSEL = {0, 1, 2}, AVCC = AVCC(min) for
each reference level,
REFON = REFOUT = 1
ΔVout/ΔIo
Load-current regulation,
VREF+ terminal
REFVSEL = {0, 1, 2},
IO(VREF+) = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level,
REFON = REFOUT = 1
CVREF+/-
Capacitance at VREF+
and VREF- terminals
REFON = REFOUT = 1
TCREF+
Temperature coefficient of
built-in reference
REFVSEL = {0, 1, 2},
REFON = REFOUT = 1,
TA = –40°C to 85°C (5)
PSRR_DC
Power supply rejection
ratio (DC)
PSRR_AC
V
19
26
247
400
1053
1820
153
240
581
1030
1105
1890
–1000
+10
µA
µA
µA
1500
µV/mA
100
pF
24
50
ppm/K
AVCC = AVCC (min) to AVCC(max),
TA = 25°C, REFVSEL = {0, 1, 2},
REFON = REFOUT = 1
100
400
µV/V
Power supply rejection
ratio (AC)
dAVCC= 0.1 V at 1 kHz
3.0
tSETTLE
Settling time of reference
voltage (6)
AVCC = AVCC (min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0 → 1
40
80
µs
tbuf_settle
Settling time of ADC
reference voltage buffer (6)
AVCC = AVCC (min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 1
0.4
2
µs
(1)
(2)
(3)
(4)
(5)
(6)
62
(VREF+)
0
mV/V
Internal reference noise affects ADC performance when ADC uses the internal reference. See Designing With the MSP430FR59xx and
MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.
Buffer offset affects ADC gain error and thus total unadjusted error.
Buffer offset affects ADC gain error and thus total unadjusted error.
The internal reference current is supplied through the AVCC terminal.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
Specifications
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5.13.12 Comparator
Table 5-33 lists the characteristics of the comparator.
Table 5-33. Comparator_E
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
VCC
MIN
TYP
MAX
12
16
10
14
0.1
0.3
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 85°C
0.3
1.3
CEREFLx = 01, CERSx = 10,
REFON = 0, CEON = 1,
CEREFACC = 0
31
38
CEPWRMD = 00, CEON = 1,
CERSx = 00 (fast)
IAVCC_COMP
IAVCC_COMP_REF
VREF
Comparator operating
supply current into AVCC,
excludes reference
resistor ladder
Quiescent current of
resistor ladder into AVCC,
including REF module
current
Reference voltage level
VIC
Common-mode input
range
VOFFSET
Input offset voltage
CIN
RSIN
tPD
tPD,filter
Input capacitance
Series input resistance
Propagation delay,
response time
Propagation delay with
filter active
CEPWRMD = 01, CEON = 1,
CERSx = 00 (medium)
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 30°C
CEREFLx = 01, CERSx = 10,
REFON = 0, CEON = 1,
CEREFACC = 1
2.2 V, 3.0 V
µA
2.2 V, 3.0 V
µA
16
19
CERSx = 11, CEREFLx = 01,
CEREFACC = 0
1.8 V
1.152
1.2
1.248
CERSx = 11, CEREFLx = 10,
CEREFACC = 0
2.2 V
1.92
2.0
2.08
CERSx = 11, CEREFLx = 11,
CEREFACC = 0
2.7 V
2.40
2.5
2.60
CERSx = 11, CEREFLx = 01,
CEREFACC = 1
1.8 V
1.10
1.2
1.245
CERSx = 11, CEREFLx = 10,
CEREFACC = 1
2.2 V
1.90
2.0
2.08
CERSx = 11, CEREFLx = 11,
CEREFACC = 1
2.7 V
2.35
2.5
2.60
V
0
VCC – 1
CEPWRMD = 00
–16
16
CEPWRMD = 01
–12
12
CEPWRMD = 10
–37
37
CEPWRMD = 00 or
CEPWRMD = 01
10
CEPWRMD = 10
10
On (switch closed)
Off (switch open)
UNIT
1
V
mV
pF
3
50
kΩ
MΩ
CEPWRMD = 00, CEF = 0,
Overdrive ≥ 20 mV
193
330
CEPWRMD = 01, CEF = 0,
Overdrive ≥ 20 mV
230
400
CEPWRMD = 10, CEF = 0,
Overdrive ≥ 20 mV
5
15
µs
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 00
700
1000
ns
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 01
1.0
1.9
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 10
2.0
3.7
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 11
4.0
7.7
ns
Specifications
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PARAMETER
µs
63
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Table 5-33. Comparator_E (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TYP
MAX
CEON = 0 → 1,
VIN+ and VIN– from pins,
Overdrive ≥ 20 mV,
CEPWRMD = 00
0.9
1.5
CEON = 0 → 1,
VIN+ and VIN– from pins,
Overdrive ≥ 20 mV,
CEPWRMD = 01
0.9
1.5
CEON = 0 → 1,
VIN+ and VIN– from pins,
Overdrive ≥ 20 mV,
CEPWRMD = 10
15
65
tEN_CMP_VREF
CEON = 0 → 1, CEREFLX = 10,
Comparator and reference
CERSx = 10 or 11,
ladder and reference
CEREF0 = CEREF1 = 0x0F,
voltage enable time
REFON = 0
120
220
tEN_CMP_RL
CEON = 0 → 1, CEREFLX = 10,
Comparator and reference
CERSx = 10, REFON = 1,
ladder enable time
CEREF0 = CEREF1 = 0x0F
10
30
VCE_REF
Reference voltage for a
given tap
VIN ×
(n + 1)
/ 32
VIN ×
(n + 1.5)
/ 32
tEN_CMP
TEST CONDITIONS
Comparator enable time
VCC
MIN
UNIT
µs
µs
ADVANCE INFORMATION
VIN ×
(n +
0.5)
/ 32
VIN = reference into resistor ladder,
n = 0 to 31
V
5.13.13 FRAM
Table 5-34 lists the characteristics of the FRAM.
Table 5-34. FRAM Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
Data retention duration
IWRITE
Current to write into FRAM (1)
IERASE
Erase current (2)
tWRITE
Write time (4)
tREAD
Read time (5)
(1)
(2)
(3)
(4)
(5)
64
TYP
15
Read and write endurance
tRetention
MIN
10
25°C
100
70°C
40
85°C
10
MAX
UNIT
cycles
years
IREAD
nA
N/A (3)
nA
tREAD
ns
NWAITSx = 0
1 / fSYSTEM
NWAITSx = 1
2 / fSYSTEM
ns
Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption, IAM,FRAM.
FRAM does not require a special erase sequence.
N/A = Not applicable
Writing into FRAM is as fast as reading.
The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
Specifications
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5.13.14 USS
Table 5-35 lists the USS recommended operating conditions.
Table 5-35. USS Recommended Operating Conditions
PARAMETER
PVCC
TEST CONDITIONS
Analog supply voltage at PVCC pins
MIN
MAX
For LDO operation
2.2
3.6
For USS operation
2.2
3.6
UNIT
V
Table 5-36 lists the characteristics of the USS LDO.
Table 5-36. USS LDO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC_ldo
Analog supply voltage at PVCC pins
Vuss
USS voltage
MIN
TYP
2.2
0 ≤ ILOAD ≤ ILOAD,MAX
1.52
1.6
MAX
UNIT
3.6
V
1.65
V
ADVANCE INFORMATION
Table 5-37 lists the characteristics of the USS crystal.
Table 5-37. USSXTAL
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Nphase_osc
Integrated phase noise
FRQXTAL
Resonator frequency
DCosc
Duty cycle
Iosc
OSC supply current
Aosc
Oscillation allowance
Tstart_osc
Start-up time (gate)
TEST CONDITIONS
MIN
TYP
fosc = 4 MHz or 8 MHz, range = 10 kHz to 4 MHz
MAX
UNIT
–74
dBc
4
8
MHz
35
65
%
fosc = 4 MHz or 8 MHz, CL = 18 pF, CS = 4 pF, fully
settled, ceramic resonator
180
fosc = 4 MHz or 8 MHz, CL = 12 pF (4 MHz) or 16 pF
(8 MHz), CS = 7 pF, fully settled, crystal resonator
240
µA
fosc = 4 MHz, CL = 18 pF, CS = 4 pF, ceramic resonator
1500
fosc = 4 MHz, CL = 12 pF, CS = 7 pF, crystal resonator
1000
Ω
fosc = 8 MHz, CL = 18 pF, CS = 4 pF, ceramic resonator
500
fosc = 8 MHz, CL = 16 pF, CS = 7 pF, crystal resonator
350
fosc = 4 MHz, crystal resonator
2.8
fosc = 8 MHz, crystal resonator
1
1.9
fosc = 4 MHz, ceramic resonator
0.14
0.17
fosc = 8 MHz, ceramic resonator
0.08
0.12
4.6
ms
Table 5-38 lists the characteristics of the USS HSPLL.
Table 5-38. USS HSPLL
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
PLL_CLKin
Input clock to HSPLL
PLL_CLKout
Output clock from HSPLL
LOCKpwr
Lock time from PLL power up
TEST CONDITIONS
Reference clock = PLL_CLKin,
Sequence: Set USS.CTL.USSPWRUP bit = 1, then
measure the time from when PSQ_PLLUP (internal
control signal) is set to 1 to when
HSPLL.CTL.PLL_LOCK is set to 1.
MIN
TYP
MAX
UNIT
4
8
MHz
68
80
MHz
64
cycles
Specifications
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Table 5-39 lists the characteristics of the USS SDHS.
Table 5-39. USS SDHS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.52
1.6
1.65
V
Vsdhs
SDHS power domain
supply voltage
Vsdhs = Vuss
Isdhs_product
Operating supply
current into AVCC and
DVCC
Includes PLL, PGA, SDHS, and DTC,
modulator clock = 80 MHz, output data rate = 8 Msps
VSDHS_FS
Full-scale voltage (1)
755
mVpp
VIN_SDHS_MAX
Maximum input voltage
to SDHS (1)
600
mVpp
fm
Modulator clock
frequency (1)
80
MHz
BWmod
Frequency at –3-dB
SNR
ADVANCE INFORMATION
Signal-to-noise ratio (2)
SNR
4.75
68
Modulator clock = 80 MHz, modulator only (no filter is
enabled)
1.5
Input signal level
= 1000 mVpp, PVCC = 3.0 V,
fmod = 80 MHz, OSR = 20
60
63
Input signal level = 760 mVpp,
PVCC = 2.5 V, fmod = 80 MHz,
OSR = 20
60
63
56
58
51
54
40
43
Bandwidth up to
1.5 MHz, PGA gain: a
Input signal level = 200 mVpp,
gain from the PGA gain PVCC = 2.5 V, fmod = 80 MHz,
table for the maximum OSR = 20
SNR
Input signal level = 100 mVpp,
PVCC = 2.5 V, fmod = 80 MHz,
OSR = 20
Input signal level = 30 mVpp,
PVCC = 2.5 V, fmod = 80 MHz,
OSR = 20
TM2 – TM1, AUTOSSDIS = 0, 5% of settled DC level
SDHS settling time
(PGA + modulator)
tMOD_Settle
DROUTsdhs
(1)
(2)
mA
MHz
dB
40
TM2 – TM1, AUTOSSDIS = 1, 5% of settled DC level
40
TM2 – TM1, AUTOSSDIS = 0, 1% of settled DC level
170
TM2 – TM1, AUTOSSDIS = 1, 1% of settled DC level
170
Output data rate
µs
8
Msps
MAX
UNIT
Informative parameter, not characterized
SNR as specified, SINAD and THD not specified over complete signal chain
Table 5-40 lists the characteristics of the USS PHY outputs.
Table 5-40. USS PHY Output Stage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
PVCC
PHY supply voltage
PVCC = VCC, PVSS = VSS
RDSonT
Output impedance of CH0OUT and CH1OUT for
high and low sides (trimmed at 3-V PVDD)
PVCC ≥ 2.5 V
4
Ω
RTerm
Termination impedance of CH0OUT and
CH1OUT toward PVSS (trimmed)
PVCC ≥ 2.5 V
4
Ω
DrvM
High-side to low-side drive mismatch (trimmed)
PVCC ≥ 2.5 V
5%
12%
TermM
Termination to drive mismatch (trimmed)
PVCC ≥ 2.5 V
5%
12%
fMAX
Maximum output frequency
PVCC = VCC (2.5 V to 3.6 V)
4.5
CSUPP
Supply buffering capacitance (low-ESR type)
PVCC = VCC
22
RSUPP
Series resistance to CSUPP
PVCC = VCC
66
Specifications
2.2
3.6
V
MHz
100
uF
22
Ω
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Table 5-41 lists the characteristics of the USS PHY inputs.
Table 5-41. USS PHY Input Stage, Multiplexer
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VIN
TEST CONDITIONS
Input voltage on CH0IN or CH1IN
PVCC = VCC, PVSS = VSS
MIN
MAX
PVSS – 0.3
1.8
UNIT
V
MAX
UNIT
Table 5-42 lists the characteristics of the USS PGA.
Table 5-42. USS_PGA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
MIN
Supply voltage
(1)
TYP
2.2
3.6
V
GN
Gain
–6.5
30.8
dB
Vinr1
Input range
2.2 V ≤ PVCC
30
800
mVpp
Vinr2
Input range
2.5 V ≤ PVCC
30
1000
mVpp
Gtol
Gain tolerance
Full PGA gain range, VOUT = 600 mV
–2
1
GTdrift
Gain drift over
temperature
Full PGA gain range, VOUT = 600 mV
0.0019
dB/℃
GVdrift
Gain drift over voltage
Full PGA gain range, VOUT = 600 mV
0.0086
dB/V
TSET
Gain settling time
Gain setting: from 0 dB to 6 dB, to ±5%
DCoffset
DC offset (PGA and
SDHS)
Full PGA gain range, measured at SDHS output
5.5
DCdrift
DC offset drift (PGA
and SDHS)
Full PGA gain range, measured at SDHS output
2
PSRR_AC
AC power supply
rejection ratio
VCC = 3 V + 50 mVpp × sin (2π × fC)
where fC = 1 MHz, VIN = ground,
PSRR_AC = 20log(VOUT / 50 mV)
(1)
0.65
PGA gain = 0 dB
–41
PGA gain = 10 dB
–37
PGA gain = 30 dB
–19
1.4
dB
µs
mV
µV/℃
dB
See the PGA Gain Table in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide.
Table 5-43 lists the characteristics of the USS bias voltage generator.
Table 5-43. USS Bias Voltage Generator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
200
EXCBIAS = 1
300
EXCBIAS = 2
400
EXCBIAS = 3
600
EXCBIAS = 0
250
EXCBIAS = 1
250
Vexc_bias
RVBE
Impedace of excitation bias
generator
PVCC = VCC (2.2 V to 3.6 V)
tSBE
Excitation bias settling time
PVCC = VCC (2.2 V to 3.6 V), to 0.1% of end value,
RET = 200 Ω, CK + C0P = 1 nF
Vpga_bias
PGA bias voltage (coupling
capacitors)
PVCC = VCC (2.2 V to 3.6 V)
TYP
EXCBIAS = 0
Excitation bias voltage (coupling
capacitors)
PVCC = VCC (2.2 V to 3.6 V)
MIN
4
PGABIAS = 0
750
PGABIAS = 1
800
PGABIAS = 2
900
PGABIAS = 3
950
EXCBIAS = 0
250
EXCBIAS = 1
250
RVBA
Impedace of acquisition bias
generator
PVCC = VCC (2.2 V to 3.6 V)
tSBA
Acquisition bias settling time
PVCC = VCC (2.2 V to 3.6 V), to 0.1% of end value,
RET = 200 Ω, CK + C0P = 1 nF
MAX
4
Specifications
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UNIT
mV
Ω
µs
mV
Ω
µs
67
ADVANCE INFORMATION
PARAMETER
PVcc
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5.13.15 Emulation and Debug
Table 5-44 lists the characteristics of the JTAG and SBW interface.
Table 5-44. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
40
UNIT
IJTAG
Supply current adder when JTAG active (but not clocked)
2.2 V, 3.0 V
100
μA
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3.0 V
0
10
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3.0 V
0.04
15
μs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2.2 V, 3.0 V
110
μs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
μs
15
100
2.2 V
0
16
3.0 V
0
16
2.2 V, 3.0 V
20
ADVANCE INFORMATION
fTCK
TCK input frequency, 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
50
kΩ
fTCLK
TCLK/MCLK frequency during JTAG access, no FRAM access
(limited by fSYSTEM)
16
MHz
tTCLK,Low/High
TCLK low or high clock pulse duration, no FRAM access
25
ns
fTCLK,FRAM
TCLK/MCLK frequency during JTAG access, including FRAM access
(limited by fSYSTEM with no FRAM wait states)
4
MHz
tTCLK,FRAM,
TCLK low or high clock pulse duration, including FRAM accesses
35
100
MHz
ns
Low/High
(1)
(2)
68
Tools that access the Spy-Bi-Wire and the BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK
pin (low to high), before the second transition of the pin (high to low) during the entry sequence.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
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6 Detailed Description
6.1
Overview
The TI MSP430FR60xx(1) family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals. The architecture, combined with seven low-power modes, is optimized to
achieve extended battery life for example in portable measurement applications. The devices features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency.
The device is an MSP430FR6xx family device with Ultrasonic Sensing Solution (USS), Low-Energy
Accelerator (LEA), up to six 16-bit timers, up to six eUSCIs that support UART, SPI, and I2C, a
comparator, a hardware multiplier, an AES accelerator, a 6-channel DMA, an RTC module with alarm
capabilities, up to 76 I/O pins, and a high-performance 12-bit ADC. The MSP430FR60xx(1) devices also
include an LCD module with contrast control for displays with up to 264 segments.
CPU
The MSP430™ CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses. The peripherals can be
managed with all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
6.3
Ultrasonic Sensing Solution (USS) Module
The USS module provides a high-precision ultrasonic sensing solution. The USS module is a
sophisticated system that consists of six submodules:
• UUPS (universal USS power supply)
• HSPLL (high-speed PLL) with oscillator
• ASQ (acquisition sequencer)
• PPG (programmable pulse generator) with low-output-impedance driver
• PGA (programmable gain amplifier)
• SDHS (sigma-delta high-speed ADC) with DTC (data transfer controller)
The submodules have different roles, and together they enable high-precision data acquisition in
ultrasonic applications.
The USS module performs complete measurement sequence without CPU involvement to achieve ultralow power consumption for ultrasonic metrology. Figure 6-1 shows the USS subsystem block diagram.
The USS module has dedicated I/O pins, which are not I/O ports (P1.x to PJ.x) . See the Ultrasonic
Sensing Solution (USS) chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx,
MSP430FR69xx Family User's Guide for details.
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ADVANCE INFORMATION
6.2
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USS Module
USSXT
USSXTIN USSXTOUT
USSXT_BOUT
MSP430FRxxxx
SAPH
CH0_OUT
CH1_OUT
PHY
OSC
ASQ
PPG
PVSS
PVCC
PLL_CLK
PLL
VOUT
UUPS
HSPLL
PVSS
SDHS
CH0_IN
PGA
RAM
(Shared with LEA)
MOD
Filter
DTC
CH1_IN
ADVANCE INFORMATION
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Figure 6-1. USS Subsystem Block Diagram
6.4
Low-Energy Accelerator (LEA) for Signal Processing
The LEA is a hardware engine designed for operations that involve vector-based signal processing, such
as FIR, IIR, and FFT. The LEA offers fast performance and low energy consumption when performing
vector-based digital signal processing computations. For performance benchmarks comparing LEA to
using the CPU or other processors, see Benchmarking the Signal Processing Capabilities of the LowEnergy Accelerator.
The LEA requires MCLK to be operational; therefore, LEA operates only in active mode or LPM0 (see ).
While the LEA is running, the LEA data operations are performed on a shared 4KB of RAM out of the 8KB
of total RAM (see ). This shared RAM can also be used by the regular application. The MSP CPU and the
LEA can run simultaneously and independently unless they access the same system RAM.
Direct access to LEA registers is not supported, and TI recommends using the optimized Digital Signal
Processing (DSP) Library for MSP Microcontrollers for the operations that the LEA module supports.
70
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Operating Modes
The MCU has one active mode and seven software selectable low-power modes of operation. An interrupt event can wake up the device from lowpower modes LPM0 to LPM4, service the request, and restore back to the low-power mode on return from the interrupt program. Low-power
modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption. Table 6-1 lists the operating modes and the clocks and
peripherals that are available in each.
Table 6-1. Operating Modes
AM
ACTIVE,
FRAM
OFF (1)
ACTIVE
Maximum system clock
Typical current consumption,
TA = 25°C
16 MHz
103 µA/MHz
Typical wake-up time
65 µA/MHz
N/A
LPM0
LPM1
LPM2
LPM3
LPM4
LPM3.5
LPM4.5
CPU OFF (2)
CPU OFF
STANDBY
STANDBY
OFF
RTC ONLY
16 MHz
16 MHz
50 kHz
50 kHz
0 (3)
50 kHz
70 µA at 1 MHz
35 µA at 1 MHz
0.7 µA
0.4 µA
0.3 µA
0.25 µA
0.2 µA
0.02 µA
instant
6 µs
6 µs
7 µs
7 µs
250 µs
250 µs
1000 µs
LF
RTC
I/O
Comp
I/O
Comp
RTC
I/O
I/O
SHUTDOWN
WITH SVS
SHUTDOWN
WITHOUT SVS
0 (3)
Wake-up events
N/A
all
all
LF
RTC
I/O
Comp
CPU
on
off
off
off
off
off
reset
reset
USS
on
on
off
off
off
off
reset
reset
LEA
on
off
off
off
off
reset
reset
standby
(or off (1))
off
off
off
off
off
off
available
available
off
off
off
reset
reset
reset
FRAM
High-frequency peripherals
on (4)
off (1)
on
available
Low-frequency peripherals
available
Unclocked peripherals (6)
available
MCLK
SMCLK
available
available
available
available (5)
off
RTC
MTIF
available
available
available
available (5)
available (5)
reset
reset
off
off
off
off
off
off
on (4)
on
(7)
off
optional
(7)
off
off
off
off
off
on
on
on
on
on
off
off
off
Full retention
yes
yes
yes
yes
yes
yes
no
no
(3)
(4)
(5)
(6)
(7)
optional
(7)
ACLK
(1)
(2)
optional
off
ADVANCE INFORMATION
MODE
FRAM is disabled in the FRAM controller (FRCTL_A).
Disabling the FRAM through the FRAM controller (FRCTL_A) allows the application to lower the LPM current consumption but the wake-up time increases when FRAM is accessed (for
example, to fetch an interrupt vector). For a wakeup that does not involve FRAM (for example, a DMA transfer to RAM) the wake-up time is not increased.
All clocks disabled
Only while LEA is performing the task enabled by CPU during AM. LEA cannot be enabled in LPM0.
See Section 6.5.2, which describes the use of peripherals in LPM3 and LPM4.
"Unclocked peripherals" are peripherals that do not require a clock source to operate; for example, the comparator and REF, or the eUSCI when operated as an SPI slave.
Controlled by SMCLKOFF.
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Table 6-1. Operating Modes (continued)
MODE
AM
ACTIVE
ACTIVE,
FRAM
OFF (1)
LPM0
LPM1
LPM2
LPM3
LPM4
LPM3.5
CPU OFF (2)
CPU OFF
STANDBY
STANDBY
OFF
RTC ONLY
SHUTDOWN
WITH SVS
SHUTDOWN
WITHOUT SVS
on (9)
off (10)
SVS
always
always
always
optional (8)
optional (8)
optional (8)
optional (8)
Brownout
always
always
always
always
always
always
always
LPM4.5
always
(8) Activated SVS (SVSHE = 1) results in higher current consumption. SVS is not included in typical current consumption.
(9) SVSHE = 1
(10) SVSHE = 0
ADVANCE INFORMATION
72
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Peripherals in Low-Power Modes
Peripherals can be in different states that affect the achievable power modes of the device. The states
depend on the operational modes of the peripherals (see Table 6-2). The states are:
• A peripheral is in a "high-frequency state" if it requires or uses a clock with a "high" frequency of more
than 50 kHz.
• A peripheral is in a "low-frequency state" if it requires or uses a clock with a "low" frequency of 50 kHz
or less.
• A peripheral is in an "unclocked state" if it does not require or use an internal clock.
If the CPU requests a power mode that does not support the current state of all active peripherals, the
device does not enter the requested power mode, but it does enter a power mode that still supports the
current state of the peripherals, except if an external clock is used. If an external clock is used, the
application must use the correct frequency range for the requested power mode.
PERIPHERAL
WDT
IN HIGH-FREQUENCY STATE
Clocked by SMCLK
IN LOW-FREQUENCY STATE (2)
IN UNCLOCKED STATE (3)
Clocked by ACLK
Not applicable
(4)
Not applicable
Not applicable
Waiting for a trigger
RTC_C
Not applicable
Clocked by LFXT.
Not applicable
LCD_C
Not applicable
Clocked by ACLK or VLOCLK.
Not applicable
Timer_A, TAx
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Timer_B, TBx
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Ax in
UART mode
Clocked by SMCLK
Clocked by ACLK
Waiting for first edge of START bit.
eUSCI_Ax in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Ax in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Bx in I C
master mode
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Not applicable
eUSCI_Bx in I2C
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Waiting for START condition or
clocked by external clock ≤50 kHz
eUSCI_Bx in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Bx in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Clocked by SMCLK or by MODOSC
Clocked by ACLK
Waiting for a trigger
REF_A
Not applicable
Not applicable
Always
COMP_E
Not applicable
Not applicable
Always
CRC (5)
Not applicable
Not applicable
Not applicable
MPY (5)
Not applicable
Not applicable
Not applicable
AES (5)
Not applicable
Not applicable
Not applicable
DMA
2
ADC12_B
(1)
(2)
(3)
(4)
(5)
ADVANCE INFORMATION
Table 6-2. Peripheral States
(1)
Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz
Peripherals are in a state that requires or uses a clock with a "low" frequency of 50kHz or less.
Peripherals are in a state that does not require or does not use an internal clock.
The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power
mode causes a temporary transition into active mode for the time of the transfer.
This peripheral operates during active mode only and will delay the transition into a low-power mode until its operation is completed.
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6.5.2
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Idle Currents of Peripherals in LPM3 and LPM4
Most peripherals can be operational in LPM3 if clocked by ACLK. Some modules are operational in LPM4,
because they do not require a clock to operate (for example, the comparator). Activating a peripheral in
LPM3 or LPM4 increases the current consumption due to its active supply current contribution but also
due to an additional idle current. To reduce the idle current adder, certain peripherals are grouped
together. To achieve optimal current consumption, use modules within one group and limit the number of
groups with active modules. Table 6-3 lists the peripheral groups. Modules not listed in this table are either
already included in the standard LPM3 current consumption or cannot be used in LPM3 or LPM4.
The idle current adder is very small at room temperature (25°C) but increases at high temperatures
(85°C); see the IIDLE current parameters in for details.
Table 6-3. Peripheral Groups
GROUP A
GROUP B
GROUP C
Timer TA1
Timer TA0
Timer TA4
Timer TA2
Timer TA3
eUSCI_A2
ADVANCE INFORMATION
Timer TB0
Comparator
eUSCI_A3
eUSCI_A0
ADC12_B
eUSCI_B1
eUSCI_A1
REF_A
LCD_C
eUSCI_B0
6.6
Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address, and signatures are in the address range 0FFFFh to
0FF80h. Figure 6-2 summarizes the content of this address range.
Reset Vector
0FFFFh
BSL Password
Interrupt
Vectors
0FFE0h
JTAG Password
Reserved
Signatures
0FF88h
0FF80h
Figure 6-2. Interrupt Vectors, Signatures and Passwords
The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing
to the start address of the application program.
The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence. Table 6-4 shows the device-specific
interrupt vector locations.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if
enabled by the corresponding signature).
74
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The signatures are located at 0FF80h and extend to higher addresses. Signatures are evaluated during
device start-up. Table 6-5 shows the device-specific signature locations.
A JTAG password can be programmed starting from address 0FF88h and extending to higher addresses.
The password can extend into the interrupt vector locations using the interrupt vector addresses as
additional bits for the password. The length of the JTAG password depends on the JTAG signature.
See the chapter System Resets, Interrupts, and Operating Modes, System Control Module (SYS) in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide for details.
Table 6-4. Interrupt Sources, Flags, and Vectors
System Reset
Power up, brownout, supply
supervisor
External reset RST
Watchdog time-out (watchdog
mode)
WDT, FRCTL MPU, CS,
PMM password violation
FRAM uncorrectable bit error
detection
MPU segment violation
Software POR, BOR
System NMI
Vacant memory access
JTAG mailbox
FRAM access time error
FRAM write protection error
FRAM bit error detection
MPU segment violation
(1)
(2)
(3)
(4)
INTERRUPT FLAG
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV) (1) (2)
VMAIFG
JMBINIFG, JMBOUTIFG
ACCTEIFG, WPIFG
CBDIFG, UBDIFG
MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG
(SYSSNIV) (1) (3)
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
Highest
(Non)maskable
0FFFCh
User NMI
External NMI
Oscillator fault
LEA RAM access conflict
NMIIFG, OFIFG
DACCESSIFG
(SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
Comparator_E
CEIFG, CEIIFG
(CEIV) (1)
Maskable
0FFF8h
TB0
TB0CCR0.CCIFG
Maskable
0FFF6h
TB0
TB0CCR1.CCIFG to TB0CCR6.CCIFG,
TB0CTL.TBIFG
(TB0IV) (1)
Maskable
0FFF4h
Watchdog timer (interval timer
mode)
WDTIFG
Maskable
0FFF2h
eUSCI_A0 receive or transmit
UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA0IV) (1)
Maskable
0FFF0h
eUSCI_B0 receive or transmit
UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV) (1)
Maskable
0FFEEh
ADC12_B
ADC12IFG0 to ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG,
ADC12RDYIFG, ADC21OVIFG, ADC12TOVIFG
(ADC12IV) (1) (4)
Maskable
0FFECh
TA0
TA0CCR0.CCIFG
Maskable
0FFEAh
ADVANCE INFORMATION
INTERRUPT SOURCE
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.
Only on devices with ADC, otherwise reserved.
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Table 6-4. Interrupt Sources, Flags, and Vectors (continued)
ADVANCE INFORMATION
76
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
TA0
TA0CCR1.CCIFG, TA0CCR2.CCIFG,
TA0CTL.TAIFG
(TA0IV) (1)
Maskable
0FFE8h
eUSCI_A1 receive or transmit
UCA1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA1IV) (1)
Maskable
0FFE6h
DMA
DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,
DMA2CTL.DMAIFG
(DMAIV) (1)
Maskable
0FFE4h
TA1
TA1CCR0.CCIFG
Maskable
0FFE2h
TA1
TA1CCR1.CCIFG, TA1CCR2.CCIFG,
TA1CTL.TAIFG
(TA1IV) (1)
Maskable
0FFE0h
I/O port P1
P1IFG.0 to P1IFG.7
(P1IV) (1)
Maskable
0FFDEh
TA2
TA2CCR0.CCIFG
Maskable
0FFDCh
TA2
TA2CCR1.CCIFG
TA2CTL.TAIFG
(TA2IV) (1)
Maskable
0FFDAh
I/O port P2
P2IFG.0 to P2IFG.7
(P2IV) (1)
Maskable
0FFD8h
TA3
TA3CCR0.CCIFG
Maskable
0FFD6h
TA3
TA3CCR1.CCIFG
TA3CTL.TAIFG
(TA3IV) (1)
Maskable
0FFD4h
I/O port P3
P3IFG.0 to P3IFG.7
(P3IV) (1)
Maskable
0FFD2h
I/O port P4
P4IFG.0 to P4IFG.2
(P4IV) (1)
Maskable
0FFD0h
LCD_C
LCD_C Interrupt Flags (LCDCIV) (1)
Maskable
0FFCEh
RTC_C
RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG,
RT1PSIFG, RTCOFIFG
(RTCIV) (1)
Maskable
0FFCCh
AES
AESRDYIFG
Maskable
0FFCAh
TA4
TA4CCR0.CCIFG
Maskable
0FFC8h
TA4
TA4CCR1.CCIFG
TA4CTL.TAIFG
(TA4IV) (1)
Maskable
0FFC6h
I/O port P5
P5IFG.0 to P5IFG.2
(P5IV) (1)
Maskable
0FFC4h
I/O port P6
P6IFG.0 to P6IFG.2
(P6IV) (1)
Maskable
0FFC2h
eUSCI_A2 receive or transmit
UCA2IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA2IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA2IV) (1)
Maskable
0FFC0h
eUSCI_A3 receive or transmit
UCA3IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA3IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA3IV) (1)
Maskable
0FFBEh
eUSCI_B1 receive or transmit
UCB1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB1IV) (1)
Maskable
0FFBCh
Detailed Description
PRIORITY
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Table 6-4. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
I/O Port P7
P7IFG.0 to P7IFG.2
(P7IV) (1)
Maskable
0FFBAh
I/O Port P8
P8IFG.0 to P8IFG.2
(P8IV) (1)
Maskable
0FFB8h
I/O Port P9
P9IFG.0 to P9IFG.2
(P9IV) (1)
Maskable
0FFB6h
LEA
CMDIFG, SDIIFG, OORIFG, TIFG, COVLIFG
(LEAIV) (1)
Maskable
0FFB4h
UUPS
PTMOUT, PREQIG
(IIDX) (1)
Maskable
0FFB2h
HSPLL
PLLUNLOCK
(IIDX) (1)
Maskable
0FFB0h
SAPH
DATAERR, TAMTO, SEQDN, PNGDN
(IIDX) (1)
Maskable
0FFAEh
SDHS
OVF, ACQDONE, SSTRG, DTRDY, WINHI,
WINLO
(IIDX) (1)
Maskable
0FFACh
PRIORITY
Lowest
Table 6-5. Signatures
SIGNATURE
WORD ADDRESS
IP Encapsulation Signature2
IP Encapsulation Signature1
(1)
6.7
(1)
0FF8Ah
0FF88h
BSL Signature2
0FF86h
BSL Signature1
0FF84h
JTAG Signature2
0FF82h
JTAG Signature1
0FF80h
Must not contain 0AAAAh if used as the JTAG password.
Bootloader (BSL)
The BSL can program the FRAM or RAM using a UART serial interface (FRxxxx devices) or an I2C
interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an userdefined password. Table 6-6 lists the pins that are required for use of the BSL. BSL entry requires a
specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description
of the features of the BSL and its implementation, see the MSP430FR57xx, FR58xx, FR59xx, FR68xx,
and FR69xx Bootloader (BSL) User's Guide. More information on the BSL can be found at
www.ti.com/tool/mspbsl.
Detailed Description
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INTERRUPT SOURCE
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Table 6-6. BSL Pin Requirements and Functions
6.8
6.8.1
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P2.0
Devices with UART BSL (FRxxxx): Data transmit
P2.1
Devices with UART BSL (FRxxxx): Data receive
P1.6
Devices with I2C BSL (FRxxxx1): Data
P1.7
Devices with I2C BSL (FRxxxx1): Clock
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
ADVANCE INFORMATION
The MSP family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP development tools and device programmers. Table 6-7 lists the JTAG pin requirements. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools
User's Guide. For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming With the JTAG Interface.
Table 6-7. JTAG Pin Requirements and Functions
6.8.2
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP family supports the two wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP development tools and device programmers. The Spy-BiWire interface pin requirements are shown in Table 6-8. For further details on interfacing to development
tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete
description of the features of the JTAG interface and its implementation, see MSP430 Programming With
the JTAG Interface.
Table 6-8. Spy-Bi-Wire Pin Requirements and Functions
78
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
VCC
Power supply
VSS
Ground supply
Detailed Description
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6.9
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FRAM Controller A (FRCTL_A)
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
• Ultra-low-power ultra-fast-write nonvolatile memory
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
NOTE
Wait States
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
MSP430™ FRAM Technology – How To and Best Practices.
6.10 RAM
The RAM is made up of three sectors: Sector 0 = 2KB, Sector 1 = 2KB, Sector 2 = 4KB (shared with
LEA). Each sector can be individually powered down in LPM3 and LPM4 to save leakage. Data is lost
when sectors are powered down in LPM3 and LPM4.
6.11 Tiny RAM
Twenty-two bytes of Tiny RAM are provided in addition to the complete RAM (see Table 6-47). This
memory is always available, even in LPM3 and LPM4, while the complete RAM can be powered down in
LPM3 and LPM4. Tiny RAM can be used to hold data or a very small stack when the complete RAM is
powered down in LPM3 and LPM4. No memory is available in LPMx.5.
6.12 Memory Protection Unit (MPU) Including IP Encapsulation
The FRAM can be protected by the MPU from inadvertent CPU execution, read access, or write access.
Features of the MPU include:
• IP encapsulation with programmable boundaries in steps of 1KB (prevents reads from "outside"; for
example, through JTAG or by non-IP software).
• Main memory partitioning is programmable up to three segments in steps of 1KB.
• Access rights of each segment can be individually selected (main and information memory).
• Access violation flags with interrupt capability for easy servicing of access violations.
Detailed Description
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For MCLK frequencies > 8 MHz, wait states must be configured following the flow described
in the "Wait State Control" section of the FRAM Controller A (FRCTRL_A) chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
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6.13 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
controlled using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
6.13.1 Digital I/O
ADVANCE INFORMATION
Up to nine 8-bit I/O ports are implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input is available for all pins of ports P1,
P2, P3, P4, P5, P6, P7, P8, and P9.
• Read and write access to port control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• All pins of ports P1, P2, P3, P4, P5, P6, P7, P8, P9, and PJ support capacitive-touch functionality.
• No cross currents during start-up.
NOTE
Configuration of Digital I/Os After BOR Reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and their module functions disabled. To enable the I/O functionality after
a BOR reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared.
For details, see the Configuration After Reset section of the "Digital I/O" chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
6.13.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-lowpower low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements
of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources.
The clock system module provides the following clock signals:
• Auxiliary clock (ACLK). ACLK can be sourced from a 32-kHz watch crystal (LFXT1), the internal VLO,
or a digital external low-frequency (<50 kHz) clock source.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency
crystal (HFXT2), the internal DCO, a 32-kHz watch crystal (LFXT1), the internal VLO, or a digital
external clock source.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to MCLK.
6.13.3 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device . The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout circuit provides the
proper internal reset signal to the device during power on and power off. The SVS circuitry detects if the
supply voltage drops below a safe level and below a user-selectable level. SVS circuitry is available on the
primary and core supplies.
80
Detailed Description
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6.13.4 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed multiplication, unsigned
multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate operations.
6.13.5 Real-Time Clock (RTC_C)
The RTC_C module contains an integrated real-time clock (RTC) with the following features:
• Calendar mode with leap year correction
• General-purpose counter mode
The internal calendar compensates for months with fewer than 31 days and includes leap year correction.
The RTC_C also supports flexible alarm functions and offset-calibration hardware. RTC operation is
available in LPM3.5 modes to minimize power consumption.
The MTIF module provides a simple pulse-based test interface that is used to implement consumption
monitoring of "legal relevant data" with high integrity. MTIF consists of the a pulse generator, a pulse
counter, and a pulse interface. MTIF has following features:
• Independent passwords for generator counter and pulse interface
• Pulse rates up to 1016 pulses/second
• Pulse frame duration from 1/16 s to 16 s
• Count capacity up to 65535 (16 bit)
• Operating in LPM3.5 with 200 nA
• 2-pin interface with MTIF_OUT_IN and MTIF_PIN_EN
6.13.7 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart if a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as an interval timer and can generate interrupts at
selected time intervals. Table 6-9 lists the clocks that can source the WDT_A module.
Table 6-9. WDT_A Clocks
WDTSSEL
NORMAL OPERATION
(WATCHDOG AND INTERVAL TIMER MODE)
00
SMCLK
01
ACLK
10
VLOCLK
11
LFMODCLK
6.13.8 System Module (SYS)
The SYS module manages many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators, bootloader (BSL) entry mechanisms, and configuration management (device descriptors). The
SYS module also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be
used in the application. Table 6-10 lists the SYS module interrupt vector registers.
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6.13.6 Measurement Test Interface (MTIF)
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Table 6-10. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV, System Reset
ADDRESS
019Eh
ADVANCE INFORMATION
SYSSNIV, System NMI
82
019Ch
INTERRUPT EVENT
VALUE
No interrupt pending
00h
Brownout (BOR)
02h
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
06h
LPMx.5 wake up (BOR)
08h
Security violation (BOR)
0Ah
Reserved
0Ch
SVSHIFG SVSH event (BOR)
0Eh
Reserved
10h
Reserved
12h
PMMSWPOR software POR (POR)
14h
WDTIFG watchdog time-out (PUC)
16h
WDTPW password violation (PUC)
18h
FRCTLPW password violation (PUC)
1Ah
Uncorrectable FRAM bit error detection (PUC)
1Ch
Peripheral area fetch (PUC)
1Eh
PMMPW PMM password violation (PUC)
20h
MPUPW MPU password violation (PUC)
22h
CSPW CS password violation (PUC)
24h
MPUSEGIPIFG encapsulated IP memory segment violation
(PUC)
26h
Reserved
28h
MPUSEG1IFG segment 1 memory violation (PUC)
2Ah
MPUSEG2IFG segment 2 memory violation (PUC)
2Ch
MPUSEG3IFG segment 3 memory violation (PUC)
2Eh
Reserved
30h to 3Eh
No interrupt pending
00h
Reserved
02h
Uncorrectable FRAM bit error detection
04h
FRAM access time error
06h
MPUSEGIPIFG encapsulated IP memory segment violation
08h
Reserved
0Ah
MPUSEG1IFG segment 1 memory violation
0Ch
MPUSEG2IFG segment 2 memory violation
0Eh
MPUSEG3IFG segment 3 memory violation
10h
VMAIFG vacant memory access
12h
JMBINIFG JTAG mailbox input
14h
JMBOUTIFG JTAG mailbox output
16h
Correctable FRAM bit error detection
18h
FRAM Write Protection Detection
1Ah
LEA time-out fault
1Ch
LEA command fault
1Eh
Detailed Description
PRIORITY
Highest
Lowest
Highest
Lowest
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Table 6-10. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR
REGISTER
ADDRESS
SYSUNIV, User NMI
019Ah
INTERRUPT EVENT
VALUE
No interrupt pending
00h
NMIIFG NMI pin
02h
OFIFG oscillator fault
04h
DACCESSIFG
06h
PRIORITY
Highest
Reserved
08h
Reserved
0Ah to 1Eh
Lowest
6.13.9 DMA Controller
ADVANCE INFORMATION
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. Table 6-11 lists the available triggers for the DMA.
Table 6-11. DMA Trigger Assignments (1)
TRIGGER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
0
DMAREQ
DMAREQ
DMAREQ
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
TA2CCR0 CCIFG
TA2CCR0 CCIFG
TA2CCR0 CCIFG
TA2CCR0 CCIFG
TA2CCR0 CCIFG
TA2CCR0 CCIFG
6
TA3CCR0 CCIFG
TA3CCR0 CCIFG
TA3CCR0 CCIFG
TA3CCR0 CCIFG
TA3CCR0 CCIFG
TA3CCR0 CCIFG
7
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
8
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
9
TA4CCR0 CCIFG
TA4CCR0 CCIFG
TA4CCR0 CCIFG
TA4CCR0 CCIFG
TA4CCR0 CCIFG
10
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
11
AES Trigger 0
AES Trigger 0
AES Trigger 0
AES Trigger 0
AES Trigger 0
AES Trigger 0
12
AES Trigger 1
AES Trigger 1
AES Trigger 1
AES Trigger 1
AES Trigger 1
AES Trigger 1
13
AES Trigger 2
AES Trigger 2
AES Trigger 2
AES Trigger 2
AES Trigger 2
AES Trigger 2
14
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
UCA2RXIFG
UCA2RXIFG
UCA2RXIFG
15
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
UCA2TXIFG
UCA2TXIFG
UCA2TXIFG
16
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
UCA3RXIFG
UCA3RXIFG
UCA3RXIFG
17
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
UCA3TXIFG
UCA3TXIFG
UCA3TXIFG
18
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
19
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
20
UCB0RXIFG1 (I2C)
UCB0RXIFG1 (I2C)
UCB0RXIFG1 (I2C)
UCB1RXIFG1 (I2C)
UCB1RXIFG1 (I2C)
UCB1RXIFG1 (I2C)
21
UCB0TXIFG1 (I C)
UCB0TXIFG1 (I C)
UCB0TXIFG1 (I C)
UCB1TXIFG1 (I C)
UCB1TXIFG1 (I C)
UCB1TXIFG1 (I2C)
22
UCB0RXIFG2 (I2C)
UCB0RXIFG2 (I2C)
UCB0RXIFG2 (I2C)
UCB1RXIFG2 (I2C)
UCB1RXIFG2 (I2C)
UCB1RXIFG2 (I2C)
23
(1)
CHANNEL 5
2
2
UCB0TXIFG2 (I C)
2
2
2
UCB0TXIFG2 (I C)
2
2
2
UCB0TXIFG2 (I C)
2
2
2
UCB1TXIFG2 (I C)
2
2
2
UCB1TXIFG2 (I2C)
2
UCB1TXIFG2 (I C)
24
UCB0RXIFG3 (I C)
UCB0RXIFG3 (I C)
UCB0RXIFG3 (I C)
UCB1RXIFG3 (I C)
UCB1RXIFG3 (I C)
UCB1RXIFG3 (I2C)
25
UCB0TXIFG3 (I2C)
UCB0TXIFG3 (I2C)
UCB0TXIFG3 (I2C)
UCB1TXIFG3 (I2C)
UCB1TXIFG3 (I2C)
UCB1TXIFG3 (I2C)
26
ADC12 end of
conversion
ADC12 end of
conversion
ADC12 end of
conversion
ADC12 end of
conversion
ADC12 end of
conversion
ADC12 end of
conversion
27
LEA ready
LEA ready
LEA ready
LEA ready
LEA ready
LEA ready
28
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
29
MPY ready
MPY ready
MPY ready
MPY ready
MPY ready
MPY ready
If a reserved trigger source is selected, no trigger is generated.
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Table 6-11. DMA Trigger Assignments(1) (continued)
TRIGGER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
30
DMA2IFG
DMA0IFG
DMA1IFG
DMA5IFG
DMA3IFG
DMA4IFG
31
DMAE0
DMAE0
DMAE0
DMAE0
DMAE0
DMAE0
6.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baud-rate detection, and IrDA.
The eUSCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3 or 4 pin) and I2C.
Up to four eUSCI_A modules and up to four eUSCI_B modules are implemented.
6.13.11 TA0, TA1, and TA4
ADVANCE INFORMATION
TA0, TA1, and TA4 are 16-bit timers and counters (Timer_A type) with three (TA0 and TA1) or two (TA4)
capture/compare registers each. Each timer can support multiple captures or compares, PWM outputs,
and interval timing (see Table 6-12, Table 6-13, and Table 6-14). Each timer has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-12. TA0 Signal Connections
INPUT PORT PIN
P2.4, P4.5, P5.5
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
TA0CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
P2.4. P4.5, P5.5
TA0CLK
INCLK
P2.3
TA0.0
CCI0A
P2.7
TA0.0
CCI0B
DVSS
GND
P7.4
P7.7
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PORT PIN
P2.3
CCR0
TA0
TA0.0
P2.7
DVCC
VCC
TA0.1
CCI1A
P7.4
COUT (internal)
CCI1B
ADC12(internal) (1)
ADC12SHSx = {1}
DVSS
GND
CCR1
TA1
TA0.1
DVCC
VCC
TA0.2
CCI2A
P7.7
ACLK (internal)
CCI2B
UUPS Trigger
(USSPWRUP)
UUPS.CTL.USSPWRU
PSEL = {2}
DVSS
GND
DVCC
VCC
(1)
Only on devices with ADC.
84
Detailed Description
CCR2
TA2
TA0.2
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Table 6-13. TA1 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
P2.4, P4.5
TA1CLK
TACLK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PORT PIN
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
P2.4. P4.5
TA1CLK
INCLK
P1.0
TA1.0
CCI0A
P9.0
TA1.0
CCI0B
DVSS
GND
DVCC
VCC
TA1.1
CCI1A
P7.5
COUT (internal)
CCI1B
ADC12(internal) (1)
ADC12SHSx = {4}
DVSS
GND
P7.5
P8.4
(1)
MODULE
BLOCK
P1.0
CCR0
CCR1
TA0
TA1
TA1.0
TA1.1
P9.0
DVCC
VCC
TA1.2
CCI2A
P8.4
ACLK (internal)
CCI2B
ASQ Trigger
(ASQTRIG)
SAPH.ASCTL0.TRIGS
EL= {2}
DVSS
GND
DVCC
VCC
CCR2
TA2
TA1.2
Only on devices with ADC.
Table 6-14. TA4 Signal Connections
INPUT PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
PJ.1,P4.6
TA4CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PJ.1, P4.6
TA4CLK
INCLK
P1.1
TA4.0
CCI0A
P2.5
(1)
TA4.0
CCI0B
DVSS
GND
DVCC
VCC
P7.6
TA4.1
CCI1A
P2.6
TA4.1
CCI1B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PORT PIN
P1.1
CCR0
TA0
TA4.0
P2.5
P7.6
P2.6
CCR1
TA1
TA4.1
ADC12(internal) (1)
ADC12SHSx = {7}
Only on devices with ADC.
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6.13.12 TA2 and TA3
TA2 and TA3 are 16-bit timers and counters (Timer_A type) with two capture/compare registers each and
with internal connections only. Each timer can support multiple captures or compares, PWM outputs, and
interval timing (see Table 6-15 and Table 6-16). Each timer has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 6-15. TA2 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
COUT (internal)
TACLK
ADVANCE INFORMATION
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
From Capacitive Touch
I/O 0 (internal)
INCLK
TA3 CCR0 output
(internal)
CCI0A
ACLK (internal)
CCI0B
DVSS
GND
DVCC
VCC
From Capacitive Touch
I/O 0 (internal)
CCI1A
COUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
(1)
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT SIGNAL
TA3 CCI0A input
CCR0
TA0
ADC12(internal) (1)
ADC12SHSx = {5}
CCR1
TA1
PPG Trigger (PPGTRIG)
SAPH.PGCTL.TRSEL= {2}
Only on devices with ADC
Table 6-16. TA3 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
COUT (internal)
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
From Capacitive Touch
I/O 1 (internal)
INCLK
TA2 CCR0 output
(internal)
CCI0A
ACLK (internal)
CCI0B
DVSS
GND
DVCC
VCC
From Capacitive Touch
I/O 1 (internal)
CCI1A
COUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
(1)
Only on devices with ADC
86
Detailed Description
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
DEVICE OUTPUT
SIGNAL
TA2 CCI0A input
CCR0
TA0
ADC12(internal) (1)
ADC12SHSx = {6}
CCR1
TA1
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6.13.13 TB0
TB0 is a 16-bit timer and counter (Timer_B type) with seven capture/compare registers. TB0 can support
multiple captures or compares, PWM outputs, and interval timing (see Table 6-17). TB0 has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 6-17. TB0 Signal Connections
P2.4, P4.6
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
TB0CLK
TBCLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
P2.4, P4.6
TB0CLK
INCLK
P7.2
TB0.0
CCI0A
P3.0
TB0.0
CCI0B
DVSS
P7.3
P8.0
DVCC
VCC
TB0.1
CCI1A
COUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
TB0.2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
P8.1
TB0.3
CCI3A
P3.3
TB0.3
CCI3B
DVSS
GND
DVCC
VCC
P1.4
TB0.4
CCI4A
P3.5
TB0.4
CCI4B
DVSS
GND
P1.5
P3.6
PJ.3
P3.7
(1)
GND
DVCC
VCC
TB0.5
CCI5A
TB0.5
CCI5B
DVSS
GND
DVCC
VCC
TB0.6
CCI6A
TB0.6
CCI6B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PORT PIN
P7.2
P3.0
CCR0
TB0
TB0.0
ADC12 (internal) (1)
ADC12SHSx = {2}
P7.3
P3.1
CCR1
TB1
TB0.1
ADC12 (internal) (1)
ADC12SHSx = {3}
P8.0
CCR2
TB2
TB0.2
P3.2
P8.1
CCR3
TB3
TB0.3
P3.3
P1.4
CCR4
TB4
TB0.4
P3.5
P1.5
CCR5
TB5
TB0.5
P3.6
PJ.3
CCR6
TB6
TB0.6
P3.7
Only on devices with ADC.
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6.13.14 ADC12_B
The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended
inputs. The module implements a 12-bit SAR core, sample select control, a reference generator, and a
conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result
monitoring with three window comparator interrupt flags.
Table 6-18 lists the external trigger sources.
Table 6-19 lists the available multiplexing between internal and external analog inputs.
Table 6-18. ADC12_B Trigger Signal Connections
ADC12SHSx
ADVANCE INFORMATION
BINARY
DECIMAL
CONNECTED TRIGGER
SOURCE
000
0
Software (ADC12SC)
001
1
TA0 CCR1 output
010
2
TB0 CCR0 output
011
3
TB0 CCR1 output
100
4
TA1 CCR1 output
101
5
TA2 CCR1 output
110
6
TA3 CCR1 output
111
7
TA4 CCR1 output
Table 6-19. ADC12_B External and Internal Signal Mapping
CONTROL BIT IN ADC12CTL3
REGISTER
EXTERNAL ADC INPUT
(CONTROL BIT = 0)
ADC12BATMAP
A31
Battery monitor
ADC12TCMAP
A30
Temperature sensor
ADC12CH0MAP
A29
N/A (1)
ADC12CH1MAP
A28
N/A (1)
ADC12CH2MAP
A27
N/A (1)
ADC12CH3MAP
A26
N/A (1)
(1)
88
INTERNAL ADC INPUT
(CONTROL BIT = 1)
N/A = No internal signal is available on this device.
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6.13.15 USS
Table 6-20 lists the available UUPS triggers.
Table 6-20. UUPS Trigger Signal Connections
UUPS.CTL.USSPWR
UPSEL
CONNECTED TRIGGER SOURCE
BINARY
00
Software (UUPS.CTL.USSPWRUP)
01
RTC (any enabled interrupt events)
10
TA0 CCR2 output
11
P1.7
Table 6-21 lists the available PPG triggers.
SAPH.PGCTL.TRSEL
BINARY
ADVANCE INFORMATION
Table 6-21. PPG Trigger Signal Connections
CONNECTED TRIGGER SOURCE
00
Software (SAPH.PPGTRIG.PPGTRIG)
01
ASQ (Acquisition Sequencer)
10
TA2 CCR1 output
11
Reserved
Table 6-22 lists the available ASQ triggers.
Table 6-22. ASQ Trigger Signal Connections
SAPH.ASCTL0.TRIG
SEL
CONNECTED TRIGGER SOURCE
BINARY
00
Software (SAPH.ASQTRIG.ASQTRIG)
01
PSQ (Power Sequencer)
10
TA1 CCR2 output
11
Reserved
6.13.16 Comparator_E
The primary function of the Comparator_E module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
6.13.17 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.13.18 CRC32
The CRC32 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC32 signature is based on the ISO 3309 standard.
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6.13.19 AES256 Accelerator
The AES accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.
6.13.20 True Random Seed
The device descriptor information (TLV) section contains a 128-bit true random seed that can be used to
implement a deterministic random number generator.
6.13.21 Shared Reference (REF)
The REF module generates critical reference voltages that can be used by the various analog peripherals
in the device.
6.13.22 LCD_C
ADVANCE INFORMATION
The LCD_C driver generates the segment and common signals required to drive a liquid crystal display
(LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Common
and segment signals are generated as defined by the mode. Static and 2-mux to 8-mux LCDs are
supported. The module can provide an LCD voltage independent of the supply voltage with its integrated
charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The
module also provides an automatic blinking capability for individual segments in static, 2-, 3-, and 4-mux
modes.
To reduce system noise, the charge pump can be temporarily disabled. Table 6-23 lists the available
automatic charge pump disable options.
Table 6-23. LCD Automatic Charge Pump Disable Bits (LCDCPDISx)
CONTROL BIT
LCDCPDIS0
LCDCPDIS1 to LCDCPDIS7
DESCRIPTION
LCD charge pump disable during ADC12 conversion
0b = LCD charge pump not automatically disabled during conversion.
1b = LCD charge pump automatically disabled during conversion.
No functionality.
6.13.23 Embedded Emulation
6.13.23.1 Embedded Emulation Module (EEM) (S Version)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
6.13.23.2 EnergyTrace++ Technology
The devices implement circuitry to support EnergyTrace++ technology. The EnergyTrace++ technology
allows you to observe information about the internal states of the microcontroller. These states include the
CPU Program Counter (PC), the on or off status of the peripherals and system clocks (regardless of the
clock source), and the low-power mode currently in use. These states can always be read by a debug
tool, even when the microcontroller sleeps in LPMx.5 modes.
The activity of the following modules can be observed:
• LEA is running
• MPY is calculating.
90
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WDT is counting.
RTC is counting.
ADC: a sequence, sample, or conversion is active.
REF: REFBG or REFGEN active and BG in static mode.
COMP is on.
AES is encrypting or decrypting.
eUSCI_A0 is transferring (receiving or transmitting) data.
eUSCI_A1 is transferring (receiving or transmitting) data.
eUSCI_A2 is transferring (receiving or transmitting) data.
eUSCI_A3 is transferring (receiving or transmitting) data.
eUSCI_B0 is transferring (receiving or transmitting) data.
eUSCI_B1 is transferring (receiving or transmitting) data.
TB0 is counting.
TA0 is counting.
TA1 is counting.
TA2 is counting.
TA3 is counting.
TA4 is counting.
LCD_C is running.
USS status
ADVANCE INFORMATION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SLASEB7 – JUNE 2017
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6.14 Input/Output Diagrams
6.14.1 Capacitive Touch Functionality on Ports P1, P2, P3, P4, P5, P6, P7, P8, P9 and PJ
All port pins provide the Capacitive Touch functionality as shown in Figure 6-3. The Capacitive Touch
functionality is controlled using the Capacitive Touch I/O control registers CAPTIO0CTL and CAPTIO1CTL
as described in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's
Guide. The Capacitive Touch functionality is not shown in the individual pin diagrams in the following
sections.
Analog Enable
PxREN.y
Capacitive Touch Enable 0
Capacitive Touch Enable 1
DVSS
0
DVCC
1
1
Direction Control
ADVANCE INFORMATION
PxOUT.y
0
1
Output Signal
Px.y
Input Signal
Q
D
EN
Capacitive Touch Signal 0
Capacitive Touch Signal 1
NOTE: Functional representation only.
Figure 6-3. Capacitive Touch Functionality
92
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6.14.2 Port Function Select Registers (PySEL1 , PySEL0)
Port pins are multiplexed with peripheral module functions as described in the MSP430FR58xx,
MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide. The functions of each port pin
are controlled by its port function select registers, PySEL1 and PySEL0, where y = port number. The bits
in the registers are mapped to the pins in the port. The primary module function, secondary module
function, and tertiary module function of the pins are determined by the configuration of the PySEL1.x bit
and the PySEL0.x bit as shown in Table 6-24. For example, P1SEL1.0 and P1SEL0.0 determine the
primary module function, secondary module function, and tertiary module function of the P1.0 pin, which is
in port 1. The module functions may also require the PxDIR bits to be configured according to the direction
needed for the module function.
PySEL1.x
PySEL1.x
General purpose I/O is selected
I/O FUNCTIONS
0
0
Primary module function is selected
0
1
Secondary module function is selected
1
0
Tertiary module function is selected
1
1
See the port pin function tables in the following section for the configurations of the function and direction
for each pin.
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Table 6-24. I/O Function Selection
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6.14.3 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
Figure 6-4 shows the port diagram. Table 6-25 summarizes the selection of the pin function.
Pad Logic
(ADC) Reference
To ADC
From ADC
To Comparator
From Comparator
CBPD.x
PxREN.x
ADVANCE INFORMATION
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
EN
To modules
Bus
Keeper
D
NOTE: Functional representation only.
Figure 6-4. Port P1 (P1.0 to P1.1) Diagram
94
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Table 6-25. Port P1 (P1.0 to P1.1) Pin Functions
P1.0/UCA1CLK/TA1.0/A0/C0/VREF/VeREF-
P1.1/UCA1STE/TA4.0/A1/C1/VREF+/VeR
EF+
(1)
(2)
(3)
(4)
x
0
1
FUNCTION
CONTROL BITS AND SIGNALS (1)
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.0 (I/O)
I: 0; O: 1
0
0
UCA1CLK
X (2)
0
1
TA1.CCI0A
0
TA1.0
1
1
0
A0, C0, VREF-, VeREF- (3) (4)
X
1
1
P1.1 (I/O)
I: 0; O: 1
0
0
UCA1STE
X (2)
0
1
TA4.CCI0A
0
TA4.0
1
1
0
A1, C1, VREF+, VeREF+ (3) (4)
X
1
1
X = Don't care
Direction controlled by eUSCI_A1 module.
Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
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PIN NAME (P1.x)
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6.14.4 Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
Figure 6-5 shows the port diagram. Table 6-26 summarizes the selection of the pin function.
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CBPD.x
PxREN.x
ADVANCE INFORMATION
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
EN
To modules
Bus
Keeper
D
NOTE: Functional representation only.
Figure 6-5. Port P1 (P1.2 to P1.7) Diagram
96
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Table 6-26. Port P1 (P1.2 to P1.7) Pin Functions
P1.2/UCA1SIMO/UCA1TXD/A8/C8
x
2
FUNCTION
P1.2 (I/O)
UCA1SIMO/UCA1TXD
P1.3/UCA1SOMI/UCA1RXD/A9/C9
3
P1.5/TB0.5/UCB0CLK/A3/C3
5
7
(5)
1
0
1
1
I: 0; O: 1
0
0
X (2)
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
P1.3 (I/O)
N/A
0
Internally tied to DVSS
1
P1.4 (I/O)
TB0.CCI4A
0
TB0.4
1
UCB0STE
X (5)
1
0
A2, C2 (3) (4)
X
1
1
I: 0; O: 1
0
0
0
1
X (5)
1
0
X
1
1
I: 0; O: 1
0
0
0
1
P1.5(I/O)
TB0.CCI5A
0
TB0.5
1
(3) (4)
P1.6(I/O)
N/A
0
Internally tied to DVSS
1
UCB0SIMO/UCB0SDA
X (5)
1
0
X
1
1
0
0
P1.7(I/O)
I: 0; O: 1
0
X
1
1
X
Internally tied to DVSS
1
0
1
UCB0SOMI/UCB0SCL
X (5)
1
0
X
1
1
A5, C5 (3) (4)
(4)
1
X
USSTRG (independent function)
(1)
(2)
(3)
0
A8, C8 (3) (4)
A4, C4 (3) (4)
P1.7/USSTRG/UCB0SOMI/UCB0SCL/A
5/C5
0
X (2)
1
A3, C3
6
P1SEL0.x
0
0
UCB0CLK
P1.6/UCB0SIMO/UCB0SDA/A4/C4
P1SEL1.x
Internally tied to DVSS
A9, C9 (3) (4)
4
P1DIR.x
I: 0; O: 1
N/A
UCA1SOMI/UCA1RXD
P1.4/TB0.4/UCB0STE/A2/C2
CONTROL BITS AND SIGNALS (1)
ADVANCE INFORMATION
PIN NAME (P1.x)
X = Don't care
Direction controlled by eUSCI_A1 module.
Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
Direction controlled by eUSCI_B0 module.
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6.14.5 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
Figure 6-6 shows the port diagram. Table 6-27 summarizes the selection of the pin function.
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CBPD.x
PxREN.x
ADVANCE INFORMATION
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
EN
To modules
Bus
Keeper
D
NOTE: Functional representation only.
Figure 6-6. Port P2 (P2.0 to P2.3) Diagram
98
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Table 6-27. Port P2 (P2.0 to P2.3) Pin Functions
P2.0/UCA0SIMO/UCA0TXD/A6/C6
x
0
FUNCTION
P2.0 (I/O)
1
2
1
X (2)
1
0
X
1
1
I: 0; O: 1
0
0
0
1
P2.1 (I/O)
N/A
0
Internally tied to DVSS
1
UCA0SOMI/UCA0RXD
X (2)
1
0
X
1
1
I: 0; O: 1
0
0
0
1
X (2)
1
0
X
1
1
I: 0; O: 1
0
0
0
1
X (2)
1
0
X
1
1
(3) (4)
P2.2 (I/O)
N/A
0
COUT
1
P2.3(I/O)
TA0.CCI0A
0
TA0.0
1
A15, C15
(4)
0
UCA0SIMO/UCA0TXD
UCA0STE
(1)
(2)
(3)
0
1
A14, C14 (3) (4)
3
P2SEL0.x
0
Internally tied to DVSS
UCA0CLK
P2.3/TA0.0/UCA0STE/A15/C15
P2SEL1.x
0
A7, C7
P2.2/COUT/UCA0CLK/A14/C14
P2DIR.x
I: 0; O: 1
N/A
A6, C6 (3) (4)
P2.1/UCA0SOMI/UCA0RXD/A7/C7
CONTROL BITS AND SIGNALS (1)
(3) (4)
X = Don't care
Direction controlled by eUSCI_A0 module.
Setting P2SEL1.x and P2SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
Detailed Description
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6.14.6 Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
Figure 6-7 shows the port diagram. Table 6-28 summarizes the selection of the pin function.
Pad Logic
Sz
LCDSz
PxREN.x
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
ADVANCE INFORMATION
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
Bus
Keeper
EN
To modules
D
NOTE: Functional representation only.
Figure 6-7. Port P2 (P2.4 to P2.7) Diagram
Table 6-28. Port P2 (P2.4 to P2.7) Pin Functions
PIN NAME (P2.x)
x
P2.4/TA0LCK/TB0CLK/TA1CLK/LCD
S32
4
FUNCTION
100
(1)
P2DIR.x
P2SEL1.x
P2SEL0.x
LCDSz
P2.4 (I/O)
I: 0; O: 1
0
0
0
TA0LCK
0
Internally tied to DVSS
1
0
1
0
TB0LCK
0
Internally tied to DVSS
1
1
0
0
TA1LCK
0
Internally tied to DVSS
1
1
1
0
X
X
1
Sz
(1)
(2)
CONTROL BITS OR SIGNALS
(2)
X
X = Don't care
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.1.
Detailed Description
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Table 6-28. Port P2 (P2.4 to P2.7) Pin Functions (continued)
P2.5/TA4.0/LCDS31
x
5
FUNCTION
P2.5 (I/O)
6
7
P2SEL1.x
P2SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
0
Internally tied to DVSS
1
TA4.CCI0B
0
TA4.0
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P2.6 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
TA4.CCI1B
0
TA4.1
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P2.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
Sz
P2.7/TA0.0/LCDS21
(1)
P2DIR.x
N/A
Sz
P2.6/TA4.1/LCDS30
CONTROL BITS OR SIGNALS
N/A
0
Internally tied to DVSS
1
TA0.CCI0B
0
TA0.0
1
N/A
0
Internally tied to DVSS
1
Sz
(2)
X
Detailed Description
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6.14.7 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
Figure 6-8 shows the port diagram. Table 6-29 summarizes the selection of the pin function.
Pad Logic
Sz
LCDSz
PxREN.x
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
ADVANCE INFORMATION
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
Bus
Keeper
EN
To modules
D
NOTE: Functional representation only.
Figure 6-8. Port P3 (P3.0 to P3.7) Diagram
Table 6-29. Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)
P3.0/TB0.0/LCDS29
x
0
FUNCTION
P3.0 (I/O)
102
(1)
P3DIR.x
P3SEL1.x
P3SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
TB0.CCI0B
0
TB0.0
1
N/A
0
Internally tied to DVSS
1
Sz
(1)
(2)
CONTROL BITS OR SIGNALS
(2)
X
X = Don't care
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.1.
Detailed Description
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Table 6-29. Port P3 (P3.0 to P3.7) Pin Functions (continued)
P3.1/TB0.1/LCDS28
x
1
FUNCTION
P3.1 (I/O)
2
3
4
5
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
1
N/A
0
TB0.1
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P3.2 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
N/A
0
TB0.2
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P3.3 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
TB0.CCI3B
0
TB0.3
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P3.4 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
TB0OUTH
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P3.5 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
Sz
P3.5/TB0.4/LCDS24
P3SEL0.x
Internally tied to DVSS
Sz
P3.4/TB0OUTH/LCDS25
P3SEL1.x
0
Sz
P3.3/TB0.3/LCDS26
(1)
P3DIR.x
N/A
Sz
P3.2/TB0.2/LCDS27
CONTROL BITS OR SIGNALS
N/A
0
Internally tied to DVSS
1
TB0.CCI4B
0
TB0.4
1
N/A
0
Internally tied to DVSS
1
Sz
(2)
X
Detailed Description
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PIN NAME (P3.x)
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Table 6-29. Port P3 (P3.0 to P3.7) Pin Functions (continued)
PIN NAME (P3.x)
P3.6/TB0.5/LCDS23
x
6
FUNCTION
P3.6 (I/O)
7
P3SEL1.x
P3SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
0
Internally tied to DVSS
1
TB0.CCI5B
0
TB0.5
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P3.7 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
ADVANCE INFORMATION
N/A
0
Internally tied to DVSS
1
TB0.CCI6B
0
TB0.6
1
N/A
0
Internally tied to DVSS
1
Sz
104
(1)
P3DIR.x
N/A
Sz
P3.7/TB0.6/LCDS22
CONTROL BITS OR SIGNALS
(2)
X
Detailed Description
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6.14.8 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
Figure 6-9 shows the port diagram. Table 6-30 summarizes the selection of the pin function.
Pad Logic
Sz
LCDSz
PxREN.x
00
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
ADVANCE INFORMATION
PxDIR.x
module 1 or PxDIR.x
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
Bus
Keeper
EN
To modules
D
NOTE: Functional representation only.
Figure 6-9. Port P4 (P4.0 to P4.7) Diagram
Table 6-30. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)
P4.0/RTCCLK/LCDS16
x
0
FUNCTION
P4.0 (I/O)
(1)
P4DIR.x
P4SEL1.x
P4SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
N/A
0
RTCCLK
1
N/A
0
Internally tied to DVSS
1
Sz
(1)
(2)
CONTROL BITS OR SIGNALS
(2)
X
X = Don't care
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.1.
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Table 6-30. Port P4 (P4.0 to P4.7) Pin Functions (continued)
PIN NAME (P4.x)
P4.1/UCA0CLK/LCDS15
x
1
FUNCTION
2
P4SEL1.x
P4SEL0.x
LCDSz
P4.1 (I/O)
I: 0; O: 1
0
0
0
UCA0CLK
X (3)
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P4.2 (I/O)
I: 0; O: 1
0
0
0
UCA0STE
X (3)
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
ADVANCE INFORMATION
(2)
X
X
X
1
P4.3 (I/O)
I: 0; O: 1
0
0
0
X (3)
0
1
0
1
0
0
1
1
0
Sz
P4.3/UCA0SIMO/UCA0TXD/LCDS13
3
UCA0SIMO/UCA0TXD
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P4.4 (I/O)
I: 0; O: 1
0
0
0
X (3)
0
1
0
1
0
0
1
1
0
Sz
P4.4/UCA0SOMI/UCA0RXD/LCDS12
4
UCA0SOMI/UCA0RXD
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P4.5 (I/O)
I: 0; O: 1
0
0
0
TA0CLK
0
Internally tied to DVSS
1
0
1
0
TA1CLK
0
Internally tied to DVSS
1
1
0
0
N/A
0
Internally tied to DVSS
1
1
1
0
Sz
P4.5/TA0LCK/TA1CLK/LCDS11
5
(2)
X
X
X
1
P4.6 (I/O)
I: 0; O: 1
0
0
0
TB0CLK
0
Internally tied to DVSS
1
0
1
0
TA4CLK
0
Internally tied to DVSS
1
1
0
0
N/A
0
Internally tied to DVSS
1
1
1
0
X
X
1
Sz
P4.6/TB0CLK/TA4CLK/LCDS10
6
Sz
(3)
106
(1)
P4DIR.x
Sz
P4.2/UCA0STE/LCDS14
CONTROL BITS OR SIGNALS
(2)
X
Direction controlled by eUSCI_A0 module.
Detailed Description
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Table 6-30. Port P4 (P4.0 to P4.7) Pin Functions (continued)
PIN NAME (P4.x)
P4.7/DMAE0/LCDS9
x
7
FUNCTION
P4.7 (I/O)
CONTROL BITS OR SIGNALS
P4DIR.x
P4SEL1.x
P4SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
DMAE0
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
X
ADVANCE INFORMATION
Sz
(1)
Detailed Description
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6.14.9 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
Figure 6-10 shows the port diagram. Table 6-31 summarizes the selection of the pin function.
Pad Logic
Sz
LCDSz
PxREN.x
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
ADVANCE INFORMATION
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
Bus
Keeper
EN
To modules
D
NOTE: Functional representation only.
Figure 6-10. Port P5 (P5.0 to P5.7) Diagram
Table 6-31. Port P5 (P5.0 to P5.7) Pin Functions
PIN NAME (P5.x)
P5.0/UCA2SIMO/UCA2TXD/LCDS8
x
0
FUNCTION
P5.0 (I/O)
108
(1)
P5DIR.x
P5SEL1.x
P5SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
UCA2SIMO/UCA2TXD
X (2)
N/A
0
Internally tied to DVSS
1
Sz
(1)
(2)
(3)
CONTROL BITS OR SIGNALS
(3)
X
X = Don't care
Direction controlled by eUSCI_A3 module.
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.1.
Detailed Description
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Table 6-31. Port P5 (P5.0 to P5.7) Pin Functions (continued)
P5.1/UCA2SOMI/UCA2RXD/LCDS7
x
1
FUNCTION
P5.1 (I/O)
2
P5SEL1.x
P5SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
0
Internally tied to DVSS
1
UCA2SOMI/UCA2RXD
X (2)
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P5.2 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
X (2)
UCA2CLK
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P5.3 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
Sz
P5.3/UCA2STE/LCDS5
3
N/A
0
Internally tied to DVSS
1
X (2)
UCA2STE
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P5.4 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
Sz
P5.4/UCB1CLK/LCDS4
4
N/A
0
Internally tied to DVSS
1
X (4)
UCB1CLK
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P5.5 (I/O)
I: 0; O: 1
0
0
0
TA0CLK
0
Internally tied to DVSS
1
0
1
0
UCB1SIMO/UCB1SDA
X (4)
1
0
0
1
1
0
Sz
P5.5/TA0CLK/UCB1SIMO/UCB1SDA
/LCDS3
5
N/A
0
Internally tied to DVSS
1
(3)
X
X
X
1
P5.6 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
Sz
P5.6/UCB1SOMI/UCB1SCL/LCDS2
6
N/A
0
Internally tied to DVSS
1
UCB1SOMI/UCB1SCL
X (4)
N/A
0
Internally tied to DVSS
1
Sz
(4)
(1)
P5DIR.x
N/A
Sz
P5.2/UCA2CLK/LCDS6
CONTROL BITS OR SIGNALS
(3)
X
ADVANCE INFORMATION
PIN NAME (P5.x)
Direction controlled by eUSCI_B1 module.
Detailed Description
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Table 6-31. Port P5 (P5.0 to P5.7) Pin Functions (continued)
PIN NAME (P5.x)
P5.7/UCB1STE/LCDS1
x
7
FUNCTION
P5.7 (I/O)
CONTROL BITS OR SIGNALS
P5DIR.x
P5SEL1.x
P5SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
UCB1STE
X (4)
N/A
0
Internally tied to DVSS
1
Sz
(1)
(3)
X
ADVANCE INFORMATION
110
Detailed Description
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6.14.10 Port P6 (P6.0) Input/Output With Schmitt Trigger
Figure 6-11 shows the port diagram. Table 6-32 summarizes the selection of the pin function.
Pad Logic
Sz
LCDSz
PxREN.x
00
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
ADVANCE INFORMATION
PxDIR.x
module 1 or PxDIR.x
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
Bus
Keeper
EN
To modules
D
NOTE: Functional representation only.
Figure 6-11. Port P6 (P6.0) Diagram
Table 6-32. Port P6 (P6.0) Pin Functions
PIN NAME (P6.x)
P6.0/COUT/LCDS0
x
0
FUNCTION
P6.0 (I/O)
(1)
P6DIR.x
P6SEL1.x
P6SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
N/A
0
Internally tied to DVSS
1
N/A
0
COUT
1
N/A
0
Internally tied to DVSS
1
Sz
(1)
(2)
CONTROL BITS OR SIGNALS
(2)
X
X = Don't care
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.1.
Detailed Description
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6.14.11 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
Figure 6-12 shows the port diagram. Table 6-33 summarizes the selection of the pin function.
Pad Logic
To/From LCD
PxREN.x
PxDIR.x
00
ADVANCE INFORMATION
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
Bus
Keeper
EN
To modules
D
NOTE: Functional representation only.
Figure 6-12. Port P6 (P6.1 to P6.5) Diagram
112
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Table 6-33. Port P6 (P6.1 to P6.5) Pin Functions
P6.1/R03
x
1
FUNCTION
P6.1 (I/O)
P6.2/R13/LCDREF
2
3
4
5
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
N/A
0
Internally tied to DVSS
1
(2)
P6.2 (I/O)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
P6.3 (I/O)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
P6.4 (I/O)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
(2)
P6.5 (I/O)
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
COM1
(1)
(2)
0
1
COM0
P6.5/COM1
P6SEL0.x
0
Internally tied to DVSS
R23
P6.4/COM0
P6SEL1.x
0
R13/LCDREF
P6.3/R23
P6DIR.x
I: 0; O: 1
N/A
R03
(2)
(1)
CONTROL BITS OR SIGNALS
X
ADVANCE INFORMATION
PIN NAME (P6.x)
X = Don't care
Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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6.14.12 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
Figure 6-13 shows the port diagram. Table 6-34 summarizes the selection of the pin function.
Pad Logic
Sz
LCDSz
COMx
PxREN.x
ADVANCE INFORMATION
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
Bus
Keeper
EN
To modules
D
NOTE: Functional representation only.
Figure 6-13. Port P6 (P6.6 and P6.7) Diagram
114
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Table 6-34. Port P6 (P6.6 to P6.7) Pin Functions
P6.6/COM2/LCDS38
x
6
FUNCTION
P6.6(I/O)
7
(2)
P6SEL0.x
LCDSz
0
0
0
0
1
0
1
0
0
0
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
COM2 (1)
X
(2)
X
P6.7(I/O)
I: 0; O: 1
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
COM3 (1)
X
Sz
(1)
P6SEL1.x
I: 0; O: 1
N/A
Sz
P6.7/COM3/LCDS37
CONTROL BITS OR SIGNALS
P6DIR.x
(2)
X
1
1
X
0
0
X
0
0
0
0
1
0
1
0
0
0
1
1
X
0
0
X
1
ADVANCE INFORMATION
PIN NAME (P6.x)
1
Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.1.
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6.14.13 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
Figure 6-14 shows the port diagram. Table 6-35 summarizes the selection of the pin function.
Pad Logic
Sz
LCDSz
COMx
PxREN.x
ADVANCE INFORMATION
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
Bus
Keeper
EN
To modules
D
NOTE: Functional representation only.
Figure 6-14. Port P7 (P7.0 to P7.3) Diagram
116
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Table 6-35. Port P7 (P7.0 to P7.3) Pin Functions
x
P7.0/UCA2SIMO/UCA2TXD/ACLK/C
OM4/LCDS36
0
FUNCTION
P7.0(I/O)
(3)
0
X (1)
0
1
0
1
0
0
1
1
0
0
1
COM4 (2)
X
(3)
X
1
P7.1(I/O)
I: 0; O: 1
UCA2SOMI/UCA2RXD
2
X
0
SMCLK
1
COM5 (2)
X
(3)
X
P7.2(I/O)
I: 0; O: 1
UCA2CLK
3
(1)
N/A
X
(1)
TB0.CCI0A
0
TB0.0
1
COM6 (2)
X
(3)
X
P7.3(I/O)
I: 0; O: 1
UCA2STE
X
(1)
TB0.CCI1A
0
TB0.1
1
COM7 (2)
X
Sz
(1)
(2)
LCDSz
0
ACLK
Sz
P7.3/UCA2STE/TB0.1/COM7/LCDS3
3
P7SEL0.x
0
N/A
Sz
P7.2/UCA2CLK/TB0.0/COM6/LCDS3
4
P7SEL1.x
I: 0; O: 1
UCA2SIMO/UCA2TXD
Sz
P7.1/UCA2SOMI/UCA2RXD/SMCLK/
COM5/LCDS35
CONTROL BITS OR SIGNALS
P7DIR.x
(3)
X
X
0
0
X
0
0
0
0
1
0
1
0
0
1
1
0
1
X
0
0
X
0
0
0
0
1
0
1
0
0
0
1
1
1
X
0
0
X
0
0
0
0
1
0
1
0
0
0
1
1
X
0
0
X
ADVANCE INFORMATION
PIN NAME (P7.x)
1
1
Direction controlled by eUSCI_A2 module.
Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.1.
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6.14.14 Port P7 (P7.4) Input/Output With Schmitt Trigger
Figure 6-15 shows the port diagram. Table 6-36 summarizes the selection of the pin function.
ACTIVATE
Pad Logic
MTIF_PIN_EN
1
1
TPOE
0
From MTIF
0
PxREN.x
1
0
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
00
Direction
0: Input
1: Output
1
DVSS
0
DVCC
1
1
1
0
ADVANCE INFORMATION
module 1 or DVSS
01
1
module 2 or DVSS
10
0
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
EN
To modules
Bus
Keeper
D
To MTIF
TPIE
NOTE: Functional representation only.
Figure 6-15. Port P7 (P7.4) Diagram
118
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Table 6-36. Port P7 (P7.4) Pin Functions
CONTROL BITS OR SIGNALS
P7.4/TA0.1/MTIF_
OUT_IN
(1)
(2)
x
4
FUNCTION
P7.4(I/O)
TPIE (1)
ACTIVATE
(1)
Signal on
MTIF_PIN_E
N pin (2)
0
0
X
X
1
0
0
X
X
1
0
0
0
X
X
1
1
0
0
X
X
P7DIR.x
P7SEL
1.x
P7SEL0.x
I: 0; O: 1
0
0
0
TPOE
(1)
TA0.CCI1A
0
TA0.1
1
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
MTIF_IN
X
X
X
0
1
X
X
MTIF_OUT (1)
X
X
X
1
X
0
X
Internally tied to
DVSS (1)
X
X
X
1
X
1
0
MTIF_OUT (1)
X
X
X
1
X
1
1
ADVANCE INFORMATION
PIN NAME (P7.x)
See MTIF.TPCTL register
When P7.5 pin is configured as MTIF_PIN_EN (See Table 6-37 for details)
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6.14.15 Port P7 (P7.5) Input/Output With Schmitt Trigger
Figure 6-16 shows the port diagram. Table 6-37 summarizes the selection of the pin function.
Pad Logic
ACTIVATE
0
PxREN.x
1
0
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
00
ADVANCE INFORMATION
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
Direction
0: Input
1: Output
0
DVSS
0
DVCC
1
1
1
0
PxSEL1.x
PxSEL0.x
PxIN.x
EN
To modules
Bus
Keeper
D
MTIF_PIN_EN
NOTE: Functional representation only.
Figure 6-16. Port P7 (P7.5) Diagram
120
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Table 6-37. Port P7 (P7.5) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P7.x)
x
P7.5/TA1.1/MTIF_PIN_EN
(1)
5
FUNCTION
P7.5(I/O)
P7DIR.x
P7SEL1.
x
P7SEL0.x
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
TA1.CCI1A
0
TA1.1
1
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
MTIF_PIN_EN
X
ACTIVATE
(1)
See MTIF.TPCTL register
6.14.16 Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
ADVANCE INFORMATION
Figure 6-17 shows the port diagram. Table 6-38 summarizes the selection of the pin function.
Pad Logic
PxREN.x
PxDIR.x
module 1 or PxDIR.x
00
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
EN
To modules
D
NOTE: Functional representation only.
Figure 6-17. Port P7 (P7.6 and P7.7) Diagram
Detailed Description
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Table 6-38. Port P7 (P7.6 to P7.7) Pin Functions
PIN NAME (P7.x)
x
P7.6/TA4.1/DMAE0/COUT
6
P7.7/TA0.2/TB0OUTH/COUT
7
CONTROL BITS OR SIGNALS
FUNCTION
P7.6(I/O)
P7DIR.x
P7SEL1.x
P7SEL0.x
I: 0; O: 1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
TA4.CCI1A
0
TA4.1
1
DMAE0
0
Internally tied to DVSS
1
N/A
0
COUT
1
P7.7(I/O)
I: 0; O: 1
ADVANCE INFORMATION
TA0.CCI2A
0
TA0.2
1
TB0OUTH
0
Internally tied to DVSS
1
N/A
0
COUT
1
6.14.17 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
Figure 6-18 shows the port diagram. Table 6-39 summarizes the selection of the pin function.
Pad Logic
PxREN.x
PxDIR.x
module 1 or PxDIR.x
00
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
EN
To modules
D
NOTE: Functional representation only.
Figure 6-18. Port P8 (P8.0 to P8.3) Diagram
122
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Table 6-39. Port P8 (P8.0 to P8.3) Pin Functions
x
P8.0/UCA3STE/TB0.2/DMAE0
0
P8.1/UCA3CLK/TB0.3/TB0OUTH
P8.2/UCA3SOMI/UCA3RXD/MCLK
1
2
FUNCTION
P8SEL1.x
P8SEL0.x
P8.0(I/O)
I: 0; O: 1
0
0
UCA3STE
X (1)
0
1
TB0.CCI2A
0
TB0.2
1
1
0
DMAE0
0
Internally tied to DVSS
1
1
1
P8.1(I/O)
I: 0; O: 1
0
0
UCA3CLK
X (1)
0
1
TB0.CCI3A
0
TB0.3
1
1
0
TB0OUTH
0
Internally tied to DVSS
1
1
1
I: 0; O: 1
0
0
X (1)
0
1
1
0
1
1
I: 0; O: 1
0
0
X (1)
0
1
1
0
1
1
P8.2(I/O)
UCA3SOMI/UCA3RXD
P8.3/UCA3SIMO/UCA3TXD/RTCCLK
3
N/A
0
MCLK
1
N/A
0
Internally tied to DVSS
1
P8.3(I/O)
/UCA3SIMO/UCA3TXD
(1)
CONTROL BITS OR SIGNALS
P8DIR.x
N/A
0
RTCCLK
1
N/A
0
Internally tied to DVSS
1
ADVANCE INFORMATION
PIN NAME (P8.x)
Direction controlled by eUSCI_A3 module.
Detailed Description
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6.14.18 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
Figure 6-19 shows the port diagram. Table 6-40 summarizes the selection of the pin function.
Pad Logic
To ADC
From ADC
PxREN.x
ADVANCE INFORMATION
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
Bus
Keeper
EN
To modules
D
NOTE: Functional representation only.
Figure 6-19. Port P8 (P8.4 to P8.7) Diagram
124
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Table 6-40. Port P8 (P8.4 to P8.7) Pin Functions
P8.4/UCB1CLK/TA1.2/A10
P8.5/UCB1SIMO/UCB1SDA/A11
x
4
5
FUNCTION
P8SEL1.x
P8SEL0.x
P8.4(I/O)
I: 0; O: 1
0
0
UCB1CLK
X (1)
0
1
TA1.CCI2A
0
TA1.2
1
1
0
A10 (2)
X
1
1
I: 0; O: 1
0
0
X (1)
0
1
1
0
P8.5(I/O)
UCB1SIMO/UCB1SDA
N/A
0
Internally tied to DVSS
1
A11 (2)
P8.6/UCB1SOMI/UCB1SCL/A12
6
P8.6(I/O)
UCB1SOMI/UCB1SCL
P8.7/UCB1STE/USSXT_BOUT/A13
(1)
(2)
(3)
7
CONTROL BITS OR SIGNALS
P8DIR.x
X
1
1
I: 0; O: 1
0
0
X (1)
0
1
1
0
N/A
0
Internally tied to DVSS
1
A12 (2)
X
1
1
P8.7(I/O)
I: 0; O: 1
0
0
UCB1STE
X (1)
0
1
1
0
1
1
N/A
0
USSXT_BOUT (3)
1
A13 (2)
X
ADVANCE INFORMATION
PIN NAME (P8.x)
Direction controlled by eUSCI_B1 module.
Setting P8SEL1.x and P8SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
USSXTHSPLL.PLLXTLCTL.XTOUTOFF bit must be set to '0' as well.
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6.14.19 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
Figure 6-20 shows the port diagram. Table 6-41 summarizes the selection of the pin function.
Pad Logic
Sz
LCDSz
PxREN.x
PxDIR.x
00
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
ADVANCE INFORMATION
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
00
module 1 or DVSS
01
module 2 or DVSS
10
module 3 or DVSS
11
PxSEL1.x
PxSEL0.x
PxIN.x
Bus
Keeper
EN
To modules
D
NOTE: Functional representation only.
Figure 6-20. Port P9 (P9.0 to P9.3) Diagram
Table 6-41. Port P9 (P9.0 to P9.3) Pin Functions
PIN NAME (P9.x)
P9.0/TA1.0/LCDS20
x
0
FUNCTION
P9.0 (I/O)
126
(1)
P9DIR.x
P9SEL1.x
P9SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
TA1.CCI0B
0
TA1.0
1
N/A
0
Internally tied to DVSS
1
N/A
0
Internally tied to DVSS
1
Sz
(1)
(2)
CONTROL BITS OR SIGNALS
(2)
X
X = Don't care
Associated LCD segment is package dependent. Refer to the pin diagrams and signal descriptions in Section 4.1.
Detailed Description
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Table 6-41. Port P9 (P9.0 to P9.3) Pin Functions (continued)
P9.1/SMCLK/LCDS19
x
1
FUNCTION
P9.1 (I/O)
2
3
P9SEL1.x
P9SEL0.x
LCDSz
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
0
Internally tied to DVSS
1
N/A
0
SMCLK
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P9.2 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
N/A
0
Internally tied to DVSS
1
N/A
0
MCLK
1
N/A
0
Internally tied to DVSS
1
(2)
X
X
X
1
P9.3 (I/O)
I: 0; O: 1
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
Sz
P9.3/ACLK/LCDS17
(1)
P9DIR.x
N/A
Sz
P9.2/MCLK/LCDS18
CONTROL BITS OR SIGNALS
N/A
0
Internally tied to DVSS
1
N/A
0
ACLK
1
N/A
0
Internally tied to DVSS
1
Sz
(2)
X
Detailed Description
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PIN NAME (P9.x)
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6.14.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With
Schmitt Trigger
Figure 6-21 shows the port diagram. Table 6-42 summarizes the selection of the pin function.
To Comparator
From Comparator
Pad Logic
CBPD.x
JTAG enable
From JTAG
From JTAG
PJREN.x
PJDIR.x
00
ADVANCE INFORMATION
module 1 or PxDIR.x
01
module 2 or PxDIR.x
10
module 3 or PxDIR.x
11
PJOUT.x
1
DVSS
0
DVCC
1
0
Direction
0: Input
1: Output
1
00
module 1 or DVSS
01
1
module 2 or DVSS
10
0
module 3 or DVSS
11
PJSEL1.x
PJSEL0.x
PJIN.x
EN
Bus
Keeper
D
To modules
and JTAG
NOTE: Functional representation only.
Figure 6-21. Port PJ (PJ.0 to PJ.3) Diagram
128
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Table 6-42. Port PJ (PJ.0 to PJ.3) Pin Functions
x
PJ.0/TDO/ACLK/SRSCG1/D
MAE0/C10
0
FUNCTION
PJDIR.x
PJSEL1.x
PJSEL0.x
CEPDx (Cx)
I: 0; O: 1
0
0
0
TDO (3)
X
X
X
0
N/A
0
ACLK
1
0
1
0
N/A
0
CPU Status Register Bit SCG1
1
1
0
0
DMAE0
0
Internally tied to DVSS
1
1
1
0
PJ.0 (I/O) (2)
C10 (4)
PJ.1/TDI/TCLK/SMCLK/SRS
CG0/TA4CLK/C11
PJ.2/TMS/MCLK/SROSCOF
F/TB0OUTH/C12
1
PJ.1 (I/O) (2)
TDI/TCLK (3)
2
(5)
(1)
(2)
(3)
(4)
(5)
X
X
1
0
0
0
X
X
X
0
0
1
0
1
0
0
1
1
0
X
X
1
0
SMCLK
1
N/A
0
CPU Status Register Bit SCG0
1
TA4CLK
0
Internally tied to DVSS
1
C11 (4)
X
PJ.2 (I/O)
TMS (3)
3
X
I: 0; O: 1
N/A
(2)
(5)
I: 0; O: 1
0
0
0
X
X
X
0
0
1
0
1
0
0
1
1
0
N/A
0
MCLK
1
N/A
0
CPU Status Register Bit OSCOFF
1
TB0OUTH
0
Internally tied to DVSS
1
C12 (4)
PJ.3/TCK/RTCCLK/SRCPU
OFF/TB0.6/C13
CONTROL BITS/ SIGNALS (1)
PJ.3 (I/O) (2)
TCK
(3) (5)
X
X
X
1
I: 0; O: 1
0
0
0
X
X
X
0
0
1
0
1
0
0
1
1
0
X
X
1
N/A
0
RTCCLK
1
N/A
0
CPU Status Register Bit CPUOFF
1
TB0.CCI6A
0
TB0.6
1
C13 (4)
X
ADVANCE INFORMATION
PIN NAME (PJ.x)
X = Don't care
Default condition
The pin direction is controlled by the JTAG module. JTAG mode selection is made through the SYS module or by the Spy-Bi-Wire fourwire entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPDx bits have an effect in these cases.
Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables The output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
Detailed Description
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6.14.21 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
Figure 6-22 and Figure 6-23 show the port diagrams. Table 6-43 summarizes the selection of the pin
function.
Pad Logic
To LFXT XIN
PJREN.4
PJDIR.4
00
01
10
Direction
0: Input
1: Output
11
ADVANCE INFORMATION
PJOUT.4
00
DVSS
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
PJ.4/LFXIN
PJSEL1.4
PJSEL0.4
PJIN.4
EN
To modules
Bus
Keeper
D
NOTE: Functional representation only.
Figure 6-22. Port PJ (PJ.4) Diagram
130
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Pad Logic
To LFXT XOUT
PJSEL0.4
PJSEL1.4
LFXTBYPASS
PJREN.5
PJDIR.5
00
01
10
Direction
0: Input
1: Output
11
PJOUT.5
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.5/LFXOUT
PJSEL1.5
EN
To modules
ADVANCE INFORMATION
PJSEL0.5
PJIN.5
Bus
Keeper
D
NOTE: Functional representation only.
Figure 6-23. Port PJ (PJ.5) Diagram
Detailed Description
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Table 6-43. Port PJ (PJ.4 and PJ.5) Pin Functions
CONTROL BITS AND SIGNALS (1)
PIN NAME (PJ.x)
PJ.4/LFXIN
x
4
FUNCTION
PJ.4 (I/O)
PJSEL0.4
LFXT
BYPASS
I: 0; O: 1
X
X
0
0
X
X
X
1
X
X
1
LFXIN crystal mode (2)
X
X
X
0
1
0
X
X
X
0
1
1
0
0
1
X
X
X
(2)
5
I: 0; O: 1
0
ADVANCE INFORMATION
Internally tied to DVSS
LFXOUT crystal mode (2)
132
PJSEL1.4
0
N/A
(3)
(4)
PJSEL0.5
Internally tied to DVSS
PJ.5 (I/O)
(1)
(2)
PJSEL1.5
N/A
LFXIN bypass mode
PJ.5/LFXOUT
PJDIR.x
1
X
0
see (4)
see (4)
0
see (4)
see (4)
X
X
0
0
1
X
X
X
0
1 (3)
0
1 (3)
0
0
1
X
X
X
1 (3)
0
1
0
0
X = Don't care
If PJSEL1.4 = 0 and PJSEL0.4 = 1, the general-purpose I/O is disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are configured for
crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When LFXTBYPASS = 1, PJ.4 is configured for bypass operation and
PJ.5 is configured as general-purpose I/O.
When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
If PJSEL0.5 = 1 or PJSEL1.5 = 1, the general-purpose I/O functionality is disabled. No input function is available. Configured as output,
the pin is actively pulled to zero.
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6.14.22 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
Figure 6-24 and Figure 6-25 show the port diagrams. Table 6-44 summarizes the selection of the pin
function.
Pad Logic
To HFXT XIN
PJREN.6
00
01
10
Direction
0: Input
1: Output
11
PJOUT.6
00
DVSS
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
ADVANCE INFORMATION
PJDIR.6
PJ.6/HFXIN
PJSEL1.6
PJSEL0.6
PJIN.6
EN
To modules
Bus
Keeper
D
NOTE: Functional representation only.
Figure 6-24. Port PJ (PJ.6) Diagram
Detailed Description
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Pad Logic
To HFXT XOUT
PJSEL0.6
PJSEL1.6
HFXTBYPASS
PJREN.7
PJDIR.7
00
01
10
Direction
0: Input
1: Output
11
PJOUT.7
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.7/HFXOUT
PJSEL1.7
ADVANCE INFORMATION
PJSEL0.7
PJIN.7
EN
To modules
Bus
Keeper
D
NOTE: Functional representation only.
Figure 6-25. Port PJ (PJ.7) Diagram
134
Detailed Description
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Table 6-44. Port PJ (PJ.6 and PJ.7) Pin Functions
PJ.6/HFXIN
PJ.7/HFXOUT
x
6
CONTROL BITS AND SIGNALS (1)
FUNCTION
PJ.6 (I/O)
PJSEL1.6
PJSEL0.6
HFXTBYPASS
X
0
0
X
X
X
1
X
X
Internally tied to DVSS
1
HFXIN crystal mode (2)
X
X
X
0
1
0
HFXIN bypass mode (2)
X
X
X
0
1
1
I: 0; O: 1
0
0
7
0
Internally tied to DVSS
1
HFXOUT crystal mode (2)
(4)
PJSEL0.7
X
0
N/A
(3)
PJSEL1.7
N/A
PJ.7 (I/O) (3)
(1)
(2)
PJDIR.x
I: 0; O: 1
X
see
see
X
(3)
(3)
see
see
X
(3)
(3)
0
0
1
X
X
X
0
1 (4)
0
0
1
X
X
X
0
0
1
X
X
X
1 (4)
0
1
0
0
1 (4)
0
X = Don't care
Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are
configured for crystal operation and PJSEL1.6 and PJSEL0.7 are do not care. When HFXTBYPASS = 1, PJ.6 is configured for bypass
operation and PJ.7 is configured as general-purpose I/O.
With PJSEL0.7 = 1 or PJSEL1.7 =1 the general-purpose I/O functionality is disabled. No input function is available. Configured as output
the pin is actively pulled to zero.
When PJ.6 is configured in bypass mode, PJ.7 is configured as general-purpose I/O.
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PIN NAME (PJ.x)
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6.15 Device Descriptors (TLV)
Table 6-45 lists the Device IDs of the MSP430FR60xx(1) devices.
Table 6-45. Device IDs for MSP430FR60xx(1) Devices
DEVICE
PACKAGE
MSP430FR6047
DEVICE ID
01A05h
01A04h
PZ
82h
EAh
MSP430FR60471
PZ
82h
EEh
MSP430FR6045
PZ
82h
EBh
MSP430FR6037
PZ
82h
ECh
MSP430FR60371
PZ
82h
EFh
MSP430FR6035
PZ
82h
EDh
Table 6-46 lists the contents of the device descriptor tag-length-value (TLV) structure for
MSP430FR60xx(1) devices.
ADVANCE INFORMATION
Table 6-46. Device Descriptor Table MSP430FR60xx(1) (1)
DESCRIPTION
ADDRESS
VALUE
ADDRESS
VALUE
01A00h
06h
01A00h
06h
CRC length
01A01h
06h
01A01h
06h
01A02h
Per unit
01A02h
Per unit
01A03h
Per unit
01A03h
Per unit
see Table 6-45
01A04h
see Table 6-45
CRC value
Device ID
01A04h
01A05h
Hardware revision
01A06h
Per unit
01A06h
Per unit
Firmware revision
01A07h
Per unit
01A07h
Per unit
Die record tag
01A08h
08h
01A08h
08h
Die record length
Lot/wafer ID
Die Record
Die X position
Die Y position
Test results
136
MSP430FR60xx1 (I2C BSL)
Info length
Info Block
(1)
MSP430FR60xx (UART BSL)
01A09h
0Ah
01A09h
0Ah
01A0Ah
Per unit
01A0Ah
Per unit
01A0Bh
Per unit
01A0Bh
Per unit
01A0Ch
Per unit
01A0Ch
Per unit
01A0Dh
Per unit
01A0Dh
Per unit
01A0Eh
Per unit
01A0Eh
Per unit
01A0Fh
Per unit
01A0Fh
Per unit
01A10h
Per unit
01A10h
Per unit
01A11h
Per unit
01A11h
Per unit
01A12h
Per unit
01A12h
Per unit
01A13h
Per unit
01A13h
Per unit
NA = Not applicable, Per unit = content can differ from device to device
Detailed Description
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Table 6-46. Device Descriptor Table MSP430FR60xx(1)(1) (continued)
ADDRESS
VALUE
ADDRESS
VALUE
ADC12 calibration tag
01A14h
11h
01A14h
11h
ADC12 calibration length
01A15h
10h
01A15h
10h
01A16h
Per unit
01A16h
Per unit
01A17h
Per unit
01A17h
Per unit
01A18h
Per unit
01A18h
Per unit
01A19h
Per unit
01A19h
Per unit
ADC 1.2-V reference
temperature sensor 30°C
01A1Ah
Per unit
01A1Ah
Per unit
01A1Bh
Per unit
01A1Bh
Per unit
ADC 1.2-V reference
temperature sensor 85°C
01A1Ch
Per unit
01A1Ch
Per unit
01A1Dh
Per unit
01A1Dh
Per unit
ADC 2.0-V reference
temperature sensor 30°C
01A1Eh
Per unit
01A1Eh
Per unit
01A1Fh
Per unit
01A1Fh
Per unit
ADC 2.0-V reference
temperature sensor 85°C
01A20h
Per unit
01A20h
Per unit
01A21h
Per unit
01A21h
Per unit
ADC 2.5-V reference
temperature sensor 30°C
01A22h
Per unit
01A22h
Per unit
01A23h
Per unit
01A23h
Per unit
ADC 2.5-V reference
temperature sensor 85°C
01A24h
Per unit
01A24h
Per unit
01A25h
Per unit
01A25h
Per unit
REF calibration tag
01A26h
12h
01A26h
12h
REF calibration length
01A27h
06h
01A27h
06h
01A28h
Per unit
01A28h
Per unit
01A29h
Per unit
01A29h
Per unit
01A2Ah
Per unit
01A2Ah
Per unit
ADC gain factor (2)
ADC offset (3)
ADC12 Calibration
REF 1.2-V reference
REF Calibration
REF 2.0-V reference
REF 2.5-V reference
(2)
(3)
MSP430FR60xx1 (I2C BSL)
01A2Bh
Per unit
01A2Bh
Per unit
01A2Ch
Per unit
01A2Ch
Per unit
01A2Dh
Per unit
01A2Dh
Per unit
ADVANCE INFORMATION
MSP430FR60xx (UART BSL)
DESCRIPTION
ADC gain: The gain correction factor is measured at room temperature using a 2.5-V external voltage reference without internal buffer
(ADC12VRSEL = 0x2, 0x4, or 0xE). Other settings (for example, using internal reference) can result in different correction factors.
ADC offset: the offset correction factor is measured at room temperature using ADC12VRSEL= 0x2 or 0x4, an external reference, VR+ =
external 2.5 V, VR– = AVSS.
Detailed Description
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Table 6-46. Device Descriptor Table MSP430FR60xx(1)(1) (continued)
MSP430FR60xx (UART BSL)
DESCRIPTION
ADDRESS
VALUE
ADDRESS
VALUE
128-bit random number tag
01A2Eh
15h
01A2Eh
15h
Random Number Length
01A2Fh
10h
01A2Fh
10h
01A30h
Per unit
01A30h
Per unit
01A31h
Per unit
01A31h
Per unit
01A32h
Per unit
01A32h
Per unit
01A33h
Per unit
01A33h
Per unit
01A34h
Per unit
01A34h
Per unit
01A35h
Per unit
01A35h
Per unit
01A36h
Per unit
01A36h
Per unit
01A37h
Per unit
01A37h
Per unit
01A38h
Per unit
01A38h
Per unit
01A39h
Per unit
01A39h
Per unit
01A3Ah
Per unit
01A3Ah
Per unit
Random Number
128-bit random number (4)
ADVANCE INFORMATION
01A3Bh
Per unit
01A3Bh
Per unit
01A3Ch
Per unit
01A3Ch
Per unit
01A3Dh
Per unit
01A3Dh
Per unit
01A3Eh
Per unit
01A3Eh
Per unit
01A3Fh
Per unit
01A3Fh
Per unit
BSL tag
01A40h
1Ch
01A40h
1Ch
BSL length
01A41h
02h
01A41h
02h
BSL interface
01A42h
00h
01A42h
01h
BSL interface configuration
01A43h
00h
01A43h
48h
BSL Configuration
(4)
138
MSP430FR60xx1 (I2C BSL)
128-bit random number: The random number is generated during production test using Microsoft's CryptGenRandom() function.
Detailed Description
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6.16 Memory Map
Table 6-47 summarizes the memory organization for all device variants.
MSP430FR6047(1), FR6037(1)
MSP430FR6045, FR6035
256KB
00FFFFh to 00FF80h
043FFFh to 004000h
128KB
00FFFFh to 00FF80h
0023FFFh to 004000h
RAM (shared with LEA)
4KB
003BFFh to 002C00h
4KB
003BFFh to 002C00h
RAM
4KB
002BFFh to 001C00h
4KB
002BFFh to 001C00h
Device descriptor info (TLV)
(FRAM)
256 B
001AFFh to 001A00h
256 B
001AFFh to 001A00h
TI calibration and configuration
(FRAM)
256 B
0019FFh to 001900h
256 B
0019FFh to 001900h
BSL 3
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 2
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
BSL 1
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
BSL 0
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
Size
4KB
000FFFh to 000020h
4KB
000FFFh to 000020h
Size
22 B
000001Fh to 00000Ah
22 B
000001Fh to 00000Ah
Size
10 B
000009h to 000000h
10 B
000009h to 000000h
Memory (FRAM)
Main: interrupt vectors and
signatures
Main: code memory
Total Size
Bootloader (BSL) memory (ROM)
Peripherals
Tiny RAM
Reserved
(1)
ADVANCE INFORMATION
Table 6-47. Memory Organization (1)
All address space not listed is considered vacant memory.
Detailed Description
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6.16.1 Peripheral File Map
For complete module register descriptions, see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx,
MSP430FR69xx Family User's Guide. Table 6-48 lists the base and end addresses of the registers for
each peripheral.
Table 6-48. Peripherals
ADVANCE INFORMATION
140
MODULE NAME
BASE ADDRESS
END ADDRESS
Special Functions (see Table 6-49)
0100h
011Fh
PMM (see Table 6-50)
0120h
013Fh
FRAM Control (see Table 6-51)
0140h
014Fh
CRC (see Table 6-52)
0150h
0157h
RAM Control (see Table 6-53)
0158h
0159h
Watchdog (see Table 6-54)
015Ch
015Dh
CS (see Table 6-55)
0160h
016Fh
SYS (see Table 6-56)
0180h
019Fh
Shared Reference (see Table 6-57)
01B0h
01B1h
Digital I/O (see Table 6-58)
0200h
033Fh
TA0 (see Table 6-59)
0340h
036Fh
TA1 (see Table 6-60)
0380h
03AFh
TB0 (see Table 6-61)
03C0h
03EFh
TA2 (see Table 6-62)
0400h
042Fh
Capacitive Touch IO 0 (see Table 6-63)
0430h
043Fh
046Fh
TA3 (see Table 6-64)
0440h
Capacitive Touch IO 1 (see Table 6-65)
0470h
047Fh
RTC_C (see Table 6-66)
04A0h
04BFh
32-Bit Hardware Multiplier (see Table 6-67)
04C0h
04EFh
DMA (see Table 6-68)
0500h
056Fh
MPU Control (see Table 6-69)
05A0h
05AFh
eUSCI_A0 (see Table 6-70)
05C0h
05DFh
eUSCI_A1 (see Table 6-71)
05E0h
05FFh
eUSCI_A2 (see Table 6-72)
0600h
061Fh
eUSCI_A3 (see Table 6-73)
0620h
063Fh
eUSCI_B0 (see Table 6-74)
0640h
066Fh
eUSCI_B1 (see Table 6-75)
0680h
06AFh
TA4 (see Table 6-76)
07C0h
07EFh
ADC12_B (see Table 6-77)
0800h
089Fh
Comparator E (see Table 6-78)
08C0h
08CFh
CRC32 (see Table 6-79)
0980h
09AFh
AES256 (see Table 6-80)
09C0h
09CFh
LCD_C (see Table 6-81)
0A00h
0A5Fh
LEA (see Table 6-82)
0A80h
0AFFh
SAPH (see Table 6-83)
0E00h
0E7Fh
SDHS (see Table 6-84)
0E80h
0EBFh
UUPS (see Table 6-85)
0EC0h
0EDFh
HSPLL (see Table 6-86)
0EE0h
0EFFh
MTIF (see Table 6-87)
0F00h
0F1Fh
Detailed Description
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Table 6-49. Special Functions Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Interrupt Enable
SFRIE1
0100h
Interrupt Flag
SFRIFG1
0102h
Reset Pin Control
SFRRPCR
0104h
Table 6-50. PMM Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
PMM control register 0
PMMCTL0
0120h
PMM interrupt flag register
PMMIFG
012Ah
Power mode 5 control register 0
PM5CTL0
0130h
Table 6-51. FRAM Control Registers
ACRONYM
ADDRESS
FRCTL0
0140h
General Control Register 0
GCCTL0
0144h
General Control Register 1
GCCTL1
0146h
ADVANCE INFORMATION
REGISTER DESCRIPTION
FRAM Controller A Control Register 0
Table 6-52. CRC Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
CRC Data In
CRCDI
0150h
CRC Data In Reverse Byte
CRCDIRB
0152h
CRC Initialization and Result
CRCINIRES
0154h
CRC Result Reverse
CRCRESR
0156h
Table 6-53. RAM Control Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
RAM Controller Control 0
RCCTL0
0158h
RAM Controller Control 1
RCCTL1
015Ah
Table 6-54. Watchdog Registers
REGISTER DESCRIPTION
Watchdog Timer Control Register
ACRONYM
WDTCTL
ADDRESS
015Ch
Table 6-55. CS Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Clock System Control 0
CSCTL0
0160h
Clock System Control 1
CSCTL1
0162h
Clock System Control 2
CSCTL2
0164h
Clock System Control 3
CSCTL3
0166h
Clock System Control 4
CSCTL4
0168h
Clock System Control 5
CSCTL5
016Ah
Clock System Control 6
CSCTL6
016Ch
Detailed Description
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Table 6-56. SYS Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
System Control
SYSCTL
0180h
JTAG Mailbox Control
SYSJMBC
0186h
JTAG Mailbox Input
SYSJMBI0
0188h
JTAG Mailbox Input
SYSJMBI1
018Ah
JTAG Mailbox Output
SYSJMBO0
018Ch
JTAG Mailbox Output
SYSJMBO1
018Eh
User NMI Vector Generator
SYSUNIV
019Ah
System NMI Vector Generator
SYSSNIV
019Ch
Reset Vector Generator
SYSRSTIV
019Eh
Table 6-57. Shared Reference Registers
REGISTER DESCRIPTION
REF Control Register 0
ACRONYM
REFCTL0
ADDRESS
01B0h
ADVANCE INFORMATION
Table 6-58. Digital I/O Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Port A Input
PAIN
0200h
Port 1 Input
P1IN
0200h
Port 2 Input
P2IN
0201h
Port A Output
PAOUT
0202h
Port 1 Output
P1OUT
0202h
Port 2 Output
P2OUT
0203h
Port A Direction
PADIR
0204h
Port 1 Direction
P1DIR
0204h
Port 2 Direction
P2DIR
0205h
Port A Resistor Enable
PAREN
0206h
Port 1 Resistor Enable
P1REN
0206h
Port 2 Resistor Enable
P2REN
0207h
Port A Select 0
PASEL0
020Ah
Port 1 Select 0
P1SEL0
020Ah
Port 2 Select 0
P2SEL0
020Bh
Port A Select 1
PASEL1
020Ch
Port 1 Select 1
P1SEL1
020Ch
Port 2 Select 1
P2SEL1
020Dh
Port 1 Interrupt Vector Register
P1IV
020Eh
Port A Complement Select
PASELC
0216h
Port 1 Complement Select
P1SELC
0216h
Port 2 Complement Select
P2SELC
0217h
Port A Interrupt Edge Select
PAIES
0218h
Port 1 Interrupt Edge Select
P1IES
0218h
Port 2 Interrupt Edge Select
P2IES
0219h
Port A Interrupt Enable
PAIE
021Ah
Port 1 Interrupt Enable
P1IE
021Ah
Port 2 Interrupt Enable
P2IE
021Bh
Port A Interrupt Flag
PAIFG
021Ch
Port 1 Interrupt Flag
P1IFG
021Ch
Port 2 Interrupt Flag
P2IFG
021Dh
142
Detailed Description
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Table 6-58. Digital I/O Registers (continued)
ACRONYM
ADDRESS
P2IV
021Eh
Port B Input
PBIN
0220h
Port 3 Input
P3IN
0220h
Port 4 Input
P4IN
0221h
Port B Output
PBOUT
0222h
Port 3 Output
P3OUT
0222h
Port 4 Output
P4OUT
0223h
Port B Direction
PBDIR
0224h
Port 3 Direction
P3DIR
0224h
Port 4 Direction
P4DIR
0225h
Port B Resistor Enable
PBREN
0226h
Port 3 Resistor Enable
P3REN
0226h
Port 4 Resistor Enable
P4REN
0227h
Port B Select 0
PBSEL0
022Ah
Port 3 Select 0
P3SEL0
022Ah
Port 4 Select 0
P4SEL0
022Bh
Port B Select 1
PBSEL1
022Ch
Port 3 Select 1
P3SEL1
022Ch
Port 4 Select 1
P4SEL1
022Dh
Port 3 Interrupt Vector Register
P3IV
022Eh
Port B Complement Select
PBSELC
0236h
Port 3 Complement Select
P3SELC
0236h
Port 4 Complement Select
P4SELC
0237h
Port B Interrupt Edge Select
PBIES
0238h
Port 3 Interrupt Edge Select
P3IES
0238h
Port 4 Interrupt Edge Select
P4IES
0239h
Port B Interrupt Enable
PBIE
023Ah
Port 3 Interrupt Enable
P3IE
023Ah
Port 4 Interrupt Enable
P4IE
023Bh
Port B Interrupt Flag
PBIFG
023Ch
Port 3 Interrupt Flag
P3IFG
023Ch
Port 4 Interrupt Flag
P4IFG
023Dh
Port 4 Interrupt Vector Register
P4IV
023Eh
Port C Input
PCIN
0240h
Port 5 Input
P5IN
0240h
Port 6 Input
P6IN
0241h
Port C Output
PCOUT
0242h
Port 5 Output
P5OUT
0242h
Port 6 Output
P6OUT
0243h
Port C Direction
PCDIR
0244h
Port 5 Direction
P5DIR
0244h
Port 6 Direction
P6DIR
0245h
Port C Resistor Enable
PCREN
0246h
Port 5 Resistor Enable
P5REN
0246h
Port 6 Resistor Enable
P6REN
0247h
Port C Select 0
PCSEL0
024Ah
Port 5 Select 0
P5SEL0
024Ah
Detailed Description
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ADVANCE INFORMATION
REGISTER DESCRIPTION
Port 2 Interrupt Vector Register
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Table 6-58. Digital I/O Registers (continued)
REGISTER DESCRIPTION
ACRONYM
ADDRESS
ADVANCE INFORMATION
Port 6 Select 0
P6SEL0
024Bh
Port C Select 1
PCSEL1
024Ch
Port 5 Select 1
P5SEL1
024Ch
Port 6 Select 1
P6SEL1
024Dh
Port 5 Interrupt Vector Register
P5IV
024Eh
Port C Complement Select
PCSELC
0256h
Port 5 Complement Select
P5SELC
0256h
Port 6 Complement Select
P6SELC
0257h
Port C Interrupt Edge Select
PCIES
0258h
Port 5 Interrupt Edge Select
P5IES
0258h
Port 6 Interrupt Edge Select
P6IES
0259h
Port C Interrupt Enable
PCIE
025Ah
Port 5 Interrupt Enable
P5IE
025Ah
Port 6 Interrupt Enable
P6IE
025Bh
Port C Interrupt Flag
PCIFG
025Ch
Port 5 Interrupt Flag
P5IFG
025Ch
Port 6 Interrupt Flag
P6IFG
025Dh
Port 6 Interrupt Vector Register
P6IV
025Eh
Port D Input
PDIN
0260h
Port 7 Input
P7IN
0260h
Port 8 Input
P8IN
0261h
Port D Output
PDOUT
0262h
Port 7 Output
P7OUT
0262h
Port 8 Output
P8OUT
0263h
Port D Direction
PDDIR
0264h
Port 7 Direction
P7DIR
0264h
Port 8 Direction
P8DIR
0265h
Port D Resistor Enable
PDREN
0266h
Port 7 Resistor Enable
P7REN
0266h
Port 8 Resistor Enable
P8REN
0267h
Port D Select 0
PDSEL0
026Ah
Port 7 Select 0
P7SEL0
026Ah
Port 8 Select 0
P8SEL0
026Bh
Port D Select 1
PDSEL1
026Ch
Port 7 Select 1
P7SEL1
026Ch
Port 8 Select 1
P8SEL1
026Dh
Port 7 Interrupt Vector Register
P7IV
026Eh
Port D Complement Select
PDSELC
0276h
Port 7 Complement Select
P7SELC
0276h
Port 8 Complement Select
P8SELC
0277h
Port D Interrupt Edge Select
PDIES
0278h
Port 7 Interrupt Edge Select
P7IES
0278h
Port 8 Interrupt Edge Select
P8IES
0279h
Port D Interrupt Enable
PDIE
027Ah
Port 7 Interrupt Enable
P7IE
027Ah
Port 8 Interrupt Enable
P8IE
027Bh
Port D Interrupt Flag
PDIFG
027Ch
144
Detailed Description
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Table 6-58. Digital I/O Registers (continued)
ACRONYM
ADDRESS
P7IFG
027Ch
Port 8 Interrupt Flag
P8IFG
027Dh
Port 8 Interrupt Vector Register
P8IV
027Eh
Port E Input
PEIN
0280h
Port 9 Input
P9IN
0280h
Port E Output
PEOUT
0282h
Port 9 Output
P9OUT
0282h
Port E Direction
PEDIR
0284h
Port 9 Direction
P9DIR
0284h
Port E Resistor Enable
PEREN
0286h
Port 9 Resistor Enable
P9REN
0286h
Port E Select 0
PESEL0
028Ah
Port 9 Select 0
P9SEL0
028Ah
Port E Select 1
PESEL1
028Ch
Port 9 Select 1
P9SEL1
028Ch
Port 9 Interrupt Vector Register
P9IV
028Eh
Port E Complement Select
PESELC
0296h
Port 9 Complement Select
P9SELC
0296h
Port E Interrupt Edge Select
PEIES
0298h
Port 9 Interrupt Edge Select
P9IES
0298h
Port E Interrupt Enable
PEIE
029Ah
Port 9 Interrupt Enable
P9IE
029Ah
Port E Interrupt Flag
PEIFG
029Ch
Port 9 Interrupt Flag
P9IFG
029Ch
Port J Input
PJIN
0320h
Port J Output
PJOUT
0322h
Port J Direction
PJDIR
0324h
Port J Resistor Enable
PJREN
0326h
Port J Select 0
PJSEL0
032Ah
Port J Select 1
PJSEL1
032Ch
Port J Complement Select
PJSELC
0336h
ADVANCE INFORMATION
REGISTER DESCRIPTION
Port 7 Interrupt Flag
Table 6-59. TA0 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Timer_A0 Control Register
TA0CTL
0340h
Timer_A0 Capture/Compare Control Register
TA0CCTL0
0342h
Timer_A0 Capture/Compare Control Register
TA0CCTL1
0344h
Timer_A0 Capture/Compare Control Register
TA0CCTL2
0346h
Timer_A0 Counter
TA0R
0350h
Timer_A0 Capture/Compare Register
TA0CCR0
0352h
Timer_A0 Capture/Compare Register
TA0CCR1
0354h
Timer_A0 Capture/Compare Register
TA0CCR2
0356h
Timer_A0 Expansion 0 Register
TA0EX0
0360h
Timer_A0 Interrupt Vector Register
TA0IV
036Eh
Detailed Description
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Table 6-60. TA1 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Timer_A1 Control Register
TA1CTL
0380h
Timer_A1 Capture/Compare Control Register
TA1CCTL0
0382h
Timer_A1 Capture/Compare Control Register
TA1CCTL1
0384h
Timer_A1 Capture/Compare Control Register
TA1CCTL2
0386h
Timer_A1 Counter
TA1R
0390h
Timer_A1 Capture/Compare Register
TA1CCR0
0392h
Timer_A1 Capture/Compare Register
TA1CCR1
0394h
Timer_A1 Capture/Compare Register
TA1CCR2
0396h
Timer_A1 Expansion 0 Register
TA1EX0
03A0h
Timer_A1 Interrupt Vector Register
TA1IV
03AEh
Table 6-61. TB0 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
ADVANCE INFORMATION
Timer_B0 Control Register
TB0CTL
03C0h
Timer_B0 Capture/Compare Control Register
TB0CCTL0
03C2h
Timer_B0 Capture/Compare Control Register
TB0CCTL1
03C4h
Timer_B0 Capture/Compare Control Register
TB0CCTL2
03C6h
Timer_B0 Capture/Compare Control Register
TB0CCTL3
03C8h
Timer_B0 Capture/Compare Control Register
TB0CCTL4
03CAh
Timer_B0 Capture/Compare Control Register
TB0CCTL5
03CCh
Timer_B0 Capture/Compare Control Register
TB0CCTL6
03CEh
Timer_B0 Counter
TB0R
03D0h
Timer_B0 Capture/Compare Register
TB0CCR0
03D2h
Timer_B0 Capture/Compare Register
TB0CCR1
03D4h
Timer_B0 Capture/Compare Register
TB0CCR2
03D6h
Timer_B0 Capture/Compare Register
TB0CCR3
03D8h
Timer_B0 Capture/Compare Register
TB0CCR4
03DAh
Timer_B0 Capture/Compare Register
TB0CCR5
03DCh
Timer_B0 Capture/Compare Register
TB0CCR6
03DEh
Timer_B0 Expansion Register 0
TB0EX0
03E0h
Timer_B0 Interrupt Vector Register
TB0IV
03EEh
Table 6-62. TA2 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Timer_A2 Control Register
TA2CTL
0400h
Timer_A2 Capture/Compare Control Register
TA2CCTL0
0402h
Timer_A2 Capture/Compare Control Register
TA2CCTL1
0404h
Timer_A2 Counter
TA2R
0410h
Timer_A2 Capture/Compare Register
TA2CCR0
0412h
Timer_A2 Capture/Compare Register
TA2CCR1
0414h
Timer_A2 Expansion 0 Register
TA2EX0
0420h
Timer_A2 Interrupt Vector Register
TA2IV
042Eh
Table 6-63. Capacitive Touch IO 0 Registers
REGISTER DESCRIPTION
Capacitive Touch IO 0 Control Register
146
ACRONYM
CAPTIO0CTL
Detailed Description
ADDRESS
043Eh
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Table 6-64. TA3 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Timer_A3 Control Register
TA3CTL
0440h
Timer_A3 Capture/Compare Control Register
TA3CCTL0
0442h
Timer_A3 Capture/Compare Control Register
TA3CCTL1
0444h
Timer_A3 Counter
TA3R
0450h
Timer_A3 Capture/Compare Register
TA3CCR0
0452h
Timer_A3 Capture/Compare Register
TA3CCR1
0454h
Timer_A3 Expansion 0 Register
TA3EX0
0460h
Timer_A3 Interrupt Vector Register
TA3IV
046Eh
Table 6-65. Capacitive Touch IO 1 Registers
REGISTER DESCRIPTION
Capacitive Touch IO 1 Control Register
ACRONYM
CAPTIO1CTL
ADDRESS
047Eh
REGISTER DESCRIPTION
ACRONYM
ADVANCE INFORMATION
Table 6-66. RTC_C Registers
ADDRESS
RTCCTL0 Register
RTCCTL0
04A0h
RTCCTL13 Register
RTCCTL13
04A2h
RTCOCAL Register
RTCOCAL
04A4h
RTCTCMP Register
RTCTCMP
04A6h
Real-Time Clock Prescale Timer 0 Control Register
RTCPS0CTL
04A8h
Real-Time Clock Prescale Timer 1 Control Register
RTCPS1CTL
04AAh
Real-Time Clock Prescale Timer Counter Register
RTCPS
04ACh
Prescale timer 0 counter value
RT0PS
04ACh
Prescale timer 1 counter value
RT1PS
04ADh
Real-Time Clock Interrupt Vector Register
RTCIV
04AEh
RTCTIM0 Register – Hexadecimal Format
RTCTIM0
04B0h
Real-Time Clock Hour, Day of Week
RTCTIM1
04B2h
RTCDATE - Hexadecimal Format
RTCDATE
04B4h
RTCYEAR Register – Hexadecimal Format
RTCYEAR
04B6h
RTCMINHR - Hexadecimal Format
RTCAMINHR
04B8h
RTCADOWDAY - Hexadecimal Format
RTCADOWDAY
04BAh
Binary-to-BCD Conversion Register
BIN2BCD
04BCh
BCD-to-Binary Conversion Register
BCD2BIN
04BEh
Table 6-67. 32-Bit Hardware Multiplier Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
16-bit operand one – multiply
MPY
04C0h
16-bit operand one – signed multiply
MPYS
04C2h
16-bit operand one – multiply accumulate
MAC
04C4h
16-bit operand one – signed multiply accumulate
MACS
04C6h
16-bit operand two
OP2
04C8h
16x16-bit result low word
RESLO
04CAh
16x16-bit result high word
RESHI
04CCh
16x16-bit sum extension register
SUMEXT
04CEh
32-bit operand 1 – multiply – low word
MPY32L
04D0h
32-bit operand 1 – multiply – high word
MPY32H
04D2h
Detailed Description
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Table 6-67. 32-Bit Hardware Multiplier Registers (continued)
REGISTER DESCRIPTION
ACRONYM
ADDRESS
32-bit operand 1 – signed multiply – low word
MPYS32L
04D4h
32-bit operand 1 – signed multiply – high word
MPYS32H
04D6h
32-bit operand 1 – multiply accumulate – low word
MAC32L
04D8h
32-bit operand 1 – multiply accumulate – high word
MAC32H
04DAh
32-bit operand 1 – signed multiply accumulate – low word
MACS32L
04DCh
32-bit operand 1 – signed multiply accumulate – high word
MACS32H
04DEh
32-bit operand 2 – low word
OP2L
04E0h
32-bit operand 2 – high word
OP2H
04E2h
32x32-bit result 0 – least significant word
RES0
04E4h
32x32-bit result 1
RES1
04E6h
32x32-bit result 2
RES2
04E8h
32x32-bit result 3 – most significant word
RES3
04EAh
MPY32 control register 0
MPY32CTL0
04ECh
ADVANCE INFORMATION
Table 6-68. DMA Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
DMA Control 0
DMACTL0
0500h
DMA Control 1
DMACTL1
0502h
DMA Control 2
DMACTL2
0504h
DMA Control 4
DMACTL4
0508h
DMA Interrupt Vector
DMAIV
050Eh
DMA Channel 0 Control
DMA0CTL
0510h
DMA Channel 0 Source Address
DMA0SA
0512h
DMA Channel 0 Destination Address
DMA0DA
0516h
DMA Channel 0 Transfer Size
DMA0SZ
051Ah
DMA Channel 1 Control
DMA1CTL
0520h
DMA Channel 1 Source Address
DMA1SA
0522h
DMA Channel 1 Destination Address
DMA1DA
0526h
DMA Channel 1 Transfer Size
DMA1SZ
052Ah
DMA Channel 2 Control
DMA2CTL
0530h
DMA Channel 2 Source Address
DMA2SA
0532h
DMA Channel 2 Destination Address
DMA2DA
0536h
DMA Channel 2 Transfer Size
DMA2SZ
053Ah
DMA Channel 3 Control
DMA3CTL
0540h
DMA Channel 3 Source Address
DMA3SA
0542h
DMA Channel 3 Destination Address
DMA3DA
0546h
DMA Channel 3 Transfer Size
DMA3SZ
054Ah
DMA Channel 4 Control
DMA4CTL
0550h
DMA Channel 4 Source Address
DMA4SA
0552h
DMA Channel 4 Destination Address
DMA4DA
0556h
DMA Channel 4 Transfer Size
DMA4SZ
055Ah
DMA Channel 5 Control
DMA5CTL
0560h
DMA Channel 5 Source Address
DMA5SA
0562h
DMA Channel 5 Destination Address
DMA5DA
0566h
DMA Channel 5 Transfer Size
DMA5SZ
056Ah
148
Detailed Description
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Table 6-69. MPU Control Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Memory Protection Unit Control 0
MPUCTL0
05A0h
Memory Protection Unit Control 1
MPUCTL1
05A2h
Memory Protection Unit Segmentation Border 2 Register
MPUSEGB2
05A4h
Memory Protection Unit Segmentation Border 1 Register
MPUSEGB1
05A6h
Memory Protection Unit Segmentation Access Management Register
MPUSAM
05A8h
Memory Protection Unit IP Control 0 Register
MPUIPC0
05AAh
Memory Protection Unit IP Encapsulation Segment Border 2 Register
MPUIPSEGB2
05ACh
Memory Protection Unit IP Encapsulation Segment Border 1 Register
MPUIPSEGB1
05AEh
Table 6-70. eUSCI_A0 Registers
ACRONYM
ADDRESS
UCA0CTLW0
05C0h
eUSCI_A0 Control Word Register 1
UCA0CTLW1
05C2h
eUSCI_A0 Baud Rate Control Word Register
UCA0BRW
05C6h
eUSCI_A0 Modulation Control Word Register
UCA0MCTLW
05C8h
eUSCI_A0 Status Register
UCA0STATW
05CAh
eUSCI_A0 Receive Buffer Register
UCA0RXBUF
05CCh
eUSCI_A0 Transmit Buffer Register
UCA0TXBUF
05CEh
eUSCI_A0 Auto Baud Rate Control Register
UCA0ABCTL
05D0h
eUSCI_A0 IrDA Control Word Register
UCA0IRCTL
05D2h
eUSCI_A0 Interrupt Enable Register
UCA0IE
05DAh
eUSCI_A0 Interrupt Flag Register
UCA0IFG
05DCh
eUSCI_A0 Interrupt Vector Register
UCA0IV
05DEh
ADVANCE INFORMATION
REGISTER DESCRIPTION
eUSCI_A0 Control Word Register 0
Table 6-71. eUSCI_A1 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
eUSCI_A1 Control Word Register 0
UCA1CTLW0
05E0h
eUSCI_A1 Control Word Register 1
UCA1CTLW1
05E2h
eUSCI_A1 Baud Rate Control Word Register
UCA1BRW
05E6h
eUSCI_A1 Modulation Control Word Register
UCA1MCTLW
05E8h
eUSCI_A1 Status Register
UCA1STATW
05EAh
eUSCI_A1 Receive Buffer Register
UCA1RXBUF
05ECh
eUSCI_A1 Transmit Buffer Register
UCA1TXBUF
05EEh
eUSCI_A1 Auto Baud Rate Control Register
UCA1ABCTL
05F0h
eUSCI_A1 IrDA Control Word Register
UCA1IRCTL
05F2h
eUSCI_A1 Interrupt Enable Register
UCA1IE
05FAh
eUSCI_A1 Interrupt Flag Register
UCA1IFG
05FCh
eUSCI_A1 Interrupt Vector Register
UCA1IV
05FEh
Table 6-72. eUSCI_A2 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
eUSCI_A2 Control Word Register 0
UCA2CTLW0
0600h
eUSCI_A2 Control Word Register 1
UCA2CTLW1
0602h
eUSCI_A2 Baud Rate Control Word Register
UCA2BRW
0606h
eUSCI_A2 Modulation Control Word Register
UCA2MCTLW
0608h
eUSCI_A2 Status Register
UCA2STATW
060Ah
Detailed Description
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Table 6-72. eUSCI_A2 Registers (continued)
REGISTER DESCRIPTION
ACRONYM
ADDRESS
eUSCI_A2 Receive Buffer Register
UCA2RXBUF
060Ch
eUSCI_A2 Transmit Buffer Register
UCA2TXBUF
060Eh
eUSCI_A2 Auto Baud Rate Control Register
UCA2ABCTL
0610h
eUSCI_A2 IrDA Control Word Register
UCA2IRCTL
0612h
eUSCI_A2 Interrupt Enable Register
UCA2IE
061Ah
eUSCI_A2 Interrupt Flag Register
UCA2IFG
061Ch
eUSCI_A2 Interrupt Vector Register
UCA2IV
061Eh
Table 6-73. eUSCI_A3 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
ADVANCE INFORMATION
eUSCI_A3 Control Word Register 0
UCA3CTLW0
0620h
eUSCI_A3 Control Word Register 1
UCA3CTLW1
0622h
eUSCI_A3 Baud Rate Control Word Register
UCA3BRW
0626h
eUSCI_A3 Modulation Control Word Register
UCA3MCTLW
0628h
eUSCI_A3 Status Register
UCA3STATW
062Ah
eUSCI_A3 Receive Buffer Register
UCA3RXBUF
062Ch
eUSCI_A3 Transmit Buffer Register
UCA3TXBUF
062Eh
eUSCI_A3 Auto Baud Rate Control Register
UCA3ABCTL
0630h
eUSCI_A3 IrDA Control Word Register
UCA3IRCTL
0632h
eUSCI_A3 Interrupt Enable Register
UCA3IE
063Ah
eUSCI_A3 Interrupt Flag Register
UCA3IFG
063Ch
eUSCI_A3 Interrupt Vector Register
UCA3IV
063Eh
Table 6-74. eUSCI_B0 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
eUSCI_B0 Control Word Register 0
UCB0CTLW0
0640h
eUSCI_B0 Control Word Register 1
UCB0CTLW1
0642h
eUSCI_B0 Baud Rate Control Word Register
UCB0BRW
0646h
eUSCI_B0 Status Register
UCB0STATW
0648h
eUSCI_B0 Byte Counter Threshold Register
UCB0TBCNT
064Ah
eUSCI_B0 Receive Buffer Register
UCB0RXBUF
064Ch
eUSCI_B0 Transmit Buffer Register
UCB0TXBUF
064Eh
eUSCI_B0 I2C Own Address 0 Register
UCB0I2COA0
0654h
eUSCI_B0 I2C Own Address 1 Register
UCB0I2COA1
0656h
eUSCI_B0 I2C Own Address 2 Register
UCB0I2COA2
0658h
eUSCI_B0 I2C Own Address 3 Register
UCB0I2COA3
065Ah
eUSCI_B0 I2C Received Address Register
UCB0ADDRX
065Ch
eUSCI_B0 I2C Address Mask Register
UCB0ADDMASK
065Eh
eUSCI_B0 I2C Slave Address Register
UCB0I2CSA
0660h
eUSCI_B0 Interrupt Enable Register
UCB0IE
066Ah
eUSCI_B0 Interrupt Flag Register
UCB0IFG
066Ch
eUSCI_B0 Interrupt Vector Register
UCB0IV
066Eh
150
Detailed Description
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Table 6-75. eUSCI_B1 Registers
ACRONYM
ADDRESS
UCB1CTLW0
0680h
eUSCI_B1 Control Word Register 1
UCB1CTLW1
0682h
eUSCI_B1 Baud Rate Control Word Register
UCB1BRW
0686h
eUSCI_B1 Status Register
UCB1STATW
0688h
eUSCI_B1 Byte Counter Threshold Register
UCB1TBCNT
068Ah
eUSCI_B1 Receive Buffer Register
UCB1RXBUF
068Ch
eUSCI_B1 Transmit Buffer Register
UCB1TXBUF
068Eh
eUSCI_B1 I2C Own Address 0 Register
UCB1I2COA0
0694h
eUSCI_B1 I2C Own Address 1 Register
UCB1I2COA1
0696h
eUSCI_B1 I2C Own Address 2 Register
UCB1I2COA2
0698h
eUSCI_B1 I2C Own Address 3 Register
UCB1I2COA3
069Ah
eUSCI_B1 I2C Received Address Register
UCB1ADDRX
069Ch
eUSCI_B1 I2C Address Mask Register
UCB1ADDMASK
069Eh
eUSCI_B1 I2C Slave Address Register
UCB1I2CSA
06A0h
eUSCI_B1 Interrupt Enable Register
UCB1IE
06AAh
eUSCI_B1 Interrupt Flag Register
UCB1IFG
06ACh
eUSCI_B1 Interrupt Vector Register
UCB1IV
06AEh
ADVANCE INFORMATION
REGISTER DESCRIPTION
eUSCI_B1 Control Word Register 0
Table 6-76. TA4 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Timer_A4 Control Register
TA4CTL
07C0h
Timer_A4 Capture/Compare Control Register
TA4CCTL0
07C2h
Timer_A4 Capture/Compare Control Register
TA4CCTL1
07C4h
Timer_A4 Counter
TA4R
07D0h
Timer_A4 Capture/Compare Register
TA4CCR0
07D2h
Timer_A4 Capture/Compare Register
TA4CCR1
07D4h
Timer_A4 Expansion 0 Register
TA4EX0
07E0h
Timer_A4 Interrupt Vector Register
TA4IV
07EEh
Table 6-77. ADC12_B Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
ADC12_B Control 0
ADC12CTL0
0800h
ADC12_B Control 1
ADC12CTL1
0802h
ADC12_B Control 2
ADC12CTL2
0804h
ADC12_B Control 3
ADC12CTL3
0806h
ADC12_B Window Comparator Low Threshold Register
ADC12LO
0808h
ADC12_B Window Comparator High Threshold Register
ADC12HI
080Ah
ADC12_B Interrupt Flag 0
ADC12IFGR0
080Ch
ADC12_B Interrupt Flag 1
ADC12IFGR1
080Eh
ADC12_B Interrupt Flag 2
ADC12IFGR2
0810h
ADC12_B Interrupt Enable 0
ADC12IER0
0812h
ADC12_B Interrupt Enable 1
ADC12IER1
0814h
ADC12_B Interrupt Enable 2
ADC12IER2
0816h
ADC12_B Interrupt Vector
ADC12IV
0818h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL0
0820h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL1
0822h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL2
0824h
Detailed Description
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Table 6-77. ADC12_B Registers (continued)
REGISTER DESCRIPTION
ACRONYM
ADDRESS
ADVANCE INFORMATION
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL3
0826h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL4
0828h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL5
082Ah
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL6
082Ch
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL7
082Eh
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL8
0830h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL9
0832h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL10
0834h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL11
0836h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL12
0838h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL13
083Ah
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL14
083Ch
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL15
083Eh
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL16
0840h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL17
0842h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL18
0844h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL19
0846h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL20
0848h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL21
084Ah
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL22
084Ch
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL23
084Eh
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL24
0850h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL25
0852h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL26
0854h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL27
0856h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL28
0858h
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL29
085Ah
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL30
085Ch
ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register
ADC12MCTL31
085Eh
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM0
0860h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM1
0862h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM2
0864h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM3
0866h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM4
0868h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM5
086Ah
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM6
086Ch
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM7
086Eh
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM8
0870h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM9
0872h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM10
0874h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM11
0876h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM12
0878h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM13
087Ah
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM14
087Ch
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM15
087Eh
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM16
0880h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM17
0882h
152
Detailed Description
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Table 6-77. ADC12_B Registers (continued)
ACRONYM
ADDRESS
ADC12MEM18
0884h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM19
0886h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM20
0888h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM21
088Ah
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM22
088Ch
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM23
088Eh
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM24
0890h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM25
0892h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM26
0894h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM27
0896h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM28
0898h
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM29
089Ah
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM30
089Ch
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
ADC12MEM31
089Eh
ADVANCE INFORMATION
REGISTER DESCRIPTION
ADC12_B Memory 0 Register to ADC12_B Memory 31 Register
Table 6-78. Comparator E Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Comparator Control Register 0
CECTL0
08C0h
Comparator Control Register 1
CECTL1
08C2h
Comparator Control Register 2
CECTL2
08C4h
Comparator Control Register 3
CECTL3
08C6h
Comparator Interrupt Control Register
CEINT
08CCh
Comparator Interrupt Vector Word Register
CEIV
08CEh
Table 6-79. CRC32 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
CRC32 Data Input Word 0
CRC32DIW0
0980h
CRC32 Data Input Word 1
CRC32DIW1
0982h
CRC32 Data In Reverse Word 1
CRC32DIRBW1
0984h
CRC32 Data In Reverse Word 0
CRC32DIRBW0
0986h
CRC32 Initialization and Result Word 0
CRC32INIRESW0
0988h
CRC32 Initialization and Result Word 1
CRC32INIRESW1
098Ah
CRC32 Result Reverse Word 1
CRC32RESRW1
098Ch
CRC32 Result Reverse Word 0
CRC32RESRW0
098Eh
CRC16 Data Input
CRC16DIW0
0990h
CRC16 Data In Reverse
CRC16DIRBW0
0996h
CRC16 Init and Result
CRC16INIRESW0
0998h
CRC16 Result Reverse
CRC16RESRW0
099Eh
Table 6-80. AES256 Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
AES Accelerator Control Register 0
AESACTL0
09C0h
AES Accelerator Control Register 1
AESACTL1
09C2h
AES Accelerator Status Register
AESASTAT
09C4h
AES Accelerator Key Register
AESAKEY
09C6h
AES Accelerator Data In Register
AESADIN
09C8h
Detailed Description
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Table 6-80. AES256 Registers (continued)
REGISTER DESCRIPTION
ACRONYM
ADDRESS
AES Accelerator Data Out Register
AESADOUT
09CAh
AES Accelerator XORed Data In Register
AESAXDIN
09CCh
AES Accelerator XORed Data In Register
AESAXIN
09CEh
Table 6-81. LCD_C Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
ADVANCE INFORMATION
LCD_C control 0
LCDCCTL0
0A00h
LCD_C control 1
LCDCCTL1
0A02h
LCD_C blinking control
LCDCBLKCTL
0A04h
LCD_C memory control
LCDCMEMCTL
0A06h
LCD_C Voltage Control Register
LCDCVCTL
0A08h
LCD_C port control 0
LCDCPCTL0
0A0Ah
LCD_C port control 1
LCDCPCTL1
0A0Ch
LCD_C port control 2 (≥256 segments)
LCDCPCTL2
0A0Eh
LCD_C port control 3 (384 segments)
LCDCPCTL3
0A10h
LCD_C charge pump control
LCDCCPCTL
0A12h
LCD_C interrupt vector
LCDCIV
0A1Eh
LCD memory 1
LCDM1
0A20h
LCD memory 2
LCDM2
0A21h
LCD memory 3
LCDM3
0A22h
LCD memory 4
LCDM4
0A23h
LCD memory 5
LCDM5
0A24h
LCD memory 6
LCDM6
0A25h
LCD memory 7
LCDM7
0A26h
LCD memory 8
LCDM8
0A27h
LCD memory 9
LCDM9
0A28h
LCD memory 10
LCDM10
0A29h
LCD memory 11
LCDM11
0A2Ah
LCD memory 12
LCDM12
0A2Bh
LCD memory 13
LCDM13
0A2Ch
LCD memory 14
LCDM14
0A2Dh
LCD memory 15
LCDM15
0A2Eh
LCD memory 16
LCDM16
0A2Fh
LCD memory 17
LCDM17
0A30h
LCD memory 18
LCDM18
0A31h
LCD memory 19
LCDM19
0A32h
LCD memory 20
LCDM20
0A33h
LCD blinking memory 1
LCDM33_LCDBM1
0A40h
LCD blinking memory 2
LCDM34_LCDBM2
0A41h
LCD blinking memory 3
LCDM35_LCDBM3
0A42h
LCD blinking memory 4
LCDM36_LCDBM4
0A43h
LCD blinking memory 5
LCDM37_LCDBM5
0A44h
LCD blinking memory 6
LCDM38_LCDBM6
0A45h
LCD blinking memory 7
LCDM39_LCDBM7
0A46h
LCD blinking memory 8
LCDM40_LCDBM8
0A47h
LCD blinking memory 9
LCDM41_LCDBM9
0A48h
LCDMX = 0 ... 4
154
Detailed Description
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Table 6-81. LCD_C Registers (continued)
REGISTER DESCRIPTION
ACRONYM
ADDRESS
LCD blinking memory 10
LCDM42_LCDBM10
0A49h
LCD blinking memory 11
LCDM43_LCDBM11
0A4Ah
LCD blinking memory 11
LCDM44_LCDBM12
0A4Bh
LCD blinking memory 13
LCDM45_LCDBM13
0A4Ch
LCD blinking memory 14
LCDM46_LCDBM14
0A4Dh
LCD blinking memory 15
LCDM47_LCDBM15
0A4Eh
LCD blinking memory 16
LCDM48_LCDBM16
0A4Fh
LCD blinking memory 17
LCDM49_LCDBM17
0A50h
LCD blinking memory 18
LCDM50_LCDBM18
0A51h
LCD blinking memory 19
LCDM51_LCDBM19
0A52h
LCD blinking memory 20
LCDM52_LCDBM20
0A53h
LCD memory 1
LCDM1
0A20h
LCD memory 2
LCDM2
0A21h
LCD memory 3
LCDM3
0A22h
LCD memory 4
LCDM4
0A23h
LCD memory 5
LCDM5
0A24h
LCD memory 6
LCDM6
0A25h
LCD memory 7
LCDM7
0A26h
LCD memory 8
LCDM8
0A27h
LCD memory 9
LCDM9
0A28h
LCD memory 10
LCDM10
0A29h
LCD memory 11
LCDM11
0A2Ah
LCD memory 12
LCDM12
0A2Bh
LCD memory 13
LCDM13
0A2Ch
LCD memory 14
LCDM14
0A2Dh
LCD memory 15
LCDM15
0A2Eh
LCD memory 16
LCDM16
0A2Fh
LCD memory 17
LCDM17
0A30h
LCD memory 18
LCDM18
0A31h
LCD memory 19
LCDM19
0A32h
LCD memory 20
LCDM20
0A33h
LCD memory 21
LCDM21
0A34h
LCD memory 22
LCDM22
0A35h
LCD memory 23
LCDM23
0A36h
LCD memory 24
LCDM24
0A37h
LCD memory 25
LCDM25
0A38h
LCD memory 26
LCDM26
0A39h
LCD memory 27
LCDM27
0A3Ah
LCD memory 28
LCDM28
0A3Bh
LCD memory 29
LCDM29
0A3Ch
LCD memory 30
LCDM30
0A3Dh
LCD memory 31
LCDM31
0A3Eh
LCD memory 32
LCDM32
0A3Fh
LCD memory 33
LCDM33_LCDBM1
0A40h
LCD memory 34
LCDM34_LCDBM2
0A41h
LCD memory 35
LCDM35_LCDBM3
0A42h
Detailed Description
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ADVANCE INFORMATION
LCDMX = 5 ... 8
155
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SLASEB7 – JUNE 2017
www.ti.com
Table 6-81. LCD_C Registers (continued)
REGISTER DESCRIPTION
LCD memory 36
ACRONYM
LCDM36_LCDBM4
ADDRESS
0A43h
Table 6-82. LEA Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
ADVANCE INFORMATION
LEA Capability Register
LEACAP
0A80h
Configuration Register 0
LEACNF0
0A84h
Configuration Register 1
LEACNF1
0A88h
Configuration Register 2
LEACNF2
0A8Ch
Memory Bottom Register
LEAMB
0A90h
Memory Top Register
LEAMT
0A94h
Code Memory Access Register
LEACMA
0A98h
Code Memory Control Register
LEACMCTL
0A9Ch
LEA Command Status Register
LEACMDSTAT
0AA8h
LEA Source 1 Status Register
LEAS1STAT
0AACh
LEA Source 0 Status Register
LEAS0STAT
0AB0h
LEA Result Status Register
LEADSTSTAT
0AB4h
PM Control Register
LEAPMCTL
0AC0h
PM Result Register
LEAPMDST
0AC4h
PM Source 1 Register
LEAPMS1
0AC8h
PM Source 0 Register
LEAPMS0
0ACCh
PM Command Buffer Register
LEAPMCB
0AD0h
Interrupt Flag and Set Register
LEAIFGSET
0AF0h
Interrupt Enable Register
LEAIE
0AF4h
Interrupt Flag and Clear Register
LEAIFG
0AF8h
Interrupt Vector Register
LEAIV
0AFCh
Table 6-83. SAPH Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Interrupt Index
SAPHIIDX
0E00h
Masked Interrupt Satus
SAPHMIS
0E02h
Raw Interrupt Status
SAPHRIS
0E04h
Interrupt Mask
SAPHIMSC
0E06h
Interrupt Clear
SAPHICR
0E08h
Interrupt Set
SAPHISR
0E0Ah
Module-Descriptor Low Word
SAPHDESCLO
0E0Ch
Module-Descriptor High Word
SAPHDESCHI
0E0Eh
Key
SAPHKEY
0E10h
Physical Interface Output Control #0
SAPHOCTL0
0E12h
Physical Interface Output Control #1
SAPHOCTL1
0E14h
Physical Interface Output Function Select
SAPHOSEL
0E16h
Channel 0 Pull UpTrim Register
SAPHCH0PUT
0E20h
Channel 0 Pull DownTrim Register
SAPHCH0PDT
0E22h
Channel 0 Termination Trim
SAPHCH0TT
0E24h
Channel 1 Pull UpTrim
SAPHCH1PUT
0E26h
Channel 1 Pull DownTrim
SAPHCH1PDT
0E28h
Channel 1 Termination Trim
SAPHCH1TT
0E2Ah
Trim Access Control
SAPHTACTL
0E2Eh
156
Detailed Description
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Table 6-83. SAPH Registers (continued)
ACRONYM
ADDRESS
SAPHICTL0
0E30h
Bias Control
SAPHBCTL
0E34h
PPG Count
SAPHPGC
0E40h
Pulse Generator Low Period
SAPHPGLPER
0E42h
Pulse Generator High Period
SAPHPGHPER
0E44h
PPG Control
SAPHPGCTL
0E46h
PPG Software Trigger
SAPHPPGTRIG
0E48h
A-SEQ control register 0
SAPHASCTL0
0E60h
A-SEQ control register 1
SAPHASCTL1
0E62h
ASQ Software Trigger
SAPHASQTRIG
0E64h
ASQ ping output polarity
SAPHAPOL
0E66h
ASQ ping pause level
SAPHAPLEV
0E68h
ASQ ping pause impedance
SAPHAPHIZ
0E6Ah
A-SEQ start to 1st ping
SAPHATM_A
0E6Eh
ASQ start to ADC arm
SAPHATM_B
0E70h
Count for the TIMEMARK C Event
SAPHATM_C
0E72h
ASQ start to ADC trig
SAPHATM_D
0E74h
ASQ start to restart
SAPHATM_E
0E76h
ASQ start to time-out
SAPHATM_F
0E78h
Time Base Control
SAPHTBCTL
0E7Ah
Acquisition Timer Low Part
SAPHATIMLO
0E7Ch
Acquisition Timer High Part
SAPHATIMHI
0E7Eh
ADVANCE INFORMATION
REGISTER DESCRIPTION
Physical Interface Input Control #0
Table 6-84. SDHS Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Interrupt Index Register
SDHSIIDX
0E80h
Masked Interrupt Status and Clear Register
SDHSMIS
0E82h
Raw Interrupt Status Register
SDHSRIS
0E84h
Interrupt Mask Register
SDHSIMSC
0E86h
Interrupt Clear Register.
SDHSICR
0E88h
Interrupt Set Register.
SDHSISR
0E8Ah
SDHS Descriptor Register L.
SDHSDESCLO
0E8Ch
SDHS Descriptor Register H.
SDHSDESCHI
0E8Eh
SDHS Control Register 0
SDHSCTL0
0E90h
SDHS Control Register 1
SDHSCTL1
0E92h
SDHS Control Register 2
SDHSCTL2
0E94h
SDHS Control Register 3
SDHSCTL3
0E96h
SDHS Control Register 4
SDHSCTL4
0E98h
SDHS Control Register 5
SDHSCTL5
0E9Ah
SDHS Control Register 6
SDHSCTL6
0E9Ch
SDHS Control Register 7
SDHSCTL7
0E9Eh
SDHS Data Converstion Register
SDHSDT
0EA2h
SDHS Window Comparator High Threshold Register.
SDHSWINHITH
0EA4h
SDHS Window Comparator Low Threshold Register.
SDHSWINLOTH
0EA6h
DTC destination address register
SDHSDTCDA
0EA8h
Detailed Description
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Table 6-85. UUPS Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Interrupt Index Register
UUPSIIDX
0EC0h
Masked Interrupt Status Register
UUPSMIS
0EC2h
Raw Interrupt Status Register
UUPSRIS
0EC4h
Interrupt Mask Register
UUPSIMSC
0EC6h
Interrupt Clear Register.
UUPSICR
0EC8h
Interrupt Flag Set Register.
UUPSISR
0ECAh
UUPS Descriptor Register L.
UUPSDESCLO
0ECCh
UUPS Descriptor Register H.
UUPSDESCHI
0ECEh
UUPS Control
UUPSCTL
0ED0h
Table 6-86. HSPLL Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
ADVANCE INFORMATION
Interrupt Index Register
HSPLLIIDX
0EE0h
Masked Interrupt Status Register.
HSPLLMIS
0EE2h
Raw Interrupt Status Register
HSPLLRIS
0EE4h
Interrupt Mask Register
HSPLLIMSC
0EE6h
Interrupt Flag Clear Register.
HSPLLICR
0EE8h
Interrupt Flag Set Register.
HSPLLISR
0EEAh
HSPLL Descriptor Register L.
HSPLLDESCLO
0EECh
HSPLL Descriptor Register H.
HSPLLDESCHI
0EEEh
HSPLL Control Register
HSPLLCTL
0EF0h
USSXT Control Register
HSPLLUSSXTLCTL
0EF2h
Table 6-87. MTIF Registers
REGISTER DESCRIPTION
ACRONYM
ADDRESS
Pulse Generator Configuration Register
MTIFPGCNF
0F00h
Pulse Generator Value Register
MTIFPGKVAL
0F02h
Pulse Generator Control Register
MTIFPGCTL
0F04h
Pulse Generator Status Register
MTIFPGSR
0F06h
Pulse Counter Configuration Register
MTIFPCCNF
0F08h
Pulse Counter Value Register
MTIFPCR
0F0Ah
Pulse Counter Control Register
MTIFPCCTL
0F0Ch
Pulse Counter Status Register
MTIFPCSR
0F0Eh
Measurement Test Port Control Register
MTIFTPCTL
0F10h
158
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6.17 Identification
6.17.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this
data sheet, see Section 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in the Device Descriptor structure (see
Section 6.15).
6.17.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see
Section 8.4.
6.17.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
MSP430 Programming With the JTAG Interface.
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A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in the Device Descriptor structure.
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7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP MCU. These
guidelines are to make sure that the device has proper connections for powering, programming,
debugging, and optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
ADVANCE INFORMATION
TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor
to each AVCC and DVCC pin (see Figure 7-1). Higher-value capacitors may be used but can affect supply
rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they
decouple (within a few millimeters). Additionally, TI recommends separated grounds with a single-point
connection for better noise isolation from digital to analog circuits on the board and to achieve high analog
accuracy.
DVCC
Digital Power
Supply Decoupling
+
1 µF
100 nF
DVSS
AVCC
Analog Power
Supply Decoupling
+
1 µF
100 nF
AVSS
Figure 7-1. Power Supply Decoupling
For PVCC and PVSS, TI recommends connecting a combination of a 1-µF plus a 22-µF low-ESR ceramic
decoupling capacitor between the PVCC and PVSS pins and a serial 22-Ω resistor to filter low-frequency
noise on the supply line (see Figure 7-2).
22 W
PVCC
22 µF
+
1 nF
PVSS
USS module power supply decoupling
Figure 7-2. Power Supply Decoupling for PVCC and PVSS
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External Oscillator (HFXT and LFXT)
Depending on the device variant (see Section 3), the device can support a low-frequency crystal (32 kHz)
on the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the
crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If they
are left unused, they must be terminated according to Section 4.6.
Figure 7-3 shows a typical connection diagram.
CL1
LFXOUT
or
HFXOUT
CL2
Figure 7-3. Typical Crystal Connection
See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP MCUs.
7.1.3
USS Oscillator (USSXT)
Depending on the device variant (see Section 3), the device with USS module supports a high-frequency
crystal on the USSXT pins. External bypass capacitors for the crystal oscillator pins are required. A 22-Ω
resistor is required to be serially connected closely to the USSXTOUT pin as shown in Figure 7-4. The
USSXT does not support bypass mode, so it is not possible to apply digital clock signals to the USSXTIN
pin. Never connect the USSXTIN pin to a power supply line (AVCC, DVCC, or PVCC). If the USSXT pins
are not used, terminate them according to Section 4.6.
Figure 7-4 shows a typical connection diagram.
USSXTIN
USSXTOUT
22 W
CL1
CL2
Figure 7-4. Typical Crystal Connection
Consider the following items for the USSXT layout:
•
•
•
•
Keep the trace of USSXTIN and USSXTOUT as short as possible. In case one must be longer than
the other, keep USSXTIN shorter because USSXTIN is more sensitive to EMI.000
Make ground shield open ended without making a loop
Use ground plane to reduce the impedance of ground trace
In case USSXT_BOUT is used, keep coupling to USSXTIN and CH0_IN to a minimum
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LFXIN
or
HFXIN
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In case USSXT_BOUT is feeding other clock or device inputs, apply a small capacitor (10 pF) as the
line termination load at end of line. This avoids reflection artifacts on sensitive inputs (for example,
HFXTIN).
Figure 7-5 shows recommended PCB layout.
Plane
Transducer
Interface
Area
CL1
CL2
Oscillator
Area
Plane
Oscillator
Area
CL2
Transducer
Interface
Area
XTAL
XTAL
CL1
22R
22R
Keep-out area for
high currents down
to next GND plane
USSXT_BOUT
ADVANCE INFORMATION
USSXT_BOUT
Keep-out area for
high currents down
to next GND plane
Figure 7-5. USSXT PCB Layout Recommendation
7.1.4
Transducer Connection to the USS Module
Figure 7-6 shows a typical connection of two transducers to the USS output and input pins. TI
recommends 1% error tolerance for the external termination resistors (Rterm0 and Rterm1) and the AC
coupling capacitors (Cac0 and Cac1). Typical value of the termination resistors is in the range of 150 to
400 Ω, the AC coupling capacitors are 1 to 2 nF. Actual values should be determined to meet the
requirements of each application.
Rterm0
CH0_OUT
Rterm1
CH1_OUT
T0
T1
Cac0
CH1_IN
Cac1
CH0_IN
Figure 7-6. Typical Transducer Connection
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Charge Pump Control of Input Multiplexer
Figure 7-7 shows the control logic of the charge pump control of the input multiplexer of CHx_IN. The
charge pump is enabled as long the RxBias switch is turned on and during the arming of the SDHS. Use
the CPDA bit to control the CP during data acquisition.
CPDA
ASQ.adc_arming
RxBiasSwitchEn
SDHS.adc_arming
SDHS.acquisition
Charge
Pump
Enable
CH0_IN
CH1_IN
en
CP
MUX
ASQ.acquisition
PGA
To SDHS
7.1.6
JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-8 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-9 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-8 and Figure 7-9 show a jumper block that supports both scenarios of supplying VCC to the target
board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the
jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s
Guide.
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Figure 7-7. Control Of Input Multiplexer
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
TEST
2
RST/NMI/SBWTDIO
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
TDO/TDI
TDI
TDI
TMS
TMS
TCK
TCK
GND
RST
ADVANCE INFORMATION
TEST/SBWTCK
C1
2.2 nF
(see Note B)
AVSS/DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 7-8. Signal Connections for 4-Wire JTAG Communication
164
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kΩ
See Note B
JTAG
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
TEST/SBWTCK
C1
2.2 nF
See Note B
AVSS/DVSS
Copyright © 2016, Texas Instruments Incorporated
A.
B.
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 7-9. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.7
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the SFRRPCR
register.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown
capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or
in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide for
more information on the referenced control registers and bits.
7.1.8
Unused Pins
For details on the connection of unused pins, see Section 4.6.
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VCC TOOL
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7.1.9
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General Layout Recommendations
•
•
•
•
•
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators for recommended layout guidelines.
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
See Circuit Board Layout Techniques for a detailed discussion of PCB layout considerations. This
document is written primarily about op amps, but the guidelines are generally applicable for all mixedsignal applications.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
7.1.10 Do's and Don'ts
ADVANCE INFORMATION
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in . Exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC12_B Peripheral
7.2.1.1
Partial Schematic
Figure 7-10 shows the recommended connections for the reference input pins.
AVSS
Using an
External
Positive
Reference
Using an
External
Negative
Reference
VREF+/VEREF+
+
10 µF
4.7 µF
VEREF-
+
10 µF
4.7 µF
Figure 7-10. ADC12_B Grounding and Noise Considerations
7.2.1.2
Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Figure 7-10 prevent these offsets.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. A noise-free design using
separate analog and digital ground planes with a single-point connection is recommend to achieve high
accuracy.
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Figure 7-10 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as specified in the IO(VREF+) specification of the
REF module.
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor buffers the reference pin and filter any low-frequency
ripple. A 4.7-µF bypass capacitor filters out any high-frequency noise.
7.2.1.3
Detailed Design Procedure
For additional design information, see Designing With the MSP430FR58xx, FR59xx, FR68xx, and FR69xx
ADC.
7.2.1.4
Layout Guidelines
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
If differential mode is used for the ADC12_B, the analog differential input signals must be routed closely
together to minimize the effect of noise on the resulting signal.
7.2.2
LCD_C Peripheral
7.2.2.1
Partial Schematic
Required LCD connections greatly vary by the type of display that is used (static or multiplexed), whether
external or internal biasing is used, and whether the on-chip charge pump is employed. Also, there is a
fair amount of flexibility as to how the segment (Sx) and common (COMx) signals are connected to the
MCU, which can provide unique benefits. Because LCD connections are application-specific, it is difficult
to provide a single one-fits-all schematic. However, for examples and how-to circuit design guidance, see
Designing With MSP430™ MCUs and Segment LCDs.
7.2.2.2
Design Requirements
Due to the flexibility of the LCD_C peripheral module to accommodate various segment-based LCDs,
selecting the correct display for the application in combination with determining specific design
requirements is often an iterative process. TI strongly recommends reviewing the LCD_C peripheral
module chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family
User's Guide and Designing With MSP430™ MCUs and Segment LCDs during the initial design
requirements and decision process.
7.2.2.3
Detailed Design Procedure
A major component in designing the LCD solution is determining the exact connections between the
LCD_C peripheral module and the display itself. Two basic design processes can be employed for this
step, although in reality often a balanced co-design approach is recommended:
• PCB layout-driven design, optimizing signal routing
• Software-driven design, focusing on optimizing computational overhead
For a detailed discussion of the design procedure as well as for design information regarding the LCD
controller input voltage selection including internal and external options, contrast control, and bias
generation, see Designing With MSP430™ MCUs and Segment LCDs and the LCD_C Controller chapter
in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide.
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Component that are shown in the partial schematic (see Figure 7-10) should be placed as close as
possible to the respective device pins. Avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal.
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Layout Guidelines
LCD segment (Sx) and common (COMx) signal traces are continuously switching while the LCD is
enabled and should, therefore, be kept away from sensitive analog signals such as ADC inputs to prevent
any noise coupling. TI recommends keeping the LCD signal traces on one side of the PCB grouped
together in a bus-like fashion. A ground plane beneath the LCD traces and guard traces alongside the
LCD traces can provide shielding.
If the internal charge pump of the LCD module is used, place the externally provided capacitor on the
LCDCAP pin as close as possible to the MCU. Connect the capacitor to the device using a short and
direct trace and also have a solid connection to the ground plane that supplies the VSS pins of the MCU.
For an example layouts and a more in-depth discussion, see Designing With MSP430™ MCUs and
Segment LCDs.
ADVANCE INFORMATION
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8 Device and Documentation Support
8.1
Getting Started and Next Steps
For more information on the MSP family of microcontrollers and the tools and libraries that are available to
help with your development, visit the Getting Started page.
8.2
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices and support tools. Each MSP MCU commercial family member has one of three
prefixes: MSP, PMS, or XMS (for example, MSP430FR6047). TI recommends two of three possible prefix
designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of product
development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI internal qualification testing.
MSP – Fully-qualified development-support product
XMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZP) and temperature range (for example, T). Figure 8-1 provides a legend
for reading the complete device name for any family member.
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XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
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MSP
430 FR 6 0471
I
PZ
T
Feature Set
Processor Family
MCU Platform
Optional: Distribution Format
Device Type
Packaging
Series
Optional: Temperature Range
AES
Oscillators, LEA
ADVANCE INFORMATION
Processor
Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
MCU
Platform
430 = 16-Bit Low-Power Platform
Device
Type
Memory Type
FR = FRAM
Series
6 = Up to 16 MHz with LCD
Feature
Set
First Digit: Feature
0 = USS
Optional:
Temperature
Range
S = 0°C to 50°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional:
Distribution
Format
T = Small reel
R = Large reel
No Markings = Tube or tray
Optional:
Additional
Features
-Q1 = Automotive Qualified
-EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
Optional: BSL
FRAM
Second Digit: Oscillators, LEA
4 = HFXT + LFXT + LEA + USS
3 = HFXT + LFXT + LEA
2 = HFXT + LFXT
1 = LFXT
Third Digit: FRAM (KB)
7 = 256
6 = 192
5 = 128
4 = 96
3 = 64
Optional Fourth Digit: BSL
2
1=IC
No value = UART
Figure 8-1. Device Nomenclature
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8.3
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Tools and Software
Table 8-1 lists the debug features supported by these microcontrollers. See the Code Composer Studio™
IDE v7.2 for MSP430 User's Guide for details on the available features. See Advanced Debugging Using
the Enhanced Emulation Module (EEM) With Code Composer Studio™ IDE v7 and MSP430™ Advanced
Power Optimizations: ULP Advisor™ Software and EnergyTrace™ Technology for further usage
information.
Table 8-1. Hardware Features
MSP
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
EnergyTrace++
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
Yes
Yes
Design Kits and Evaluation Modules
Software
MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 design resources,
MSP430Ware software also includes a high-level API called MSP430 Driver Library. This
library makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of Code Composer Studio IDE or as a stand-alone package.
MSP430FR604x(1), MSP430FR603x(1) Code Examples C Code examples are available for every MSP
device that configures each of the integrated peripherals for various application needs.
MSP Driver Library Driver Library's abstracted API keeps you above the bits and bytes of the MSP430
hardware by providing easy-to-use function calls. Thorough documentation is delivered
through a helpful API Guide, which includes details on each function call and the recognized
parameters. Developers can use Driver Library functions to write complete projects with
minimal overhead.
MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the application's energy profile and
helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully use the unique ultra-low power features of MSP430 and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to squeeze every last nano amp
out of your application. At build time, ULP Advisor provides notifications and remarks on
areas of your code that can be further optimized for lower power.
Fixed-Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Device and Documentation Support
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MSP-TS430PZ100E 100-pin Target Development Board The MSP-TS430PZ100E is a stand-alone 100pin ZIF socket target board used to program and debug the MSP430 MCU in-system through
the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.
MSP430FR6047
SLASEB7 – JUNE 2017
www.ti.com
Floating-Point Math Library for MSP430 Continuing to innovate in the low power and low cost
microcontroller space, TI brings you MSPMATHLIB. Leveraging the intelligent peripherals of
our devices, this floating point math library of scalar functions brings you up to 26x better
performance. Mathlib is easy to integrate into your designs. This library is free and is
integrated in both Code Composer Studio and IAR IDEs. Read the user's guide for an in
depth look at the math library and relevant benchmarks.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio is an integrated development environment (IDE) that supports all MSP
microcontroller devices. Code Composer Studio comprises a suite of embedded software
utilities used to develop and debug embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment, debugger, profiler, and many other
features. The intuitive IDE provides a single user interface taking you through each step of
the application development flow. Familiar utilities and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse
software framework with advanced embedded debug capabilities from TI resulting in a
compelling feature-rich development environment for embedded developers. When using
CCS with an MSP MCU, a unique and powerful set of plugins and embedded software
utilities are made available to fully leverage the MSP microcontroller.
ADVANCE INFORMATION
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) files directly to
the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which allows users to quickly begin application development on MSP
low-power microcontrollers (MCU). Creating MCU software usually requires downloading the
resulting binary program to the MSP device for validation and debugging. The MSP-FET
provides a debug communication pathway between a host computer and the target MSP.
Furthermore, the MSP-FET also provides a Backchannel UART connection between the
computer's USB interface and the MSP UART. This affords the MSP programmer a
convenient method for communicating serially between the MSP and a terminal running on
the computer. It also supports loading programs (often called firmware) to the MSP target
using the BSL (bootloader) through the UART and I2C communication protocols.
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 Flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that allow
the user to fully customize the process. The MSP Gang Programmer is provided with an
expansion board, called the Gang Splitter, that implements the interconnections between the
MSP Gang Programmer and multiple target devices. Eight cables are provided that connect
the expansion board to eight target devices (through JTAG or Spy-Bi-Wire connectors). The
programming can be done with a PC or as a stand-alone device. A PC-side graphical user
interface is also available and is DLL-based.
8.4
Documentation Support
The following documents describe the MSP430FR6047 MCUs. Copies of these documents are available
on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (for example, MSP430FR6047). In the upper-right corner, click the "Alert me" button.
This registers you to receive a weekly digest of product information that has changed (if any). For change
details, check the revision history of any revised document.
Errata
MSP430FR6047 Device Erratasheet Describes the known exceptions to the functional specifications.
172
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MSP430FR6047
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SLASEB7 – JUNE 2017
User's Guides
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide Detailed
description of all modules and peripherals available in this device family.
MSP430FR57xx, FR58xx, FR59xx, FR68xx, and FR69xx Bootloader (BSL) User's Guide The BSL
provides a method to program memory during MSP430 FRAM-based MCU project
development and updates. The BSL can be activated by a utility that sends commands using
a serial protocol. The BSL lets the user control the activity of the MSP430 MCUs and
exchange data using a personal computer or other device.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller.
MSP430 32-kHz Crystal Oscillators Selection of the correct crystal, correct load circuit, and proper
board layout are important for a stable crystal oscillator. This application report summarizes
crystal oscillator function and explains the parameters to select the correct crystal for
MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to
ensure stable oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs: (1) Component-level ESD testing and system-level ESD testing, their differences
and why component-level ESD rating does not ensure system-level robustness. (2) General
design guidelines for system-level ESD protection at different levels including enclosures,
cables, PCB layout, and onboard ESD protection devices. (3) Introduction to System Efficient
ESD Design (SEED), a codesign methodology of onboard and on-chip ESD protection to
achieve system-level ESD robustness, with example simulations and test results. A few realworld system-level ESD protection design examples and their results are also discussed.
8.5
Trademarks
MSP430Ware, MSP430, EnergyTrace, ULP Advisor, Code Composer Studio are trademarks of Texas
Instruments.
ARM, Cortex are registered trademarks of ARM Limited.
All other trademarks are the property of their respective owners.
8.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
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SLASEB7 – JUNE 2017
8.8
www.ti.com
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
ADVANCE INFORMATION
174
Mechanical, Packaging, and Orderable Information
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Copyright © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jun-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FR6047IPZ
PREVIEW
LQFP
PZ
100
90
TBD
Call TI
Call TI
-40 to 85
MSP430FR6047IPZR
PREVIEW
LQFP
PZ
100
1000
TBD
Call TI
Call TI
-40 to 85
XMS430FR6047IPZR
PREVIEW
LQFP
PZ
100
1000
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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