STMicroelectronics M29F002NT-70XK6TR 2 mbit 256kb x8, boot block single supply flash memory Datasheet

M29F002T, M29F002NT
M29F002B
2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory
5V ± 10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
FAST ACCESS TIME: 70ns
FAST PROGRAMMING TIME: 10µs typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M29F002T: B0h
– Device Code, M29F002NT: B0h
– Device Code, M29F002B: 34h
32
1
PLCC32 (K)
PDIP32 (P)
TSOP32 (N)
8 x 20mm
Figure 1. Logic Diagram
VCC
18
8
A0-A17
DESCRIPTION
The M29F002 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single5V VCC supply.For Program and
Erase operations the necessary high voltages are
generated internally. The device can also be programmed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against programing and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
W
E
DQ0-DQ7
M29F002T
M29F002B
M29F002NT
G
(*) RPNC
VSS
AI02078C
Note: * RPNC function is not available for the M29F002NT
July 1998
1/29
M29F002T, M29F002NT, M29F002B
Figure 2A. DIP Pin Connections
A12
A15
A16
RPNC
VCC
W
A17
VCC
W
A17
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
9
M29F002T
M29F002B
25
A14
A13
A8
A9
A11
G
A10
E
DQ7
17
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
1
32
2
31
3
30
4
29
5
28
6
27
7
26
M29F002T
8
25
M29F002B
9 M29F002NT24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
(*) RPNC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Figure 2B. LCC Pin Connections
AI02079C
AI02080C
Note: Pin 1 is not connected for the M29F002NT
Figure 2C. TSOP Pin Connections
A11
A9
A8
A13
A14
A17
W
VCC
RPNC
A16
A15
A12
A7
A6
A5
A4
1
8
9
16
32
M29F002T
M29F002B
25
24
17
AI02361B
2/29
Table 1. Signal Names
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
A0-A17
Address Inputs
DQ0-DQ7
Data Input/Outputs, Command Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RPNC (*)
Reset / Block Temporary Unprotect
VCC
Supply Voltage
VSS
Ground
DESCRIPTION (cont’d)
Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Suspend and Resume are written to the device in
cycles of commandsto a CommandInterfaceusing
standard microprocessor write timings. The device
is offered in PLCC32, PDIP32 and TSOP32 (8 x 20
mm) packages.
M29F002T, M29F002NT, M29F002B
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Ambient Operating Temperature
TA
(3)
Value
Unit
–40 to 125
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
Input or Output Voltages
–0.6 to 7
V
Supply Voltage
–0.6 to 7
V
A9, E, G, RPNC Voltage
–0.6 to 13.5
V
VIO
(2)
VCC
V(A9, E, G, RPNC)
(2)
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
Organisation
The M29F002 is organised as 256K x 8. Memory
control is provided by Chip Enable E, Output Enable G and Write Enable W inputs.
A Reset/Block Temporary Unprotection RPNC
(NOT available on M29F002NT) tri-level input provides a hardwarereset when pulled Low, and when
held High (at VID) temporarily unprotects blocks
previously protected allowing them to be programed and erased. Erase and Program operations
are controlled by an internal Program/Erase Controller (P/E.C.).StatusRegister data outputon DQ7
provides a Data Polling signal, and DQ6 and DQ2
provide Toggle signals to indicate the state of the
P/E.C operations.
Memory Blocks
The devices feature asymmetrically blocked architecture providing system memory integration. The
M29F002 has an array of 7 blocks, one Boot Block
of 16 KBytes, two Parameter Blocks of 8 KBytes,
one Main Block of 32 KBytes and three Main Blocks
of 64 KBytes.
The memory map is shown in Figure 3. Each block
can be erased separately, any combination of
blocks can be specified for multi-block erase or the
entire chip may be erased. The Erase operations
are managedautomaticallyby the P/E.C.The block
erase operation can be suspended in order to read
from or program to any block not being ersased,
and then resumed. Block protection provides additional data security. Each block can be separately
protectedor unprotectedagainstProgram or Erase
on programming equipment. All previously protected blocks can be temporarily unprotectedin the
application.
Bus Operations
The following operations can be performed using
the appropriatebus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write command, Output Disable, Standby, Reset, Block Prot ec t io n , Unp ro t e ct io n, P ro t e cti on Verif y,
Unprotection Verify and Block Temporary Unprotection. See Tables 4 and 5.
Command Interface
Instructions, made up of commands written in cycles, can be given to the Program/EraseController
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Program/Erase Controller instructions. The ’Command’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command sequence will reset the device to Read Array mode.
3/29
M29F002T, M29F002NT, M29F002B
Figure 3. Memory Map and Block Address Table
M29F002T, M29F002NT
M29F002B
3FFFFh
3FFFFh
16K BOOT BLOCK
64K MAIN BLOCK
3C000h
3BFFFh
30000h
2FFFFh
8K PARAMETER BLOCK
64K MAIN BLOCK
3A000h
39FFFh
20000h
1FFFFh
8K PARAMETER BLOCK
64K MAIN BLOCK
38000h
37FFFh
10000h
0FFFFh
32K MAIN BLOCK
32K MAIN BLOCK
30000h
2FFFFh
08000h
07FFFh
64K MAIN BLOCK
8K PARAMETER BLOCK
20000h
1FFFFh
06000h
05FFFh
64K MAIN BLOCK
8K PARAMETER BLOCK
10000h
0FFFFh
04000h
03FFFh
64K MAIN BLOCK
16K BOOT BLOCK
00000h
00000h
AI02081C
Table 3A. M29F002T, M29F002NT Block Address Table
Address Range
A17
A16
A15
A14
A13
00000h-0FFFFh
0
0
X
X
X
10000h-1FFFFh
0
1
X
X
X
20000h-2FFFFh
1
0
X
X
X
30000h-37FFFh
1
1
0
X
X
38000h-39FFFh
1
1
1
0
0
3A000h-3BFFFh
1
1
1
0
1
3C000h-3FFFFh
1
1
1
1
X
Table 3B. M29F002B Block Address Table
4/29
Address Range
A17
A16
A15
A14
A13
00000h-03FFFh
0
0
0
0
X
04000h-05FFFh
0
0
0
1
0
06000h-07FFFh
0
0
0
1
1
08000h-0FFFFh
0
0
1
X
X
10000h-1FFFFh
0
1
X
X
X
20000h-2FFFFh
1
0
X
X
X
30000h-3FFFFh
1
1
X
X
X
M29F002T, M29F002NT, M29F002B
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the ElectronicSignature
or Block ProtectionStatus), Program, Block Erase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all timing and verification of the Program and Erase
operations.The Status Register Data Polling, Toggle, Error bits may be read at any time, during
programming or erase, to monitor the progress of
the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interfacewhich iscommon to all instructions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to give additional data protection,the instructions for Program and Block or Chip Erase require
further command inputs. For a Programinstruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
block may be suspended,in orderto read data from
another block or to program data in another block,
and then resumed.
When power is first applied or if VCC falls below
VLKO, the command interface is reset to Read
Array.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A17). The address inputs for
the memory array are latched during a write operation on the falling edge of Chip Enable E or Write
Enable W. When A9 is raised to VID, either a Read
ElectronicSignature Manufactureror Device Code,
Block Protection Status or a Write Block Protection
or Block Unprotection is enabled depending on the
combination of levels on A0, A1, A6, A12 and A15.
Data Input/Outputs (DQ0-DQ7). The input is data
to be programmed in the memory array or a command to be written to the C.I. Both are latched on
the rising edge of Chip Enable E or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputs are disabled and when RPNC is at a Low
level.
Chip Enable (E). The Chip Enable input activates
the memory control logic, input buffers, decoders
and sense amplifiers. E High deselectsthe memory
and reduces the power consumptionto the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. The Chip Enable must be
forced to VID during the Block Unprotection operation.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to VID level during
Block Protection and Unprotection operations.
Write Enable (W). This input controls writing to the
Command Registerand Addressand Datalatches.
Reset/Block Temporary Unprotect/No Connect
Input (RPNC). The RPNC (not available for the
M29F002NT) input provides hardware reset and
protected block(s) temporary unprotection functions. In read or write mode, the RPNC pin can be
left open (Not Connected) or held at VIH. Reset of
the memory is acheived by pulling RPNC to VIL for
at least 500ns. When the reset pulse is given, if the
memory is in Read or Standby modes, it will be
available for new operations in 50ns after the rising
edge of RPNC. If the memory is in Erase, Erase
Suspend or Program modes the reset will take
10µs. Ahardware reset duringan Eraseor Program
operation will corrupt the data being programmed
or the sector(s) being erased.
Temporary block unprotection is made by holding
RPNC at VID. In this condition previously protected
blocks can be programmed or erased. The transition of RPNC from VIH to VID must slower than
500ns. When RPNC is returned from VID to VIH all
blocks temporarily unprotected will be again protected.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
DEVICE OPERATIONS
See Tables 4, 5 and 6.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Signature, the Status Register or the Block Protection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
5/29
M29F002T, M29F002NT, M29F002B
Table 4. User Bus Operations (1)
Operation
E
Read Byte
VIL
G
VIL
W
VIH
RPNC (6)
A0
A1
A6
A9
A12
A15
DQ0-DQ7
VIH/NC
(5)
A0
A1
A6
A9
A12
A15
Data Output
(5)
A0
A1
A6
A9
A12
A15
Data Input
Write Byte
VIL
VIH
VIL
VIH/NC
Output Disable
VIL
VIH
VIH
VIH/NC (5)
X
X
X
X
X
X
Hi-Z
(5)
X
X
X
X
X
X
Hi-Z
Standby
VIH
X
X
X
X
X
VIL
X
X
X
X
X
X
Hi-Z
Block
(2,4)
Protection
VIL
VID
VIL Pulse
VIH/NC (5)
X
X
X
VID
X
X
X
Blocks
Unprotection(4)
VID
VID
VIL Pulse
VIH/NC (5)
X
X
X
VID
VIH
VIH
X
Block
Protection
Verify(2,4)
VIL
VIL
VIH
VIH/NC (5)
VIL
VIH
VIL
VID
A12
A15
Block Protect
Status (3)
Block
Unprotection
Verify(2,4)
VIL
VIL
VIH
VIH/NC (5)
VIL
VIH
VIH
VID
A12
A15
Block Protect
Status (3)
Block
Temporary
Unprotection (6)
X
X
X
VID
X
X
X
X
X
X
X
Reset
(6)
Notes: 1.
2.
3.
4.
5.
6.
VIH/NC
X = VIL or VIH
Block Address must be given on A13-A17 bits.
See Table 6.
Operation performed on programming equipment.
RPNC can be held at VIH or left open (Not Connected).
Not Available on M29F002NT.
Table 5. Read Electronic Signature (following AS instruction or with A9 = VID)
E
G
W
A0
A1
Other
Addresses
DQ0 - DQ7
VIL
VIL
VIH
VIL
VIL
Don’t Care
20h
M29F002T
M29F002NT
VIL
VIL
VIH
VIH
VIL
Don’t Care
B0h
M29F002B
VIL
VIL
VIH
VIH
VIL
Don’t Care
34h
Code
Device
Manufact. Code
Device Code
Table 6. Read Block Protection with AS Instruction
E
G
W
A0
A1
A13 - A17
Other
Addresses
DQ0 - DQ7
Protected Block
VIL
VIL
VIH
VIL
VIH
Block Address
Don’t Care
01h
Unprotected Block
VIL
VIL
VIH
VIL
VIH
Block Address
Don’t Care
00h
Code
6/29
M29F002T, M29F002NT, M29F002B
Write. Write operations are used to give Instruction
Commands to the memory or to latch input data to
be programmed. A write operationis initiated when
Chip Enable E is Low and Write Enable W is Low
with Output Enable G High. Addresses are latched
on the falling edge of W or E whicheveroccurs last.
Commandsand InputData are latchedon the rising
edge of W or E whichever occurs first.
Output Disable. The data outputs are high impedance when the Output Enable G is High with Write
Enable W High.
Standby. The memory is in standby when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G or Write Enable W inputs.
Automatic Standby. After 150ns of bus inactivity
and when CMOS levels are driving the addresses,
the chip automatically enters a pseudo-standby
mode where consumption is reduced to the CMOS
standby value, while outputs still drive the bus.
Electronic Signature. Two codes identifying the
manufacturerand the device can be read from the
memory. These codes allow programming equipment or applications to automatically match their
interface to the characteristics of the M29F002.
The Electronic Signature is output by a Read operation when the voltage applied to A9 is at VID and
address input A1 is Low. The manufacturer code is
output when the Address input A0 is Low and the
device code when this input is High. Other Address
inputs are ignored.
The Electronic Signature can also be read, without
raising A9 to VID, by giving the memory the Instruction AS.
Block Protection. Each block can be separately
protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or
erase operations. This mode is activated when
both A9 and G are raised to VID and an address in
the block is applied on A13-A17. The Block Protection algorithm is shown in Figure 14. Block protection is initiated on the edge of W falling to VIL. Then
after a delay of 100µs, the edge of W rising to VIH
ends the protection operations. Block protection
verify is achieved by bringing G, E, A0 and A6 to
VIL and A1 to VIH, while W is at VIH and A9 at VID.
Underthese conditions, reading the dataoutput will
yield 01h if the block defined by the inputs on
A13-A17 is protected. Any attempt to program or
erase a protected block will be ignored by the
device.
Block Temporary Unprotection. This feature is
available on M29F002T and M29F002B only. Any
previously protected block can be temporarily unprotected in order to change stored data. The
temporaryunprotectionmode is activated by bringing RPNC to VID. During the temporary unprotection mode the previously protected blocks are
unprotected.A block can be selected and data can
be modified by executing the Erase or Program
instruction with the RPNC signal held at VID. When
RPNC is returned to VIH, all the previously protected blocks are again protected.
Block Unprotection. All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protected before the unprotection operation. Block
unprotection is activated when A9, G and E are at
VID and A12, A15 at VIH. The Block Unprotection
algorithm is shown in Figure 15. Unprotection is
initiated by the edge of W fallingto VIL. Aftera delay
of 10ms, the unprotection operation is ended by
rising W to VIH. Unprotection verify is achieved by
bringing G and E to VIL while A0 is at VIL, A6 and
A1 are at VIH and A9 remains at VID. In these
conditions, reading the output data will yield 00h if
the block defined by the inputs A13-A17 has been
succesfullyunprotected.Each block must be separately verified by giving its address in order to
ensure that it has been unprotected.
INSTRUCTIONS AND COMMANDS
The Command Interface latches commands written to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Read Block Protection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences.
Table 7. Commands
Hex Code
Command
00h
Invalid/Reserved
10h
Chip Erase Confirm
20h
Reserved
30h
Block Erase Resume/Confirm
80h
Set-up Erase
90h
Read Electronic Signature/
Block Protection Status
A0h
Program
B0h
Erase Suspend
F0h
Read Array/Reset
7/29
M29F002T, M29F002NT, M29F002B
Table 8. Instructions (1)
Mne.
RD (2,4)
Instr.
Read/Reset
Memory Array
Cyc.
1+
3+
AS (4)
PG
BE
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
Addr.
Program
Block Erase
Chip Erase
Addr. (3,7)
555h
AAAh
555h
Data
AAh
55h
F0h
555h
AAAh
555h
Data
AAh
55h
90h
Addr. (3,7)
555h
AAAh
555h
Data
AAh
55h
A0h
555h
AAAh
555h
555h
AAAh
AAh
55h
80h
AAh
55h
30h
555h
AAAh
555h
555h
AAAh
555h
AAh
55h
80h
AAh
55h
10h
(3,7)
3+
4
6
Addr.
(3,7)
6
Addr.
(3,7)
Data
ES (10)
ER
Erase
Suspend
Erase
Resume
Read Memory Array until a new write cycle is initiated.
F0h
Data
CE
X
Data
Addr.
Auto Select
(3,7)
1
Addr. (3,7)
Data
1
Addr.
Data
X
B0h
(3,7)
X
30h
Read Memory Array until a new write
cycle is initiated.
Read Electronic Signature or Block
Protection Status until a new write cycle
is initiated. See Note 5 and 6.
Program
Address Read Data Polling or Toggle
Bit until Program completes.
Program
Data
Block
Additional
Address Block (8)
30h
Note 9
Read until Toggle stops, then read all the data needed from
any Block(s) not being erased then Resume Erase.
Read Data Polling or Toggle Bits until Erase completes or
Erase is suspended another time
Notes: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation (see Table 14 and Figure 9).
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
the command cycles.
5. Signature Address bits A0, A1 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1 at VIL will output
Device code.
6. Block Protection Address: A0 at VIL, A1 at VIH and A13-A17 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A12-A17 are don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry,
timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description).
When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
The instructions require from 1 to 6 cycles, the first
or first three of which are always write operations
used to initiate the instruction.They are followed by
either further write cycles to confirm the first command or execute the command immediately. Command sequencing must be followed exactly. Any
invalid combination of commands will reset the
device to Read Array. The increased number of
cycles has been chosen to assure maximum data
security. Instructions are initialised by two initial
Coded cycles which unlock the Command Interface. In addition, for Erase, instruction confirmation
is again preceded by the two Coded cycles.
8/29
Status Register Bits
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase command execution will automatically output these five
Status Register bits. The P/E.C. automatically sets
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables 9 and 10.
M29F002T, M29F002NT, M29F002B
Table 9. Status Register Bits
DQ
7
Name
Data
Polling
Logic Level
Toggle Bit
Erase Complete or erase
block in Erase Suspend
’0’
Erase On-going
DQ
Program Complete or data
of non erase block during
Erase Suspend
DQ
Program On-going
DQ
’-1-1-1-1-1-1-1-’
5
4
3
Error Bit
Erase or Program On-going
Program Complete
Erase Complete or Erase
Suspend on currently
addressed block
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
’1’
Program or Erase Error
’0’
Program or Erase On-going
’1’
Erase Timeout Period Expired
P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES).
’0’
Erase Timeout Period
On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
This bit is set to ’1’ in the case of
Programming or Erase failure.
Reserved
Erase
Time Bit
’-1-0-1-0-1-0-1-’
2
Note
’1’
’-1-0-1-0-1-0-1-’
6
Definition
Toggle Bit
1
DQ
1
Reserved
0
Reserved
Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
Erase Error due to the
currently addressed block
(when DQ5 = ’1’).
Indicates the erase status and allows to
identify the erased block
Program on-going, Erase
on-going on another block or
Erase Complete
Erase Suspend read on
non Erase Suspend block
Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After completion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. It must be performed at the address being programmed or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 will
be set to ’0’ for about 100µs, and then return to the
previous addressed memory data value.
9/29
M29F002T, M29F002NT, M29F002B
Table 10. Polling and Toggle Bits
Mode
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Note 1
Erase Suspend Read
(in Erase Suspend
block)
1
1
Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program
DQ7
Toggle
N/A
Program
Note: 1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
See Figure 11 for the Data Polling flowchart and
Figure 10 for the Data Polling waveforms. DQ7 will
also flag the Erase Suspend mode by switching
from ’0’ to ’1’ at the start of the Erase Suspend. In
order to monitor DQ7 in the Erase Suspend mode
an address within a block being erased must be
provided. For a Read Operationin Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
on a blockbeing erased and the datavalue on other
blocks. During Program operation in Erase Suspend Mode, DQ7 will have the same behaviour as
in the normal program execution outside of the
suspend mode.
Toggle Bit (DQ6). When Programming or Erasing
operations are in progress, successive attempts to
read DQ6 will output complementarydata. DQ6 will
toggle following toggling of either G, or E when G
is low. The operation is completed when two successive reads yield the same output data. The next
read will output the bit last programmed or a ’1’ after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are protected, DQ6 will toggle for about 100µs and then
return back to Read. DQ6 will be set to ’1’ if a Read
operationis attemptedon an Erase Suspendblock.
When erase is suspended DQ6 will toggle during
programming operations in a block different to the
block in Erase Suspend. Either E or G toggling will
cause DQ6 to toggle. See Figure 12 for Toggle Bit
flowchart and Figure 13 for Toggle Bit waveforms.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. It can also be used to
10/29
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to ’1’ during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to ’1’
during program operation and when erase is complete. After erase completion and if the error bit
DQ5 is set to ’1’, DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In caseof an error in block erase
or program, the block in which the error occured or
to which the programmed data belongs, must be
discarded. The DQ5 failure condition will also appear if a user tries to program a ’1’ to a location that
is previously programmed to ’0’. Other Blocks may
stillbe used.The error bit resets after a Read/Reset
(RD) instruction. In case of success of Program or
Erase, the error bit will be set to ’0’ .
Erase Timer Bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 50µs to 120µs, DQ3 returns
to ’1’.
Coded Cycles
The two Coded cycles unlock the Command Interface. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address 555h during the
first cycle. During the second cycle the Coded
cycles consist of writing the data 55h at address
AAAh. The address lines A0 to A11 are valid, other
address lines are ’don’t care’. The Coded cycles
happen on first and second cycles of the command
write or on the fourth and fifth cycles.
Instructions
See Table 8.
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It canbe optionallypreceded by the
two Coded cycles. Subsequentread operationswill
read the memory array addressed and output the
data read. A wait state of 10µs is necessary after
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instruction is
given.
M29F002T, M29F002NT, M29F002B
Table 11. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
≤ 10ns
≤ 10ns
Input Pulse Voltages
0 to 3V
0.45V to 2.4V
1.5V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 4. AC Testing Input Output Waveform
Figure 5. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
Standard
2.4V
OUT
CL
2.0V
0.8V
0.45V
CL = 30pF for High Speed
CL = 100pF for Standard
AI01275B
CL includes JIG capacitance
AI01276B
Table 12. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
C IN
C OUT
Parameter
Test Condition
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Input Capacitance
Output Capacitance
Min
Note: 1. Sampled only, not 100% tested.
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 555h for
command set-up. Asubsequentread will output the
manufacturer code and the device code or the
block protection status depending on the levels of
A0 and A1. The manufacturer code, 20h, is output
when the addresses lines A0 and A1 are Low, the
device code is output when A0 is High with A1 Low.
The AS instruction also allows access to the block
protectionstatus. After givingthe AS instruction, A0
is set to VIL with A1 at VIH, while A13-A17 define
the address of the block to be verified. A read in
these conditions will output a 01h if the block is
protected and a 00h if the block is not protected.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0h is
written to address 555h on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W or E and the Data
to be written on the rising edge and starts the
P/E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing ’0’ in place of
’1’. Status bits DQ6 and DQ7 determine if programming is on-goingand DQ5 allows verification of any
possible error. Programming at an address not in
blocks being erased is also possible during erase
suspend. In this case, DQ2 will toggle at the address being programmed.
11/29
M29F002T, M29F002NT, M29F002B
Table 13. DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 5V ± 10%)
Symbol
ILI
(2)
Parameter
Test Condition
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
±1
µA
–10
µA
E = VIL, G = VIH, f = 6MHz
20
mA
E = VIH
1
mA
E = VCC ± 0.2V
100
µA
Byte program, Block or
Chip Erase in progress
20
mA
Input Leakage Current
ILO
Output Leakage Current
ILR1
RPNC Leakage Current High
RPNC = VCC
ILR2
RPNC Leakage Current Low
RPNC = VSS
ICC1
Supply Current (Read) TTL Byte
ICC2
Supply Current (Standby) TTL
ICC3
Supply Current (Standby) CMOS
ICC4 (1)
Supply Current (Program or Erase)
Min
–0.2
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2
VCC + 0.5
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage TTL
IOH = –2.5mA
2.4
V
Output High Voltage CMOS
IOH = –100µA
VCC –0.4V
V
VID
A9, E, G, RPNC High Voltage
IID
A9, E, G, RPNC High Current
VLKO
IOL = 5.8mA
11.5
A9, E, G or RPNC = VID
Supply Voltage (Erase and
Program lock-out)
3.2
12.5
V
100
µA
4.2
V
Note: 1. Sampled only, not 100% tested.
2. Except RPNC.
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 555h on
third cycle after the two Coded cycles. The Block
Erase Confirm command 30h is similarly written on
the sixth cycle after another two Coded cycles.
During the input of the second command an address within the block to be erased is given and
latched into the memory. Additional block Erase
Confirm commands and block addresses can be
written subsequently to erase other blocks in parallel, without further Coded cycles. The erase will
start after the erase timeout period (see Erase
Timer Bit DQ3 description). Thus, additional Erase
Confirm commands for other blocks must be given
within this delay. The input of a new Erase Confirm
command will restart thetimeout period. The status
of the internal timer can be monitored through the
level of DQ3, if DQ3 is ’0’ the Block Erase Command has been given and the timeout is running,if
DQ3 is ’1’, the timeout has expired and the P/E.C.
12/29
is erasing the Block(s). If the second command
given is not an erase confirm or if the Coded cycles
are wrong, the instruction aborts, and the device is
reset to Read Array. It is not necessary to program
the block with 00h as the P/E.C. will do this automatically before to erasingto FFh. Read operations
after the sixth rising edge of W or E output the
status register status bits.
During the executionof the erase by the P/E.C.,the
memory accepts only the Erase Suspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
Status Register bit DQ5 returns’1’ if there has been
an erase failure. In such a situation, the Toggle bit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/Reset RD instruction is necessary in order to
reset the P/E.C.
M29F002T, M29F002NT, M29F002B
Table 14. Read AC Characteristics
(TA = 0 to 70°C or –40 to 85°C)
M29F002T / M29F002NT / M29F002B
-70
Symbol
Alt
Parameter
Test Condition
-90
VCC = 5V ± 10% VCC = 5V ± 10% VCC = 5V ± 10%
Standard
Interface
Min
tAVAV
tRC
Address Valid to
Next Address Valid
E = VIL, G = VIL
tAVQV
tACC
Address Valid to
Output Valid
E = VIL, G = VIL
tELQX (1)
tLZ
Chip Enable Low to
Output Transition
G = VIL
tELQV (2)
tCE
Chip Enable Low to
Output Valid
G = VIL
(1)
tOLZ
Output Enable Low
to Output Transition
E = VIL
tGLQV (2)
tOE
Output Enable Low
to Output Valid
E = VIL
tEHQX
tOH
Chip Enable High to
Output Transition
G = VIL
tEHQZ (1)
tHZ
Chip Enable High to
Output Hi-Z
G = VIL
tGHQX
tOH
Output Enable High
to Output Transition
E = VIL
tGHQZ (1)
tDF
Output Enable High
to Output Hi-Z
E = VIL
tAXQX
tOH
Address Transition
to Output Transition
E = VIL, G = VIL
tGLQX
tPLEL (1,3) tREADY
-120
Max
70
Standard
Interface
Min
90
70
0
0
0
0
0
0
20
0
0
0
10
ns
ns
30
0
10
ns
ns
30
20
ns
ns
50
20
ns
ns
120
35
20
ns
120
90
30
Max
0
0
0
Min
120
0
0
Standard
Interface
90
70
RPNC Low to Read
Mode
Max
Unit
ns
ns
10
µs
tPHEL
tRSP
RPNC High to Chip
Enable Low
50
50
50
ns
tPLPX
tRP
RPNC Pulse Width
500
500
500
ns
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
3. To be considered only if the Reset pulse is given while the memory is in Erase mode.
13/29
14/29
Note: Write Enable (W) = High
DQ0-DQ7
G
E
A0-A17
ADDRESS VALID
AND CHIP ENABLE
tAVQV
tGLQV
OUTPUT ENABLE
tGLQX
tELQX
tELQV
VALID
tAVAV
DATA VALID
VALID
tGHQZ
tGHQX
tEHQX
tEHQZ
tAXQX
AI02082
M29F002T, M29F002NT, M29F002B
Figure 6. Read Mode AC Waveforms
M29F002T, M29F002NT, M29F002B
Table 15. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C or –40 to 85°C)
M29F002T / M29F002NT / M29F002B
-70
Symbol
Alt
Parameter
-90
-120
VCC = 5V ± 10% VCC = 5V ± 10% VCC = 5V ± 10%
Standard
Interface
Min
Max
Standard
Interface
Min
Max
Unit
Standard
Interface
Min
Max
tAVAV
tWC
Address Valid to Next Address
Valid
70
90
120
ns
tELWL
tCS
Chip Enable Low to Write Enable
Low
0
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable
High
35
45
50
ns
tDVWH
tDS
Input Valid to Write Enable High
30
45
50
ns
tWHDX
tDH
Write Enable High to Input
Transition
0
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable
High
0
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable
Low
20
20
20
ns
tAVWL
tAS
Address Valid to Write Enable Low
5
5
5
ns
tWLAX
tAH
Write Enable Low to Address
Transition
45
45
50
ns
Output Enable High to Write
Enable Low
0
0
0
ns
tGHWL
tVCHEL
tVCS
VCC High to Chip Enable Low
50
50
50
µs
tWHGL
tOEH
Write Enable High to Output
Enable Low
0
0
0
ns
tPHPHH (1,2)
tVIDR
RPNC Rise Time to VID
500
500
500
ns
tPLPX
tRP
RPNC Pulse Width
500
500
500
ns
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
ChipErase (CE) Instruction. This instructionuses
six write cycles. The Erase Set-up command 80h
is written to address 555h on the third cycle after
the two Coded cycles. The Chip Erase Confirm
command 10h is similarly written on the sixth cycle
after another two Coded cycles. If the second
command given is not an erase confirm or if the
Coded cycles are wrong, the instruction aborts and
the device is reset to Read Array. It is not necessary
to program the array with 00h first as the P/E.C. will
automaticallydo this before erasing it to FFh. Read
operations after the sixth rising edge of W or E
output the Status Register bits. During the executionof theerase by the P/E.C.,Data Polling bit DQ7
returns ’0’, then ’1’ on completion. The Toggle bits
DQ2 and DQ6 toggle during erase operation and
stop when erase is completed. After completionthe
Status Register bit DQ5 returns’1’ if there has been
an Erase Failure.
15/29
M29F002T, M29F002NT, M29F002B
Figure 7. Write AC Waveforms, W Controlled
tAVAV
A0-A17
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7
tWHDX
VALID
VCC
tVCHEL
AI02083
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
Erase Suspend (ES) Instruction. The Block
Erase operation may be suspended by this instruction which consists of writing the command B0h
without any specific address. No Coded cycles are
required. It permits reading of data from another
block and programming in another block while an
erase operation is in progress. Erase suspend is
accepted only during the Block Erase instruction
execution. Writing this command during Erase
timeout will, in addition to suspending the erase,
terminate the timeout. The Toggle bit DQ6 stops
togglingwhen the P/E.C. is suspended.The Toggle
bits will stop toggling between 0.1µs and 15µs after
the Erase Suspend (ES) command has been written. The device will then automatically be set to
Read Memory Array mode. When erase is suspended, a Read from blocks being erased will
output DQ2 toggling and DQ6 at ’1’. A Read from
a block not being erased returns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instructions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in both DQ2 and DQ6 toggling
when the data is beingprogrammed. ARead/Reset
16/29
command will definitively abort erasure and result
in invalid data in the blocks being erased.
Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
Coded cycles.
POWER SUPPLY
Power Up
The memory Command Interface is reset on power
up to Read Array. Either E or W must be tied to VIH
during Power Up to allow maximum security and
the possibility to write a command on the first rising
edge of E and W. Any write cycle initiation is
blocked when Vcc is below VLKO.
Supply Rails
Normal precautions must be taken for supply voltage decoupling; each device in a system should
have the VCC rail decoupledwith a 0.1µF capacitor
close to the VCC and VSS pins. The PCB trace
widths should be sufficient to carry the VCC program and erase currents required.
M29F002T, M29F002NT, M29F002B
Table 16. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C or –40 to 85°C)
M29F002T / M29F002NT / M29F002B
Symbol
Alt
Parameter
-70
-90
-120
VCC = 5V ± 10%
VCC = 5V ± 10%
VCC = 5V ± 10%
Standard
Interface
Standard
Interface
Standard
Interface
Min
Max
Min
Max
Min
Unit
Max
tAVAV
tWC
Address Valid to Next Address
Valid
70
90
120
ns
tWLEL
tWS
Write Enable Low to Chip
Enable Low
0
0
0
ns
tELEH
tCP
Chip Enable Low to Chip
Enable High
35
45
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
30
45
50
ns
tEHDX
tDH
Chip Enable High to Input
Transition
5
5
5
ns
tEHWH
tWH
Chip Enable High to Write
Enable High
0
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip
Enable Low
20
20
20
ns
tAVEL
tAS
Address Valid to Chip Enable
Low
0
0
0
ns
tELAX
tAH
Chip Enable Low to Address
Transition
45
45
50
ns
Output Enable High Chip
Enable Low
0
0
0
ns
tGHEL
tVCHWL
tVCS
VCC High to Write Enable Low
50
50
50
µs
tEHGL
tOEH
Chip Enable High to Output
Enable Low
0
0
0
ns
tPHPHH (1,2)
tVIDR
RPNC Rise TIme to VID
500
500
500
ns
tPLPX
tRP
RPNC Pulse Width
500
500
500
ns
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
17/29
M29F002T, M29F002NT, M29F002B
Figure 8. Write AC Waveforms, E Controlled
tAVAV
A0-A17
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7
tEHDX
VALID
VCC
tVCHWL
AI02084
Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.
Figure 9. Read and Write AC Characteristics, RP Related
E
tPHEL
RPNC
tPLPX
tPHPHH
tPLEL
AI02085
18/29
M29F002T, M29F002NT, M29F002B
Table 17. Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C or –40 to 85°C)
M29F002T / M29F002NT / M29F002B
Symbol
tWHQ7V
tEHQ7V
tQ7VQV
tWHQV
tEHQV
Alt
Parameter
-70
-90
-120
VCC = 5V ± 10%
VCC = 5V ± 10%
VCC = 5V ± 10%
Standard
Interface
Standard
Interface
Standard
Interface
Unit
Min
Max
Min
Max
Min
Max
Write Enable High to DQ7 Valid
(Program, W Controlled)
10
2400
10
2400
10
2400
µs
Write Enable High to DQ7 Valid
(Chip Erase, W Controlled)
1.0
30
1.0
30
1.0
30
sec
Chip Enable High to DQ7 Valid
(Program, E Controlled)
10
2400
10
2400
10
2400
µs
Chip Enable High to DQ7 Valid
(Chip Erase, E Controlled)
1.0
30
1.0
30
1.0
30
sec
50
ns
Q7 Valid to Output Valid (Data
Polling)
30
35
Write Enable High to Output
Valid (Program)
10
2400
10
2400
10
2400
µs
Write Enable High to Output
Valid (Chip Erase)
1.0
30
1.0
30
1.0
30
sec
Chip Enable High to Output
Valid (Program)
10
2400
10
2400
10
2400
µs
Chip Enable High to Output
Valid (Chip Erase)
1.0
30
1.0
30
1.0
30
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
19/29
20/29
DQ0-DQ6
DQ7
W
G
E
A0-A17
LAST WRITE
CYCLE OF
PROGRAM
OR ERASE
INSTRUCTION
DATA POLLING
READ CYCLES
tWHQ7V
tEHQ7V
tELQV
tAVQV
tQ7VQV
IGNORE
DQ7
DATA POLLING (LAST) CYCLE
tGLQV
ADDRESS (WITHIN BLOCKS)
VALID
VALID
DATA OUTPUT VALID
AI02086
MEMORY
ARRAY
READ CYCLE
M29F002T, M29F002NT, M29F002B
Figure 10. Data Polling DQ7 AC Waveforms
M29F002T, M29F002NT, M29F002B
Figure 11. Data Polling Flowchart
Figure 12. Data Toggle Flowchart
START
START
READ
DQ2, DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
NO
NO
YES
NO
DQ5
=1
DQ5
=1
YES
YES
READ DQ2, DQ6
READ DQ7
DQ7
=
DATA
NO
DQ2, DQ6
=
TOGGLE
YES
YES
DQ2, DQ6
=
TOGGLE
NO
FAIL
NO
YES
PASS
FAIL
PASS
AI01369
AI01873
Table 18. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C)
M29F002T / M29F002NT / M29F002B
Parameter
Unit
Typ
Typical after
100k W/E Cycles
Chip Erase (Preprogrammed)
0.7
0.9
sec
Chip Erase
2.4
2.5
sec
Boot Block Erase
0.6
sec
Parameter Block Erase
0.5
sec
Main Block (32Kb) Erase
0.9
sec
Main Block (64Kb) Erase
1.0
sec
Chip Program (Byte)
3.2
3.2
sec
Byte Program
11
11
µs
Min
Program/Erase Cycles (per Block)
100,000
cycles
21/29
22/29
DATA
TOGGLE
READ CYCLE
Note: All other timings are as a normal Read cycle.
LAST WRITE
CYCLE OF
PROGRAM
OF ERASE
INSTRUCTION
DQ0-DQ1,DQ3-DQ5,DQ7
DQ6,DQ2
W
G
E
A0-A17
DATA TOGGLE
READ CYCLE
IGNORE
STOP TOGGLE
tWHQV
tEHQV
tAVQV
MEMORY ARRAY
READ CYCLE
VALID
VALID
tGLQV
tELQV
VALID
AI02087
M29F002T, M29F002NT, M29F002B
Figure 13. Data Toggle DQ6, DQ2 AC Waveforms
M29F002T, M29F002NT, M29F002B
Figure 14. Block Protection Flowchart
START
BLOCK ADDRESS
on A13-A17
W = VIH
Set-up
n=0
G, A9 = VID,
E = VIL
Wait 4µs
W = VIL
Protect
Wait 100µs
W = VIH
E, G = VIH
Verify
VERIFY BLOCK PROTECTION
A0, A6 = VIL; A1 = VIH; A9 = VID
A13-A17 IDENTIFY BLOCK
E = VIL
Wait 4µs
G = VIL
Wait 60ns
VERIFY BLOCK
PROTECT STATUS
DATA
=
01h
NO
YES
A9 = VIH
++n
= 25
NO
PASS
YES
A9 = VIH
FAIL
AI02088B
23/29
M29F002T, M29F002NT, M29F002B
Figure 15. All Blocks Unprotecting Flowchart
START
PROTECT
ALL BLOCKS
n=0
Set-up
W = VIH
E, G, A9 = VID
A12, A15 = VIH
Wait 4µs
W = VIL
Unprotect
Wait 10ms
W = VIH
Verify
E, G = VIH
E, A0 = VIL; A1, A6 = VIH; A9 = VID
A13-A17 IDENTIFY BLOCK
NEXT
BLOCK
Wait 4µs
G = VIL
Wait 60ns
VERIFY BLOCK
PROTECT STATUS
NO
NO
++n
= 1000
YES
DATA
=
00h
YES
LAST
BLK.
NO
YES
A9 = VIH
A9 = VIH
FAIL
PASS
AI02089C
24/29
M29F002T, M29F002NT, M29F002B
ORDERING INFORMATION SCHEME
Example:
M29F002T
-70
X
K
1
TR
Option
Operating Voltage
F
TR Tape & Reel
Packing
5V
Array Matrix
T
B
NT
Top Boot
Speed
-70 70ns
Bottom Boot
-90 90ns
Top Boot
without
RPNC function
-120 120ns
Package
Power Supplies
blank VCC ± 10%
X
VCC ± 5%
Temp. Range
P
PDIP32
1
0 to 70 °C
K
PLCC32
6
–40 to 85 °C
N
TSOP32
(8 x 20 mm)
Devices are shipped from the factory with the memory content erased (to FFh).
For a list of available options (Speed, Package, etc...) or for further informationon any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
25/29
M29F002T, M29F002NT, M29F002B
PDIP32 - 32 pin Plastic DIP, 600 mils width
mm
Symb
Typ
inches
Min
Max
A
–
A1
Min
Max
5.08
–
0.200
0.38
–
0.015
–
A2
3.56
4.06
0.140
0.160
B
0.38
0.51
0.015
0.020
–
–
–
–
0.20
0.30
0.008
0.012
B1
1.52
C
D
Typ
0.060
41.78
42.04
1.645
1.655
D2
38.10
–
–
1.500
–
–
E
15.24
–
–
0.600
–
–
13.59
13.84
0.535
0.545
E1
e1
2.54
–
–
0.100
–
–
eA
15.24
–
–
0.600
–
–
eB
15.24
17.78
0.600
0.700
L
3.18
3.43
0.125
0.135
S
1.78
2.03
0.070
0.080
α
0°
10°
0°
10°
N
32
32
A2
A1
B1
B
A
L
e1
α
eA
D2
C
eB
D
S
N
E1
E
1
PDIP
Drawing is not to scale.
26/29
M29F002T, M29F002NT, M29F002B
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Symb
Typ
inches
Min
Max
A
2.54
A1
Min
Max
3.56
0.100
0.140
1.52
2.41
0.060
0.095
A2
–
0.38
–
0.015
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
–
–
–
–
0.00
0.25
0.000
0.010
–
–
–
–
e
1.27
F
R
0.89
Typ
0.050
0.035
N
32
32
Nd
7
7
Ne
9
9
CP
0.10
0.004
D
D1
A1
A2
1 N
B1
E1 E
Ne
e
D2/E2
F
B
0.51 (.020)
1.14 (.045)
A
Nd
R
CP
PLCC
Drawing is not to scale.
27/29
M29F002T, M29F002NT, M29F002B
TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
1.20
0.047
A1
0.05
0.15
0.002
0.007
A2
0.95
1.05
0.037
0.041
B
0.15
0.27
0.006
0.011
C
0.10
0.21
0.004
0.008
D
19.80
20.20
0.780
0.795
D1
18.30
18.50
0.720
0.728
E
7.90
8.10
0.311
0.319
-
-
-
-
L
0.50
0.70
0.020
0.028
α
0°
5°
0°
5°
N
32
e
0.50
0.020
32
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
Drawing is not to scale.
28/29
Max
A1
α
L
M29F002T, M29F002NT, M29F002B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
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29/29
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