AD AD629AR-REEL High common-mode voltage difference amplifier Datasheet

a
High Common-Mode Voltage
Difference Amplifier
AD629
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Improved Replacement for:
INA117P and INA117KU
ⴞ270 V Common-Mode Voltage Range
Input Protection to:
ⴞ500 V Common Mode
ⴞ500 V Differential
Wide Power Supply Range (ⴞ2.5 V to ⴞ18 V)
ⴞ10 V Output Swing on ⴞ12 V Supply
1 mA Max Power Supply Current
8-Lead Plastic Mini-DIP (N) and SOIC (R) Packages
21.1k⍀
380k⍀
REF(–) 1
8
NC
7
+VS
6
OUTPUT
5
REF(+)
380k⍀
–IN 2
+IN 3
380k⍀
20k⍀
–VS 4
AD629
NC = NO CONNECT
HIGH ACCURACY DC PERFORMANCE
3 ppm Max Gain Nonlinearity
20 ␮V/ⴗC Max Offset Drift (AD629A)
10 ␮V/ⴗC Max Offset Drift (AD629B)
10 ppm/ⴗC Max Gain Drift
GENERAL DESCRIPTION
The AD629 is a difference amplifier with a very high input
common-mode voltage range. It is a precision device that
allows the user to accurately measure differential signals in the
presence of high common-mode voltages up to ± 270 V.
EXCELLENT AC SPECIFICATIONS
77 dB Min CMRR @ 500 Hz (AD629A)
86 dB Min CMRR @ 500 Hz (AD629B)
500 kHz Bandwidth
The AD629 can replace costly isolation amplifiers in applications
that do not require galvanic isolation. The device will operate
over a ± 270 V common-mode voltage range and has inputs
that are protected from common-mode or differential mode
transients up to ± 500 V.
APPLICATIONS
High Voltage Current Sensing
Battery Cell Voltage Monitor
Power Supply Current Monitor
Motor Control
Isolation
The AD629 has low offset, low offset drift, low gain error drift,
as well as low common-mode rejection drift, and excellent CMRR
over a wide frequency range.
The AD629 is available in low-cost, plastic 8-lead DIP and
SOIC packages. For all packages and grades, performance is
guaranteed over the entire industrial temperature range from
–40°C to +85°C.
2mV/DIV
95
90
OUTPUT ERROR – 2mV/DIV
COMMON-MODE REJECTION RATIO – dB
100
85
80
75
70
65
60
60V/DIV
55
50
20
100
1k
FREQUENCY – Hz
10k
20k
Figure 1. Common-Mode Rejection Ratio vs. Frequency
–240
–120
0
120
COMMON-MODE VOLTAGE – Volts
240
Figure 2. Common-Mode Operating Range. Error Voltage
vs. Input Common-Mode Voltage
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD629–SPECIFICATIONS (T = 25ⴗC, V = ⴞ15 V unless otherwise noted)
A
S
AD629A
Parameter
Condition
GAIN
Nominal Gain
Gain Error
Gain Nonlinearity
VOUT = ± 10 V, RL = 2 kΩ
Gain vs. Temperature
Min
RL = 10 kΩ
TA = TMIN to TMAX
INPUT
Common-Mode Rejection Ratio
Operating Voltage Range
Input Operating Impedance
OUTPUT
Operating Voltage Range
Output Short Circuit Current
Capacitive Load
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
Slew Rate
Full Power Bandwidth
Settling Time
VS = ± 5 V
TA = TMIN to TMAX
VS = ± 5 V to ± 15 V
84
VCM = ± 250 V dc
TA = TMIN to TMAX
VCM = 500 V p-p DC to 500 Hz
VCM = 500 V p-p DC to 1 kHz
Common-Mode
Differential
Common-Mode
Differential
77
73
77
RL = 10 kΩ
RL = 2 kΩ
VS = ± 12 V, RL = 2 kΩ
± 13
± 12.5
± 10
Stable Operation
1000
TEMPERATURE RANGE
For Specified Performance
Max
Min
Max
Unit
10
1
0.01
4
1
3
0.03
10
3
10
V/V
%
ppm
ppm
ppm/°C
0.2
1
0.1
6
100
20
0.05
10
90
88
86
82
86
88
VOUT = 20 V p-p
0.01%, VOUT = 10 V Step
0.1%, VOUT = 10 V Step
0.01%, VCM = 10 V Step, VDIFF = 0 V
96
± 270
± 13
200
800
± 13
± 12.5
± 10
± 25
500
2.1
28
15
12
5
1.7
± 2.5
0.9
1.2
–40
± 18
1
± 2.5
+85
–40
mV
mV
µV/°C
dB
dB
dB
dB
dB
V
V
kΩ
kΩ
V
V
V
mA
pF
± 25
1000
15
550
VOUT = 0 V
TMIN to TMAX
0.5
1
10
90
200
800
1.7
TA = TMIN to TMAX
3
110
± 270
± 13
OUTPUT NOISE VOLTAGE
0.01 Hz to 10 Hz
Spectral Density, ≥100 Hz1
POWER SUPPLY
Operating Voltage Range
Quiescent Current
AD629B
Typ
1
0.01
4
1
3
OFFSET VOLTAGE
Offset Voltage
vs. Temperature
vs. Supply (PSRR)
Typ
500
2.1
28
15
12
5
kHz
V/µs
kHz
µs
µs
µs
15
550
µV p-p
nV/√Hz
0.9
1.2
± 18
1
V
mA
mA
+85
°C
NOTES
1
See Figure 19.
Specifications subject to change without notice.
–2–
REV. A
AD629
ABSOLUTE MAXIMUM RATINGS 1
THEORY OF OPERATION
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
DIP (N) . . . . . . . . . . . . . . . . . . . . . . . . See Derating Curves
SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . See Derating Curves
Input Voltage Range, Continuous . . . . . . . . . . . . . . . . ± 300 V
Common-Mode and Differential, 10 sec . . . . . . . . . . . ± 500 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Pin 1, Pin 5 . . . . . . . . . . . . . . . . . . –VS – 0.3 V to +VS + 0.3 V
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
The AD629 is a unity gain differential-to-single-ended amplifier
(Diff Amp) that can reject extremely high common-mode
signals (in excess of 270 V with 15 V supplies). It consists of an
operational amplifier (Op Amp) and a resistor network.
In order to achieve high common-mode voltage range, an internal
resistor divider (Pin 3, Pin 5) attenuates the noninverting signal
by a factor of 20. Other internal resistors (Pin 1, Pin 2, and the
feedback resistor) restores the gain to provide a differential gain
of unity. The complete transfer function equals:
VOUT = V (+IN ) – V (–IN )
Laser wafer trimming provides resistor matching so that commonmode signals are rejected while differential input signals are
amplified.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
2
Specification is for device in free air: 8-Lead Plastic DIP, θJA = 100°C/W; 8-Lead
SOIC Package, θJA = 155°C/W.
The op amp itself, in order to reduce output drift, uses super
beta transistors in its input stage The input offset current and
its associated temperature coefficient contribute no appreciable
output voltage offset or drift. This has the added benefit of
reducing voltage noise because the corner where 1/f noise becomes
dominant is below 5 Hz. In order to reduce the dependence of
gain accuracy on the op amp, the open-loop voltage gain of the
op amp exceeds 20 million, and the PSRR exceeds 140 dB.
MAXIMUM POWER DISSIPATION – Watts
2.0
TJ = 150ⴗC
8-LEAD MINI-DIP PACKAGE
1.5
21.1k⍀
380k⍀
REF(–) 1
8
NC
7
+VS
6
OUTPUT
5
REF(+)
380k⍀
–IN
1.0
2
+IN 3
380k⍀
20k⍀
8-LEAD SOIC PACKAGE
–VS 4
0.5
AD629
NC = NO CONNECT
Figure 4. Functional Block Diagram
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60
AMBIENT TEMPERATURE – ⴗC
70
80
90
Figure 3. Derating Curve of Maximum Power Dissipation
vs. Temperature for SOIC and PDIP Packages
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD629AR
AD629AR-REEL1
AD629AR-REEL72
AD629BR
AD629BR-REEL1
AD629BR-REEL72
AD629AN
AD629BN
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic DIP
SO-8
SO-8
SO-8
SO-8
SO-8
SO-8
N-8
N-8
NOTES
1
13" Tape and Reel of 2500 each
2
7" Tape and Reel of 1000 each
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD629 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
AD629 –Typical Performance Characteristics (@25ⴗC, V = ⴞ15 V unless otherwise noted)
S
400
360
90
COMMON-MODE VOLTAGE – ⴞVolts
COMMON-MODE REJECTION RATIO – dB
100
80
70
60
50
40
30
20
TA = +25ⴗC
320
280
TA = +85ⴗC
240
TA = –40ⴗC
200
160
120
80
40
10
0
0
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
20
VS = ⴞ18V
OUTPUT ERROR – 2mV/DIV
OUTPUT ERROR – 2mV/DIV
18
RL = 2k⍀
VS = ⴞ15V
VS = ⴞ12V
VS = ⴞ10V
–12
4
6
8
10
12
14
16
POWER SUPPLY VOLTAGE – ⴞVolts
RL = 10k⍀
VS = ⴞ18V
–20 –16
2
Figure 8. Common-Mode Operating Range vs. Power
Supply Voltage
Figure 5. Common-Mode Rejection Ratio vs. Frequency
2mV/DIV
0
–8
VS = ⴞ15V
VS = ⴞ12V
VS = ⴞ10V
4V/DIV
–4
0
4
VOUT – Volts
8
12
16
–20 –16
20
Figure 6. Typical Gain Error Normalized @ VOUT = 0 V and
Output Voltage Operating Range vs. Supply Voltage,
RL = 10 kΩ (Curves Offset for Clarity)
–12
–8
–4
0
4
VOUT – Volts
4V/DIV
8
12
16
20
Figure 9. Typical Gain Error Normalized @ VOUT = 0 V and
Output Voltage Operating Range vs. Supply Voltage,
RL = 2 kΩ (Curves Offset for Clarity)
RL = 1k⍀
VS = ⴞ5V, RL = 10k⍀
OUTPUT ERROR – 2mV/DIV
OUTPUT ERROR – 2mV/DIV
VS = ⴞ18V
VS = ⴞ15V
VS = ⴞ12V
VS = ⴞ10V
–20 –16
–12
–8
–4
0
4
VOUT – Volts
VS = ⴞ5V, RL = 2k⍀
VS = ⴞ5V, RL = 1k⍀
VS = ⴞ2.5V, RL = 1k⍀
4V/DIV
8
12
16
–5
20
Figure 7. Typical Gain Error Normalized @ VOUT = 0 V
and Output Voltage Operating Range vs. Supply Voltage,
RL = 1 kΩ (Curves Offset for Clarity)
–4
–3
–2
–1
0
1
VOUT – Volts
1V/DIV
2
3
4
5
Figure 10. Typical Gain Error Normalized @ VOUT = 0 V
and Output Voltage Operating Range vs. Supply Voltage
(Curves Offset for Clarity)
–4–
REV. A
ERROR – 2ppm/DIV
ERROR – 0.8ppm/DIV
AD629
–10
–5
0
VOUT – Volts
5
10
–10
Figure 11. Gain Nonlinearity; VS = ± 15 V, RL =10 kΩ
–8
–6
–4
–2
0
2
VOUT – Volts
4
6
8
10
Figure 14. Gain Nonlinearity; VS = ± 15 V, RL = 2 kΩ
14.0
13.0
–40ⴗC
–40ⴗC
ERROR – 1ppm/DIV
OUTPUT VOLTAGE – Volts
12.0
VS = ⴞ15V
11.0
+85ⴗC
+25ⴗC
10.0
9.0
–11.5
–12.0
–12.5
–40ⴗC
+25ⴗC
–13.0
+85ⴗC
–10
–8
–6
–4
–2
0
2
VOUT – Volts
4
6
8
–13.5
10
Figure 12. Gain Nonlinearity; VS = ± 12 V, RL =10 kΩ
0
2
4
6
8
10
12
14
OUTPUT CURRENT – mA
16
18
20
Figure 15. Output Voltage Operating Range vs. Output
Current; VS = ± 15 V
11.5
+85ⴗC
10.5
–40ⴗC
–40ⴗC
ERROR – 6.67ppm/DIV
OUTPUT VOLTAGE – Volts
9.5
+25ⴗC
8.5
VS = ⴞ12V
7.5
+85ⴗC
6.5
–9.0
–9.5
–40ⴗC
–10.0
+25ⴗC
–10.5
–3.0 –2.4 –1.8 –1.2
–0.6
0
0.6
VOUT – Volts
1.2
1.8
2.4
–11.0
3.0
0
2
4
6
8
10
12
14
OUTPUT CURRENT – mA
16
18
20
Figure 16. Output Voltage Operating Range vs. Output
Current; VS = ± 12 V
Figure 13. Gain Nonlinearity; VS = ± 5 V, RL =1 kΩ
REV. A
+85ⴗC
–5–
AD629
+85ⴗC
4.5
–40ⴗC
3.5
RL = 2k⍀
CL = 0pF
–40ⴗC
OUTPUT VOLTAGE – Volts
2.5
+85ⴗC
1.5
VS = ⴞ5V
0.5
+25ⴗC
+85ⴗC
–2.0
–2.5
–40ⴗC
–3.0
+25ⴗC
–3.5
+25ⴗC
–4.0
0
2
25mV/DIV
+85ⴗC
4
6
8
10
12
14
OUTPUT CURRENT – mA
16
18
20
Figure 20. Small Signal Pulse Response; G = 1, RL = 2 kΩ
Figure 17. Output Voltage Operating Range vs. Output
Current; VS = ± 5 V
POWER SUPPLY REJECTION RATIO – dB
120
4␮s/DIV
+VS
110
RL = 2k⍀
CL = 1000pF
–VS
100
90
80
70
60
50
40
30
25mV/DIV
0.1
1
10
100
FREQUENCY – Hz
1k
4␮s/DIV
10k
Figure 18. Power Supply Rejection Ratio vs. Frequency
Figure 21. Small Signal Pulse Response; G = 1, RL = 2 kΩ,
CL = 1000 pF
5.0
4.5
G = +1
RL = 2k⍀
CL = 1000pF
4.0
␮V/ Hz
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5V/DIV
0.01
0.1
1
10
100
FREQUENCY – Hz
1k
10k
5␮s/DIV
100k
Figure 22. Large Signal Pulse Response; G = 1,
RL = 2 kΩ, CL = 1000 pF
Figure 19. Voltage Noise Spectral Density vs. Frequency
–6–
REV. A
AD629
5V/DIV
5V/DIV
+10V
0V
VOUT
VOUT
0V
–10V
1mV = 0.01%
OUTPUT
ERROR
OUTPUT
ERROR
Figure 26. Settling Time to 0.01% for 0 V to –10 V Output
Step; G = –1, RL = 2 kΩ
Figure 23. Settling Time to 0.01%, For 0 V to 10 V Output
Step; G = –1, RL = 2 kΩ
300
350
N = 2180
n ⬇ 200 PCS. FROM
10 ASSEMBLY LOTS
N = 2180
n ⬇ 200 PCS. FROM
10 ASSEMBLY LOTS
250
250
NUMBER OF UNITS
NUMBER OF UNITS
300
10␮s/DIV
1mV/DIV
10␮s/DIV
1mV/DIV
1mV = 0.01%
200
150
200
150
100
100
50
50
0
–150
0
–100
–50
0
50
100
COMMON-MODE REJECTION RATIO – ppm
150
N = 2180
n ⬇ 200 PCS. FROM
10 ASSEMBLY LOTS
350
NUMBER OF UNITS
NUMBER OF UNITS
600
900
N = 2180
n ⬇ 200 PCS. FROM
10 ASSEMBLY LOTS
300
300
250
200
150
250
200
150
100
100
50
50
–400
–200
0
200
–1 GAIN ERROR – ppm
400
0
–600
600
–400
–200
0
200
+1 GAIN ERROR – ppm
400
600
Figure 28. Typical Distribution of +1 Gain Error;
Package Option N-8
Figure 25. Typical Distribution of –1 Gain Error;
Package Option N-8
REV. A
–300
0
300
OFFSET VOLTAGE – ␮V
400
400
0
–600
–600
Figure 27. Typical Distribution of Offset Voltage;
Package Option N-8
Figure 24. Typical Distribution of Common-Mode
Rejection; Package Option N-8
350
–900
–7–
AD629
APPLICATIONS
Basic Connections
1
Figure 29 shows the basic connections for operating the AD629
with a dual supply. A supply voltage of between ± 3 V and
± 18 V is applied between Pins 7 and 4. Both supplies should be
decoupled close to the pins using 0.1 µF capacitors. 10 µF electrolytic capacitors, also located close to the supply pins, may
also be required if low frequency noise is present on the power
supply. While multiple amplifiers can be decoupled by a single
set of 10 µF capacitors, each in amp should have its own set of
0.1 µF capacitors so that the decoupling point can be located
physically close to the power pins.
REF(–)
1
–IN
ISHUNT
RSHUNT
+IN
–VS
(SEE
TEXT)
8
NC
380k⍀ 380k⍀
2
7
+VS
380k⍀
3
20k⍀
(SEE
TEXT)
VOUT = ISHUNT ⴛ RSHUNT
6
4
0.1␮F
ISHUNT
RSHUNT
8
380k⍀ 380k⍀
2
7
VX
+IN
–VS
NC
+VS
0.1␮F
380k⍀
3
6
VY
20k⍀
4
REF(+)
5
OUTPUT = VOUT –VREF
NC = NO CONNECT
VREF
Figure 30. Operation with a Single Supply
+VS
3V TO 18V
21.1k⍀ AD629
–IN
+VS
21.1k⍀ AD629
REF(–)
REF(+)
5
0.1␮F
NC = NO CONNECT
–VS
–3V TO –18V
Applying a reference voltage to REF(+) and REF(–) and operating
on a single supply will reduce the input common-mode range of
the AD629. The new input common-mode range depends upon
the voltage at the inverting and noninverting inputs of the internal
operational amplifier, labeled VX and VY in Figure 30. These
nodes can swing to within 1 V of either rail. So for a (single)
supply voltage of 10 V, VX and VY can range between 1 V and
9 V. If VREF is set to 5 V, the permissible common-mode range
is +85 V to –75 V. The common-mode voltage ranges can be
calculated using the following equation.
()
The differential input signal, which will typically result from a
load current flowing through a small shunt resistor, is applied to
Pins 2 and 3 with the polarity shown in order to obtain a positive gain. The common-mode range on the differential input
signal can range from –270 V to +270 V and the maximum differential range is ± 13 V. When configured as shown, the device
operates as a simple gain-of-one differential-to-single-ended
amplifier, the output voltage being the shunt resistance times the
shunt current. The output is measured with respect to Pins 1 and 5.
Pins 1 and 5 (REF(–) and REF(+)) should be grounded for a
gain of unity and should be connected to the same low impedance ground plane. Failure to do this will result in degraded
common-mode rejection. Pin 8 is a no connect pin and should
be left open.
Single Supply Operation
Figure 30 shows the connections for operating the AD629 with
a single supply. Because the output can swing to within only
about 2 V of either rail, it is necessary to apply an offset to the
output. This can be conveniently done by connecting REF(+) and
REF(–) to a low impedance reference voltage (some analogto-digital converters provide this voltage as an output), which is
capable of sinking current. Thus, for a single supply of 10 V,
VREF might be set to 5 V for a bipolar input signal. This would
allow the output to swing ± 3 V around the central 5 V reference
voltage. Alternatively, for unipolar input signals, VREF could be
set to about 2 V, allowing the output to swing from +2 V (for a 0 V
input) to within 2 V of the positive rail.
()
VCM ± = 20 VX / Y ± − 19 VREF
Figure 29. Basic Connections
System-Level Decoupling and Grounding
The use of ground planes is recommended to minimize the
impedance of ground returns (and hence the size of dc errors).
Figure 31 shows how to work with grounding in a mixed-signal
environment, that is, with digital and analog signals present. In
order to isolate low-level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground returns. All ground pins from mixedsignal components such as analog-to-digital converters should
be returned through the “high quality” analog ground plane.
This includes the digital ground lines of mixed-signal converters
that should also be connected to the analog ground plane. This
may seem to break the rule of keeping analog and digital grounds
separate, but in general, there is also a requirement to keep the
voltage difference between digital and analog grounds on a converter as small as possible (typically <0.3 V). The increased
noise, caused by the converter’s digital return currents flowing
through the analog ground plane, will typically be negligible.
Maximum isolation between analog and digital is achieved by
connecting the ground planes back at the supplies. Note that
Figure 31, as drawn, suggests a “star” ground system for the
analog circuitry, with all ground lines being connected, in this
case, to the ADC’s analog ground. However, when ground planes
are used, it is sufficient to connect ground pins to the nearest
point on the low impedance ground plane.
–8–
REV. A
AD629
shows some sample error voltages generated by a common-mode
voltage of 200 V dc with shunt resistors from 20 Ω to 2000 Ω.
Assuming that the shunt resistor has been selected to utilize the
full ± 10 V output swing of the AD629, the error voltage becomes
quite significant as RSHUNT increases.
DIGITAL
POWER SUPPLY
GND +5V
ANALOG POWER
SUPPLY
–5V
+5V
GND
0.1␮F
0.1␮F
0.1␮F 0.1␮F
+IN
+VS
–VS
–IN
VDD AGND DGND
AD629
VOUT
VIN1
AD7892-2
GND
12
Table I. Error Resulting from Large Values of R SHUNT
(Uncompensated Circuit)
VDD
␮PROCESSOR
VIN2
REF(–) REF(+)
Figure 31. Optimal Grounding Practice for a Bipolar Supply
Environment with Separate Analog and Digital Supplies
RS (⍀)
Error VOUT (V)
Error Indicated (mA)
20
1000
2000
0.01
0.498
1
0.5
0.498
0.5
If it is desired to measure low current or current near zero in a
high common-mode environment, an external resistor equal to
the shunt resistor value may be added to the low impedance side
of the shunt resistor as shown in Figure 33.
POWER SUPPLY
GND
+5V
0.1␮F
0.1␮F
0.1␮F
8 NC
1
+IN
–IN
+VS
AD629
–VS
VOUT
REF(–) REF(+)
VDD
AGND DGND
RCOMP
VDD GND
VIN
ADC
ISHUNT
␮PROCESSOR
380k⍀ 380k⍀
–IN
RSHUNT
2
3
+VS
0.1␮F
VOUT
6
20k⍀
–VS
–VS
7
380k⍀
+IN
VREF
Figure 32. Optimal Ground Practice in a Single Supply
Environment
+VS
21.1k⍀ AD629
REF(–)
4
5
REF(+)
0.1␮F
NC = NO CONNECT
Figure 33. Compensating for Large Sense Resistors
If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 32 shows how to
minimize interference between the digital and analog circuitry.
In this example, the ADC’s reference is used to drive the
AD629’s REF(+) and REF(–) pins. This means that the reference
must be capable of sourcing and sinking a current equal to VCM/
200 kΩ. As in the previous case, separate analog and digital
ground planes should be used (reasonably thick traces can be
used as an alternative to a digital ground plane). These ground
planes should be connected at the power supply’s ground pin.
Separate traces (or power planes) should be run from the power
supply to the supply pins of the digital and analog circuits. Ideally,
each device should have its own power supply trace, but these
can be shared by a number of devices as long as a single trace is
not used to route current to both digital and analog circuitry.
Output Filtering
A simple 2-pole low-pass Butterworth filter can be implemented
using the OP177 at the output of the AD629 to limit noise at
the output, as shown in Figure 34. Table II gives recommended
component values for various corner frequencies, along with the
peak-to-peak output noise for each case.
+VS
21.1k⍀ AD629
REF(–)
1
8
0.1␮F
380k⍀ 380k⍀
–IN
2
+VS
NC
7
R1
–VS
Using a Large Sense Resistor
3
–VS
0.1␮F
R2
OP177
0.1␮F
+VS
380k⍀
+IN
C1
6
20k⍀
4
5
REF(+)
VOUT
C2
–VS
0.1␮F
Insertion of a large shunt resistance across the input Pins 2 and 3
will imbalance the input resistor network, introducing a commonmode error. The magnitude of the error will depend on the
common-mode voltage and the magnitude of RSHUNT. Table I
NC = NO CONNECT
Figure 34. Filtering of Output Noise Using a 2-Pole
Butterworth Filter
Table II. Recommended Values for 2-Pole Butterworth Filter
Corner Frequency
R1
R2
C1
C2
Output Noise (p-p)
No Filter
50 kHz
5 kHz
500 Hz
50 Hz
2.94 kΩ ± 1%
2.94 kΩ ± 1%
2.94 kΩ ± 1%
2.7 kΩ ± 10%
1.58 kΩ ± 1%
1.58 kΩ ± 1%
1.58 kΩ ± 1%
1.5 kΩ ± 10%
2.2 nF ± 10%
22 nF ± 10%
220 nF ± 10%
2.2 µF ± 20%
1 nF ± 10%
10 nF ± 10%
0.1 µF ± 10%
1 µF ± 20%
3.2 mV
1 mV
0.32 mV
100 µV
32 µV
REV. A
–9–
AD629
Output Current and Buffering
The AD629 is designed to drive loads of 2 kΩ to within 2 V of
the rails, but can deliver higher output currents at lower output
voltages (see Figure 15). If higher output current is required,
the AD629’s output should be buffered with a precision op
amp such as the OP113 as shown in Figure 35. This op amp
can swing to within 1 V of either rail while driving a load as
small as 600 Ω.
1
8
2
0.1␮F
5
5
VOUT
REF(+)
Figure 36. A Gain of 19 Thermocouple Amplifier
OP113
20k⍀
6
20k⍀
Error Budget Analysis Example 1
6
4
380k⍀
3
NC = NO CONNECT
380k⍀
–VS
7
4
7
3
NC
0.1␮F
380k⍀ 380k⍀
2
VREF
0.1␮F
+IN
8
NC
380k⍀ 380k⍀
–IN
–IN
+IN
+VS
21.1k⍀ AD629
REF(–)
1
THERMOCOUPLE
+VS
21.1k⍀ AD629
REF(–)
REF(+)
0.1␮F
NC = NO CONNECT
VOUT
0.1␮F
–VS
Figure 35. Output Buffering Application
A Gain of 19 Differential Amplifier
While low level signals can be connected directly to the –IN and
+IN inputs of the AD629, differential input signals can also be
connected as shown in Figure 36 to give a precise gain of 19.
However, large common-mode voltages are no longer permissible.
Cold junction compensation can be implemented using a temperature sensor such as the AD590.
In the dc application below, the 10 A output current from a
device with a high common-mode voltage (such as a power supply or current-mode amplifier) is sensed across a 1 Ω shunt
resistor (Figure 37). The common-mode voltage is 200 V, and
the resistor terminals are connected through a long pair of lead
wires located in a high-noise environment, for example, 50 Hz/
60 Hz 440 V ac power lines. The calculations in Table III
assume an induced noise level of 1 V at 60 Hz on the leads, in
addition to a full-scale dc differential voltage of 10 V. The error
budget table quantifies the contribution of each error source.
Note that the dominant error source in this example is due to
the dc common-mode voltage.
Table III. AD629 vs. INA117 Error Budget Analysis Example 1 (V CM = 200 V dc)
Error, ppm of FS
AD629
INA117
Error Source
AD629
ACCURACY, TA = 25°C
Initial Gain Error
Offset Voltage
DC CMR (Over Temperature)
(0.0005 × 10) ÷ 10 V × 106
(0.0005 × 10) ÷ 10 V × 106
6
(0.001 V ÷ 10 V) × 10
(0.002 V ÷ 10 V) × 106
-6
6
(224 × 10 × 200 V) ÷ 10 V × 10 (500 × 10-6 × 200 V) ÷ 10 V × 106
TEMPERATURE DRIFT (85°C)
Gain
Offset Voltage
INA117
10 ppm/°C × 60°C
(20 µV/°C × 60°C) × 106/10 V
500
100
4,480
500
200
10,000
Total Accuracy Error: 5,080
10,700
10 ppm/°C × 60°C
(40 µV/°C × 60°C) × 106/10 V
600
120
600
240
720
840
2
14
10
3
50
10
Total Resolution Error:
26
63
Total Error:
5,826
11,603
Total Drift Error:
RESOLUTION
Noise, Typ, 0.01–10 Hz, µV p-p
CMR, 60 Hz
Nonlinearity
15 µV ÷ 10 V × 106
(141 × 10–6 × 1 V) ÷ 10 V × 106
(10–5 × 10 V) ÷ 10 V × 106
–10–
25 µV ÷ 10 V × 106
(500 × 10–6 × 1 V) ÷ 10 V × 106
(10–5 × 10 V) ÷ 10 V × 106
REV. A
AD629
before. Note that the same kind of power line interference can
happen as detailed in Example 1. However, the ac commonmode component of 200 V p-p coming from the shunt is much
larger than the interference of 1 V p-p, so that this interference
component can be neglected.
OUTPUT
CURRENT
21.1k⍀
REF(–)
10 AMPS
200VCM DC
TO GROUND
1
–IN
1⍀
SHUNT
+IN
8
380k⍀ 380k⍀
2
7
–VS
+VS
0.1␮F
380k⍀
3
6
20k⍀
60Hz
POWER LINE
NC
4
0.1␮F
5
VOUT
OUTPUT
CURRENT
REF(+)
REF(–)
10 AMPS
ⴞ100V AC CM
TO GROUND
AD629
–IN
NC = NO CONNECT
1⍀
SHUNT
Figure 37. Error Budget Analysis Example 1. VIN = 10 V
Full-Scale, VCM = 200 V DC. RSHUNT = 1 Ω, 1 V p-p 60 Hz
Power-Line Interference
21.1k⍀
1
8
380k⍀ 380k⍀
2
+VS
7
0.1␮F
+IN
380k⍀
3
6
20k⍀
60Hz
POWER LINE
Error Budget Analysis Example 2
NC
–VS
4
5
VOUT
REF(+)
AD629
0.1␮F
NC = NO CONNECT
This application is similar to the previous example except that
the sensed load current is from an amplifier with an ac commonmode component of ± 100 V (frequency = 500 Hz) present on
the shunt (Figure 38). All other conditions are the same as
Figure 38. Error Budget Analysis Example 2. VIN = 10 V
Full-Scale, VCM = ± 100 V at 500 Hz, RSHUNT = 1 Ω
Table IV. AD629 vs. INA117 AC Error Budget Example 2 (V CM = ⴞ100 V @ 500 Hz)
Error, ppm of FS
AD629
INA117
Error Source
AD629
INA117
ACCURACY, TA = 25°C
Initial Gain Error
Offset Voltage
(0.0005 × 10) ÷ 10 V × 106
(0.001 V ÷ 10 V) × 106
(0.0005 × 10) ÷ 10 V × 106
(0.002 V ÷ 10 V) × 106
500
100
500
200
600
700
600
120
600
240
720
840
2
14
10
2,820
3
50
10
10,000
Total Resolution Error:
2,846
10,063
Total Error:
4,166
11,603
Total Accuracy Error:
TEMPERATURE DRIFT (85°C)
Gain
10 ppm/°C × 60°C
Offset Voltage
(20 µV/°C × 60°C) × 106/10 V
10 ppm/°C × 60°C
(40 µV/°C × 60°C) × 106/10 V
Total Drift Error:
RESOLUTION
Noise, Typ, 0.01–10 Hz, µV p-p
CMR @ 60 Hz
Nonlinearity
AC CMR @ 500 Hz
REV. A
15 µV ÷ 10 V × 106
(141 × 10–6 × 1 V) ÷ 10 V × 106
(10–5 × 10 V) ÷ 10 V × 106
(141 × 10–6 × 200 V) ÷ 10 V × 106
–11–
25 µV ÷ 10 V × 106
(500 × 10–6 × 1 V) ÷ 10 V × 106
(10–5 × 10 V) ÷ 10 V × 106
(500 × 10–6 × 200 V) ÷ 10 V × 106
AD629
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.1968 (5.00)
0.1890 (4.80)
0.430 (10.92)
0.348 (8.84)
8
5
0.1574 (4.00)
0.1497 (3.80)
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
0.160 (4.06)
0.115 (2.93)
1
4
0.2440 (6.20)
0.2284 (5.80)
4
0.325 (8.25)
0.300 (7.62)
PIN 1
0.210
(5.33)
MAX
5
0.060 (1.52)
0.015 (0.38)
PIN 1
0.195 (4.95)
0.115 (2.93)
0.0098 (0.25)
0.0040 (0.10)
0.130
(3.30)
MIN
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15) PLANE
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
0.0500 (1.27)
BSC
SEATING
PLANE
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
8ⴗ
0.0098 (0.25) 0ⴗ 0.0500 (1.27)
0.0160 (0.41)
0.0075 (0.19)
0.015 (0.381)
0.008 (0.204)
PRINTED IN U.S.A.
1
8
C3717a–6–3/00 (rev. A)
8-Lead SOIC
(SO-8)
8-Lead Plastic DIP
(N-8)
–12–
REV. A