Ordering number : ENN6472 CMOS IC LC72348G/W, 72349G/W Low-Voltage ETR Controller with On-Chip LCD Driver Overview Package Dimensions The LC72348G/W and LC72349G/W are low-voltage electronic tuning microcontrollers that include a PLL that operates up to 230 MHz and a 1/4 duty 1/2 bias LCD driver on chip. These ICs can contribute to further end product cost reduction than the LC72341 series while providing improved standby current characteristics. Also these ICs can use the application program for the LC72341 series except the IF counter function. These ICs are optimal for use in low-voltage portable audio equipment that includes a radio receiver. unit: mm 3231-QIP64G [LC72348G, 72349G] 17.2 14.0 0.8 0.35 1.0 1.6 1.0 0.15 48 32 49 17.2 14.0 1.0 1.6 33 0.8 Function 17 1.0 1 3.0max 64 16 15.6 0.8 0.1 2.15 SANYO: QFP64G unit: mm 3190-SQFP64 [LC72348W, 72349W] 12.0 10.0 1.25 0.5 0.18 1.25 0.15 33 48 49 1.25 32 0.5 12.0 10.0 16 0.1 1 1.7max 17 64 1.25 • Program memory (ROM): — 3072 × 16 bits (6K bytes) LC72348G/W — 4096 × 16 bits (8K bytes) LC72349 G/W • Data memory (RAM): — 192 × 4 bits LC72348 G/W — 256 × 4 bits LC72349 G/W • Cycle time: 40 µs (all 1-word instructions) at 75kHz crystal oscillation • Stack: 8 levels • LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive) • Interrupts: One external interrupt Timer interrupts (1, 5, 10, and 50 ms) • A/D converter: Three input channels (5-bit successive approximation conversion) • Input ports: 7 ports (of which three can be switched for use as A/D converter inputs) • Output ports: 6 ports (of which 1 can be switched for use as the beep tone output and 2 are opendrain ports) • I/O ports: 16 ports (of which 8 can be switched for use as LCD ports and as mask options) 0.5 0.5 SANYO: SQFP64 Continued on next page. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 32700RM (OT) No. 6472-1/14 LC72348G/W, 72349G/W Continued from preceding page. • PLL: Supports dead zone control (two types) • Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz • Input frequencies: FM band: 10 to 230 MHz AM band: 0.5 to 10 MHz • Input sensitivity: FM band: 35 mVrms (50 mVrms at 130 MHz or higher frequency) AM band: 35 mVrms • External reset input: During CPU and PLL operations, instruction execution is started from location 0. • Built-in power-on reset circuit: The CPU starts execution from location 0 when power is first applied. • Halt mode: The controller-operating clock is stopped. • Backup mode: The crystal oscillator is stopped. • Static power-on function: Backup state is cleared with the PF port • Beep tone: 1.5 and 3.1 kHz • Built-in tuner voltage generating circuit: Cost reduced in tuner-use power supply circuit • Built-in low-pass filter amplifier • Optional function switches: — PH0 to PH3 (general-purpose input, open-drain output/general-purpose input and output/S13 to S16) — PG0 to PG3 (general-purpose input, open-drain output/general-purpose input and output/S17 to S20) — VSENSE circuit (provided/not provided) — FM DC/DC clock (1/256, 75 kHz) • Memory retention voltage: 0.9 V at least • Package: SQFP-64 (0.5-mm pitch), QIC-64 (0.8-mm pitch) Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Input voltage Output voltage Output current Allowable power dissipation Symbol Conditions VDD max VIN All input pins Ratings Unit –0.3 to +4.0 V –0.3 to VDD +0.3 V VOUT(1) AOUT, PE VOUT(2) All output pins except VOUT(1) –0.3 to +15 V –0.3 to VDD + 0.3 V IOUT(1) PC, PD, PG, PH, EO 0 to 3 mA IOUT(2) PB 0 to 1 mA mA IOUT(3) AOUT, PE 0 to 2 IOUT(4) S1 to S20 300 µA IOUT(5) COM1 to COM4 3 mA Pdmax Ta = –20 to +70°C 300 mW Operating temperature Topr –20 to +70 °C Storage temperature Tstg –45 to +125 °C No. 6472-2/14 LC72348G/W, 72349G/W Allowable Operating Ranges at Ta = –20 to +70°C, VDD = 1.8 to 3.6 V Parameter Supply voltage Input high-level voltage Input low-level voltage Input amplitude Input voltage range Input frequency Symbol Conditions Ratings min typ Unit max VDD(1) PLL operating voltage 1.8 VDD(2) Memory retention voltage 1.0 VDD(3) CPU operating voltage VDD(4) A/D converter operating voltage VIH(1) Input ports other than VIH(2), VIH(3), AMIN, FMIN, and XIN 0.7 VDD VDD V VIH(2) RES 0.8 VDD VDD V VIH(3) Port PF 0.6 VDD VDD V VIL(1) Input ports other than VIL(2), VIL(3), AMIN, FMIN, and XIN 0 0.3 VDD V VIL(2) RES 0 0.2 VDD V VIL(3) Port PF 0 0.2 VDD VIN(1) XIN 0.5 0.6 Vrms 0.035 0.35 Vrms 0.05 0.35 Vrms 0 VDD 3.0 3.6 1.4 3.0 3.6 1.6 3.0 3.6 V V VIN(2) FMIN, AMIN VIN(3) FMIN VIN(5) ADIO, ADI1, ADI3 FIN(1) XIN: CI ≤ 35 kΩ FIN(2) FMIN: VIN(2), VDD(1) 10 130 MHz FIN(3) FMIN: VIN(3), VDD(1) 130 250 MHz FIN(4) AMIN(L): VIN(2), VDD(1) 0.5 10 MHz 70 75 80 V kHz Electrical Characteristics within the allowable operating ranges Parameter Symbol IIH(1) XIN: VI = VDD = 3.0 V IIH(2) FMIN, AMIN: VI = VDD = 3.0 V IIH(3) PA/PF (without pull-down resistors), the PC, PD, PG, and PH ports, and RES: VI = VDD = 3.0 V Input high-level current IIL(1) XIN: VI = VDD = VSS IIL(2) FMIN, AMIN: VI = VDD = VSS IIL(3) PA/PF (without pull-down resistors), the PC, PD, PG, and PH ports, and RES: VI = VDD = VSS Input low-level current Input floating voltage Pull-down resistor values Hysteresis Voltage doubler reference voltage Voltage doubler step-up voltage Output high-level voltage Conditions VIF RPD(1) RPD(2) VH DBR4 DBR1, 2, 3 Ratings min typ 3 –3 8 –8 PA/PF (with pull-down resistors) PA/PF (with pull-down resistors), VDD = 3.0 V Unit max 3 µA 20 µA 3 µA –3 µA –20 µA –3 µA 0.05 VDD 100 0.1 VDD 0.2 VDD Referenced to VDD, C(3) = 0.47 µF, Ta = 25°C *1 1.3 1.5 1.7 V C(1) = 0.47 µF C(2) = 0.47 µF, without loading, Ta = 25°C *1 2.7 3.0 3.3 V VDD – 0.3 VDD V TEST1, TEST2 RES 200 V 75 10 kΩ kΩ V VOH(1) PB: IO = –1 mA VDD – 0.7 VDD VOH(2) PC, PD, PG, PH: IO = –1 mA VDD – 0.3 VDD V VOH(3) EO: IO = –500 µA VDD – 0.3 VDD V VOH(4) XOUT: IO = –1 µA VDD – 0.3 VDD V VOH(5) S1 to S20: IO = –20 µA *1 2.0 V VOH(6) COM1, COM2, COM3, COM4: IO = –100 µA *1 2.0 V Continued on next page. No. 6472-3/14 LC72348G/W, 72349G/W Continued from preceding page. Parameter Symbol Output low-level voltage Output off leakage current max Unit PB: IO = –50 µA 0.7 VDD V PC, PD, PE, PG, PH: IO = –1 mA 0.3 VDD V VOL(3) EO: IO = –500 µA 0.3 VDD V VOL(4) XOUT: IO = –1 µA 0.3 VDD V VOL(5) S1 to S20: IO = –20 µA *1 1.0 V VOL(6) COM1, COM2, COM3, COM4: IO = –100 µA *1 1.0 V V 0.3 VDD VOL(7) PE: IO = 2 mA 1.0 VOL(8) AOUT(AIN = 1.3 V), TU: IO = 1 mA, VDD = 3 V 0.5 V IOFF(1) Ports PB, PC, PD, PG, PH, and EO –3 +3 µA IOFF(2) AOUT and port PE –100 +100 nA ADI0, ADI1, ADI3 VDD(4) –1/2 +1/2 LSB 1.9 V (1)max +0.2 V VSENSE(2) Current drain typ VOL(1) VSENSE(1) Supply voltage rise detection voltage min VOL(2) A/D converter error Supply voltage drop detection voltage Ratings Conditions Ta = 25°C *2 1.6 Ta = 25°C *2 (1)min +0.1 IDD(1) VDD(1): FIN(2) 130 MHz, Ta = 25°C IDD(2) VDD(2): In HALT mode, Ta = 25°C *3 IDD(3) IDD(4) 1.75 5 15 mA 0.1 mA VDD = 3.6 V, with the oscillator stopped, Ta = 25°C *4 1 µA VDD = 1.8 V, with the oscillator stopped, Ta = 25°C *4 0.5 µA Note: The halt mode current is due to the CPU executing 20 instruction steps every 125 ms. XIN TEST1 AGND AOUT AIN EO VSS AMIN FMIN VDD TU RES DBR1 DBR2 DBR3 DBR4 Pin Assignment 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 6 43 7 LC72348G, 72348W LC72349G, 72349W 8 9 42 41 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 COM1 COM2 COM3 COM4 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 PD1 INT/PD0 PE1 BEEP/PE0 ADI3/PF2 ADI1/PF1 ADI0/PF0 VSS PG3/S20 PG2/S19 PG1/S18 PG0/S17 PH3/S16 PH2/S15 PH1/S14 PH0/S13 XOUT TEST2 PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 PC3 PC2 PC1 PC0 PD3 PD2 No. 6472-4/14 LC72348G/W, 72349G/W Note: * C(1), C(2), and C(3) must be connected even if an LCD is not used. DBR1 0.1 to 1 µF DBR2 C(C1) 0.1 to 1 µF DBR3 C(C2) 0.1 to 1 µF DBR4 C(C3) Notes: *1. The capacitors C(1), C(2), and C(3) must be connected to the DBR pins. *2. VSENSE When the VDD voltage drops, the VSENSE flag is set when that voltage is 1.75 V (typical). Applications can check the VSENSE flag using the TST instruction. Battery or other power source depletion can be easily measured by monitoring this flag. Note that the voltage for VSENSE detection differs for the falling and rising directions. Thus, after the VSENSE flag has been set due to a voltage drop, it will not be reset if the voltage rises by under 0.1 V. VDD VDD 2.1 V 1.9 V 1.7 V 1.6 V → RESET← VSENSE (1) SET t VSENSE (2) For a rising voltage For a falling voltage *3. Halt mode current measurement circuit 7 pF 7 pF A TEST1, 2 A 75 kHz XOUT VDD RES DBR1 XIN DBR2 DBR3 FMIN AMIN t *4. Backup mode current measurement circuit 75 kHz 7pF →RESET SET← DBR4 VSS PA, PF AGND AIN 0.1 µF 0.1 µF 7pF XOUT VDD RESDBR1 XIN DBR2 DBR3 0.1 µF DBR4 0.1 µF 0.1 µF With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected. FMIN AMIN TEST1, 2 0.1 µF VSS AGND AIN With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected. No. 6472-5/14 LC72348G/W, 72349G/W Block Diagram DIVIDER XIN REFERENCE DIVIDER PHASE DETECTOR SYSTEM CLOCK GENERATOR XOUT 1/2 FMIN EO 75kHz 1/16,1/17 PROGRAMMBLE DIVIDER FM LOCAL 1/256 1/2 TU AM LOCAL 1/2 AMIN PLL DATA LATCH VDD VSS PLL CONTROL S1 LCDA/B VSENSE TIME BASE COUNT CONTROL END LCD 80 PORT DRIVER SEG 4 LA 7 LCPA/B RES * S12 P-ON RESET RAM ADDRESS 192 × 4bits(LC72348) DECODER 256 × 4bits(LC72349) BANK TEST1 TEST2 PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 BUS DRIVER ROM * DATA LATCH / BUS DRIVER PC0 PC1 PC2 PC3 DATA LATCH / BUS DRIVER INT/PD0 PD1 PD2 PD3 DATA LATCH / BUS DRIVER AIN AOUT AGND BUS CONTROL 3k × 16bits (LC72348) 4k × 16bits (LC72349) INSTRUCTION DECODER ADDRESS DECODER S13/PH0 S14/PH1 S15/PH2 S16/PH3 DATA LATCH / BUS DRIVER S17/PG0 S18/PG1 S19/PG2 S20/PG3 DOUBLER CIRCUIT DBR1 DBR2 DBR3 DBR4 COMMON DRIVER COM4 COM3 COM2 COM1 SKIP JMP 14 CAL ADDRESS COUNTER RETURN INTERRUPT 14 RESET STACK BANK CF JUDGE LATCH A DATA LATCH / BUS DRIVER BEEP TONE DATA LATCH / BUS DRIVER PE0/BEEP MPX PE1 ALU LATCH B MPX TIMER 0 ADC (5bits) DATA LATCH / BUS DRIVER PF0/ADI0 PF1/ADI1 PF2/ADI3 DATA BUS No. 6472-6/14 LC72348G/W, 72349G/W Pin Functions Pin No. Pin I/O 64 XIN I 1 XOUT O 63 TEST1 I 2 TEST2 I Function I/O circuit 75 kHz oscillator connections IC testing. These pins must be connected to ground during normal operation. — Input with built-in pull-down resistor 6 PA0 5 PA1 4 PA2 3 PA3 I Special-purpose key return signal input ports designed with a low threshold voltage. When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key presses can be detected. The four pull-down resistors are selected together in a single operation using the IOS instruction (PWn = 2, b1); they cannot be specified individually. Input is disabled in backup mode, and the pull-down resistors are disabled after a reset. General-purpose CMOS and n-channel open-drain output shared-function ports. Unbalanced CMOS pushpull/n-channel open-drain The IOS instruction (Pwn = 2) is used for function switching. 10 PB0 9 PB1 8 PB2 7 PB3 (b0: PB0, b2: PB1, b3: PB2, PB3) (0: general-purpose CMOS, 1: n-channel opendrain) O Special-purpose key source signal output ports. Since unbalanced CMOS output transistor circuits are used, diodes to prevent short-circuits when multiple keys are pressed are not required. These ports go to the output high-impedance state in backup mode. These ports go to the output high-impedance state after a reset and remain in that state until an output instruction (OUT, SPB, or RPB) is executed. *: Verify the output impedance conditions carefully if these pins are used for functions other than key source outputs. 14 PC0 13 PC1 12 PC2 11 PC3 CMOS push-pull General-purpose I/O ports. I/O 18 INT/PD0 17 PD1 16 PD2 15 PD3 PD0 can be used as an external interrupt port. Input or output mode can be set individually using the IOS instruction by the bit (Pwn = 4, 5). A value of 0 specifies input, and 1 specifies output. These ports go to the input disabled high-impedance state in backup mode. They are set to function as general-purpose input ports after a reset. *2 General-purpose output ports with shared beep tone output function (PE0 only). The BEEP instruction is used to switch PE0 between the general-purpose output port and beep tone output functions. To use PE0 as a general-purpose output port, execute a BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output port. The b0 and b1 bits are used to select the beep tone frequency. There are two beep tone frequencies supported. 20 BEEP/PE0 19 PE1 N-channel open-drain *: When PE0 is set up as the beep tone output, executing an output instruction to PE0 only changes the state of the internal output latch, it does not affect the beep tone output in any way. Only the PE0 pin can be switched between the general-purpose output function and the beep tone output function; the PE1 pin only functions as a general-purpose output. These pins go to the high-impedance state in backup mode and remain in that state until an output instruction or a BEEP instruction is executed. Since these ports are open-drain ports, resistors must be inserted between these pins and VDD. These ports are set to general-purpose output port function after a reset. Continued on next page. No. 6472-7/14 LC72348G/W, 72349G/W Continued from preceding page. Pin No. Pin 23 PF0/ADI0 22 PF1/ADI1 21 PF2/ADI3 I/O I Function I/O circuit General-purpose input and A/D converter input shared function ports. The IOS instruction (Pwn = FH) is used to switch between the general-purpose input and A/D converter port functions. The general-purpose input and A/D converter port functions can be switched by the bit, with 0 specifying general-purpose input, and 1 specifying the A/D converter input function. To select the A/D converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion completes. The INR instruction is used to read in the data. CMOS input/analog input *: If an input instruction is executed for one of these pins which is set up for analog input, the read in data will be at the low level since CMOS input is disabled. In backup mode these pins go to the input disabled high-impedance state. These ports are set to their general-purpose input port function after a reset. The A/D converter is a 5-bit successive approximation type converter, and features a conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (1FH) is (63.96) VDD. LCD driver segment output, general-purpose I/O, and general-purpose n-channel open-drain output shared function ports. CMOS push-pull The IOS instruction is used for switching between the segment output and generalpurpose I/O functions. 25 PG3/S20 26 PG2/S19 27 PG1/S18 28 PG0/S17 29 PH3/S16 30 PH2/S15 31 PH1/S14 32 PH0/S13 I/O • When used as segment output ports The general-purpose I/O port function is selected with the IOS instruction (Pwn = 8). b0 = S17 to 20/PG0 to 3 (0: Segment output, 1: PG0 to 3) The general-purpose I/O port function is selected with the IOS instruction (Pwn = 9). b0 = S13 to 16/PH0 to 3 (0: Segment output, 1: PH0 to 3) • When used as general-purpose I/O ports The IOS instruction (Pwn = 6,7) is used to select input or output. Note that the mode can be set in individual by the bit. b0 = PG0 b1 = PG1 b2 = PG2 b3 = PG3 0: Input 1: Output b0 = PH0 b1 = PH1 b2 = PH2 b3 = PH3 0: Input 1: Output In backup mode, these pins go to the input disabled high-impedance state if set up as general-purpose outputs, and are fixed at the low level if set up as segment outputs. These ports are set up as segment outputs after a reset. *2 Although the general-purpose I/O port/general-purpose n-channel open-drain output/LCD port setting is a mask option, the IOS instruction must be used as described above to set up the port function. CMOS push-pull LCD driver segment output pins. 33 to 44 A 1/4-duty 1/2-bias drive technique is used. S16 to S1 O The frame frequency is 75 Hz. In backup mode, the outputs are fixed at the low level. After a reset, the outputs are fixed at the low level. 45 COM4 46 COM3 47 COM2 48 COM1 49 DBR4 50 DBR3 51 DBR2 52 DBR1 LCD driver common output pins. A 1/4-duty 1/2-bias drive technique is used. O The frame frequency is 75 Hz. In backup mode, the outputs are fixed at the low level. After a reset, the outputs are fixed at the low level. I LCD power supply step-up voltage inputs. Continued on next page. No. 6472-8/14 LC72348G/W, 72349G/W Continued from preceding page. Pin No. Pin I/O Function I/O circuit System reset input. 53 RES I In CPU operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit. N-channel open-drain Tuning voltage generation circuit outputs. These pins include an n-channel transistor, and a tuning voltage can be generated by connecting external coil, diode, and capacitor components. FM DC-DC clock switching is a mask option. 54 TU O DC-DC clock AM AM local 1/2 FM FM local 1/256 or 75 kHz CMOS amplifier input FM VCO (local oscillator) input. 56 FMIN I This pin is selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. CMOS amplifier input AM VCO (local oscillator) input. This pin and the bandwidth are selected with the PLL instruction CW1. 57 AMIN CW1 b1, b0 I 1 1 Bandwidth 0.5 to 10 MHz (MW, LW) The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. CMOS push-pull 59 EO O Main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output. The pin is set to the high-impedance state when the frequencies match. Output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode. 60 AIN 61 AOUT 62 AGND 24 VSS 58 VSS 55 VDD Note 2: O Transistor used for the low-pass filter amplifier. Connect AGND to ground. Power supply pin. — This pin must be connected to ground. This pin must be connected to ground. — This pin must be connected to VDD. When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set up output mode with an IOS instruction. No. 6472-9/14 LC72348G/W, 72349G/W Sample Application for Tuning Voltage Generation Circuit Sample Application for Low-Pass Filter Amplifier XIN 64 XOUT 1 EO 75kHz 59 AIN VDD FMIN 56 60 Mask option 55 1/256 AOUT FM mode Varactor 61 AGND AMIN 57 1/2 AM mode 62 TU+B TU 54 RADIO ON LC72348 DC-DC converter load: 100 kΩ 12 FM reception mode clock (75 kHz selected) AM reception mode clock frequency range 10 VT voltage —V 8 6 4 2 0 10 100 1000 10000 Clock frequency — kHz No. 6472-10/14 LC72348G/W, 72349G/W LC72340 Series Instruction Set Terminology ADDR b C DH DL I M N Rn Pn PW r ( ), [ ] M (DH, DL) Subtraction instructions Addition instructions Instructions Mnemonic : Program memory address : Borrow : Carry : Data memory address High (Row address) [2 bits] : Data memory address Low (Column address) [4 bits] : Immediate data [4 bits] : Data memory address : Bit position [4 bits] : Resister number [4 bits] : Port number [4 bits] : Port control word number [4 bits] : General register (One of the addresses from 00H to 0FH of BANK0) : Contents of register or memory : Data memory specified by DH, DL Operand Function 1st 2nd AD r M Add M to r ADS r M AC r M M ACS r Operations function Instruction format f e d c b a r ← (r) + (M) 0 1 0 0 0 0 9 DH 8 7 6 DL 5 4 3 2 r 1 Add M to r, then skip if carry r ← (r) + (M), skip if carry 0 1 0 0 0 1 DH DL r Add M to r with carry r ← (r) + (M) + C 0 1 0 0 1 0 DH DL r Add M to r with carry, then skip if carry r ← (r) + (M) + C skip if carry 0 1 0 0 1 1 DH DL r AI M I Add I to M M ← (M) + I 0 1 0 1 0 0 DH DL I AIS M I Add I to M, then skip if carry M ← (M) + I, skip if carry 0 1 0 1 0 1 DH DL I AIC M I Add I to M with carry M ← (M) + I + C 0 1 0 1 1 0 DH DL I Add I to M with carry, then skip if carry M ← (M) + I + C, skip if carry 0 1 0 1 1 1 DH DL I AICS M I SU r M Subtract M from r r ← (r) – (M) 0 1 1 0 0 0 DH DL r r ← (r) – (M), skip if borrow 0 1 1 0 0 1 DH DL r SUS r M Subtract M from r, then skip if borrow SB r M Subtract M from r with borrow r ← (r) – (M) – b 0 1 1 0 1 0 DH DL r Subtract M from r with borrow, then skip if borrow r ← (r) – (M) – b, skip if borrow 0 1 1 0 1 1 DH DL r SBS r M SI M I Subtract I from M M ← (M) – I 0 1 1 1 0 0 DH DL I M ← (M) – I, skip if borrow 0 1 1 1 0 1 DH DL I SIS M I Subtract I from M, then skip if borrow SIB M I Subtract I from M with borrow M ← (M) – I – b 0 1 1 1 1 0 DH DL I I Subtract I from M with borrow, then skip if borrow M ← (M) – I – b, skip if borrow 0 1 1 1 1 1 DH DL I SIBS M 0 Continued on next page. No. 6472-11/14 LC72348G/W, 72349G/W Continued from preceding page. Logic instructions Comparison instructions Instructions Mnemonic SEQ Transfer instructions 2nd r M Function Operations function Instruction format f e d c b a 9 8 7 6 5 4 3 2 1 Skip if r equal to M (r) – (M), skip if zero 0 0 0 1 0 0 DH DL r SEQI M I Skip if M equal to I (M) – I, skip if zero 0 0 0 1 0 1 DH DL I SNEI M I Skip if M not equal to I (M) – I, skip if not zero 0 0 0 0 0 1 DH DL I (r) – (M), skip if not borrow 0 0 0 1 1 0 DH DL r (M) – I, skip if not borrow 0 0 0 1 1 1 DH DL I SGE r M Skip if r is greater than or equal to M SGEI M I Skip if M is greater than equal to I SLEI M I Skip if M is less than I (M) – I, skip if borrow 0 0 0 0 1 1 DH DL I AND r M AND M with r r ← (r) AND (M) 0 0 1 0 0 0 DH DL r ANDI M I AND I with M M ← (M) AND I 0 0 1 0 0 1 DH DL I OR r M OR M with r r ← (r) OR (M) 0 0 1 0 1 0 DH DL r ORI M I OR I with M M ← (M) OR I 0 0 1 0 1 1 DH DL I EXL r M Exclusive OR M with r r ← (r) XOR (M) 0 0 1 1 0 0 DH DL r EXLI M I Exclusive OR M with M M ← (M) XOR I 0 0 1 1 0 1 DH DL I 0 0 0 0 0 0 SHR Jump and subroutine Bit test call instructions instructions Operand 1st r carry (r) Shift r right with carry 0 0 1 1 1 0 r LD r M Load M to r r ← (M) 1 1 0 1 0 0 DH DL r ST M r Store r to M M ← (r) 1 1 0 1 0 1 DH DL r [DH, Rn] ← (M) 1 1 0 1 1 0 DH DL r M ← [DH, Rn] 1 1 0 1 1 1 DH DL r MVRD r M Move M to destination M referring to r in the same row MVRS M r Move source M referring to r to M in the same row MVSR M1 M2 Move M to M in the same row [DH, DL1] ← [DH, DL2] 1 1 1 0 0 0 DH DL1 DL2 MVI M I Move I to M M←I 1 1 1 0 0 1 DH DL I if M (N) = all 1s, then skip 1 1 1 1 0 0 DH DL N if M (N) = all 0s, then skip 1 1 1 1 0 1 DH DL N Jump to the address PC ← ADDR 1 0 0 ADDR (13 bits) Call subroutine PC ← ADDR Stack ← (PC) + 1 1 0 1 ADDR (13 bits) Return from subroutine PC ← Stack 0 0 0 0 0 0 0 0 1 0 0 0 Return from interrupt PC ← Stack, BANK ← Stack, CARRY ← Stack 0 0 0 0 0 0 0 0 1 0 0 1 TMT M N Test M bits, then skip if all bits specified are true TMF M N Test M bits, then skip if all bits specified are false JMP CAL RT RTI ADDR ADDR 0 Continued on next page. No. 6472-12/14 LC72348G/W, 72349G/W Continued from preceding page. Other instructions LCD instructions Bank switching instructions I/O instructions Hardware control instructions Status register instructions Instructions Mnemonic Operand 1st 2nd SS SWR N Function Set status register Operations function Instruction format f e d c b a 9 8 7 6 5 (Status W-reg) N ← 1 1 1 1 1 1 1 1 1 0 0 0 SWR 4 3 2 N 1 RS SWR N Reset status register (Status W-reg) N ← 0 1 1 1 1 1 1 1 1 0 0 1 SWR N TST SRR N Test status register true if (Status R-reg) N = all 1 1 1 1 1 1 1 1 0 1 SRR N TSF SRR N Test status register false if (Status R-reg) N = all 1 1 1 1 1 1 1 1 1 0 SRR N Test Unlock F/F if Unlock F/F (N) = all 0s, then skip 0 0 0 0 0 0 0 0 1 1 0 N TUL N 1 PLL M Load M to PLL register PLL reg ← PLL data 1 1 1 1 1 0 UCS I Set I to UCCW1 UCCW1 ← I 0 0 0 0 0 0 0 0 0 0 0 1 I UCC I Set I to UCCW2 UCCW2 ← I 0 0 0 0 0 0 0 0 0 0 1 0 I BEEP I Beep control BEEP reg ← I 0 0 0 0 0 0 0 0 0 1 1 0 I DZC I Dead zone control DZC reg ← I 0 0 0 0 0 0 0 0 1 0 1 1 I TMS I Set timer register Timer reg ← I 0 0 0 0 0 0 0 0 1 1 0 0 1 0 IOS PWn N Set port control word IOS reg PWn ← N 1 1 1 1 1 1 DH DL r I PWn N IN M Pn Input port data to M M ← (Pn) 1 1 1 0 1 0 DH DL Pn OUT M Pn Output contents of M to port P1n ← M 1 1 1 0 1 1 DH DL Pn INR M Pn Input port data to M M ← (Pn) 0 0 1 1 1 0 DH DL Pn SPB P1n N Set port1 bits (Pn)N ← 1 0 0 0 0 0 0 1 0 Pn N RPB P1n N Reset port1 bits (Pn)N ← 0 0 0 0 0 0 0 1 1 Pn N 1 1 1 1 1 0 0 Pn N 1 1 1 1 1 0 1 Pn N 0 0 0 0 0 0 0 0 1 1 0 0 0 0 DH DL DIGIT 1 1 0 0 0 1 DH DL DIGIT 1 1 0 0 1 0 DH DL DIGIT 1 1 0 0 1 1 DH DL DIGIT TPT P1n N Test port1 bits, then skip if all bits if (Pn)N = all 1s, then skip 1 specified are true TPF P1n N Test port1 bits, then skip if all bits if (Pn)N = all 0s, then skip 1 specified are false BANK I LCDA M I LCDB M I LCPA M I LCPB M I HALT CKSTP NOP I Select Bank BANK ← I Output segment pattern to LCD digit direct LCD (DIGIT) ← M 0 1 1 0 1 Output segment pattern to LCD digit through LA LCD (DIGIT) ← LA ← M Halt mode control HALT reg ← I, then CPU clock stop 0 0 0 0 0 0 0 0 0 1 0 0 Clock stop Stop x’tal OSC 0 0 0 0 0 0 0 0 0 1 0 1 No operation No operation 0 0 0 0 0 0 0 0 0 0 0 0 I I No. 6472-13/14 LC72348G/W, 72349G/W Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 2000. Specifications and information herein are subject to change without notice. PS No. 6472-14/14