MOTOROLA MPC932 Low voltage pll clock driver Datasheet

SEMICONDUCTOR TECHNICAL DATA
The MPC932 is a 3.3V compatible PLL based clock driver device
targetted for zero delay applications. The device provides 6 outputs for
driving clock loads plus a single dedicated PLL feedback clock output.
The dedicated feedback output gives the user six choices of input
multiplcation factors: x1, x1.25, x1.5, x2, x2.5 and x3.
•
•
•
•
•
•
•
•
LOW VOLTAGE
PLL CLOCK DRIVER
6 Low Skew Clock Outputs
1 Dedicated PLL Feedback Output
Individual Output Enable Control
Fully Integrated PLL
Output Frequency Up TO 120MHz
32–lead TQFP Packaging
3.3V VCC
±100ps Cycle–Cycle Jitter
The MPC932 provides individual output enable control. The enables
are synchronized to the internal clock such that upon assertion the shut
down signals will hold the clocks LOW without generating a runt pulse on
the outputs. The shut down pins provide a means of powering down
certain portions of a system or a means of disabling outputs when the full
compliment are not required for a specific design. The shut down pins will
disable the outputs when driven LOW. A common shut down pin is
provided to disable all of the outputs (except the feedback output) with a
single control signal.
FA SUFFIX
TQFP PACKAGE
CASE 873A-02
Two feedback select pins are provided to select the multiplication factor of the PLL. The MPC932 provides six multiplication
factors: x1, x1.25, x1.5, x2, x2.5 and x3. In the x1.25 and x2.5 modes, the QFB output will not provide a 50% duty cycle. The
phase detector of the MPC932 only monitors rising edges of its feedback signals, thus for this function a 50% duty cycle is not
required. As the QFB signal can also be used to drive other clocks in a system it is important the user understand that the duty
cycle will not be 50%. In the x1 and x1.5 modes the QFB output will produce 50% duty cycle signals.
The MPC932 provides two pins for use in system test and debug operations. The MR/OE input will force all of the outputs into
a high impedance state to allow for back driving the outputs during system test. In addition the PLL_EN pin allows the user to
bypass the PLL and drive the outputs directly through the Ref_CLK input. Note the Ref_CLK signal will be routed through the
dividers so that it will take several transitions on the Ref_CLK input to create a transition on the outputs.
The MPC932 is fully 3.3V compatible and requires no external loop filter components. All of the inputs are LVCMOS/LVTTL
compatible and the outputs produce rail–to–rail 3.3V swings. For series terminated applications each output can drive two series
terminated 50Ω transmission lines. For parallel terminated lines the device can drive terminations of 50Ω into VCC/2. The device
is packaged in a 32–lead TQFP package to provide the optimum combination of performance, board density and cost.
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
11/96
 Motorola, Inc. 1996
1
REV 0
MPC932
24
23
22
21
20
19
18
Q5
VCCO
FUNCTION TABLES
Q4
GNDO
Q3
VCCO
Q2
GNDO
Pinout: 32-Lead TQFP Package (Top View)
SDn, COM_SD
Qn
0
1
Held LOW
Enabled
PLL_En
PLL Status
17
Q1
25
16
GND_QFB
VCCO
26
15
QFB
Q0
27
14
VCCO_QFB
GNDO
28
13
FB_In
SD2
29
12
SD3
SD0:1
30
11
SD4
MODE
FBSEL1
FBSEL0
Qn
QFB
MODE
31
10
SD5
VCCA
32
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/4
VCO/4
VCO/4
NA
VCO/4
VCO/4
VCO/4
NA
VCO/8
VCO/10
VCO/12
NA
VCO/4
VCO/5
VCO/6
NA
MPC932
2
3
4
5
6
7
8
VCCI
REF_CLK
PLL_EN
FBSEL0
FBSEL1
MR/OE
COM_SD
GNDI
9
1
0
1
GNDA
Test Mode
PLL Enabled
MR/OE
PLL Status
0
1
Disabled
Enabled
LOGIC DIAGRAM
SD0:1
PLL_EN
REF_CLK
FB_In
PLL
200–480MHz
÷4
STOP
Q0
÷4
STOP
Q1
STOP
Q2
STOP
Q3
STOP
Q4
STOP
Q5
÷5
÷2
÷6
SD2
MODE
MR/OE
COM_SD
SD3
SD4
SD5
QFB
FBSEL0
FBSEL1
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — REV 5
MPC932
Qn
SDn
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
Min
Max
Unit
VCC
Symbol
Supply Voltage
Parameter
–0.3
4.6
V
VI
Input Voltage
–0.3
VDD + 0.3
V
IIN
Input Current
±20
mA
TStor
Storage Temperature Range
125
°C
–40
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
tr, tf
TCLK Input Rise/Falls
fref
Reference Input Frequency
Min
Max
Unit
3.0
ns
Note 1.
Note 1.
MHz
Condition
frefDC
Reference Input Duty Cycle
25
75
%
1. Maximum and Maximum input reference frequency is limited by the VCO lock range and the feedback divider.
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIN
Min
Typ
2.0
Max
Unit
3.6
V
0.8
V
2.4
Condition
V
IOH = –20mA (Note 2.)
0.5
V
IOL = 20mA (Note 2.)
Input Current
±120
µA
Note 3.
ICC
Maximum Core Supply Current
100
mA
ICCPLL
Maximum PLL Supply Current
20
mA
4
pF
15
CIN
Cpd
25
pF
Per Output
2. The MPC932 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
3. Inputs have pull–up/pull–down resistors which affect input current.
TIMING SOLUTIONS
BR1333 — REV 5
3
MOTOROLA
MPC932
MPC932 AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
fref
Input Reference Frequency
tos
Output-to-Output Skew
fVCO
VCO Lock Range
fmax
Maximum Output Frequency
tpd
Reference to EXT_FB Average Delay TCLK
PECL_CLK
tpw
Output Duty Cycle (Note 4.)
tr, tf
Output Rise/Fall Time (Note 4.)
tPLZ, tPHZ
Typ
Note 6.
Max
Unit
Note 6.
MHz
300
ps
480
MHz
120
96
80
MHz
200
200
(÷4)
(÷5)
(÷6)
Condition
Note 4.
X – 150
X
X + 150
ps
tCYCLE/2
–750
tCYCLE/2
±500
tCYCLE/2
+750
ps
0.1
1.0
ns
0.8 to 2.0V
Output Disable Time
2.0
8.0
ns
50Ω to VCC/2
tPZL
Output Enable Time
2.0
10
ns
50Ω to VCC/2
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
ps
Note 5.
±100
tlock
Maximum PLL Lock Time
10
4. Measured with 50Ω to VCC/2 termination.
5. See Applications Info section for more jitter information.
6. Input reference frequency is bounded by VCO lock range and feedback divide selection.
7. tpd measurement uses the averaging feature of the oscilliscope to remove the jitter component.
fref = 50MHz; Note 7.
ms
APPLICATIONS INFORMATION
MPC932
‘0’
‘0’
FBSEL0
FBSEL1
66MHz
Input Ref
MPC932
Qn
QFB
6
1
66MHz
‘1’
‘0’
FBSEL0
FBSEL1
66MHz
Input Ref
66MHz
QFB
FB_In
FBSEL0
FBSEL1
60MHz
Input Ref
6
1
83MHz
66MHz
FB_In
MPC932
‘1’
‘0’
Qn
MPC932
Qn
QFB
6
1
75MHz
‘0’
‘1’
FBSEL0
FBSEL1
66MHz
Input Ref
60MHz
Qn
QFB
FB_In
6
1
100MHz
66MHz
FB_In
Figure 2. MPC932 Potential Configurations
(Mode = 1)
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — REV 5
MPC932
adequate to eliminate power supply noise related problems
in most designs.
Power Supply Filtering
The MPC932 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC932 provides separate
power supplies for the output buffers (VCCO) and the internal
PLL (VCCA) of the device. The purpose of this design
technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC932.
Driving Transmission Lines
The MPC932 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC932 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 4 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC932 clock
driver is effectively doubled due to its capability to drive
multiple lines.
3.3V
RS=10–15Ω
VCCA
22µF
MPC932
0.01µF
VCC
0.01µF
MPC932
OUTPUT
BUFFER
Figure 3. Power Supply Filter
Figure 3 illustrates a typical power supply filter scheme.
The MPC932 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC932. From the data sheet the IVCCA current
(the current sourced through the VCCA pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.0V must be
maintained on the VCCA pin very little DC voltage drop can
be tolerated when a 3.3V VCC supply is used. The resistor
shown in Figure 3 must have a resistance of 10–15Ω to meet
the voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL.
IN
MPC932
OUTPUT
BUFFER
IN
RS = 43Ω
ZO = 50Ω
OutA
RS = 43Ω
ZO = 50Ω
OutB0
7Ω
RS = 43Ω
ZO = 50Ω
OutB1
Figure 4. Single versus Dual Transmission Lines
The waveform plots of Figure 5 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC932 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC932. The output waveform
in Figure 5 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43Ω series resistor plus the output
impedance does not match the parallel combination of the
Although the MPC932 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
TIMING SOLUTIONS
BR1333 — REV 5
7Ω
5
MOTOROLA
MPC932
line impedances. The voltage wave launched down the two
lines will equal:
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 6 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50Ω || 50Ω
Rs = 43Ω || 43Ω
Ro = 7Ω
VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5)
= 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
MPC932
OUTPUT
BUFFER
RS = 36Ω
ZO = 50Ω
RS = 36Ω
ZO = 50Ω
7Ω
3.0
VOLTAGE (V)
2.5
OutA
tD = 3.8956
OutB
tD = 3.9386
7Ω + 36Ω k 36Ω = 50Ω k 50Ω
25Ω = 25Ω
2.0
In
Figure 6. Optimized Dual Line Termination
1.5
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
1.0
0.5
0
2
4
6
8
TIME (nS)
10
12
14
Figure 5. Single versus Dual Waveforms
MOTOROLA
6
TIMING SOLUTIONS
BR1333 — REV 5
MPC932
OUTLINE DIMENSIONS
A
–T–, –U–, –Z–
FA SUFFIX
TQFP PACKAGE
CASE 873A-02
ISSUE A
4X
A1
32
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
AE
P
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
G
–AB–
0.10 (0.004) AC
AC T–U Z
–AC–
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
F
8X
M_
R
J
M
N
D
0.20 (0.008)
SEATING
PLANE
SECTION AE–AE
W
K
X
DETAIL AD
TIMING SOLUTIONS
BR1333 — REV 5
Q_
GAUGE PLANE
H
0.250 (0.010)
C E
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
MOTOROLA
MPC932
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8
MPC932/D
TIMING SOLUTIONS
BR1333 — REV 5
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