AD AD7628 Cmos dual 8-bit buffered multiplying dac Datasheet

a
FEATURES
On-Chip Latches for Both DACs
+12 V to +15 V Operation
DACs Matched to 1%
Four Quadrant Multiplication
TTL/CMOS Compatible from +12 V to +15 V
Latch Free (Protection Schottkys not Required)
CMOS Dual 8-Bit
Buffered Multiplying DAC
AD7628
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Disk Drives
Programmable Filters
X-Y Graphics
Gain/Attenuation
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7628 is a monolithic dual 8-bit digital/analog converter
featuring excellent DAC-to-DAC matching. It is available in
small 0.3" wide 20-pin DIPs and in 20-terminal surface mount
packages.
1. DAC to DAC matching: since both of the AD7628 DACs
are fabricated at the same time on the same chip, precise
matching and tracking between DAC A and DAC B is inherent. The AD7628’s matched CMOS DACs make a whole
new range of applications circuits possible, particularly in the
audio, graphics and process control areas.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
Data is transferred into either of the two DAC data latches via a
common 8-bit TTL/CMOS compatible input port. Control input DAC A/DAC B determines which DAC is to be loaded.
The AD7628’s load cycle is similar to the write cycle of a random access memory, and the device is bus compatible with most
8-bit microprocessors, including 6502, 6809, 8085, Z80.
The device operates from a +12 V to +15 V power supply and is
TTL-compatible over this range. Power dissipation is a low
20 mW.
2. Small package size: combining the inputs to the on-chip
DAC latches into a common data bus and adding a DAC A/
DAC B select line has allowed the AD7628 to be packaged in
a small 20-pin 0.3" wide DIP, 20-pin SOIC, 20-terminal
PLCC and 20-terminal LCC.
3. TTL-Compatibility: All digital inputs are TTL-compatible
over a +12 V to +15 V power supply range.
Both DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for
each DAC.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
= +10.8 V to +15.75 V, V
AD7628–SPECIFICATIONS (Votherwise
noted)
DD
REF
A = VREF B = +10 V; OUT A = OUT B = 0 V unless
Parameter
TA = +258C1
TA = –408C
to +858C
TA = –558C
to +1258C1
Units
STATIC PERFORMANCE 2
Resolution
Relative Accuracy
Differential Nonlinearity
8
± 1/2
±1
8
± 1/2
±1
8
± 1/2
±l
Bits
LSB max
LSB max
±2
±3
±3
LSB max
± 0.0035
± 0.0035
%/°C max
± 50
± 50
8
15
± 200
± 200
8
15
± 200
± 200
8
15
nA max
nA max
kΩ min
kΩ max
±1
±1
±1
% max
Gain Error
Gain Temperature Coefficient 3
∆Gain/∆Temperature
Output Leakage Current
OUT A (Pin 2)
OUT B (Pin 20)
Input Resistance (V REFA, VREFB)
VREFA/VREFB Input Resistance
Match
DIGITAL INPUTS 4
Input High Voltage (V IH)
Input Low Voltage (V IL)
Input Current (IIN)
Input Capacitance
DB0–DB7
WR, CS, DACA/DACB
2.4
0.8
±1
2.4
0.8
± 10
2.4
0.8
± 10
V min
V max
µA max
10
15
10
15
10
15
pF max
pF max
SWITCHING CHARACTERISTICS 3
See Timing Diagram
Chip Select to Write Set Up Time (t CS)
Chip Select to Write Hold Time (t CH)
DAC Select to Write Set Up Time (t AS)
DAC Select to Write Hold Time (t AH)
Data Valid to Write Set Up Time (t DS)
Data Valid to Write Hold Time (t DH)
Write Pulse Width (t WR)
160
10
160
10
160
10
150
160
10
160
10
160
10
170
210
10
210
10
210
10
210
ns min
ns min
ns min
ns min
ns min
ns min
ns min
POWER SUPPLY
IDD, K Grade
B, T Grades
All Grades
2
2
100
2
2.5
500
2.5
500
mA
mA
µA
Test Conditions/Comments
This is an Endpoint Linearity Specification
All Grades Guaranteed Monotonic Over
Full Operating Temperature Range
Measured Using Internal RFB A and RFB B.
Both DAC Latches Loaded with 11111111.
Gain Error is Adjustable Using Circuits
of Figures 4 and 5.
DAC Latches Loaded with 00000000
Input Resistance TC = –300 ppm/°C, Typical
Input Resistance is 11 kΩ
VIN = 0 or VDD
See Figure 3
All Digital Inputs V IL or VIH
All Digital Inputs V IL or VIH
All Digital Inputs 0 V or V DD
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance only and are not
subject to test. VDD = +10.8 V to +15.75 V. (Measured Using Recommended PC Board Layout (Figure 7) and AD644 as Output Amplifiers)
Parameter
TA = +258C1
TA = –408C
to +858C1
TA = –558C
to +1258πC1
Units
DC SUPPLY REJECTION
(∆GAIN/∆VDD)
0.01
0.02
0.02
% per % max ∆VDD = ± 5%
CURRENT SETTLING TIME
350
400
400
ns max
To 1/2 LSB OutA/OutB Load = 100 Ω.
WR = CS = 0 V.
DB0–DB7 = 0 V to V DD or VDD to 0 V
DIGITAL-TO-ANALOG GLITCH
IMPULSE
330
nV sec typ
For Code Transition 00000000 to 11111111
OUTPUT CAPACITANCE
COUTA
COUTB
COUTA
COUTB
25
25
60
60
25
25
60
60
25
25
60
60
pF max
pF max
pF max
pF max
DAC Latches Loaded with 00000000
AC FEEDTHROUGH
VREFA to OUT A
VREFB to OUT B
–70
–70
–65
–65
–65
–65
dB max
dB max
VREFA, V REFB = 20 V p-p Sine Wave
@ 10 kHz
CHANNEL-TO-CHANNEL ISOLATION
VREFA to OUT B
–80
VREFB to OUTA
dB typ
Test Conditions/Comments
DAC Latches Loaded with 11111111
Both DAC Latches Loaded with 11111111.
VREFA = 20 V p-p Sine Wave @ 10 kHz
VREFB = 0 V See Figure 6.
VREFB = 20 V p-p Sine Wave @ 10 kHz
VREFA = 0 V See Figure 6.
–80
dB typ
DIGITAL CROSSTALK
60
nV sec typ
Measured for Code Transition 00000000
to 11111111
HARMONIC DISTORTION
–85
dB typ
VIN = 6 V rms @ 1 kHz
NOTES
1
Temperature Ranges are K Version; –40°C to +85°C; B Version; –40°C to +85°C; T Version; –55°C to +125°C.
2
Specification applies to both DACs in AD7628.
3
Guaranteed by design but not production tested.
4
Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA.
Specifications subject to change without notice.
–2–
REV. A
AD7628
TERMINOLOGY
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
Relative Accuracy:
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V, VDD + 0.3 V
VPIN2, VPIN20 to AGND . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VREF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (K) Grades . . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B) Grades . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T) Grades . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after adjusting for zero and full-scale, and is normally expressed in
LSBs or as a percentage of full-scale reading.
Differential Nonlinearity:
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error:
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC latches after offset error has been adjusted out. Gain
error of both DACs is adjustable to zero with external resistance.
Output Capacitance:
ORDERING GUIDE
Capacitance from OUT A or OUT B to AGND.
Model1
Temperature
Range
Relative Gain
Accuracy Error
Package
Option2
AD7628KN
AD7628KP
AD7628KR
AD7628BQ
AD7628TQ
AD7628TE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
N-20
P-20A
R-20
Q-20
Q-20
E-20A
± 2 LSB
± 2 LSB
± 2 LSB
± 2 LSB
± 2 LSB
± 2 LSB
Digital-to-Analog Glitch Impulse:
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs,
depending upon whether the glitch is measured as a current or
voltage signal. Glitch impulse is measured with VREF A, VREF B
= AGND.
Channel-to-Channel Isolation:
The proportion of input signal from one DAC’s reference input
that appears at the output of the other DAC, expressed as a
ratio in dB.
NOTES
1
To order MIL-STD-883, Class B process parts, add /883B to part number.
Contact your local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = SOIC.
Digital Crosstalk:
The glitch energy transferred to the output of one converter due
to a change in digital input code to the other converter. Specified in nV secs.
PIN CONFIGURATIONS
LCCC
17 VDD
DGND
5
DB6
8
13 DB1
DB5
9
12 DB2
DB4 10
11 DB3
16 WR
DB7 (MSB) 7
15 CS
DB6 8
10 11 12 13
4
5
AD7628
17 VDD
DAC A/DAC B
6
16 WR
DB7 (MSB)
7
TOP VIEW
(Not to Scale)
DB6
8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7628 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
20 19
DGND
14 DB0 (LSB)
9
1
VREF A
DB1
14 DB0 (LSB)
TOP VIEW
(Not to Scale)
DB2
7
DAC A /DAC B 6
DB3
(MSB) DB7
17 VDD
DB5
6
16 WR
TOP VIEW
(Not to Scale) 15 CS
18 VREF B
AD7628
DGND 5
DB4
DAC A/DAC B
AD7628
VREF A 4
OUT B
4
2
RFB B
VREF A
3
18 VREF B
15 CS
14 DB0 (LSB)
9
10 11 12 13
DB1
18 VREF B
DB2
3
OUT A
RFB A
AGND
1 20 19
DB3
2
RFB A
3
DB5
OUT A
19 RFB B
DB4
20 OUT B
2
RFB B
1
OUT A
OUT B
AGND
AGND
PLCC
RFB A
DIP, SOIC
WARNING!
ESD SENSITIVE DEVICE
AD7628
INTERFACE LOGIC INFORMATION
DAC Selection
weighted currents are switched between the DAC output and
AGND, thus maintaining fixed currents in each ladder leg independent of switch state.
Both DAC latches share a common 8-bit input port. The control input DAC A/DAC B selects which DAC can accept data
from the input port.
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows an approximate equivalent circuit for one of
the AD7628’s D/A converters, in this case DAC A. A similar
equivalent circuit can be drawn for DAC B. Note that AGND
(Pin 1) is common for both DAC A and DAC B.
Mode Selection
Inputs CS and WR control the operating mode of the selected
DAC. See Mode Selection Table below.
Write Mode
The current source ILEAKAGE is composed of surface and junction leakages and, as with most semiconductor devices, approximately doubles every 10°C. The resistor Ro, as shown in Figure 2, is the equivalent output resistance of the device, which
varies with input code (excluding all 0s code) from 0.8R to 2R.
R is typically 11 kΩ. COUT is the capacitance due to the N-channel
switches and varies from about 50 pF to 120 pF, depending on
the digital input. g(VREF A, N) is the Thevenin equivalent voltage generator due to the reference input voltage VREF A and the
transfer function of the R-2R ladder.
When CS and WR are both low, the selected DAC is in the write
mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on DB0–DB7.
Hold Mode
The selected DAC latch retains the data that was present on
DB0–DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
Mode Selection Table
DAC A/
DAC B
CS
WR
DAC A
DAC B
L
H
X
X
L
L
H
X
L
L
X
H
WRITE
HOLD
HOLD
HOLD
HOLD
WRITE
HOLD
HOLD
For further information on CMOS multiplying D/A converters,
refer to “CMOS DAC Application Guide, 2ND Edition” available from Analog Devices, Publication Number G872a–15–4/86.
L = Low State, H = High State, X = Don’t Care
WRITE CYCLE TIMING DIAGRAM
Figure 2. Equivalent Analog Output Circuit of DAC A
CIRCUIT INFORMATION–DIGITAL SECTION
The input buffers are simple CMOS level-shifters designed so
that when the AD7628 is operated with VDD from 10.8 V to
15.75 V, the buffer converts TTL input levels (2.4 V and 0.8 V)
into CMOS logic levels. When VIN is in the region of 1.0 volt to
2.0 volts, the input buffers operate in their linear region and
pass a quiescent current (see Figure 3). To minimize power supply currents, it is recommended that the digital input voltages be as
close to the supply rails (VDD and DGND) as practicably possible.
The AD7628 may be operated with any supply voltage in the
range 10.8 ≤ VDD ≤ 15.75 volts.
CIRCUIT INFORMATION—D/A SECTION
The AD7628 contains two identical 8-bit multiplying D/A converters, DAC A and DAC B. Each DAC consists of a highly
stable thin film R-2R ladder and eight N-channel current steering
switches. A simplified D/A circuit for DAC A is shown in Figure
1. An inverted R-2R ladder structure is used; that is, binary
Figure 3. Typical Plot of Supply Current, IDD vs. Logic
Input Voltage VIN to VDD = +15 V
Figure 1. Simplified Functional Circuit for DAC A
–4–
REV. A
AD7628
Figure 4. Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication). See Table I.
Figure 5. Dual DAC Bipolar Operation (4 Quadrant Multiplication). See Table II.
Table II. Bipolar (Offset Binary) Code Table
Table I. Unipolar Binary Code Table
DAC Latch Contents
MSB
LSB
Analog Output
(DAC A or DAC B)
 255 
–V IN 

 256 
 129 
–V IN 

 256 
 128 
V IN
–V IN 
=– 2
 256 
 127 
–V IN 

 256 
 1 
–V IN 

 256 
 0 
–V IN 
 =0
 256 
11111111
10000001
10000000
01111111
00000001
00000000
NOTE: 1 LSB = (2–8)(VIN) =
( )
1
V IN
256
DAC Latch Contents
MSB
LSB
 127 
+V IN 

 128 
 1 
+V IN 

 128 
11111111
10000001
10000000
0
 1 
–V IN 

 128 
 127 
–V IN 

 128 
01111111
00000001
128

128
–V IN 
00000000
NOTE: 1 LSB = (2 –7)(VIN) =
Table III. Recommended Trim Resistor Values
REV. A
Analog Output
(DAC A or DAC B)
Trim
Resistor
K/B/T
R1; R3
R2; R4
500
150
–5–
(
1
V IN
128
)
AD7628
APPLICATIONS INFORMATION
Application Hints
Figure 7 shows a printed circuit layout for the AD7628 and the
AD644 dual op amp, which minimizes feedthrough and crosstalk.
To ensure system performance consistent with AD7628 specifications, careful attention must be given to the following points:
SINGLE SUPPLY APPLICATIONS
1. GENERAL GROUND MANAGEMENT: AC or transient
voltages between the AD7628 AGND and DGND can cause
noise injection into the analog output. The simplest method
of ensuring that voltages at AGND and DGND are equal is
to tie AGND and DGND together at the AD7628. In more
omplex systems where the AGND–DGND intertie is on the
backplane, it is recommended that diodes be connected in
inverse parallel between the AD7628 AGND and DGND
pins (1N914 or equivalent).
2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a
code-dependent output resistance which, in turn, causes a
code-dependent amplifier noise gain. The effect is a codedependent differential nonlinearity term at the amplifier
output that depends on VOS (VOS is amplifier input offset
voltage). This differential nonlinearity term adds to the R/2R
differential nonlinearity. To maintain monotonic operation, it
is recommended that amplifier VOS be no greater than 10% of
1 LSB over the temperature range of interest.
The AD7628 DAC R-2R ladder termination resistors are connected to AGND within the device. This arrangement is particularly convenient for single supply operation because AGND
may be biased at any voltage between DGND and VDD. Figure
8 shows a circuit that provides two +5 V to +8 V analog outputs
by biasing AGND +5 V up from DGND. The two DAC reference inputs are tied together and a reference input voltage is obtained without a buffer amplifier by making use of the constant
and matched impedances of the DAC A and DAC B reference
inputs. Current flows through the two DAC R-2R ladders into
R1, and R1 is adjusted until the VREF A and VREF B inputs are
at +2 V. The two analog output voltages range from +5 V to
+8 V for DAC codes 00000000 to l l l l l l l l .
3. HIGH FREQUENCY CONSIDERATIONS: The output
capacitance of a CMOS DAC works in conjunction with the
amplifier feedback resistance to add a pole to the open loop
response. This can cause ringing or oscillation. Stability can
be restored by adding a phase compensation capacitor in
parallel with the feedback resistor.
DYNAMIC PERFORMANCE
The dynamic performance of the two DACs in the AD7628 will
depend on the gain and phase characteristics of the output amplifiers, together with the optimum choice of the PC board layout and decoupling components. Figure 6 shows the relationship
between input frequency and channel-to-channel isolation.
Figure 8. AD7628 Single Supply Operation
Figure 9 shows DAC A of the AD7628 connected in a positive
reference, voltage switching mode. This configuration is useful
because VOUT is the same polarity as VIN, allowing single supply
operation. However, to retain specified linearity, VIN must be in
the range 0 V to +2.5 V and the output buffered or loaded with
a high impedance (see Figure 10). Note that the input voltage is
connected to the DAC OUT A, and the output voltage is taken
from the DAC VREF A pin.
Figure 6. Channel-to-Channel Isolation
Figure 9. AD7628 Single Supply, Voltage Switching Mode
Figure 7. Suggested PC Board Layout for AD7628 with
AD644 Dual Op Amp
Figure 10. Typical AD7628 Performance in Single Supply
Voltage Switching Mode
REV. A
–6–
AD7628
MICROPROCESSOR INTERFACE
Figure 11. AD7628 Dual DAC to 6800 CPU Interface
Figure 12. AD7628 Dual DAC to 8085 CPU Interface
PROGRAMMABLE WINDOW COMPARATOR
In the circuit of Figure 13, the AD7628 is used to implement a
programmable window comparator. DACs A and B are loaded
with the required upper and lower voltage limits for the test,
respectively. If the test input is not within the programmed limits, the pass/fail output will indicate a fail (logic zero).
Figure 13. Digitally Programmable Window Comparator
(Upper and Lower Limit Detector)
CIRCUIT EQUATIONS
PROGRAMMABLE STATE VARIABLE FILTER
C1 = C2, R1 = R2, R4 = R5
1
fC = 2 π R C
1 1
Q=
R3 . RF
R4 RFBB1
AO = –
RF
RS
NOTE
DAC equivalent resistance equals
(
256 × DAC Ladder resistance
)
DAC Digital Code
Figure 14. Digitally Controlled State Variable Filter
In this state, variable or universal filter configuration (Figure
14) for DACs A1 and B1 control the gain and Q of the filter
characteristic, while DACs A2 and B2 control the cutoff frequency, fC. DACs A2 and B2 must track accurately for the simple
expression for fC to hold. This is readily accomplished by the
AD7628. Op amps are 2 × AD644. C3 compensates for the
effects of op amp gain-bandwidth limitations.
REV. A
The filter provides low pass, high pass and band pass outputs
and is ideally suited for applications where microprocessor control of filter parameters is required, e.g., equalizer, tone controls, etc.
Programmable range for component values shown is fC = 0 kHz
to 15 kHz and Q = 0.3 to 4.5.
–7–
AD7628
DIGITALLY CONTROLLED DUAL
TELEPHONE ATTENUATOR
MECHANICAL INFORMATION
OUTLINE DIMENSIONS
In this configuration, the AD7628 functions as a 2-channel
digitally controlled attenuator; ideal for stereo audio and telephone signal level control applications. Table IV gives input
codes vs. attenuation for a 0 dB to 15.5 dB range.
Dimensions shown in inches and (mm).
C1029a–8–3/88
20-Pin Cerdip (Q Suffix)
 Attenuation, dB 

20


Input Code = 256 × 10 exp  −
20-Pin Plastic DIP (N Suffix)
Figure 15. Digitally Controlled Dual Telephone Attenuator
Table IV. Attenuation vs. DAC A, DAC B Code for the
Circuit of Figure 15
Code in
DAC Input
Decimal Attn. dB Code
Code in
Decimal
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
255
242
228
215
203
192
181
171
162
152
144
136
128
121
114
108
102
96
91
86
81
76
72
68
64
61
57
54
51
48
46
43
11111111
11110010
11100100
11010111
11001011
11000000
10110101
10101011
10100010
10011000
10010000
10001000
10000000
0111001
01110010
01101100
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
01100110
01100000
01011011
01010110
01010001
01001100
01001000
01000100
01000000
00111101
00111001
00110110
0011001
00110000
00101110
00101011
20-Terminal
Plastic Leaded
Chip Carrier (P Suffix)
–8–
PRINTED IN U.S.A.
DAC Input
Attn. dB Code
20-Terminal
Leadless Chip
Carrier (E Suffix)
REV. A
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