CY7C1012DV33 12-Mbit (512K X 24) Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 175 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 25 mA The CY7C1012DV33 is a high performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE1, CE2, and CE3). CE1 controls the data on the I/O0 – I/O7, while CE2 controls the data on I/O8 – I/O15, and CE3 controls the data on the data pins I/O16 – I/O23. This device has an automatic power down feature that significantly reduces power consumption when deselected. ■ Operating voltages of 3.3 ± 0.3V ■ 2.0V data retention ■ Automatic power down when deselected ■ TTL compatible inputs and outputs ■ Available in Pb-free standard 119-ball PBGA Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input and output (I/O) pins is then written into the location specified on the address pins (A0 – A18). Asserting all of the chip selects LOW and write enable LOW writes all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode. Data bytes are also individually read from the device. Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH, while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins appear on the specified data input and output (I/O) pins. Asserting all the chip selects LOW reads all 24 bits of data from the SRAM. The 24 I/O pins (I/O0 – I/O23) are placed in a high impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For more information, see the Truth Table on page 8. Logic Block Diagram 512K x 24 ARRAY COLUMN DECODER I/O0 – I/O7 SENSE AMPS A(9:0) ROW DECODER INPUT BUFFER I/O8 – I/O15 I/O16 – I/O23 CONTROL LOGIC CE1, CE2, CE3 WE OE A(18:10) Cypress Semiconductor Corporation Document Number: 38-05610 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 6, 2008 [+] Feedback CY7C1012DV33 Selection Guide Description –10 Unit Maximum Access Time 10 ns Maximum Operating Current 175 mA Maximum CMOS Standby Current 25 mA Pin Configuration Figure 1. 119-Ball PBGA (Top View) [1] 1 2 3 4 5 6 7 A NC A A A A A NC B NC A A CE1 A A NC C I/O12 NC CE2 NC CE3 NC I/O0 D I/O13 VDD VSS VSS VSS VDD I/O1 E I/O14 VSS VDD VSS VDD VSS I/O2 F I/O15 VDD VSS VSS VSS VDD I/O3 G I/O16 VSS VDD VSS VDD VSS I/O4 H I/O17 VDD VSS VSS VSS VDD I/O5 J NC VSS VDD VSS VDD VSS NC K I/O18 VDD VSS VSS VSS VDD I/O6 L I/O19 VSS VDD VSS VDD VSS I/O7 M I/O20 VDD VSS VSS VSS VDD I/O8 N I/O21 VSS VDD VSS VDD VSS I/O9 P I/O22 VDD VSS VSS VSS VDD I/O10 R I/O23 A NC NC NC A I/O11 T NC A A WE A A NC U NC A A OE A A NC Note 1. NC pins are not connected on the die. Document Number: 38-05610 Rev. *D Page 2 of 11 [+] Feedback CY7C1012DV33 Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage............. ...............................>2001V Storage Temperature ................................. –65°C to +150°C Latch Up Current ..................................................... >200 mA Ambient Temperature with Power Applied ............................................ –55°C to +125°C Operating Range (MIL-STD-883, Method 3015) Supply Voltage on VCC Relative to GND [2] ....–0.5V to +4.6V Range DC Voltage Applied to Outputs in High-Z State [2] .................................. –0.5V to VCC + 0.5V Ambient Temperature VCC Industrial –40°C to +85°C 3.3V ± 0.3V DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions [3] VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA –10 Min Unit Max 2.4 V 0.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3 V VIL[2] Input LOW Voltage –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 μA IOZ Output Leakage Current GND < VOUT < VCC, output disabled –1 +1 μA ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC IOUT = 0 mA CMOS levels 175 mA ISB1 Automatic CE Power Down Max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Current —TTL Inputs Automatic CE Power Down Max VCC, CE > VCC – 0.3V, Current —CMOS Inputs VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 30 mA 25 mA ISB2 Notes 2. VIL (min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 or CE2 , or CE3 is LOW. When HIGH, CE indicates the CE1 , CE2 , and CE3 are HIGH. Document Number: 38-05610 Rev. *D Page 3 of 11 [+] Feedback CY7C1012DV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max Unit 8 pF 10 pF 119-Ball PBGA Unit 20.31 °C/W 8.35 °C/W Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (junction to ambient) ΘJC Thermal Resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board Figure 2. AC Test Loads and Waveforms[4] 50Ω Z0 = 50Ω R1 317 Ω 3.3V VTH = 1.5V OUTPUT OUTPUT 30 pF* R2 351Ω 5 pF* *Including jig and scope (a) (b) *Capacitive Load consists of all components of the test environment All input pulses 3.0V GND 90% 10% 90% 10% Fall Time:> 1V/ns Rise Time > 1V/ns (c) Note 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100μs (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document Number: 38-05610 Rev. *D Page 4 of 11 [+] Feedback CY7C1012DV33 AC Switching Characteristics Over the Operating Range [5] Parameter Description –10 Min Max Unit Read Cycle tpower [6] VCC(Typical) to the First Access 100 μs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE tDOE tLZOE 10 ns CE Active LOW to Data Valid [3] 10 ns OE LOW to Data Valid 5 ns OE LOW to Low Z [7] OE HIGH to High Z tLZCE CE Active LOW to Low Z [3, 7] tPU tPD ns 1 [7] tHZOE tHZCE 3 ns 5 CE Deselect HIGH to High Z [3, 7] CE Active LOW to Power Up [3, 8] CE Deselect HIGH to Power Down 3 ns 5 0 [3, 8] ns ns ns 10 ns Write Cycle [9, 10] tWC Write Cycle Time [3] 10 ns 7 ns tSCE CE Active LOW to Write End tAW Address Setup to Write End 7 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Setup to Write End 5.5 ns tHD Data Hold from Write End 0 ns 3 ns tLZWE tHZWE WE HIGH to Low Z [7] WE LOW to High Z [7] 5 ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in part a) of Figure 2, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 7. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of Figure 2. Transition is measured ±200 mV from steady state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal write time of the memory is defined by the overlap of CE1 or CE2 or CE3 LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate a write. The transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05610 Rev. *D Page 5 of 11 [+] Feedback CY7C1012DV33 Data Retention Characteristics Over the Operating Range Parameter Conditions [3] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR [11] Chip Deselect to Data Retention Time tR [12] Operation Recovery Time Min Typ Max Unit 25 mA 2 V VCC = 2V, CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V 3.0V VDR > 2V tCDR tR CE Switching Waveforms Figure 3. Read Cycle No. 1 [13, 14] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [3, 14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE DATA OUT HIGH IMPEDANCE DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% ICC 50% ISB Notes 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 μs or stable at VCC(min) > 50 μs. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE transition LOW. Document Number: 38-05610 Rev. *D Page 6 of 11 [+] Feedback CY7C1012DV33 Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (CE Controlled) [3, 16, 17] tWC ADDRESS tSCE CE tSCE tSA tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD tHZOE DATA I/O tHD DATAIN VALID NOTE 18 Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 18 tHD DATA VALID tHZWE tLZWE Notes 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 18. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 38-05610 Rev. *D Page 7 of 11 [+] Feedback CY7C1012DV33 Truth Table CE1 CE2 CE3 OE WE Mode Power H H H X X High Z High Z High Z Power Down Standby (ISB) L H H L H Data Out High Z High Z Read Active (ICC) H L H L H High Z Data Out High Z Read Active (ICC) H H L L H High Z High Z Data Out Read Active (ICC) L L L L H Full Data Out Full Data Out Full Data Out Read Active (ICC) L H H X L Data In High Z High Z Write Active (ICC) H L H X L High Z Data In High Z Write Active (ICC) H H L X L High Z High Z Data In Write Active (ICC) L L L X L Full Data In Full Data In Full Data In Write Active (ICC) L L L H H High Z High Z High Z Selected, Active (ICC) Outputs Disabled Document Number: 38-05610 Rev. *D I/O0 – I/O7 I/O8 – I/O15 I/O16 – I/O23 Page 8 of 11 [+] Feedback CY7C1012DV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1012DV33-10BGXI Package Name Package Type Operating Range 51-85115 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free) Industrial Package Diagram Figure 8. 119-Ball PBGA (14 x 22 x 2.4 mm) 51-85115-*B Document Number: 38-05610 Rev. *D Page 9 of 11 [+] Feedback CY7C1012DV33 Document History Page Document Title: CY7C1012DV33 12-Mbit (512K X 24) Static RAM Document Number: 38-05610 Rev. ECN No. Orig. of Change Submission Date ** 250650 SYT See ECN New data sheet *A 469517 NXR See ECN Converted from Advance Information to Preliminary Corrected typo in the Document Title Removed –10 and –12 speed bins from product offering Changed J7 Ball of BGA from DNU to NC Removed Industrial Operating range from product offering Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page 3 Changed ICC(Max) from 220 mA to 150 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot specification in footnote 1 Updated the Truth Table Updated the Ordering Information table *B 499604 NXR See ECN Added note 1 for NC pins Changed ICC specification from 150 mA to 185 mA Updated Test Condition for ICC in DC Electrical Characteristics table Added note for tACE, tLZCE, tHZCE, tPU, tPD, and tSCE in AC Switching Characteristics Table on page 4 *C 1462585 VKN See ECN Converted from preliminary to final Updated block diagram Changed ICC specification from 185 mA to 225 mA Updated thermal specs *D 2604677 VKN/PYRS 11/12/08 Removed Commercial operating range, Added Industrial operating range Removed 8 ns speed bin, Added 10 ns speed bin, Modified footnote# 3 Document Number: 38-05610 Rev. *D Description of Change Page 10 of 11 [+] Feedback CY7C1012DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05610 Rev. *D Revised November 6, 2008 Page 11 of 11 All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback