ams AS1106PL 8-digit led display driver Datasheet

a u s t ri a m i c r o s y s t e m s
A S 11 0 6 , A S 11 0 7
D a ta S he e t
8-Digit LED Display Drivers
1 General Description
2 Key Features
The AS1106 and the AS1107 are compact display drivers for 7-segment numeric displays of up to 8 digits. The
devices can be programmed via SPI, QSPI, and Microwire as well as a conventional 4-wire serial interface.
!
!
!
The devices include an integrated BCD code-B/HEX
decoder, multiplex scan circuitry, segment and display
drivers, and a 64-bit memory. Internal memory stores
the LED settings, eliminating the need for continuous
device reprogramming.
!
!
!
Every segment can be individually addressed and
updated separately. Only one external resistor (RSET) is
required to set the current through the LED display. LED
brightness can be controlled by analog or digital means.
The devices can be programmed to use the internal
code-B/HEX decoder to display numeric digits or to
directly address each segment.
!
!
!
!
!
The AS1106 and the AS1107 feature an extremely low
shutdown current of typically 3µA, and an operational
current of less than 500µA. The number of digits can be
programmed, the devices can be reset by software, and
an external clock is also supported. Additionally, segment blinking can be synchronized across multiple drivers.
!
!
!
10MHz SPI-, QSPI-, Microwire-Compatible
Serial I/O
Individual LED Segment Control
Segment Blinking Control (can be synchronized
across multiple drivers)
Hexadecimal- or BCD-Code/No-Decode Digit
Selection
3µA Low-Power Shutdown Current (typ; data
retained)
Extremely Low Operating Current 0.5mA in OpenLoop
Digital and Analog Brightness Control
Display Blanked on Power-Up
Drive Common-Cathode LED Displays
Low-EMI Low Slew-Rate Limited Segment
Drivers (AS1107)
Supply Voltage Range: 2.7 to 5.5V
Software Reset
Optional External Clock
Packages:
- 24-pin DIP
- 24-pin SOIC
3 Applications
Several test modes are available for easy application
debugging.
The AS1106 and AS1107 are ideal for bar-graph displays, instrument-panel meters, LED matrix displays, dot
matrix displays, set-top boxes, white goods, professional
audio equipment, medical equipment, industrial controllers and panel meters.
The devices are available in 24-pin DIP and 24-pin
SOIC packages.
Figure 1. Typical Application Diagram
+5V
9.53kΩ
I/O
I/O
SCK
Microprocessor
VDD
8 Digits
ISET
DIG0 to
DIG7
DIN
LOAD/CSN
AS1106/
AS1107
CLK
8 Segments
SEG A to G
SEP DP
GND
GND
8-Digit Microprocessor Display
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Data Sheet
4 Absolute Maximum Ratings
Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Section 5 Electrical
Characteristics on page 3 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 1. Absolute Maximum Ratings
Parameter
Min
Max
Units
VDD
-0.3
7
V
DIN, CLK, LOAD/CSN
-0.3
7
V
-0.3
7 or
VDD + 0.3
V
DIG 0:DIG 7 Sink Current
500
mA
SEG A:SEG G, SEG DP
100
mA
Narrow plastic DIP
1066
mW
Derate 13.3mW/ºC
above +70ºC
Wide SOIC
941
mW
Derate 11.8mW/ºC
above +70ºC
Voltage (with respect to GND)
All other pins
Current
Continuous Power Dissipation
(TAMB = +85ºC)
Operating Temperature
Ranges (TMIN toTMAX)
AS1106PL, AS1106WL
0
+70
ºC
AS1106PE, AS1106WE
-40
+85
ºC
AS1107PL, AS1107WL
0
+70
ºC
-65
+150
ºC
+260
ºC
+260
ºC
Storage Temperature Range
Package Body Temperature (Wide SOIC)
Soldering Temperature (Narrow DIP)
1
2
Humidity
Electrostatic Discharge
3
85
%
Digital outputs
5
1000
V
All other pins
1000
V
4
±200
mA
Latch-Up Immunity
Notes
Non-condensing
All pins except AS1106
pin 14: ±180 mA
1. The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020C
“Moisture/Reflow Sensitivity Classification for non-hermetic Solid State Surface Mount Devices”.
2. Specified according JESD22-B106 “Resistance to Soldering Temperature for Through-Hole Mounted Devices”.
3. Norm: MIL 883 E method 3015.
4. Norm: JEDEC 17.
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AS1106, AS1107
Data Sheet
5 Electrical Characteristics
Conditions: VDD = 2.7 to 5.5V, RSET = 9.53kΩ±1%, TAMB = TMIN to TMAX (unless otherwise specified).
Table 2. Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operating Supply Voltage
VDD
2.7
5.0
5.5
V
Shutdown Supply Current
IDDSD
All digital inputs at VDD or
GND, TAMB = +25ºC
10
µA
Operating Supply Current
IDD
RSET = open circuit.
1
mA
All segments and decimal
point on; ISEG = -40mA.
330
Display Scan Rate
fOSC
8 digits scanned
500
Digit Drive Sink Current
IDIGIT
VOUT = 0.65V
320
800
1300
Segment Drive Source Current
ISEG
VDD = 5.0V, VOUT = (VDD -1V)
-30
-40
-45
mA
Segment Current Slew Rate
(AS1107 only)
ΔISEG/Δt
TAMB = +25ºC, VDD = 5.0V,
VOUT = (VDD -1V)
10
20
50
mA/µs
Segment Drive Current Matching
ΔISEG
Digit Drive Leakage
(AS1107 only)
IDIGIT
Digit off, VDIGIT = VDD
-10
µA
Segment Drive Leakage
(AS1107 only)
ISEG
Segment off, VSEG = 0V
1
µA
Digit Drive Source Current
(AS1106 only)
IDIGIT
Digit off, VDIGIT = (VDD - 0.3V)
-2
mA
Segment Drive Sink Current
(AS1106 only)
ISEG
Segment off, VSEG = 0.3V
5
mA
Slow Segment Blink Period (ON
phase, Internal Oscillator)
tSLOWBLINK
0.64
1
1.65
s
Fast Segment Blink Period
(ON phase, Internal Oscillator)
tFASTBLINK
0.32
0.5
0.83
s
49.9
50
50.1
%
Conditions
Min
Typ
Max
Unit
VIN = 0V or VDD
-1
1
µA
3.0
Fast or Slow Segment Blink Duty
Cycle (Guaranteed by design)
Hz
mA
%
Table 3. Logic Inputs/Outputs Characteristics
Parameter
Input Current DIN, CLK, LOAD/CSN
Symbol
IIH, IIL
Logic High Input Voltage
VIH
Logic Low Input Voltage
Output High Voltage
VIL
VOH
0.7 x VDD
0.8
VDD = 3.0V ± 10%
0.6
DOUT, ISOURCE = -1mA,
VDD = 5.0V ± 10%
VDD - 1
DOUT, ISOURCE = -1mA,
VDD = 3.0V ± 10%
VDD - 0.5
Output Low Voltage
VOL
DOUT, ISINK = 1.6mA
Hysteresis Voltage
ΔVI
DIN, CLK, LOAD/CSN
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V
VDD = 5.0V ± 10%
Revision 2.2
V
V
0.4
1
V
V
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AS1106, AS1107
Data Sheet
Table 4. Timing Characteristics
Parameter
CLK Clock Period
CLK Pulse Width High
CLK Pulse Width Low
CSM Fall to CLK Rise Setup Time
(AS1107 or AS1106 SPI-programmed)
CLK Rise to LOAD/CSN Rise
Hold Time
DIN Setup Time
DIN Hold Time
Output Data Propagation Delay
LOAD Rising Edge to Next Clock Rising
Edge (AS1106 only)
Minimum LOAD/CSN Pulse High
Data-to-Segment Delay
Symbol
tCP
tCH
tCL
Conditions
Min
100
50
50
Typ
Max
Unit
ns
ns
ns
tCSS
25
ns
tCSH
0
ns
tDS
tDH
tDO
25
0
ns
ns
ns
CLOAD = 50pF
25
tLDCK
50
tCSW
tDSPD
50
ns
2.25
ns
ms
Note: See Figure 11 on page 7 for more information.
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AS1106, AS1107
Data Sheet
6 Typical Operating Characteristics
VDD = 5V, RSET = 9.53kΩ, TAMB = 25ºC (unless otherwise specified).
Figure 2. Scan Frequency vs.Temperature
Figure 3. Scan Frequency vs. VDD
990
980
980
970
960
FOSC (Hz)
FOSC (Hz)
970
960
950
950
940
930
920
940
910
930
900
-40
-20
0
20
40
60
80
2
3
4
Figure 4. ISEG vs. Temperature
60
VDD = 5V, VOUT = 2.4V
50
40
VDD = 5V, VOUT = 4V
35
40
30
25
ISEG (mA)
ISEG (mA)
6
Figure 5. ISEG vs. VDD
50
45
5
VDD (V)
TAMB [°C]
VDD = 2.7V, VOUT = 2V
20
VOUT = 1.7V
30
VOUT = 4V
20
15
VDD = 2.7V, VOUT = 2.4V
10
VOUT = 2.4V
10
5
0
0
-40
-20
0
20
40
60
2
80
45
45
40
40
35
35
30
30
ISEG (mA)
ISEG (mA)
50
4.5
5
5.5
6
25
20
15
15
10
10
5
5
0
4
Intensity = 15/16 (0Fh)
50
20
3.5
Figure 7. AS1107 Segment Output Current
Intensity = 31/32 (0Fh)
25
3
VDD (V)
TAMB (°C)
Figure 6. AS1106 Segment Output Current
2.5
0
0.0
5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0
0.0
Time (µs)
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5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0
Time (µs)
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AS1106, AS1107
Data Sheet
Figure 8. ISEG vs. VOUT
Figure 9. ISEG vs. VOUT
VDD = 2.7V
50
25
RSET = 10kΩ
45
RSET = 10kΩ
40
20
30
25
ISEG (mA)
ISEG (mA)
35
RSET = 20kΩ
20
15
RSET = 20kΩ
10
15
RSET = 40kΩ
10
5
RSET = 40kΩ
5
0
0
0 0.5
1 1.5
2 2.5 3 3.5
VOUT (V)
4 4.5
0
5
0.5
1
1.5
2
2.5
VOUT (V)
Figure 10. ISEG vs. RSET
60
VOUT = 2.4V
50
ISEG (mA)
40
30
VOUT
= 4V
VOUT = 2V
20
VDD = 5V
10
VOUT = 1.7V
0
0
10
20
VDD = 2.7V
30
40
50
60
70
80
RSET (k Ω)
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AS1106, AS1107
Data Sheet
AS1106 vs. AS1107
7 Detailed Description
AS1106 vs. AS1107
The AS1106 and AS1107 are identical except for two features:
!
The AS1107 segment drivers are slew-rate limited to reduce electromagnetic interference (EMI).
!
The AS1107 serial interface is fully SPI compatible (programmable for AS1106).
Serial-Addressing Format
Programming the AS1106/AS1107 is done by writing to the device’s internal registers (see Digit- and Control-Registers
on page 8) via the 4-wire serial interface. A programming sequence consists of 16-bit packages as listed in Table 5.
The data is shifted into the internal 16-bit register with the rising edge of the CLK signal. With the rising edge of the
LOAD/CSN signal the data is latched into a digit- or control-register. The LOAD/CSN signal must go high after the 16th
rising clock edge.
The LOAD/CSN signal can also come later but this must happen just before the next rising edge of CLK, otherwise the
data will be lost. The contents of the internal shift register are applied 16.5 clock cycles later to pin DOUT. The data is
clocked out at the falling edge of CLK.
The first 4 bits (D15:D12) are “don't care”, bits D11:D8 contain the register address, and bits D7:D0 contain the data.
The first bit is D15, the most significant bit (MSB). The exact timing is shown in Figure 11.
Table 5. 16-Bit Serial Data Format
D15
X
D14
X
D13
X
D12
X
D11
D10
D9
D8
D7
Register Address (see Table 6) MSB
D6
D5
D4
D3
Data
D2
D1
D0
LSB
Initial Power-Up
On initial power-up, the AS1106/AS1107 registers are reset to their default values, the display is blanked, and the
device goes into shutdown mode. At this time, all registers should be programmed for normal operation.
Note: The default settings enable only scanning of one digit; the internal decoder is disabled and the Intensity Control
Register (see page 11) is set to the minimum values.
Figure 11. Interface Timing
LOAD/
CSN
tCSW
tCSH
tCP
tCSS
CLK
tCL
tLDCK
tCH
tDH
tDS
DIN
D15
D14
D1
D0
tDO
DOUT
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AS1106, AS1107
Data Sheet
Shutdown Mode
Shutdown Mode
The AS1106/AS1107 devices feature a shutdown mode, where they consume only 10µA (max) current. Shutdown
mode is entered via a write to the Shutdown Register (see Table 7). For the AS1106, at that point, all segment current
sources are pulled to ground and all digit drivers are connected to VDD, so that all segments are blanked. The AS1107
behavior is identical except the drivers are high impedance.
Note: During shutdown mode the Digit-Registers maintain their data.
Shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display
(repeatedly entering and leaving shutdown mode). For minimum supply current in shutdown mode, logic input should
be at GND or VDD (CMOS logic level).
The devices need typically 250µs to exit shutdown mode, and during shutdown mode the AS1106/AS1107 is fully programmable. Only the display test mode (see page 10) overrides shutdown mode.
When entering or leaving shutdown mode, the Feature Register is reset to its default values (all 0s) when Shutdown
Register bit D7 (page 9) = 0.
1
Note: If the AS1106/AS1107 is used with an external clock, Shutdown Register bit D7 should be set to 1 when writing
to the Shutdown Register.
Digit- and Control-Registers
The AS1106/AS1107 devices contain 8 Digit-Registers and 6 control-registers, which are listed in Table 6. All registers
are selected using a 4-bit address word, and communication is done via the serial interface.
!
Digit Registers – These registers are realized with an on-chip 64-bit memory. Each digit can be controlled directly
without rewriting the whole register contents.
!
Control Registers – These registers consist of decode mode, display intensity, number of scanned digits, shutdown, display test and features selection registers.
Table 6. Register Address Map
Register
HEX Code
No-Op
Address
Page
D15:D12
D11
D10
D9
D8
0xX0
X
0
0
0
0
12
Digit 0
0xX1
X
0
0
0
1
N/A
Digit 1
0xX2
X
0
0
1
0
N/A
Digit 2
0xX3
X
0
0
1
1
N/A
Digit 3
0xX4
X
0
1
0
0
N/A
Digit 4
0xX5
X
0
1
0
1
N/A
Digit 5
0xX6
X
0
1
1
0
N/A
Digit 6
0xX7
X
0
1
1
1
N/A
Digit 7
0xX8
X
1
0
0
0
N/A
Decode-Mode
0xX9
X
1
0
0
1
9
Intensity Control
0xXA
X
1
0
1
0
11
Scan Limit
0xXB
X
1
0
1
1
11
Shutdown
0xXC
X
1
1
0
0
9
N/A
0xXD
X
1
1
0
1
N/A
Feature
0xXE
X
1
1
1
0
12
Display Test
0xXF
X
1
1
1
1
10
1. When Shutdown Register bit D7 = 1, the Feature Register is left unchanged when entering or leaving shutdown mode.
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AS1106, AS1107
Data Sheet
Digit- and Control-Registers
Shutdown Register (0xXC)
The Shutdown Register controls AS1106/AS1107 shutdown mode (see Shutdown Mode on page 8).
Table 7. Shutdown Register Format (Address (HEX) = 0xXC))
Mode
HEX Code
Shutdown Mode,
Reset Feature Register to Default Settings
Shutdown Mode, Feature Register Unchanged
Normal Operation,
Reset Feature Register to Default Settings
Normal Operation, Feature Register Unchanged
Register Data
D7
D6
D5
D4
D3
D2
D1
D0
0x00
0
X
X
X
X
X
X
0
0x80
1
X
X
X
X
X
X
0
0x01
0
X
X
X
X
X
X
1
0x81
1
X
X
X
X
X
X
1
Decode Enable Register (0xX9)
The Decode Enable Register sets the decode mode. BCD/HEX decoding (either BCD code – characters 0:9, E, H, L,
P, and -, or HEX code – characters 0:9 and A:F) is selected by bit D2 (page 12) of the Feature Register. The Decode
Enable Register is used to select the decode mode or no-decode for each digit. Each bit in the Decode Enable Register corresponds to its respective display digit (i.e., bit D0 corresponds to digit 0, bit D1 corresponds to digit 1 and so
on). Table 9 lists some examples of the possible settings for the Decode Enable Register bits.
Note: A logic high enables decoding and a logic low bypasses the decoder altogether.
When decode mode is used, the decoder looks only at the lower-nibble (bits D3:D0) of the data in the Digit-Registers,
disregarding bits D6:D4. Bit D7 sets the decimal point (SEG DP) independent of the decoder and is positive logic (bit
D7 = 1 turns the decimal point on). Table 9 lists the code-B font; Table 10 lists the HEX font.
When no-decode mode is selected, data bits D7:D0 of the Digit-Registers correspond to the segment lines of the
AS1106/AS1107. Table 11 shows the 1:1 pairing of each data bit to the appropriate segment line.
Table 8. Decode Enable Register Format (Address (HEX) = 0xX9))
Decode Mode
HEX Code
No decode for digits 7:0
Code-B/HEX decode for digit 0. No decode for digits 7:1
Code-B/HEX decode for digits 3:0. No decode for digits 7:4
Code-B/HEX decode for digits 7:0
0x00
0x01
0x0F
0xFF
D7
0
0
0
1
D6
0
0
0
1
Register Data
D5 D4 D3 D2
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
D1
0
0
1
1
D0
0
1
1
1
F
1
0
0
0
1
G
0
0
1
1
1
Figure 12. Standard 7-Segment LED Intensity Control and Inter-Digit Blanking
A
F
G
B
C
E
D
DP
Table 9. Code-B Font
7-Segment
Character
Register Data
D7
†
0
1
2
3
4
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D6:D4
X
X
X
X
X
D3
0
0
0
0
0
D2
0
0
0
0
1
On Segments = 1
D1
0
0
1
1
0
D0
0
1
0
1
0
Revision 2.2
DP
†
A
1
0
1
1
0
B
1
1
1
1
1
C
1
1
0
1
1
D
1
0
1
1
0
E
1
0
1
0
0
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AS1106, AS1107
Data Sheet
Digit- and Control-Registers
Table 9. Code-B Font (Continued)
Register Data
7-Segment
Character
D7
†
5
6
7
8
9
E
H
L
P
Blank
†
D6:D4
X
X
X
X
X
X
X
X
X
X
X
D3
0
0
0
1
1
1
1
1
1
1
1
D2
1
1
1
0
0
0
0
1
1
1
1
On Segments = 1
D1
0
1
1
0
0
1
1
0
0
1
1
D0
1
0
1
0
1
0
1
0
1
0
1
DP
†
A
1
1
1
1
1
0
1
0
0
1
0
B
0
0
1
1
1
0
0
1
0
1
0
C
1
1
1
1
1
0
0
1
0
0
0
D
1
1
0
1
1
0
1
0
1
0
0
E
0
1
0
1
0
0
1
1
1
1
0
F
1
1
0
1
1
0
1
1
1
1
0
G
1
1
0
1
1
1
1
1
0
1
0
The decimal point is enabled by setting bit D7 = 1.
Table 10. HEX Font
7-Segment
Character
Register Data
D7
0
1
2
3
4
5
6
7
8
9
A
b
C
d
E
F
†
†
D6:D4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
On Segments = 1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DP
†
A
1
0
1
1
0
1
1
1
1
1
1
0
1
0
1
1
B
1
1
1
1
1
0
0
1
1
1
1
0
0
1
0
0
C
1
1
0
1
1
1
1
1
1
1
1
1
0
1
0
0
D
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
0
E
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
F
1
0
0
0
1
1
1
0
1
1
1
1
1
0
1
1
G
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
The decimal point is enabled by setting bit D7 = 1.
Table 11. No-Decode Mode Data Bits and Corresponding Segment Lines
Corresponding Segment Line
D7
DP
D6
A
D5
B
D4
C
D3
D
D2
E
D1
F
D0
G
Display-Test Register (0xXF)
The AS1106/AS1107 devices can operate in two modes: normal mode and display test mode. In display test mode all
LEDs are switched on at maximum brightness (duty cycle is 15/16 (AS1106) or 31/32 (AS1107). The devices remain in
display-test mode until the Display-Test Register is set for normal operation.
Note: All settings of the digit- and control-registers are maintained.
Table 12. Display-Test Register Format (Address (HEX) = 0xXF))
Mode
Normal Operation
Display Test Mode
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D7
X
X
D6
X
X
Revision 2.2
D5
X
X
Register Data
D4
D3
X
X
X
X
D2
X
X
D1
X
X
D0
0
1
10 - 20
austriam i c r o systems
AS1106, AS1107
Data Sheet
Digit- and Control-Registers
Intensity Control Register (0xXA)
The brightness of the display can be controlled by digital means using the Intensity Control Register and by analog
means using RSET (see Selecting RSET Resistor Value and Using External Drivers on page 13).
Display brightness is controlled by an integrated pulse-width modulator which is controlled by the lower-nibble of the
Intensity Control Register. The modulator scales the average segment-current in 16 steps from a maximum of 31/32
down to 1/32 (15/16 to 1/16 for the AS1107) of the peak current set by RSET.
Table 13. Intensity Register Format (Address (HEX) = 0xXA))
Duty Cycle
AS1106
AS1107
1/32 (min on)
1/16 (min on)
3/32
2/16
5/32
3/16
7/32
4/16
9/32
5/16
11/32
6/16
13/32
7/16
15/32
8/16
17/32
9/16
19/32
10/16
21/32
11/16
23/32
12/16
25/32
13/16
27/32
14/16
29/32
15/16
31/32 (max on) 15/16 (max on)
HEX Code
0xX0
0xX1
0xX2
0xX3
0xX4
0xX5
0xX6
0xX7
0xX8
0xX9
0xXA
0xXB
0xXC
0xXD
0xXE
0xXF
D7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register Data
D4
D3
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Scan-Limit Register (0x0B)
The Scan-Limit Register controls which of the digits are to be displayed. When all 8 digits are to be displayed, the
update frequency is typically 800Hz. If the number of digits displayed is reduced, the update frequency is increased.
The frequency can be calculated using 8fOSC/N, where N is the number of digits. Since the number of displayed digits
influences the brightness, RSET should be adjusted accordingly. Table 15 lists the maximum allowed current when
fewer than 4 digits are used.
Note: To avoid differences in brightness this register should not be used to blank parts of the display (leading zeros).
Table 14. Scan-Limit Register Format (Address (HEX) = 0xXB))
Scan Limit
HEX Code
Display digit 0 only (see Table 15)
Display digits 0:1 (see Table 15)
Display digits 0:2 (see Table 15)
Display digits 0:3
Display digits 0:4
Display digits 0:5
Display digits 0:6
Display digits 0:7
0xX0
0xX1
0xX2
0xX3
0xX4
0xX5
0xX6
0xX7
D7
X
X
X
X
X
X
X
X
D6
X
X
X
X
X
X
X
X
D5
X
X
X
X
X
X
X
X
Register Data
D4
D3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
Table 15. Maximum Segment Current for 1-, 2-, or 3-Digit Displays
Number of Digits Displayed
1
2
3
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Maximum Segment Current (mA)
10
20
30
Revision 2.2
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AS1106, AS1107
Data Sheet
Digit- and Control-Registers
Feature Register (0xXE)
The Feature Register is used for enabling various features including switching the device into external clock mode,
applying an external reset, selecting code-B or HEX decoding, enabling or disabling blinking, enabling or disabling the
SPI-compatible interface (AS1106 only), setting the blinking rate, and resetting the blink timing.
Note: At power-up the Feature Register is initialized to 0.
Table 16. Feature Register Summary
D7
blink_
start
D6
D5
D4
D3
D2
D1
D0
sync
blink_
freq_sel
blink_en
spi_en
decode_sel
reg_res
clk_en
Table 17. Feature Register Bit Descriptions (Address (HEX) = 0xXE))
Feature Register
Enables and disables various device features.
Bit Name
Default
Access
Bit Description
External clock active.
clk_en
0
R/W
0 = Internal oscillator is used for system clock.
1 = Pin CLK of the serial interface operates as system clock input.
Resets all control registers except the Feature Register.
0 = Reset Disabled. Normal operation.
reg_res
1 = All control registers are reset to default state (except the Feature
0
R/W
Register) identically after power-up.
Note: The Digit Registers maintain their data.
Selects display decoding.
0 = Enable Code-B decoding (see Table 9 on page 9).
decode_sel
0
R/W
1 = Enable HEX decoding (see Table 10 on page 10).
Enables the SPI-compatible interface.
0 = Disable SPI-compatible interface (AS1106 only).
spi_en
0
R/W
1 = Enable the SPI-compatible interface (AS1106 only).
Note: The SPI-compatible interface is always enabled in the AS1107.
Enables blinking.
blink_en
0 = Disable blinking.
0
R/W
1 = Enable blinking.
Sets blink with low frequency (with the internal oscillator enabled):
0 = Blink period typically is 1 second (0.5s on, 0.5s off).
blink_freq_sel
0
R/W
1 = Blink period is 2 seconds (1s on, 1s off).
Synchronizes blinking on the rising edge of pin LOAD/CSN. The
multiplex and blink timing counter is cleared on the rising edge of pin
sync
0
R/W
LOAD/CSN. By setting this bit in multiple AS1106/AS1107 devices, the
blink timing can be synchronized across all the devices.
Start Blinking with display enabled phase. When bit D4 (blink_en) is set,
bit D7 determines how blinking starts.
blink_start
0
R/W
0 = Blinking starts with the display turned off.
1 = Blinking starts with the display turned on.
Addr: 0xXE
Bit
D0
D1
D2
D3
D4
D5
D6
D7
No-Op Register (0xX0)
The No-Op Register is used when multiple AS1106 or AS1107 devices are cascaded in order to support displays with
more than 8 digits. The cascading must be done in such a way that all DOUT pins are connected to DIN of the next
AS1106/AS1107 (see Figure 13 on page 15). The LOAD/CSN and CLK signals are connected to all devices.
For example, if five devices are cascaded, in order to perform a write operation to the fifth device, the write-command
must be followed by four no-operation commands. When the LOAD/CSN signal goes high, all shift registers are
latched. The first four devices will receive no-operation commands and only the fifth device will receive the intended
operation command, and subsequently update its register.
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AS1106, AS1107
Data Sheet
Supply Bypassing and Wiring
8 Typical Application
Supply Bypassing and Wiring
In order to achieve optimal performance the AS1106/AS1107 should be placed very close to the LED display to minimize effects of electromagnetic interference and wiring inductance.
Furthermore, it is recommended to connect a 10µF electrolytic and a 0.1µF ceramic capacitor between pins VDD and
GND to avoid power supply ripple (see Figure 13 on page 15).
Note: Both GND pins must be connected to ground.
Selecting RSET Resistor Value and Using External Drivers
Brightness of the display segments is controlled via RSET. The current that flows between VDD and ISET defines the
current that flows through the LEDs.
Segment current is about 200 times the current in ISET. Typical values for RSET for different segment currents, operating voltages, and LED voltage drop (VLED) are given in Tables 18 - 22. The maximum current the AS1106/AS1107
devices can drive is 40mA. If higher currents are needed, external drivers must be used, in which case it is no longer
necessary that the devices drive high currents.
In cases where the devices only drive a few digits, Table 15 specifies the maximum currents, and RSET must be set
accordingly.
Note: The display brightness can also be logically controlled (see Intensity Control Register (0xXA) on page 11).
Table 18. RSET vs. Segment Current and LED Forward Voltage, VDD = 2.7V
ISEG (mA)
40
30
20
10
VLED(V)
1.5
5kΩ
6.9kΩ
10.7kΩ
22.2kΩ
2.0
4.4kΩ
5.9kΩ
9.6kΩ
20.7kΩ
Table 19. RSET vs. Segment Current and LED Forward Voltage, VDD = 3.3V
ISEG (mA)
40
30
20
10
1.5
6.7kΩ
9.1kΩ
13.9kΩ
28.8kΩ
VLED(V)
2.0
6.4kΩ
8.8kΩ
13.3kΩ
27.7kΩ
2.5
5.7kΩ
8.1kΩ
12.6kΩ
26kΩ
Table 20. RSET vs. Segment Current and LED Forward Voltage, VDD = 3.6V
ISEG (mA)
40
30
20
10
VLED(V)
1.5
7.5kΩ
10.18kΩ
15.6kΩ
31.9kΩ
2.0
7.2kΩ
9.8kΩ
15kΩ
31kΩ
2.5
6.6kΩ
9.2kΩ
14.3kΩ
29.5kΩ
3.0
5.5kΩ
7.5kΩ
13kΩ
27.3kΩ
Table 21. RSET vs. Segment Current and LED Forward Voltage, VDD = 4.0V
ISEG (mA)
40
30
1.5
8.6kΩ
11.6kΩ
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2.0
8.3kΩ
11.2kΩ
VLED(V)
2.5
7.9kΩ
10.8kΩ
Revision 2.2
3.0
7.6kΩ
9.9kΩ
3.5
5.2kΩ
7.8kΩ
13 - 20
austriam i c r o systems
AS1106, AS1107
Data Sheet
Calculating Power Dissipation
Table 21. RSET vs. Segment Current and LED Forward Voltage, VDD = 4.0V (Continued)
ISEG (mA)
1.5
17.7kΩ
36.89kΩ
20
10
VLED(V)
2.5
16.6kΩ
34.5kΩ
2.0
17.3kΩ
35.7kΩ
3.0
15.6kΩ
32.5kΩ
3.5
13.6kΩ
29.1kΩ
Table 22. RSET vs. Segment Current and LED Forward Voltage, VDD = 5.0V
ISEG (mA)
40
30
20
10
VLED (V)
1.5
11.35kΩ
15.4kΩ
23.6kΩ
48.9kΩ
2.0
11.12kΩ
15.1kΩ
23.1kΩ
47.8kΩ
2.5
10.84kΩ
14.7kΩ
22.6kΩ
46.9kΩ
3.0
10.49kΩ
14.4kΩ
22kΩ
45.4kΩ
3.5
10.2kΩ
13.6kΩ
21.1kΩ
43.8kΩ
4.0
9.9kΩ
13.1kΩ
20.2kΩ
42kΩ
Table 23. Package Thermal Data
Thermal Resistance (ΘJA)
+75°C/W
+85°C/W
Package
24 Narrow DIP
24 Wide SOIC
Calculating Power Dissipation
The upper limit for power dissipation (PD) for the AS1106/AS1107 is determined from the following equation:
PD = (VDD x 1mA) + (VDD - VLED)(DUTY x ISEG x N)
(EQ 1)
Where:
VDD is the supply voltage.
DUTY is the duty cycle set by intensity register (page 11).
N is the number of segments driven (worst case is 8)
VLED is the LED forward voltage
ISEG = segment current set by RSET
Dissipation Example:
ISEG = 40mA, N = 8, DUTY = 31/32, VLED = 1.8V at 40mA, VDD = 5.25V
(EQ 2)
PD = 5.25V(1mA) + (5.25V - 1.8V)(31/32 x 40mA x 8) = 1.075W
(EQ 3)
Thus, for a PDIP package ΘJA = +75°C/W (from Table 23), the maximum allowed TAMB is given by:
TJ,MAX = TAMB + PD x ΘJA = 150°C = TAMB +1.07W x 75°C/W
(EQ 4)
Where:
TAMB = +69.4°C.
The TAMB limit for SO Packages in the dissipation example above is +58.6°C.
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Revision 2.2
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austriam i c r o systems
AS1106, AS1107
Data Sheet
8x8 LED Dot Matrix Driver
8x8 LED Dot Matrix Driver
The application example in Figure 13 shows the AS1106 as an 8x8 LED dot matrix driver.
The LED columns have common cathodes and are connected to the DIG0:7 outputs. The rows are connected to the
segment drivers. Each of the 64 LEDs can be addressed separately. The columns are selected via the digits as listed
in Table 6 on page 8.
The Decode Enable Register (see page 9) must be set to ‘00000000’ as described in Table 8 on page 9. Single LEDs
in a column can be addressed as described in Table 11 on page 10, where bit D0 corresponds to segment G and bit
D7 corresponds to segment DP.
Note: For a multiple-digit dot matrix, multiple AS1106 devices must be cascaded.
Figure 13. Application Example as LED Dot Matrix Driver
8x8 LED Dot Matrix
Diode Arrangement
8x8 LED Dot Matrix
SEG G
SEG F
SEG E
SEG G
SEG F
SEG E
SEG D
SEG C
SEG B
SEG A
SEG DP
SEG D
SEG C
SEG B
SEG A
SEG DP
SEG A:G DIG0:7
SEG DP
SEG A:G DIG0:7
SEG DP
DOUT
VDD
DIN
MicroProcessor
LOAD/CSN
VBAT
GND
LOAD/CSN
9.53kΩ
CLK
VDD
DIN
VBAT
9.53kΩ
CLK
ISET
GND
GND
ISET
GND
Cascading Drivers
The example in Figure 4 drives 2 dot matrix digits using a 4-wire microprocessor interface. All Scan-Limit Registers
should be set to the same value so that one display will not appear brighter than the other.
For example, to display 12 digits, set both Scan-Limit Registers to display 6 digits so that both displays have a 1/6 duty
cycle per digit. If 11 digits are needed, set both Scan-Limit Registers to display 6 digits and leave one digit unconnected. Otherwise, if one driver is set to display 6 digits and the other to display 5 digits one display will appear brighter
because its duty cycle per digit will be 1/5 and the other display’s duty cycle will be 1/6.
Note: Refer to No-Op Register (0xX0) on page 12 for additional information.
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Revision 2.2
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AS1106, AS1107
Data Sheet
Pin Assignments
9 Pinout and Packaging
Pin Assignments
Figure 14. DIP and SO Pin Assignments (Top View)
DIN 1
24 DOUT
DIG 0 2
23 SEG D
DIG 4 3
22 SEG DP
21 SEG E
DIG 6 5
20 SEG C
DIG 2 6
DIG 3 7
DIG 7 8
AS1106/
AS1107
GND 4
19 VDD
18 ISET
17 SEG G
GND 9
16 SEG B
DIG 5 10
15 SEG F
DIG 1 11
14 SEG A
LOAD/CSN 12
13 CLK
Pin Descriptions
Table 24. Pin Descriptions
Pin
Name
DIN
DIG 0:DIG 7
GND
LOAD/CSN
CLK
SEG A:SEG G, SEG DP
ISET
VDD
DOUT
Pin
Number
Description
Serial-Data Input. Data is loaded into the internal 16-bit shift register on the
rising edge of pin CLK.
Digit Drive Lines. 8 Eight-digit drive lines that sink current from the display
2, 3, 5, 6, common cathode. The AS1106 pulls the digit outputs to VDD when turned
7, 8, 10, 11
off. The AS1107 digit drivers are high-impedance when turned off.
4, 9
Ground. Both GND pins must be connected.
Load-Data Input (AS1106 only). The last 16 bits of serial data are latched
on the rising edge of this pin.
12
Chip-Select Input (AS1107 or AS1106 SPI-enabled only). Serial data is
loaded into the shift register while this pin is low. The last 16 bits of serial
data are latched on the rising edge of this pin.
Serial-Clock Input. 10MHz maximum rate. Data is shifted into the internal
shift register on the rising edge of this pin. Data is clocked out of pin DOUT
13
on the falling edge of this pin. On the AS1107 or AS1106 SPI-enabled, the
CLK input is active only while LOAD/CSN is low.
Seven Segment and Decimal Point Drive Lines. 8 seven-segment drives
14, 15, 16, and decimal point drive that source current to the display. On the AS1106,
17, 20, 21,
when a segment driver is turned off it is pulled to GND. The AS1107
22, 23
segment drivers are high-impedance when turned off.
Set Segment Current. Connect to VDD through RSET to set the peak
segment current (see Selecting RSET Resistor Value and Using External
18
Drivers on page 13).
19
Positive Supply Voltage. Connect to +2.7 to +5.5V supply.
Serial-Data Output. The data into pin DIN is valid at pin DOUT 16.5 clock
24
cycles later. This pin is used to daisy-chain several AS1106/AS1107 devices
and is never high-impedance.
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1
Revision 2.2
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austriam i c r o systems
AS1106, AS1107
Data Sheet
Package Drawings and Markings
Package Drawings and Markings
The AS1106 and AS1107 are available in 24-pin DIP and 24-pin SOIC packages.
Figure 15. 24-pin DIP Package
Symbol
B
B1
C
D
D1
E
ID
ID1
E1
eA
e1
L
R
T
T1
T2
W
Min
0.30
.295
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Revision 2.2
0.60
.320
0.64
0.64
.260
.320
.370
1.00
.125
.030
.130
.060
.060
.030 REF
7º
α1
α2
α3
α4
P’
A
A1
Max
0.18
0.015
0.10
1.160
7º
7º
7º
.760
.145
.015
.170
.040
17 - 20
austriam i c r o systems
AS1106, AS1107
Data Sheet
Package Drawings and Markings
Figure 16. 24-pin SOIC Package
Symbol
Min
Max
Symbol
Min
Max
A
2.44
2.84
H
10.11
10.51
A1
0.10
0.30
h
0.31
0.71
A2
2.24
2.44
J
0.53
B
0.36
0.46
K
0.73
7º BSC
C
0.23
0.32
L
0.51
1.01
D
12.65
12.85
R
0.63
0.89
E
7.40
7.50
ZD
e
1.27 BSC
α
0.66 REF
0º
8º
Notes:
1. Controlling dimension is millimeters.
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Revision 2.2
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austriam i c r o systems
AS1106, AS1107
Data Sheet
10 Ordering Information
The AS1106 and AS1107 are available in 24-pin DIP and 24-pin SOIC packages.
Table 25. Ordering Information
Part
AS1106PL
AS1106WL
AS1106WL-T
AS1106PE
AS1106WE
AS1106WE-T
AS1107PL
AS1107WL
AS1107WL-T
Temperature Range
0 to +70°C
0 to +70°C
0 to +70°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
0 to +70°C
0 to +70°C
0 to +70°C
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Delivery Form
Tubes
Tubes
Tape and Reel
Tubes
Tubes
Tape and Reel
Tubes
Tubes
Tape and Reel
Revision 2.2
Package
24-pin Narrow Plastic DIP, Pb-free
24-pin Wide SO, Pb-free
24-pin Wide SO, Pb-free
24-pin Narrow Plastic DIP, Pb-free
24-pin Wide SO, Pb-free
24-pin Wide SO, Pb-free
24-pin Narrow Plastic DIP, Pb-free
24-pin Wide SO, Pb-free
24-pin Wide SO, Pb-free
19 - 20
austriam i c r o systems
AS1106, AS1107
Data Sheet
Copyrights
Copyright © 1997-2005, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information.
This product is intended for use in normal commercial applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for
each application.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
e-mail: [email protected]
For Sales Offices, Distributors and Representatives, please visit:
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