IC41SV44052 IC41SV44054 Document Title 4Mx4 bit Dynamic RAM with Fast Page Mode Revision History Revision No History Draft Date Remark 0A 0B Initial Draft Chang working range from VCC=1.9V~2.4V to VCC=1.9V~2.7V, VIH=1.4V to VIH=1.6V June 14,2002 July 31,2002 Preliminary The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR035-0B 7/31/2002 1 IC41SV44052 IC41SV44054 Preliminary 4M x 4 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE FEATURES DESCRIPTION • Fast Page Mode Access Cycle • TTL compatible inputs and outputs • Refresh Interval: -- 2,048 cycles/32 ms -- 4,096 cycles/64 ms • Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single power supply: 1.9V − 2.7V The ICSI 44052/44054 Series is a 4,194,304 x 4-bit highperformance CMOS Dynamic Random Access Memory. The Fast Page Mode allows 2,048 or 4,096 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word. These features make the 44052/44054 Series ideally suited for digital signal processing, and low power portable audio applications. The 44052/44054 Series is packaged in a 26-pin 300mil SOJ and a 26 pin TSOP-2 KEY TIMING PARAMETERS PIN CONFIGURATION 24 (26) Pin SOJ, TSOP-2 Parameter -70 -100 Unit RAS Access Time (tRAC) 70 100 ns CAS Access Time (tCAC) 20 25 ns Column Address Access Time (tAA) 35 50 ns Fast Page Mode Cycle Time (tPC) 45 60 ns Read/Write Cycle Time (tRC) 130 180 ns PIN DESCRIPTIONS VCC 1 24 GND A0-A11 Address Inputs (4K Refresh) I/O0 2 23 I/O3 A0-A10 Address Inputs (2K Refresh) I/O1 3 22 I/O2 I/O0-3 Data Inputs/Outputs WE 4 21 CAS RAS 5 20 OE WE Write Enable *A11(NC) 6 19 A9 OE Output Enable RAS Row Address Strobe A10 7 18 A8 CAS Column Address Strobe A0 8 17 A7 A1 9 16 A6 Vcc Power A2 10 15 A5 GND Ground A3 11 14 A4 VCC 12 13 GND *A11 is NC for 2K Refresh devices. ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. DR035-0B 7/31/2002 IC41SV44052 IC41SV44054 FUNCTIONAL BLOCK DIAGRAM OE WE CAS CONTROL LOGIC CAS WE CONTROL LOGICS CAS OE CONTROL LOGIC WE OE DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS ROW DECODER REFRESH COUNTER ADDRESS BUFFERS A0-A10 MEMORY ARRAY 4,194,304 x 4 DATA I/O BUFFERS RAS CLOCK GENERATOR RAS RAS I/O0-I/O3 TRUTH TABLE Function Standby Read Write: Word (Early Write) Read-Write Hidden Refresh Read Write(1) RAS-Only Refresh CBR Refresh RAS H L L L L→H→L L→H→L L H→L CAS H L L L L L H L WE X H L H→L H L X X OE X L X L→H L X X X Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X I/O High-Z DOUT DIN DOUT, DIN DOUT DIN High-Z High-Z Note: 1. EARLY WRITE only. Integrated Circuit Solution Inc. DR035-0B 7/31/2002 3 IC41SV44052 IC41SV44054 Functional Description Refresh Cycle The IC41SV44052 and IC41LV44054 are CMOS DRAMs optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 11 or 12 address bits. These are entered 11 bits (A0-A10) at a time for the 2K refresh device or 12 bits (A0-A11) at a time for the 4K refresh device. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter ten bits. To retain data, 2,048 refresh cycles are required in each 32 ms period, or 4,096 refresh cycles are required in each 64ms period. There are two ways to refresh the memory: 1. By clocking each of the 2,048 row addresses (A0 through A10) or 4096 row addresses (A0 through A11) with RAS at least once every 32 ms or 64ms respectively. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and t OEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 11(12)-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Power-On After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. 4 Integrated Circuit Solution Inc. DR035-0B 7/31/2002 IC41SV44052 IC41SV44054 ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters Rating Unit VT Voltage on Any Pin Relative to GND −0.5 to +3.0 V VCC Supply Voltage −0.5 to +3.0 V IOUT PD TA TSTG Output Current Power Dissipation Commercial Operation Temperature Storage Temperature 50 0.2 -10 to +70 −55 to +125 mA W o C o C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Parameter Min. Max. Unit VCC Supply Voltage 1.9 2.7 V VIH Input High Voltage 1.6 VCC + 0.3 V VIL Input Low Voltage −0.3 0.6 V TA Commercial Ambient Temperature -10 70 o C CAPACITANCE(1,2) Symbol Parameter CIN1 CIN2 CIO Input Capacitance: A0-A10 Input Capacitance: RAS, CAS, WE, OE Data Input/Output Capacitance: I/O0-I/O3 Max. Unit 5 7 7 pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25oC, f = 1 MHz. Integrated Circuit Solution Inc. DR035-0B 7/31/2002 5 IC41SV44052 IC41SV44054 ELECTRICAL CHARACTERISTICS(1) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Test Condition IIL Input Leakage Current IIO Speed Min. Max. Unit Any input 0V ≤ VIN ≤ Vcc Other inputs not under test = 0V −5 5 µA Output Leakage Current Output is disabled (Hi-Z) 0V ≤ VOUT ≤ Vcc −5 5 µA VOH Output High Voltage Level IOH = −2.0 mA 1.6 − V VOL Output Low Voltage Level IOL = 2 mA − 0.8 V ICC1 Standby Current: TTL RAS, CAS ≥ VIH − 1 mA ICC2 Standby Current: CMOS RAS, CAS ≥ VCC − 0.2V 0.5 mA ICC3 Operating Current: Random Read/Write(2,3,4) Average Power Supply Current RAS, CAS, Address Cycling, tRC = tRC (min.) -70 -100 − − 60 50 mA ICC4 Operating Current: Fast Page Mode(2,3,4) Average Power Supply Current RAS = VIL, CAS ≥ VIH tRC = tRC (min.) -70 -100 − − 45 35 mA ICC5 Refresh Current: RAS-Only(2,3) Average Power Supply Current RAS Cycling, CAS ≥ VIH tRC = tRC (min.) -70 -100 − − 60 50 mA ICC6 Refresh Current: CBR(2,3,5) Average Power Supply Current RAS, CAS Cycling tRC = tRC (min.) -70 -100 − − 60 50 mA Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each Fast page cycle. 5. Enables on-chip refresh and address counters. 6 Integrated Circuit Solution Inc. DR035-0B 7/31/2002 IC41SV44052 IC41SV44054 AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Min. -70 Max. Min. tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(23) CAS Precharge Time(9) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time CAS to Output in Low-Z(15, 24) CAS to RAS Precharge Time(21) Output Disable Time(19, 24) Output Enable Time(15, 16) OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS) 130 − − − 70 50 20 10 70 20 0 10 0 15 70 − 70 20 35 10K − 10K − − 50 − − − − − 180 − − − 100 70 25 10 100 25 0 15 0 20 100 − 100 25 50 10K − 10K − − 75 − − − − − ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 35 5 20 3 5 3 5 0 0 35 − − − − − 20 20 − − − 20 50 5 25 3 5 3 5 0 0 50 − − − − − 25 25 − − − ns ns ns ns ns ns ns ns ns ns ns 0 − 0 − ns 10 70 − − 15 100 − − ns ns 10 20 20 0 50 − − − − − 15 25 25 0 60 − − − − − ns ns ns ns ns tRAD tRAL tRPC tRSH tCLZ tCRP tOD tOE tOES tRCS tRRH tRCH tWCH tWCR tWP tRWL tCWL tWCS tDHR Integrated Circuit Solution Inc. DR035-0B 7/31/2002 -100 Max. Units 7 IC41SV44052 IC41SV44054 AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -70 Min. Max. Symbol Parameter tACH Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) Fast Page Mode READ or WRITE Cycle Time Fast Page Mode RAS Pulse Width Access Time from CAS Precharge(15) Fast Page Mode READ WRITE Cycle Time Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 24) CAS Setup Time (CBR REFRESH)(20, 25) CAS Hold Time (CBR REFRESH)( 21, 25) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Auto Refresh Period 2,048 Cycles Auto Refresh Period 4,096 Cycles Transition Time (Rise or Fall)(2, 3) tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tOFF tCSR tCHR tORD tREF tT -100 Min. Max. Units 15 − 15 − ns 20 − 25 − ns 0 15 185 100 − − − − 0 20 240 130 − − − − ns ns ns ns 45 60 45 − − − 55 85 60 − − − ns ns ns 70 − 100 100K 40 − 100 − 120 100K 55 − ns ns ns 3 15 3 15 ns 5 10 0 − − − 5 10 0 − − − ns ns ns − − 3 32 64 50 − − 3 32 64 50 ms ms ns AC TEST CONDITIONS Output load: One TTL Load and 100 pF Input timing reference levels: VIH = 1.6V, VIL = 0.6V Output timing reference levels: VOH = 1.6V, VOL = 0.8V 8 Integrated Circuit Solution Inc. DR035-0B 7/31/2002 IC41SV44052 IC41SV44054 Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD ≥ tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. Determined by falling edge of CAS. 21. Determined by rising edge of CAS. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. CAS must meet minimum pulse width. 24. The 3 ns minimum is a parameter guaranteed by design. 25. Enables on-chip refresh and address counters. Integrated Circuit Solution Inc. DR035-0B 7/31/2002 9 IC41SV44052 IC41SV44054 READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tRCD tRRH CAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLZ I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES Don’t Care Note: 1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. 10 Integrated Circuit Solution Inc. DR035-0B 7/31/2002 IC41SV44052 IC41SV44054 READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tRCD CAS tAR tRAD tASR tRAH tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tRCS tAWD tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tOD tDH Valid DIN Open tOEH OE Don’t Care Integrated Circuit Solution Inc. DR035-0B 7/31/2002 11 IC41SV44052 IC41SV44054 EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tRCD CAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don’t Care 12 Integrated Circuit Solution Inc. DR035-0B 7/31/2002 IC41SV44052 IC41SV44054 FAST PAGE MODE READ CYCLE tRASP tRP RAS tPC tCSH tCAS tCRP tRSH tCAS tCAS tRCD tCP tCRP tCP CAS tAR tRAL tRAH tRAD tASC tASR ADDRESS Row tCAH tASC tAR Column tCAH Column tCAH tASC Column tRCS WE tCPA tCPA tAA tAA tCAC tAA tCAC tOE tCAC tOE tOE OE tRAC tOD tCLZ I/O tOD tCLZ OUT tOD tCLZ OUT OUT Don’t Care Integrated Circuit Solution Inc. DR035-0B 7/31/2002 13 IC41SV44052 IC41SV44054 FAST PAGE MODE EARLY WRITE CYCLE tRASP tRP RAS tPC tCAS tCSH tCAS tCRP tRCD tRSH tCAS tCP tCRP tCP CAS tAR tRAL tRAH tRAD tASC tASR ADDRESS Row tCAH tCAH tAR Column tASC Column Column tCWL tWCS tWCH tCAH tASC tCWL tWCS tWP tRWL tWCH tWCS tWP tWCH tWP WE tWCR OE tDHR tDS I/O tDH Valid DIN tDS tDH Valid DIN tDS tDH Valid DIN Don’t Care 14 Integrated Circuit Solution Inc. DR035-0B 7/31/2002 IC41SV44052 IC41SV44054 FAST PAGE MODE READ WRITE CYCLE (LATE WRITE AND READ-MODIFY-WRITE CYCLE) tRASP tRP RAS tPRWC tCAS tCSH tCAS tCRP tRCD tRSH tCAS tCP tCRP tCP CAS tAR tRAL tRAD tRAH tASC tASR ADDRESS Row tCAH tASC tAR Column tCWL tRWD tAWD tCWD tRCS tCAH Column Column tCWL tRWL tCWL tAWD tCWD tWP tCAH tASC tAWD tCWD tWP tWP WE tAA tAA tCAC tAA tCAC tCAC tOE tOE tOE OE tOD tOD tOD tRAC I/O tDH tDH tDS tCLZ tCLZ OUT tDS IN OUT tDH tCLZ tDS OUT IN IN Don’t Care RAS RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC CAS tASR ADDRESS I/O tRAH Row Row Open Don’t Care Integrated Circuit Solution Inc. DR035-0B 7/31/2002 15 IC41SV44052 IC41SV44054 CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) tRP tRAS tRP tRAS RAS tRPC tCP tCHR tCHR tRPC tCSR tCSR CAS Open I/O Don’t Care HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRAS tRP RAS tCRP tRCD tRSH tCHR CAS tAR tRAD tRAH tASC tASR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ I/O Open Valid Data tOE Open tOD tORD OE Don’t Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. 16 Integrated Circuit Solution Inc. DR035-0B 7/31/2002 IC41SV44052 IC41SV44054 ORDERING INFORMATION Commercial Range: -10°°C to 70°° C Voltage: 2.2V Speed (ns) 70 70 70 70 100 100 100 100 IC41SV44052-70J IC41SV44052-70T IC41SV44052-70JG IC41SV44052-70TG IC41SV44052-100J IC41SV44052-100T IC41SV44052-100JG IC41SV44052-100TG Speed (ns) 70 70 70 70 100 100 100 100 Order Part No. Order Part No. IC41SV44054-70J IC41SV44054-70T IC41SV44054-70JG IC41SV44054-70TG IC41SV44054-100J IC41SV44054-100T IC41SV44054-100JG IC41SV44054-100TG Package 300mil SOJ 300mil TSOP-2 300mil SOJ Pb-free 300mil TSOP-2 Pb-free 300mil SOJ 300mil TSOP-2 300mil SOJ Pb-free 300mil TSOP-2 Pb-free Package 300mil SOJ 300mil TSOP-2 300mil SOJ Pb-free 300mil TSOP-2 Pb-free 300mil SOJ 300mil TSOP-2 300mil SOJ Pb-free 300mil TSOP-2 Pb-free Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. DR035-0B 7/31/2002 17