AVAGO ADNS-2051 Optical mouse sensor Datasheet

ADNS-2051
Optical Mouse Sensor
Data Sheet
Description
Features
The ADNS-2051 is a low cost optical sensor used to
implement a non-mechanical tracking engine for
computer mice.
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It is based on optical navigation technology, which
measures changes in position by optically acquiring
sequential surface images (frames) and mathematically determining the direction and magnitude of
movement.
The output format is two channel quadrature (X and Y
direction) which emulates encoder photo-transistors.
The current X and Y information are also available in
registers accessed via a serial port.
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Default resolution is specified as 400 counts per inch
(cpi), with rates of motion up to 14 inches per second
(ips).
•
•
The sensor is housed in a 16-pin staggered dual inline
package (DIP) that is designed for use with the HDNS2100 Lens and HDNS-2200 Clip and HLMP-ED80-XX000
(639 nm LED illuminator source). There are no moving
parts, and precision optical alignment is not required, facilitating high volume assembly.
Resolution can also be programmed to 800 cpi.
The part is programmed via a two wire serial port,
through registers.
Theory of Operation
The ADNS-2051 is based on Optical Navigation Technology. It contains an Image Acquisition System (IAS), a
Digital Signal Processor (DSP), a two-channel quadrature
output, and a two wire serial port.
The IAS acquires microscopic surface images via the lens
and illumination system provided by the HDNS-2100,
2200, and HLMP-ED80-XX000 LED. These images are
processed by the DSP to determine the direction and
distance of motion. The DSP generates the Δx and Δy
relative displacement values that are converted into two
channel quadrature signals.
•
Precise optical navigation technology
No mechanical moving parts
Complete 2D motion sensor
Serial interface and/or quadrature interface
Smooth surface navigation
Programmable frame speed up to 2300 frames per
sec (fps)
Accurate motion up to 14 ips
800 cpi resolution
High reliability
High speed motion detector
No precision optical alignment
Wave solderable
Single 5.0 volt power supply
Shutdown pin for USB suspend mode operation
Power conservation mode during times of no
movement
On chip LED drive with regulated current
Serial port registers
– Programming
– Data transfer
16-pin staggered dual inline package (DIP)
Applications
• Mice for desktop PCs, workstations, and portable PCs
• Trackballs
• Integrated input devices
Outline Drawing of ADNS-2051 Optical Mouse Sensor
Pinout
Pin
Pin
Description
1
SCLK
Serial port clock (input)
2
XA
XA quadrature output
3
XB
XB quadrature output
4
YB
YB quadrature output
5
YA
YA quadrature output
6
XY_LED
LED control
7
REFA
Internal reference
8
REFB
Internal reference
9
OSC_IN
Oscillator input
10
GND
System ground
11
OSC_OUT
Oscillator output
12
GND
System ground
13
VDD
5.0 volt power supply
14
R_BIN
LED current bin resistor
15
PD
Power down pin, active high
16
SDIO
Serial data (input and output)
SCLK
1
XA
2
XB
3
YB
4
YA
5
XY_LED
6
REFA
7
REFB
8
Figure 1. Top view
A2051
XYYWWZ
16
SDIO
15
PD
14
R_BIN
13
VDD
12
GND
11
OSC_OUT
10
GND
9
OSC_IN
PIN 1
A2051
XYYWWZ
12.85 (AT SHOULDER)
(0.506)
9.10
(0.358)
22.30
(0.878)
*
0.01
(0.000)
50° ± 0.5°
0.99
(0.039)
3.18
(0.125)
*
2.98
(0.117)
5.16
(0.203)
0.50 CHAMFER
1.26 LEAD OFFSET
(0.050)
LEAD WIDTH 0.50
(0.020)
0.25
(0.010)
GATE LOCATION
SURFACE RECESSED
BY 0.3 mm
4.55
(0.179)
6.03
(0.237)
*
6.18
(0.243)
2.54 LEAD PITCH
(0.100)
0.25
(0.010)
5° ± 3°
13.57 ± 0.45 (AT LEAD TIP)
(0.534 ± 0.018)
(MEASURED AT BASE) 5.60 ± 0.03
(0.220 ± 0.001)
PROTECTIVE KAPTON TAPE
∅ 5.00
GROOVE
1.85 ± 0.03
(0.073 ± 0.001)
*
0.06
(0.002)
7.28 ± 0.03
(0.287 ± 0.001)
A
A
PIN 1
∅ 0.80 ± 0.03
CLEAR OPTICAL PATH
13.38
(0.527)
*1.5° DRAFT
SECTION A-A
NOTES:
1. DIMENSIONS IN MILLIMETERS (INCHES).
2. DIMENSIONAL TOLERANCE: ± 0.1 mm.
3. COPLANARITY OF LEADS: 0.1 mm.
4. LEAD PITCH TOLERANCE: ± 0.15 mm.
5. CUMULATIVE PITCH TOLERANCE: ± 0.15 mm.
6. ANGULAR TOLERANCE: ± 3.0 DEGREES.
7. MAXIMUM FLASH + 0.2 mm.
8. CHAMFER (25 DEGREES x 2) ON THE TAPER SIDE OF THE LEAD.
9. * THESE DIMENSIONS ARE FOR REFERENCES ONLY AND SHOULD NOT BE USED TO MECHANICALLY REFERENCE THE SENSOR.
Figure 2. Package outline drawing
1.43 ± 0.03
(0.056 ± 0.001)
*
2.80
(0.110)
Overview of Optical Mouse Sensor Assembly
2D Assembly Drawing of ADNS‑2051
40.53
(1.596)
Figures 3 and 4, shown with
HDNS‑2100,
HDNS-2200,
and
HLMP‑ED80‑XX000.
39.39
(1.551)
30.32
(1.194)
Avago Technologies provides an
IGES file drawing describing the base
plate molding features for lens and
PCB alignment.
1.27
(0.050)
∅ 3.50
(1.38)
2.32
(0.091)
The components interlock as they
are mounted onto defined features
on the base plate.
The ADNS-2051 sensor is designed
for mounting on a through hole PCB,
looking down. There is an aperture
stop and features on the package
that align to the lens (see Figure 3).
The HDNS-2100 lens provides
optics for the imaging of the
surface as well as illumination of
the surface at the optimum angle.
Features on the lens align it to the
sensor, base plate, and clip with the
LED. The lens also has a large round
flange to provide a long creepage
path for any ESD events that occur
at the opening of the base plate (see
Figure 4).
The HDNS-2200 clip holds the LED in
relation to the lens. The LED must be
inserted into the clip and the LED’s
leads formed prior to loading on the
PCB. The clip interlocks the sensor
to the lens, and through the lens to
the alignment features on the base
plate.
5.10
(0.201)
12.60
(0.498)
13.88
(0.546)
11.38
(0.448)
0 REF.
1.28
(0.050)
7.50
(0.295)
CLEAR ZONE
0 REF.
∅ 0.80 RECOMMENDED (16 PLACES)
(0.031)
DIMENSIONS IN MILLIMETERS (INCHES)
Figure 3. Recommended PCB mechanical cutouts and spacing (top view)
ADNS-2051 fig 3
TOP VIEW
44.29
(1.744)
+x
19.10
(0.752)
+y
BASE PLATE
ESD LENS RING
The HLMP-ED80-XX000 LED is recommended for illumination. If used with
the bin table, sufficient illumination
can be guaranteed.
SIDE VIEW
PLASTIC SPRING
14.58
(0.574)
CLIP
13.82
(0.544)
10.58
(0.417)
7.45
(0.293)
SENSOR
BASE PLATE
ALIGNMENT POST
PCB
DIMENSIONS IN MILLIMETERS (INCHES).
Figure 4. 2D assembly drawing of ADNS-2051 (top and side view)
ADNS-2051 fig 4
1.22
(0.048)
HDNS-2200 (CLIP)
HLMP-ED80 (LED)
ADNS-2051 (SENSOR)
CUSTOMER SUPPLIED PCB
HDNS-2100 (LENS)
CUSTOMER SUPPLIED BASE PLATE
WITH RECOMMENDED ALIGNMENT
FEATURES PER IGES DRAWING
Figure 5. Exploded view drawing
ADNS-2051 fig 5
PCB Assembly Considerations
1. Insert the sensor and all other electrical components
into PCB.
2. Bend the LED leads 90° and then insert the LED into
the assembly clip until the snap feature locks the LED
base.
3. Insert the LED/clip assembly into PCB.
4. Wave Solder the entire assembly in a no-wash solder
process utilizing solder fixture. The solder fixture
is needed to protect the sensor during the solder
process. The fixture should be designed to expose
the sensor leads to solder while shielding the optical
aperture from direct solder contact. The solder fixture
is also used to set the reference height of the sensor
to the PCB top during wave soldering (Note: DO NOT
remove the kapton tape during wave soldering).
5. Place the lens onto the base plate.
6. Remove the protective kapton tape from optical
aperture of the sensor. Care must be taken to keep
contaminants from entering the aperture. It is recommended not to place the PCB facing up during the
entire mouse assembly process. The PCB should be
held vertically during the kapton removal process.
7. Insert PCB assembly over the lens onto the base plate
aligning post to retain PCB assembly. The sensor
aperture ring should self-align to the lens.
8. The optical position reference for the PCB is set by the
base plate and lens. Note that the PCB motion due to
button presses must be minimized to maintain optical
alignment.
9. Install mouse top case. There MUST be a feature in the
top case to press down onto the clip to ensure all components are interlocked to the correct vertical height.
SCLK
OSC_IN
SERIAL PORT
SERIAL PORT
OSCILLATOR
SDIO
XB
YA
YB
R_BIN
POWER ON
RESET
IMAGE
PROCESSOR
LED
DRIVE
LED
XY_LED
REFA
VOLTAGE REGULATOR
AND POWER CONTROL
QUADRATURE
OUTPUT
XA
QUADRATURE
OUTPUTS
RESONATOR
OSC_OUT
REFB
VOLTAGE
REFERENCE
PD
VDD
GND
5 VOLT
POWER
GND
Figure 6. Block diagram of ADNS-2051 optical mouse sensor
ADNS-2051 fig 6
Design Considerations for Improving ESD Performance
The flange on the lens has been designed to increase
the creepage and clearance distance for electrostatic
discharge. The table on the right shows typical values
assuming base plate construction per the Avago supplied
IGES file and HDNS-2100 lens flange.
Typical Distance
Millimeters
Creepage
16.0
Clearance
2.1
For improved ESD performance, the lens flange can be
sealed (i.e. glued) to the base plate. Note that the lens
material is polycarbonate and therefore, cyanoacrylatebased adhesives or other adhesives that may damage
the lens should NOT be used.
The trimmed lens, HDNS-2100#001, is not recommended for corded applications due to the ESD spec requirement.
SENSOR
CLIP
LED
PCB
LENS/LIGHT PIPE
BASE PLATE
SURFACE
Figure 7. PCB assembly
ADNS-2051 fig 7
Recommended Typical Application Using SDIO Pins
11
VDD
VDD
7
D+
13
D-
12 D1.3 kΩ
GND
GND QA
SHLD
VDD
VDD
RΩ
QB
0.1 µF
4.7 µF
0.1 µF
8
10
CYPRESS
CY7C63723A-PC
VREG
5 P1.0
14
12
VPP
D+
P1.1
Z-WHEEL
ENCODER
P0.5
P0.6
P0.7
P0.2
P0.0
GND
HDNS-2100
LENS
INTERNAL
IMAGE
SENSOR
P0.1
16
17
PD
SDIO
ADNS
2051
1
15
4
2
Z LED
9
CERAMIC RESONATOR
18 MHz
REFA
11
R_BIN
M
XA
2
XB
3
YB
4
YA
5
2.2 µF
8
14
R1
VSS 6
XTALOUT
MURATA CSALS18M0X53-B0
TDK FCR18.0M2G
7
0.1 µF
REFB
R
BUTTONS
6
SCLK
L
3
OSC_IN
OSC_OUT
16
HLMP-ED80
SURFACE
GND
XY_LED
15
P0.4 18
P0.3
1
13
VDD
XTALIN
R1 VALUE
(kΩ)
LED
BIN
15.0
15.0
15.0
15.0
15.0
15.0 ~ 18.0
15.0 ~ 22.0
15.0 ~ 27.0
15.0 ~ 33.0
15.0 ~ 37.0
K
L
M
N
P
Q
R
S
T
U
Figure 8. Application using SDIO pins
Notes on Bypass Capacitors:
Regulatory Requirements
• Caps for pins 7, 8 and 12, 13 MUST have trace lengths
LESS than 5 mm.
• Passes FCC B and worldwide analogous emission
limits when assembled into a mouse with unshielded
cable and following Avago recommendations.
• The 0.1 µF caps must be ceramic.
• Caps should have less than 5 nH of self inductance
• Caps should have less than 0.2 Ω ESR
Surface mount parts are recommended.
SDIO and SCLK pins should be grounded if not used.
• Passes EN61000-4-4/IEC801-4 EFT tests when
assembled into a mouse with unshielded cable and
following Avago recommendations.
• UL flammability level UL94 V-0.
• Provides sufficient ESD creepage/clearance distance
to avoid discharge up to 15 kV when assembled into a
mouse according to usage instructions above.
• For eye safety consideration, please refer to the
technical report available on the web site,
http://www.Avago.com
• The 15.0 kΩ resistor is determined by the absolute
maximum rating of 50 mA for the HLMP-ED80XX000. The other resistor values for brighter bins will
guarantee good signals with reduced power.
Alternative Application using Quadrature Output Pins
4.7 µF
1.5 MΩ
9
12
VDD
10
CYPRESS
CY7C63001A-PC
0.33 µF
14
D–
GND
SHLD
2
1
3
3
4
4
5
16
15
15
1
P0.2
10
P0.3
XTALIN
P1.1
11
6
M
L
P0.1 2
P0.0
D+
19
20
XTALOUT
P1.3
P1.2
P1.0
P0.5
P0.6 17
P0.4
P0.7 18
5
VSS VPP
7
8
BUTTONS
GND
HDNS-2100
LENS
INTERNAL
IMAGE
SENSOR
XA
XB
HLMP-ED80
SURFACE
GND
XY_LED
13 D–
6 MHz
R
13
VDD
12
CEXT
VDD
D+
0.1 µF
OSC_IN
6
9
ADNS-2051
OSC_OUT
YB
REFA
11
CERAMIC RESONATOR
18 MHz AVX
KBR-18-00-MSA
MURATA CSALS18M0X55-B0
7
YA
0.1 µF
PD
REFB
SCLK
R_BIN
2.2 µF
8
14
16 SDIO
R1
PANASONIC
EVQ SERIES ENCODER
R1 VALUE
(kΩ)
LED
BIN
15.0
15.0
15.0
15.0
15.0
15.0 ~ 18.0
15.0 ~ 22.0
15.0 ~ 27.0
15.0 ~ 33.0
15.0 ~ 37.0
K
L
M
N
P
Q
R
S
T
U
Z-WHEEL
D- RESISTOR CONNECTION
1.5 kΩ
ALTERNATIVE D- RESISTOR CONNECTION
7.5 kΩ
3.3 V REGULATOR
LP2950AC
Z-3.3
Figure 9. Application using quadrature output pins
ADNS-2001 fig 09
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
–40
85
˚C
Operating Temperature
TA
–15
55
˚C
Lead Solder Temperature
260
˚C
Supply Voltage
VDD
–0.5
5.5
Notes
For 10 seconds, 1.6 mm below seating
plane.
V
ESD
2
kV
All pins, human body model MIL 883
Method 3015
Input Voltage
VIN
–0.5
VDD + 0.5
V
R_BIN
PD, SDIO, SCLK, XA, XB, YA, YB, XY_LED, Input Voltage
V
OSC_IN, OSC_OUT, REF_A
VIN
–0.5
3.6
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Operating Temperature
TA
0
Max.
Units
40
˚C
Power Supply Voltage
VDD
4.25
5.0
5.5
volts
Power Supply Rise Time
VRT
100
Notes
Register values retained for
voltage transients below
4.25 V but greater than 4 V.
ms
Supply Noise
VN
100
mV
Peak to peak within
0-100 MHz.
Clock Frequency
fCLK
18.7
MHz
Set by ceramic resonator.
Serial Port Clock Frequency
SCLK
fCLK/4
MHz
Resonator Impendance
XRES
55
Ω
17.4
18.0
Distance from Lens Reference
Z
2.3
2.4
2.5
mm
Plane to Surface
Results in ±0.2 mm DOF.
(See Figure 10.)
Speed
S
Acceleration
A
Light Level onto IC
IRRINC
0
80
100
14
in/sec
@ frame rate = 1500/second.
0.15
g
@ frame rate = 1500/second.
mW/m2
λ = 639 nm
λ = 875 nm
25,000
30,000
SDIO Serial Write-Write Time
tSWW
100
µs
Time between two write
commands. (Refer to Figure 31.)
SDIO Serial Write-Read Time
tSWR
100
µs
Time between write and read
operation. (Refer to Figure 32.)
SDIO Serial Read-Write Time
tSRW
120
ns
Time between read and write
operation. (Refer to Figure 33.)
SDIO Serial Read-Read Time
tSRR
120
ns
Time between two read
commands. (Refer to Figure 33.)
Data Delay after PD
tCOMPUTE
3.2
ms
After tCOMPUTE, all registers
contain data from first image
after PD . Note that an additional 75 frames for AGC (shutter)
stabilization may be required if
mouse movement occurred
while PD was high. (Refer to
Figure 12.)
SDIO Write Setup Time
tSETUP
60
ns
Data valid time before the rising
of SCLK. (Refer to Figure 26.)
PD Pulse Width
tPDW
700
µs
(to power down the chip)
Pulse width to initiate the power
down cycle @ 1500 fps. (Refer to Figure 12 and Figure 14.)
PD Pulse Width
tPDR
100
µs
(to reset the serial port)
Pulse width to reset the serial
port @ 1500 fps (but may also
initiate a power down cycle.
Normal PD recovery sequence
to be followed. (Refer to
Figure 15.)
←
Hold time for valid data.
(Refer to Figure 28.)
←
SDIO Read Hold Time
tHOLD
100
µs
Frame Rate
FR
1500
frames/s See Frame_Period register
section.
Bin Resistor
R1
15 K
15 K
37 K
Ω
Refer to Figure 8.
ADNS-2051
HDNS-2100
Z
OBJECT SURFACE
Figure 10. Distance from lens reference plane to surface
Fig 10 Distance from Lens Reference Plane to Surface
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25˚C, VDD = 5.0 V, 1500 fps, 18
MHz.
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
Power Up from PD
tPUPD
50
ms
From PD to valid quad signals
705 µsec + 75 frames. (Refer to
Figure 12.)
Power Up from VDD
tPU
30
ms
From VDD to valid quad
signals
705 µsec + 40 frames
Rise and Fall Times:
SDIO
tr
30
ns
CL = 30 pF (the rise time is
between 10% and 90%)
tf
16
ns
CL = 30 pF (the fall time is
between 10% and 90%)
XA, XB, YA, YB
tr
50
ns
CL = 30 pF (the rise time is
between 10% and 90%)
tf
20
ns
CL = 30 pF (the fall time is
between 10% and 90%)
ILED
tr
40
ns
With HLMP-ED80-XX000 LED (the rise time is between 10% and 90%)
tf
200
ns
With HLMP-ED80-XX000 LED (the fall time is between 10% and 90%)
Serial Port Transaction Timer
tSPTT
0.7
0.9
1.0
s
Serial port will reset if current
transaction is not complete
within tSPTT. (Refer to Figure 36.)
Transient Supply Current
IDDT
20
37
mA
Max. supply current during a
VDD ramp from 0 to 5.0 V with
> 500 µs rise time. Does not include charging current for
bypass capacitors.
←
←
10
←
←
From PD
Time uncertainty due to firmware delay. (Refer to Figure 12.)
←
Power Down
tPD
700
µs
DC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25˚C, VDD = 5.0 V, 18 MHz.
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
DC Supply Current
IDD AVG
15
25
mA
(mouse moving)
No load on XA, XB, YA, YB, SCLK, SDIO. Excluding LED
current.
Peak Supply Current
IDD PEAK
20
mA
(mouse moving)
No load on XA, XB, YA, YB,
SCLK, SDIO. Excluding LED
current.
DC Supply Current
IDD
12
25
mA
(mouse not moving)
No load on XA, XB, YA, YB,
SCLK, SDIO. Excluding LED
current.
DC Supply Current
IDDPD
170
240
µA
(power down)
PD = high; SCLK, SDIO = GND
or VDD; VDD = 4.25 V to 5.25 V.
SCLK, SDIO, PD
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
0.8
V
0.5 * VDD
V
0.7
0.6 * VDD
Output Low Voltage
(XA, XB, YA, YB)
VOL
Output High Voltage
(XA, XB, YA, YB)
VOH
Output Low Voltage
(XY_LED)
VOL
0.4
0.6 * VDD
1.1
V
@ IOL = 2 mA (SDIO only)
V
@ IOH = 2 mA (SDIO only)
V
@ IOL = 0.5 mA.
V
@ IOH = 0.5 mA .
V
Refer to Figure 11.
XY LED Current
ILED
Typ–15% 630/R1
Typ + 15% A
Refer to Figure 11, see table
below.
XY LED Current
(fault mode)
R1 < 200 Ω.
ILED
500
µA
REF_A (normal mode)
VREFA
3.3
V
1.5 KΩ to 3.0 V or GND,
PD = low.
REF_A (power down mode)
VREFA
3.3
V
1.5 KΩ to 3.0 V or GND,
PD = high.
Typical LED Current Table
NORMALIZED ILED – %
100
80
60
40
20
0
R = 15 k
R = 30 k
0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (V)
Figure 11. Typical I-V characteristic of ADNS2051 XY_LED pin
ADNS-2051 fig 11
11
3.5
R1 Value
kΩ
15
18
22
27
33
37
LED current (typical)
mA
42
35
29
23
19
17
PD Pin Timing
PD
IDD
75 FRAMES
tpd
705 µs
tpupd
tCOMPUTE (SEE FIGURE 15)
Figure 12. PD timing normal mode
JOB 389 FIG 12 PD Timing Normal Mode
PD
I LED
PD
tPDW
SCLK
700 µs
REGISTER
READ OPERATION
tCOMPUTE
(POWER DOWN)
Figure 13. PD timing sleep mode
Figure 14. PD minimum pulse width
JOB 389 FIG 13 PD Timing Sleep Mode
PD
JOB 389 FIG 14 PD MINIMUM PULSE WIDTH
OSCILLATOR
START
250 µs
RESET
COUNT
INITIALIZATION
455 µs
NEW ACQUISITION
2410 µs
LED
CURRENT
SCLK
705 µs
OPTIONAL SPI TRANSACTIONS
WITH OLD IMAGE DATA
SPI TRANSACTIONS
WITH NEW IMAGE DATA
tCOMPUTE
AT DEFAULT FRAME RATE
Figure 15. Detail of PD falling edge timing
Quadrature Mode Timing
JOB 389 FIG 15
The output waveforms emulate the output from
encoders. With the resolution set to 400 cpi, from one to
five quadrature states can exist within one frame time.
The minimum state time is 133 µs. If the resolution is
800 cpi, then up to ten quadrature states can exist within
a frame time. If the motion within a frame is greater than
these values, the extra motion will be reported in the
12
next frame. The following diagrams (see Figures 16, 17,
and 18) show the timing for positive X motion, to the
right or positive Y motion, up. If a power down via the PD
pin occurs during a transfer, the transfer will resume after
PD is de-asserted. The timing for that quadrature state
will be increased by the length of the PD time.
X MOTION TO THE RIGHT
Y MOTION UP
XA/YA
FIVE OR MORE
133 µs
133 µs
133 µs
133 µs
133 µs
133 µs
133 µs
133 µs
133 µs
133 µs
XB/YB
XA/YA
FOUR
267 µs
XB/YB
XA/YA
THREE
400 µs
XB/YB
XA/YA
TWO
133 µs
533 µs
XB/YB
XA/YA
ONE
667 µs
XB/YB
~ 667µs @ 1500 FRAMES/SECOND
ONE FRAME
Job 389 Fig 16 Quadrature States Per Frames (400 cpi Mode)
Figure 16. Quadrature states per frame (400 cpi mode)
13
X MOTION TO THE RIGHT
Y MOTION UP
XA/YA
TEN OR MORE
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
XB/YB
XA/YA
NINE
133 µs
XB/YB
XA/YA
EIGHT
200 µs
XB/YB
XA/YA
SEVEN
266 µs
XB/YB
XA/YA
SIX
XB/YB
~ 667µs @ 1500 FRAMES/SECOND
ONE FRAME
Job 389 Fig 17 Quadrature States Per Frames (800 cpi Mode)
Figure 17. Quadrature states per frame (800 cp imode)
14
333 µs
X MOTION TO THE RIGHT
Y MOTION UP
XA/YA
FIVE
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
66.7 µs
400 µs
XB/YB
XA/YA
FOUR
476 µs
XB/YB
XA/YA
THREE
XB/YB
XA/YA
TWO
66.7 µs
XB/YB
XA/YA
ONE
XB/YB
~ 667µs @ 1500 FRAMES/SECOND
ONE FRAME
Job 389 Fig 18 Quadrature States Per Frames (800 cpi Mode)
Figure 18. Quadrature states per frame (800 cpi mode)
15
Quadrature State Machine
The following state machine shows the states of the
quadrature pins. The two things to note are that while
the PD pin is asserted, the state machine is halted. Once
PD is de-asserted, the state machine picks up from where
it left off. State 0 is entered after a power up reset.
PD
+1
STATE 0
-1
PD
STATE 2
STATE
+1
-1
-1
-1
STATE 1
+1
PD
+1
0
1
2
3
X AND Y
OUTPUT
A
0
0
1
1
B
0
1
0
1
STATE 3
PD
Figure 19. Quadrature state machine
Fig. 19 Quadrature State Machine
Quadrature Output Waveform
The two channel quadrature outputs are 5.0 volt CMOS
outputs. The Δx count is used to generate the XA and XB
signals, and Δy count is used for the YA and YB signals.
YA
XA
DOWN MOTION
(- DIRECTION)
LEFT MOTION
(-DIRECTION)
XB
YB
-1
-1
-1
-1
MOTION COUNT
-1
-1
-1
-1
YA
XA
RIGHT MOTION
(+ DIRECTION)
XB
UP MOTION
(+ DIRECTION)
YB
+1
+1
+1
+1
MOTION COUNT
-1
Figure 20. Quadrature output waveform
Job 389 Fig 20 Quadrature Output Waveform
16
MOTION COUNT
-1
-1
-1
MOTION COUNT
Typical Performance Characteristics
Performance characteristics over recommended operating conditions. Typical values at 25°C, VDD = 5.0 V, 18 MHz.
Parameter
Symbol
Min.
Typ.
Max.
Units
Path Error (Deviation)
PERROR
0.5
%
Notes
Path Error (Deviation) is the error from the ideal cursor path. It is expressed as a percentage of total travel and is measured over standard surfaces.
The following graphs (Figures 21, 22, 23, and 24) are the typical performance of the ADNS-2051 sensor, assembled as
shown in the 2D assembly drawing with the HDNS-2100 Lens/Prism, the HDNS-2200 clip, and the HLMP-ED80-XX000
LED (page 3, Figure 4).
TYPICAL RESOLUTION vs. HEIGHT
0.9
450
COUNTS PER INCH
400
350
300
250
200
150
100
1.0
Z
DOF
DOF
RECOMMENDED
OPERATING
REGION
WHITE PAPER
MANILA FOLDER
50
BURL FORMICA
0
DARK WALNUT
RELATIVE RESPONSIVITY
500
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
BLACK COPY
-50
1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
600
700
800
900
1000
WAVELENGTH (nm)
HEIGHT – mm (2.4 = NOMINAL FOCUS)
Figure 21. Typical resolution vs. Z (comparative
surfaces)[2,3]
500
Figure 22. Wavelength responsitivity[1]
ADNS-2051 fig 23
TYPICAL RESOLUTION vs. HEIGHT
AT DIFFERENT LED CURRENT LEVELS
[BRIGHTNESS] (MANILA FOLDER)
450
TYPICAL RESOLUTION vs. HEIGHT
AT DIFFERENT LED CURRENT LEVELS
[BRIGHTNESS] (BLACK COPY)
450
400
400
300
250
200
DOF
DOF
RECOMMENDED
OPERATING
REGION
150
100
50
100%
75%
50%
0
1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
HEIGHT – mm (2.4 = NOMINAL FOCUS)
Figure 23. Typical resolution vs. z (manila folder
and LED variation)[2,3]
ADNS-2051 fig 21
350
COUNTS PER INCH
COUNTS PER INCH
350
Z
300
250
200
150
100
50
0
Z
DOF
DOF
100%
75%
50%
RECOMMENDED
OPERATING
REGION
-50
1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
HEIGHT – mm (2.4 = NOMINAL FOCUS)
Figure 24. Typical resolution vs. z (black copy
and LED variation)[2,3]
ADNS-2051 fig 24
Note:
1. The ADNS-2051 is designed for optimal performance when used with the HLMP-ED80-XX000 (red LED 639 nm). For use with other LED colors
(i.e., blue, green), please consult factory. When using alternate LEDs, there may also be performance degradation and additional eye safety considerations.
2. Z = Distance from Lens Reference plane to Surface.
3. DOF = Depth of Field.
17
Synchronous Serial Port
Write Operation
The synchronous serial port is used to set and read parameters in the ADNS-2051, and can be used to read out the
motion information instead of the quadrature data pins.
Write operations, where data is going from the microcontroller to the ADNS-2051, is always initiated by the
micro-controller and consists of two bytes. The first byte
contains the address (seven bits) and has a “1” as its MSB to
indicate data direction. The second byte contains the data.
The transfer is synchronized by SCLK. The micro-controller
changes SDIO on falling edges of SCLK. The ADNS-2051
reads SDIO on rising edges of SCLK.
The port is a two wire, half duplex port. The host microcontroller always initiates communication; the ADNS-2051
never initiates data transfers.
SCLK:
The serial port clock. It is always generated by
the master (the micro-controller).
SDIO:
The data line.
PD:
A third line is sometimes involved. PD (Power
Down) is usually used to place the ADNS-2051
in a low power mode to meet USB suspend
specification. PD can also be used to force resynchronization between the micro-controller
and the ADNS-2051 in case of an error.
SCLK
CYCLE #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SDIO
1
SDIO DRIVEN BY MICRO-CONTROLLER
Figure 25. Write operation
ADNS-2051 fig 25
120 ns 120 ns
SCLK
SDIO
120 ns, MIN.
tsetup = 60 ns, MIN.
Figure 26. SDIO setup and hold times SCLK pulse
width
ADNS-2051 fig 26
18
DON'T
CARE
Read Operation
A read operation, which means that data is going from the
ADNS-2051 to the micro-controller, is always initiated by
the micro-controller and consists of two bytes. The first
byte contains the address, is written by the micro-controller, and has a “0” as its MSB to indicate data direction.
The second byte contains the data and is driven by the
ADNS-2051. The transfer is synchronized by SCLK. SDIO is
changed on falling edges of SCLK and read on every rising
SCLK
CYCLE #
1
2
3
4
5
6
7
A6
A5
A4
A3
A2
A1
edge of SCLK. The micro-controller must go to a high Z
state after the last address data bit. The ADNS-2051 will
go to the high Z state after the last data bit (see detail “B”
in Figure 28). One other thing to note during a read
operation is that SCLK will need to be delayed after
the last address data bit to ensure that the ADNS-2051
has at least 100 µs to prepare the requested data. This is
shown in the timing diagrams below.
8
9
10
11
12
13
14
15
16
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SDIO
0
A0
SDIO DRIVEN BY MICRO-CONTROLLER
SDIO DRIVEN BY ADNS-2051
DETAIL "A"
DETAIL "B"
Figure 27. Read operation
120 ns, MAX.
tHOLD
100 µs, MIN.
DETAIL "A"
SCLK
ADNS-2051 fig 27
MICROCONTROLLER
TO ADNS-2051
SDIO HANDOFF
60 ns, MIN.
SDIO
A1
120 ns, MAX.
0 ns, MIN.
Hi-Z
A0
D7
D6
0 ns, MIN.
120 ns, MIN.
Figure 28. Microcontroller to ADNS-2051 SDIO handoff
DETAIL "B"
120 ns, MIN.
SCLK
ADNS-2051 TO
MICROCONTROLLER
SDIO HANDOFF
ADNS-2051
fig 28
10 ns, MAX.
SDIO
D0
RELEASED BY 2051
Figure 29. ADNS-2051 to microcontroller SDIO handoff
ADNS-2051 fig 29
19
R/W BIT OF NEXT ADDRESS
DRIVEN BY MICRO
Note:
The 120 ns high state of SCLK is the minimum
data hold time of the ADNS-2051. Since the
falling edge of SCLK is actually the start of
the next read or write command, the ADNS2051 will hold the state of D0 on the SDIO line
until the falling edge of SCLK. In both write
and read operations, SCLK is driven by the
micro-controller.
Serial port communications is not allowed
while PD (power down) is high. See
“Error Detection and Recovery” regarding resynchronizing via PD.
Forcing the SDIO Line to the Hi-Z State
To place the SDIO pin into the Hi-Z state, raise the PD
pin for 100 µs (min). The PD pin can stay high, with the
ADNS-2051 in the shutdown state, or the PD pin can be
lowered, returning the ADNS-2051 to normal operation.
The SDIO line will now be in the Hi-Z state.
There are times when the SDIO line from the ADNS2051 should be in the Hi-Z state. If the microprocessor
has completed a write to the ADNS-2051, the SDIO line
is Hi-Z, since the SDIO pin is still configured as an input.
However, if the last operation from the microprocessor
was a read, the ADNS-2051 will hold the D0 state on
SDIO until a falling edge of SCLK.
100 µs
PD
Hi-Z
SDIO
Figure 30. SDIO Hi-Z state and timing
Required ADNS-2051
Timing between
Read and Write Commands (tsxx)
fig 30
There are minimum timing requirements between read
and write commands on the serial port.
second write command occurs before the 100 microsecond required delay, then the first write command may
not complete correctly.
If the rising edge of the SCLK for the last data bit of the
tSWW >100 µs
SCLK
ADDRESS
DATA
ADDRESS
WRITE OPERATION
DATA
WRITE OPERATION
Figure 31. Timing between two write commands
ADNS-2051 fig 31
If the rising edge of SCLK for the last address bit of
the read command occurs before the 100 microsecond required delay, then the write command may not
complete correctly.
tSWR >100 µs
•••
SCLK
ADDRESS
DATA
ADDRESS
•••
WRITE OPERATION
NEXT READ OPERATION
Figure 32. Timing between write and read commands
ADNS-2051 fig 32
20
The falling edge of SCLK for the first address bit of either the read or write command must be at least 120 ns after the
last SCLK rising edge of the last data bit of the previous read operation.
tHOLD >100 µs
tSRW, tSRR >120 µs
•••
SCLK
ADDRESS
DATA
ADDRESS
•••
READ OPERATION
Figure 33. Timing between read and either write or subsequent read commands
ADNS-2051 fig 33
SCLK
DATA
PD
>1 µs
Figure 34. Timing between SCLK and PD rising edge
ADNS-2051 fig 34
21
NEXT READ
OR WRITE OPERATION
Error Detection and Recovery
1. The ADNS-2051 and the micro-controller might get
out of synchronization due to ESD events, power supply droops or micro-controller firmware flaws. In such a
case, the micro-controller should raise PD for 100 µs.
The ADNS-2051 will reset the serial port but will not
reset the registers and be prepared for the beginning
of a new transmission.
2. The ADNS-2051 has a transaction timer for the serial port.
If the sixteenth SCLK rising edge is spaced more than
approximately 0.9 seconds from the first SCLK edge of
the current transaction, the serial port will reset.
3. Invalid addresses:
– Writing to an invalid address will have no effect.
Reading from an invalid address will return all
zeros.
4. Collision detection on SDIO
– The only time that the ADNS-2051 drives the SDIO
line is during a READ operation. To avoid data
collisions, the micro-controller should relinquish
SDIO before the falling edge of SCLK after the last
address bit. The ADNS-2051 begins to drive
SDIO after the next rising edge of SCLK. The
ADNS-2051 relinquishes SDIO within 120 ns of the
falling SCLK edge after the last data bit. The microcontroller can begin driving SDIO any time afterthat.
In order to maintain low power consumption in nor
mal operation or when the PD pin is pulled high, the
micro-controller should not leave SDIO floating un
til the next transmission (although that will not
cause any communication difficulties).
5. In case of synchronization failure, both the ADNS-2051
and the micro-controller may drive SDIO. The ADNS2051 can withstand 30 mA of short circuit current
and will withstand infinite duration short circuit conditions.
6. Termination of a transmission by the micro-controller may sometimes be required (for example, due to
a USB suspend interrupt during a read operation). To
accomplish this the micro-controller should raise PD.
The ADNS-2051 will not write to any register and will
reset the serial port (but nothing else) and be prepared
for the beginning of future transmissions after PD goes
low.
7. The micro-controller can verify success of write operations by issuing a read command to the same address
and comparing written data to read data.
8. The micro-controller can verify the synchronization of
the serial port by periodically reading the product ID
register.
VDD
PD
SCLK
ADDRESS = 0x00
SDIO
PROBLEM AREA
Figure 35. Power up serial port watchdog timer sequence
ADNS-2051 fig 35
22
DATA = 0x02
Notes on Power up and the Serial Port
The sequence in which VDD, PD, SCLK, and SDIO are set
during powerup can affect the operation of the serial port.
The diagram below shows what can happen shortly after
powerup when the microprocessor tries to read data from
the serial port.
This diagram shows the VDD rising to valid levels, at some
point the microcontroller starts its program, sets the SCLK
and SDIO lines to be outputs, and sets them high. It then
waits to ensure that the ADNS-2051 has powered up and
is ready to communicate. The microprocessor then tries
to read from location 0x00, Product_ID, and is expecting
a value of 0x02. If it receives this value, it then knows that
the communication to the ADNS-2051 is operational.
The problem occurs if the ADNS-2051 powers up before
the microprocessor sets the SCLK and SDIO lines to be
outputs and high. The ADNS-2051 sees the raising of the
SCLK as a valid rising edge, and clocks in the state of the
SDIO as the first bit of the address (sets either a read or a
write depending upon the state).
In the case of SDIO low, then a read operation has started.
When the microprocessor begins to actually send the
address, the ADNS-2051 already has the first bit of an
address. When the seventh bit is sent by the micro, the
ADNS-2051 has a valid address, and drives the SDIO line
high within 120 ns (see detail “A” in Figure 27 and Figure
28). This results in a bus fight for SDIO. Since the address
is wrong, the data sent back will be incorrect.
In the case of SDIO high, a write operation is started. The
address and data are out of synchronization, and the wrong
data will be written to the wrong address.
VDD
> tSPTT
PD
SCLK
ADDRESS = 0x00
DATA = 0x02
SDIO
Figure 36. Power up serial port watchdog timer sequence
ADNS-2051 fig 36
4 ms
VDD
PD
SCLK
ADDRESS = 0x00
DATA = 0x02
SDIO
Figure 37. Power up serial port PD sync sequence
Two Solutions
ADNS-2051 fig 37
There are two different ways to solve the problem, waiting
for the serial port watchdog timer to time out, or using
the PD line to reset the serial port.
1. Serial Port Watchdog Timer Timeout
If the microprocessor waits at least tSPTT from VDD
valid, it will ensure that the ADNS-2051 has powered up and the watchdog timer has timed out. This
assumes that the microprocessor and the ADNS-2051
share the same power supply. If not, then the microprocessor must wait tSPTT from ADNS-2051 VDD
valid. Then when the SCLK toggles for the address, the
ADNS-2051 will be in sync with the microprocessor.
23
2. PD Sync
The PD line can be used to resync the serial port. If the
microprocessor waits for 4 ms from VDD valid, and then
outputs a valid PD pulse (see Figure 15), then the serial
port will be ready for data.
Resync Note
If the microprocessor and the ADNS-2051 get out of sync,
then the data either written or read from the registers will
be incorrect. An easy way to solve this is to output a PD
pulse to resync the parts after an incorrect read.
SPI communication code for the Cypress CY7C63000 or CY7C63001
(Please consult factory for the CY7C63722 or CY7C63723 codes.)
Note: This programming sequence is not covered in Avago's product warranty. It is only a recommended example when using the mentioned
Cypress microcontrollers. For the latest updates on Cypress microcontrollers, please contact Cypress at email: [email protected] or call (858)
613-7929 (US).
The following code can be used to implement the SPI data communications. See the schematic in Figure 9.
; Notes:
; CY7C63001 20pin package
; ADNS-2051
; SDIO line connected to pin5 (P1.0)
; PD connected to pin 16 (P1.1)
; SCLK line connected to pin15 (P1.3)
; I/O port
Port1_Data:
equ 01h
Port1_Interrupt:
equ 05h
Port1_Pullup: equ 09h ;
; Port bit definitions
SDIO:
equ 01h
PD:
equ 02h
SCLK:
equ 08h Pt1_Current:
equ 00h ;
; GPIO Isink registers
Port1_Isink: equ 38h
Port1_Isink0: equ 38h
Port1_Isink1: equ 39h
Port1_Isink3: equ 3Bh
;
;
; data memory variables
spi_addr: equ 40h spi_data: equ 41h bit_counter:
equ 44h
port1_wrote:
equ 45h
;
;
; initialize Port 1
;
mov A, Pt1_Current iowr Port1_Isink0
iowr Port1_Isink1
iowr Port1_Isink3
mov A, 0h
iowr Port1_Pullup
mov A, ~(PD|SDIO)
mov [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data
;
;
;
;
24
;
;
;
GPIO data port 1
Interrupt enable for port 1
Pullup resistor control for port 1
;
;
;
;
bit 0
bit 1
bit 3
port1 current setting
;
;
;
;
address of spi writes
data of spi writes
SPI bit counter
what we wrote last
;
;
;
;
;
select DAC setting
isink current Port 1 bit[0]
isink current Port 1 bit[1]
isink current Port 1 bit[3]
enable Port 1 bit [7:0] pullups
;
turn on the ADNS-2051
;
PD low, SCLK, SDIO
mov A, 0
iowr Port1_Interrupt
; disable port 1 interrupts
There are possible problems with the SPI port if the microcontroller starts executing
instructionsbefore the ADNS-2051 sensor has powered up. See page 18 for details.
It is assumed that power to the microcontroller is OK if the next instructions can be executed.
These instructions will reset the SPI port of the sensor.
Resync_sensor:
;
;
;
;
;
;
;
;
;
;
;
;
mov A,~(SCLK|SDIO|PD)
and [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data
call delay700us
call delay700us
call delay700us
call delay700us
call delay700us
call delay700us
mov A, (SCLK|SDIO|PD
or [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data
call delay700us
mov A, ~PD
and [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data
call delay700us
call delay700us
call delay700us
call delay700us
call delay700us
call delay700us
set the SCLK, SDIO and PD lines low
;
;
;
;
If the power to the sensor needs more time
to stabilize, insert a delay here
wait about 4 milliseconds for the sensor
oscillator to stabilize
;
;
;
set the SCLK, SDIO and PD lines high
this shuts down the oscillator and
resets the SPI port
;
;
;
wait for the PD to reset the part
set the PD line low to put the sensor
back into normal operation
;
;
wait about 4 milliseconds for the sensor
oscillator to stabilize
;
sensor SPI port now in sync
ReadSPI routine
Includes delays for long traces or cables between the uP and ADNS-2051
Has correct timing of SCLK and SDIO
On entry:
spi_addr = Address of SPI register in the ADNS-2051
spi_data = undefined
On exit
spi_addr = undefined
spi_data = register contents from ADNS-2051
ReadSPI:
Waitrspi:
mov A, 64
mov [bit_counter], A
nop
nop
nop
nop
nop
nop
dec [bit_counter]
jnz Waitrspi
mov A,~80h
and [spi_addr], A
call writeaddr
Waitrspi2:
25
;
mov A,64
mov [bit_counter], A
nop
nop
nop
nop
nop
nop
dec [bit_counter]
jnz Waitrspi2
mov A, 0h
;
;
wait 200us (optional)
(about 3us per loop)
;
read address
;
lower MSB of address (read)
;
;
wait 200us (about 3us per loop)(100us minimum required)
wait for data to be ready
;
clear the data
nextr:
rd1:
rdx:
mov [spi_data], A
mov A, 08h
mov [bit_counter], A
mov A, SDIO
or [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data mov A, ~SCLK
and [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data nop
nop
nop
nop
nop
nop
nop
mov A,[spi_data]
asl
mov [spi_data], A
iord Port1_Data
and A, SDIO
jz rdx
mov A, 01h
or [spi_data], A
mov A, SCLK
or [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data nop
nop
nop
nop
nop
nop
nop
dec [bit_counter]
jnz nextr
ret
;
write a 1 to SDIO
;
lower SCLK
;
;
;
;
;
wait for cable to settle
if ADNS-2051 is connected to
IC via short PCB traces,
then the number of NOPs can
reduced or eliminated
;
shift next bit
;
;
shift next bit
read SDIO
;
raise SCLK
;
wait for cable to settle
;
; WriteSPI routine
;
; Includes delays for long traces or cables between the uP and ADNS-2051.
; Has correct timing of SCLK and SDIO
;
; On entry:
spi_addr = Address of SPI register in the ADNS-2051
; spi_data = Data to be written to the SPI register
;
; On exit
spi_addr = undefined
; spi_data = undefined
;
WriteSPI:
mov A, 64
; wait 200us (optional)
mov [bit_counter], A
; about 3us per loop
Waitspi:
nop
nop
nop
nop
nop
nop
dec [bit_counter]
jnz Waitspi
; write address
26
writeaddr:
nexta:
addr1:
addr0:
addrx:
wrdata:
nextw:
wr1:
wr0:
wrx:
27
mov A, 80h
or [spi_addr], A
call writeaddr
jmp wrdata
mov A, 08h
mov [bit_counter], A
mov A, ~SCLK
and [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data mov A, [spi_addr]
asl
mov [spi_addr], A
jnc addr0
mov A, SDIO
or [port1_wrote], A
jmp addrx
mov A, ~SDIO
and [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data nop
nop
nop
nop
nop
nop
nop
mov A, SCLK
or [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data nop
nop
nop
nop
nop
nop
nop
dec [bit_counter]
jnz nexta
ret
mov A, 08h
mov [bit_counter], A
mov A, ~SCLK
and [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data mov A, [spi_data]
asl
mov [spi_data], A
jnc wr0
mov A, SDIO
or [port1_wrote], A
jmp wrx
mov A, ~SDIO
and [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data nop
nop
nop
nop
nop
nop
nop
;
set MSB of address (write)
;
8 bits to shift out
;
lower SCLK
;
shift next bit
;
raise SDIO
;
lower SDIO
;
wait for cable to settle
;
raise SCLK
;
;
ADNS-2051 reads the address bit
wait for cable to settle
;
8 bits of data
;
lower SCLK
;
shift next bit
;
raise SDIO
;
lower SDIO
;
wait for cable to settle
delay700us:
waitd0:
mov A, SCLK
or [port1_wrote], A
mov A, [port1_wrote]
iowr Port1_Data
nop
nop
nop
nop
nop
nop
nop
dec [bit_counter]
jnz nextw
ret
; raise SCLK
;
;
ADNS-2051 reads the data bit
wait for cable to settle
mov A, ffh
mov [bit_counter], A
;
;
wait for 710us
reuse bit_counter
;
2us
nop
nop
nop
nop
nop
nop
dec [bit_counter]
jnz waitd0
ret
Example calling syntax
;
; WriteSPI
; ; Set register 0a to 40h, LED blink mode
mov A, 0ah
mov [spi_addr], A
mov A, 40h
mov [spi_data], A
call WriteSPI
;
;
;
;
28
; move address into A
; move address into spi_addr
; move data into A
; move data into spi_data
; call WriteSPI routine, on return, ; spi_addr and spi_data will be undefined
ReadSPI
Read register 02h, the motion register
mov A, 02h
mov [spi_addr], A
call ReadSPI
;
;
;
;
move address into A
move address into spi_addr
call ReadSPI, on return, data is in spi_data,
spi_addr is undefined
Registers
The ADNS-2051 can be programmed through registers, via the serial port, and configuration and motion data can
be read from these registers.
Address
Register
Address
Register
Address
Register
0x00
Product_ID
0x06
Average_Pixel
0x0c
Data_Out_Lower
0x01
Revision_ID
0x07
Maximum_Pixel
0x0d
Data_Out_Upper
0x02
Motion
0x08
Reserved
0x0e
Shutter_Lower
0x03
Delta_X
0x09
Reserved
0x0f
Shutter_Upper
0x04
Delta_Y
0x0a
Configuration_bits
0x10
Frame_Period_Lower
0x05
SQUAL
0x0b
Reserved
0x11
Frame_Period_Upper
Product_ID
Access: Read
Bit
Field
Address: 0x00
Reset Value: 0x02
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
PID1
PID0
Data Type: Eight bit number with the product identifier.
USAGE: The value in this register does not change, it can be used to verify that the
serial communications link is OK.
Revision_ID
Access: Read
Bit
Field
Address: 0x01
Reset Value: 0xNN
7
6
5
4
3
2
1
0
RID7
RID6
RID5
RID4
RID3
RID2
RID1
RID0
Data Type: Eight bit number with current revision of the IC.
USAGE: NN is a value between 00 and FF which represent the current design revision
of the device.
Motion
Access: Read
Address: 0x02
Reset Value: 0x00
Bit
Field
7
6
5
4
3
2
1
0
MOT
Reserved
FAULT
OVFY
OVFX
Reserved
Reserved
RES
Data Type: Bit field
USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If so, then the user
should read registers 0x03 and 0x04 to get the accumulated motion. It also tells if the motion buffers have overflowed and
whether or not an LED fault occurred since the last reading. The current resolution is also shown.
29
Field Name
Description
MOT
Motion since last report or PD
0 = No motion
1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers
Reserved
Reserved for future
FAULT
LED Fault detected – set when R_BIN is too low or too high, shorts to VDD or Ground
0 = No fault
1 = Fault detected
OVFY
Motion overflow Y, ΔY buffer has overflowed since last report
0 = No overflow
1 = Overflow has occurred
OVFX
Motion overflow X, ΔX buffer has overflowed since last report
0 = No overflow
1 = Overflow has occurred
Reserved
Reserved for future
Reserved
Reserved for future
RES
Resolution in counts per inch
0 = 400
1 = 800
Notes for Motion:
1. Reading this register freezes the Delta_X and Delta_Y register values. Read this register before reading the Delta_X and Delta_Y registers. If
Delta_X and Delta_Y are not read before the motion register is read a second time, the data in Delta_X and Delta_Y will be lost.
2. Avago RECOMMENDS that registers 0x02, 0x03 and 0x04 be read sequentially.
3. Internal buffers can accumulate more than eight bits of motion for X or Y. If either one of the internal buffers overflows, then absolute path data
is lost, and the OVFX or OVFY bit is set. These bits (OVFX and OVFY) are cleared once some motion has been read from the Delta_X and Delta_Y
registers, and if the buffers are not at full scale. Since more data is present in the buffers, the cycle of reading the Motion, Delta_X and Delta_Y
registers should be repeated until the motion bit (MOT) is cleared. Until MOT is cleared, either the Delta_X or Delta_Y registers will read either
positive or negative full scale. If the motion register has not been read for a long time, at 400 cpi it may take up to 16 read cycles to clear the
buffers, at 800 cpi, up to 32 cycles.
4. FAULT is a sticky bit that is cleared by reading the Motion register. It signifies that an LED fault has occurred since the last time the motion register
was read. Once an LED fault has cleared, the hardware will drive the LED normally.
Delta_X
Access: Read
Address: 0x03
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
X7
X6
X5
X4
X3
X2
X1
X0
Data Type: Eight bit 2‘s complement number.
USAGE: X movement is counts since last report. Absolute value is determined by
resolution. Reading clears the register.
MOTION
-128
-127
-2
-1
0
+1
+2
+126
+127
DELTA_X
80
81
FE
FF
00
01
02
7E
7F
ADNS-2051 Delta X
30
Delta_Y
Access: Read
Address: 0x04
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data Type: Eight bit 2‘s complement number.
USAGE: Y movement is counts since last report. Absolute value is determined by
resolution. Reading clears the register.
MOTION
-128
-127
-2
-1
0
+1
+2
+126
+127
DELTA_Y
80
81
FE
FF
00
01
02
7E
7F
Surface_Quality
Access: Read
Bit
Field
Address: 0x05
Reset
Value: 0x00
ADNS-2051 Delta Y
7
6
5
4
3
2
1
0
SQ7
SQ6
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Data Type: Eight bit number.
USAGE: SQUAL is a measure of the number of features visible by the sensor in the
current frame. The maximum value is 255. Since small changes in the current frame
can result in changes in SQUAL, variations in SQUAL when looking at a surface are
expected. The graph below shows 250 sequentially acquired SQUAL values, while a
sensor was moved slowly over white paper. SQUAL is nearly equal to zero, if there is
no surface below the sensor.
SQUAL VALUES (WHITE PAPER)
192
128
64
0
0
25
50
75
100
125
150
The focus point is important and could affect the squal value, the graph below
ADNS-2051
Values
showing another setup with various z-height. The
graph Squal
clearly
shows that the
squal count is dependent on focus distance.
Note: This graph is obtained by getting multiple readings over different heights.
175
200
225
250
1.4
NORMALIZED SQUAL COUNTS
SQUAL VALUE
256
1.2
1.0
0.8
0.6
0.4
X+ 3σ
X
X – 3σ
0.2
0
-1.0 -0.8 -0.5 -0.3
0
0.25
0.5
0.75 1.0
DELTA FROM NOMINAL FOCUS (mm)
Figure 38. Typical mean squal vs. Z (white paper)
ADNS-2051 fig 38
31
Average_Pixel
Access: Read
Address: 0x06
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
0
0
AP5
AP4
AP3
AP2
AP1
AP0
Data Type: Six bit number.
USAGE: Average Pixel value in current frame. Minimum value = 0,
maximum = 63. The average pixel value can be adjusted every frame. Shown below
is a graph of 250 sequentially acquired average pixel values, while the sensor was
moved slowly over white paper.
AVERAGE PIXEL VALUE
AVERAGE PIXEL (WHITE PAPER)
64
48
32
16
0
0
25
50
75
Maximum_Pixel
Access: Read
100
125
150
175
200
225
250
175
200
225
250
Address:ADNS-2051
0x07 Average Pixel
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
0
0
MP5
MP4
MP3
MP2
MP1
MP0
Data Type: Six bit number.
USAGE: Maximum Pixel value in current frame. Minimum value = 0,
maximum value = 63. The maximum pixel value can be adjusted every frame. Shown
below is a graph of 250 sequentially acquired maximum pixel values, while the sensor was moved slowly over white paper.
MAXIMUM PIXEL VALUE
MAXIMUM PIXEL (WHITE PAPER)
64
48
32
16
0
0
Reserved
Reserved
25
50
75
100
125
Address: 0x08
Address: 0x09
ADNS-2051 Max. Pixel
32
150
Configuration_bits
Access: Read/Write
Bit
Field
Address: 0x0a
Reset Value: 0x00
7
6
5
4
3
2
1
0
RESET
LED_MODE
Sys Test
RES
PixDump
Reserved
Reserved
Sleep
Data Type: Bit field
USAGE: Register 0x0a allows the user to change the configuration of the sensor. Shown below are the bits, their default values,
and optional values.
Field Name
Description
RESET
Power up defaults (bit always reads 0)
0 = No effect
1 = Reset registers and bits to power up default settings (bold entries)
LED_MODE
LED Shutter Mode
0 = Shutter mode off (LED always on) (even if no motion up to 1 sec.)
1 = Shutter mode on (LED only on when the electronic shutter is open)
Sys Test
System Tests (bit always reads 0)
0 = No tests
1 = perform all system tests, output 16 bit CRC via Data_Out_Upper and Data_Out_Lower registers.
Note: Since part of the system test is a RAM test, the RAM will be overwritten with the default values
when the test is done. If any configuration changes from the default are needed for operation, make
the changes AFTER the system test is run. This operation requires substantially more time to
complete than other register transactions.
RES
Resolution in counts per inch
0 = 400
1 = 800
Pix Dump
Dump the pixel array through Data_Out_Upper and Data_Out_Lower, 256 bytes
0 = disabled
1 = dump pixel array
Reserved
Reserved
Reserved
Reserved
Sleep
Sleep Mode
0 = Normal, fall asleep after one second of no movement (1500 frames/s)
1 = Always awake
Reserved
33
Address: 0x0b
Data_Out_Lower
Access: Read
Bit
Field
Address: 0x0c
Reset Value: undefined
7
6
5
4
3
2
1
0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Data_Out_Upper
Access: Read
Bit
Field
Address: 0x0d
Reset Value: undefined
7
6
5
4
3
2
1
0
DO15
DO14
DO13
DO12
DO11
DO10
DO9
DO8
Data Type: Sixteen bit word.
USAGE: Data can be written to these registers from the system self test, or the pixel
dump command. The data can be read out 0x0d, or 0x0d first, then 0x0c.
Data_Out_Upper
Data_Out_Lower
System test result 1:
FE
D4
System test result 2:
4D
10
Pixel Dump command
Pixel Address
Pixel Data (Lower 6 bits)
Once the pixel dump command is given, the sensor
writes the address and the value for the first pixel into
the Data_Out_Upper and Data_Out_Lower registers.
The MSB of Data_Out_Lower is the status bit for the
data. If the bit is high, the data are NOT valid. Once the
MSB is low, the data for that particular read are valid
and should be saved. The pixel address and data will
then be incremented on the next frame. Once the pixel
dump is complete, the PixDump bit in register 0x0a
should be set to zero. To obtain an accurate image, the
LED needs to be turned on by changing the sleep mode
of the configuration register 0x0a to always awake.
34
Note
One of two results returned. These
values are subject to change with
each device design revision.
Pixel Address Map
(Looking through the HDNS-2100 Lens)
LAST PIXEL
FF EF DF CF BF AF 9F 8F 7F 6F 5F 4F 3F 2F 1F 0F
FE EE DE CE BE AE 9E 8E 7E 6E 5E 4E 3E 2E 1E 0E
FD ED DD CD BD AD 9D 8D 7D 6D 5D 4D 3D 2D 1D 0D
FC EC DC CC BC AC 9C 8C 7C 6C 5C 4C 3C 2C 1C 0C
FB EB DB CB BB AB 9B 8B 7B 6B 5B 4B 3B 2B 1B 0B
FA EA DA CA BA AA 9A 8A 7A 6A 5A 4A 3A 2A 1A 0A
F9 E9 D9 C9 B9 A9 99 89 79 69 59 49 39 29 19 09
F8 E8 D8 C8 B8 A8 98 88 78 68 58 48 38 28 18 08
F7 E7 D7 C7 B7 A7 97 87 77 67 57 47 37 27 17 07
F6 E6 D6 C6 B6 A6 96 86 76 66 56 46 36 26 16 06
F5 E5 D5 C5 B5 A5 95 85 75 65 55 45 35 25 15 05
F4 E4 D4 C4 B4 A4 94 84 74 64 54 44 34 24 14 04
F3 E3 D3 C3 B3 A3 93 83 73 63 53 43 33 23 13 03
F2 E2 D2 C2 B2 A2 92 82 72 62 52 42 32 22 12 02
F1 E1 D1 C1 B1 A1 91 81 71 61 51 41 31 21 11 01
F0 E0 D0 C0 B0 A0 90 80 70 60 50 40 30 20 10 00
FIRST PIXEL
TOP X-RAY VIEW OF MOUSE
ADNS-2001 Pixel Address Map
POSITIVE Y
LB
RB
16
1
A2051
YYWW
9
8
POSITIVE X
Figure 39. Directions are for a complete mouse, with the HDNS-2100 lens
ADNS-2051 fig 39
35
Pixel Dump Pictures
The following images (Figure 40) are the output of the pixel dump command. The data ranges from zero for complete
black, to 63 for complete white. An internal AGC circuit adjusts the shutter value to keep the brightest feature (max.
pixel) in the mid 50s.
(a) White Paper
(b) Manila Folder
(c) Neoprene Mouse Pad (Gray)
(d) USAF Test Chart Group 3, Element 1 8 line pairs per mm
Figure 40. Pixel dump pictures
36
Shutter_Lower
Access: Read
Address: 0x0e
Reset Value: 0x64
Bit
7
6
5
4
3
2
1
0
Field
S7
S6
S5
S4
S3
S2
S1
S0
Shutter_Upper
Access: Read
Bit
Field
Address: 0x0f
Reset Value: 0x00
7
6
5
4
3
2
1
0
S15
S14
S13
S12
S11
S10
S9
S8
Data Type: Sixteen bit word.
USAGE: Units are clock cycles; default value is 64. Read Shutter_Upper first, then
Shutter_Lower. They should be read consecutively. The shutter is adjusted to keep
the average and maximum pixel values within normal operating ranges. The shutter
value can be adjusted to a new value on every frame. When the shutter adjusts, it
changes by ±1/16 of the current value. Shown below is a graph of 250 sequentially
acquired shutter values, while the sensor was moved slowly over white paper.
SHUTTER VALUES (WHITE PAPER)
SHUTTER VALUE
(CLOCK CYCLES)
800
600
400
200
0
0
25
50
75
100
125
NORMALIZED SHUTTER VALUE (COUNTS)
The focus point is important and could affect the shutter
value. The graph below shows another setup with various
z-height. This graph clearly shows that the shutter value
ADNS-2051 Shutter Value
is dependent on focus distance.
TYPICAL SHUTTER vs. Z (WHITE PAPER)
3.5
X+ 3σ
X
X – 3σ
3.0
2.5
2.0
1.5
1.0
0.5
0
-1.0 -0.8 -0.5 -0.3
0
0.25
0.5
0.75 1.0
DISTANCE FROM NOMINAL FOCUS (mm)
Figure 41. Typical shutter vs. Z (white paper)
ADNS-2051 Shutter Graph
Note: This graph shows average readings over different
heights.
37
150
175
200
225
250
The maximum value of the shutter is dependent upon the frame rate and clock
frequency. The formula for the maximum shutter value is:
Clock Frequency
Max. Shutter Value = Frame Rate –2816
For a clock frequency of 18 MHz, the following table shows the maximum
shutter value. 1 clock cycle is 55.56 nsec.
Max Shutter
Shutter
Frames/second
Decimal
Hex
Upper
Lower
2300
5010
0x1392
13
92
2000
6184
0x1828
18
28
1500
9184
0x23E0
23
E0
1000
15184
0x3B50
3B
50
500
33184
0x81A0
81
A0
Frame_Period_Lower
Access: Read/Write
Bit
Field
Address: 0x10
Reset Value: 0x20
7
6
5
4
3
2
1
0
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
Frame_Period_Upper
Access: Read/Write
Bit
Field
← Default Max. Shutter
Address: 0x11
Reset Value: 0xd1
7
6
5
4
3
2
1
0
FP15
FP14
FP13
FP12
FP11
FP10
FP9
FP8
Data Type: Sixteen bit 2‘s complement word.
USAGE: The frame period counter counts up until it overflows. Units are clock cycles.
The formula is:
Counts (hex)
←
←
Clock Rate = Counts (decimal)
Frame Rate
Counts (2‘s complement hex)
For an 18 MHz clock, here are the Frame_Period values for popular frame rates.
Counts
Frame_Period
Frames/second
Decimal
Hex
2‘s Comp
Upper
Lower
2300*
7826
0x1E92
0xE16E
E1
6E
2000*
9000
0x2328
0xDCD8
DC
D8
1500
12000
0x2EE0
0xD120
D1
20
1000
18000
0x4650
0xB9B0
B9
B0
500
36000
0x8CA0
0x7360
73
60
*Note:
To optimize tracking performance on dark surfaces, it is recommended that an adaptive frame
rate based on shutter value be implemented, for frame rates greater than 1500. Changing
the frame rate results in changes in the maximum speed, acceleration limits, and dark surface
performance.
To read from the registers, read Frame_Period_Upper first followed by Frame_Period_Lower.
To write to the registers, write Frame_Period_Lower first followed by Frame_Period_Upper.
38
← Default Frame Time
← Minimum Frame Time
IC Register State after Reset (power up or setting bit 7, register 0x0a)
Address
Register
Value
Meaning
0x0
Product_ID
0x02
Product ID = 2 (Fixed value)
0x01
Revision_ID
0xNN
Revision of IC (Fixed value). (For each device design revision.)
0x02
Motion
0x00
No Motion
LED = No Fault
No X data overflow
No Y data overflow
Resolution is 400 counts per inch
0x03
Delta_X
0x00
No X motion
0x04
Delta_Y
0x00
No Y motion
0x05
SQUAL
0x00
No image yet to measure
0x06
Average_Pixel
0x00
No image yet to measure
0x07
Maximum_Pixel
0x00
No image yet to measure
0x08
Reserved
—
0x09
Reserved
—
0x0a
Configuration_bits
0x00
Part is not Reset
LED Shutter Mode is off
No System tests
Resolution = 400 counts per inch
Pixel Dump is disabled
Sleep mode is enabled
0x0b
Reserved
—
0x0c
Data_Out_Lower
undefined
No data to read
0x0d
Data_Out_Upper
undefined
No data to read
0x0e
Shutter_Lower
0x64
Initial shutter value
0x0f
Shutter_Upper
0x00
Initial shutter value
0x10
Frame_Period_Lower
0x20
Initial frame period value (corresponds to 1500 fps)
0x11
Frame_Period_Upper
0xd1
Initial frame period value (corresponds to 1500 fps)
39
Optical Mouse Design References
Application Note AN1179
Eye Safety calculation AN1228
Ordering Information
Specify part number as follows:
ADNS-2051 = Sensor IC in a 16-pin staggered DIP,
20 per tube.
HDNS-2100 = Round Optical Mouse Lens
HDNS-2100#001 = Trimmed Optical Mouse Lens
HDNS-2200 = LED Assembly Clip (Black)
HDNS-2200#001 = LED Assembly Clip (Clear)
HLMP-ED80-XX000 = LED
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved. Obsoletes 5988-8477EN
AV02-1364EN - September 3, 2008