ICST ICS84314AYLF 350mhz, crystal-to-3.3v/2.5v lvpecl frequency synthesizer w/fanout buffer Datasheet

ICS84314
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS84314 is a general purpose quad output
frequency synthesizer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. When the device uses parallel loading, the M bits are programmable and
the output divider is hard-wired for divide by 2 thus providing
a frequency range of 125MHz to 350MHz. In serial programming mode, the M bits are programmable and the output divider can be set for either divide by 2 or divide by 4, providing
a frequency range of 62.5MHz to 350MHz. The low cyclecycle jitter and broad frequency range of the ICS84314 make
it an ideal clock generator for a variety of demanding applications which require high performance.
• Fully integrated PLL
ICS
• 4 differential 3.3V or 2.5V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS TEST_CLK input
• Output frequency range: 62.5MHz to 350MHz
• VCO range: 250MHz to 700MHz
• Parallel interface for programming counter
and output dividers during power-up
• Serial 3 wire interface
• Cycle-to-cycle jitter: 23ps (typical)
• Output skew: 16ps (typical)
• Output duty cycle: 49% < odc < 51%, fout ≤ 125MHz
• Full 3.3V or mixed 3.3V core, 2.5V operating supply
• 0°C to 85°C ambient operating temperature
• Lead-Free package available
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL1
XTAL2
nP_LOAD
VCO_SEL
M0
M1
M2
M3
VCO_SEL
32 31 30 29 28 27 26 25
XTAL_SEL
TEST_CLK
0
XTAL1
OSC
1
XTAL2
÷ 16
PLL
XTAL_SEL
M6
3
22
VCCA
M7
4
21
S_LOAD
M8
5
20
S_DATA
VEE
6
19
S_CLOCK
VCC
7
18
MR
VCCO
8
17
VCCO
9 10 11 12 13 14 15 16
nQ3
Q3
nQ2
Q2
Q1
nQ1
nQ1
1
÷2
÷4
ICS84314
Q1
0
÷2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
TEST_CLK
23
nQ0
÷M
24
2
Q0
VCO
1
M5
Q0
nQ0
PHASE DETECTOR
MR
M4
Q2
nQ2
Q3
nQ3
CONFIGURATION
INTERFACE
LOGIC
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
M0:M8
84314AY
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1
REV. C JANUARY 27, 2005
ICS84314
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes
operation using a 16MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined
in the Input Frequency Characteristics, Table 5, NOTE 1.
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 is passed directly to the M divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or until
a serial event occurs. As a result, the M bits can be hardwired to
set the M divider to a specific default state that will automatically
occur during power-up. In parallel mode, the N output divider is
set to 2. In serial mode, the N output divider can be set for either
÷2 or ÷4. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows:
fxtal x 2M
fVCO =
16
The ICS84314 features a fully integrated PLL and therefore requires no external components for setting the loop
bandwidth. A parallel-resonant, fundamental crystal is used
as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a
16MHz crystal, this provides a 1MHz reference frequency.
The VCO of the PLL operates over a range of 250MHz to
700MHz. The output of the M divider is also applied to the
phase detector.
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 16MHz reference are defined as 125 ≤ M ≤ 350. The frequency out
is defined as follows: fout = fVCO x 1 = fxtal x 2M x 1
N 16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each
rising edge of S_CLOCK.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values
of M (either too high or too low), the PLL will not achieve
lock. The output of the VCO is scaled by a divider prior to
being sent to each of the LVPECL output buffers. The divider
provides a 50% output duty cycle.
The programmable features of the ICS84314 support two
input modes to program the M divider. The two input operational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode, the
SERIAL LOADING
S_CLOCK
S_DATA
*NULL *NULL *NULL *NULL
t
S_LOAD
S
t
**N
M8
M7
M6
M5
M4
M3
M2
M1
M0
H
nP_LOAD
t
S
PARALLEL LOADING
M0:M8
M
nP_LOAD
t
S
t
Time
H
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
TABLE 1. N OUTPUT DIVIDER FUNCTION TABLE (SERIAL LOAD)
N Logic Value
0
Output Divide
÷2
1
÷4
*NOTE: The NULL timing slot must be observed.
**NOTE: “N” can only be controlled through serial loading.
84314AY
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2
REV. C JANUARY 27, 2005
ICS84314
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 2. PIN DESCRIPTIONS
Number
1, 2, 3, 4,
29, 30, 31, 32
5
Name
M4, M5, M6, M7,
M0, M1, M2, M3
M8
Type
Input
Input
Description
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL interface levels.
Pullup
6
VEE
Power
Negative supply pin.
7
VCC
Power
Core power supply pin.
8, 17
9, 10
11, 12
13, 14
15, 16
VCCO
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Power
Output
Output
Output
Output
Output supply pins.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low and the inver ted
18
MR
Input Pulldown outputs nQx to go high. When logic LOW, the internal dividers and
the outputs are enabled. Asser tion of MR does not affect loaded
M values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
19
S_CLOCK
Input Pulldown
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
20
S_DATA
Input Pulldown
of S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
21
S_LOAD
Input Pulldown
LVCMOS / LVTTL interface levels.
22
VCCA
Power
Analog supply pin.
Selects between the crystal oscillator or test clock as the PLL
23
XTAL_SEL
Input
Pullup reference source. Selects XTAL inputs when HIGH. Selects
TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
24
TEST_CLK
Input Pulldown Test clock input. LVCMOS interface levels.
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
25, 26
XTAL1, XTAL2
Input
Parallel load input. Determines when data present at M8:M0
27
nP_LOAD
Input Pulldown
is loaded into the M divider. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
28
VCO_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
KΩ
RPULLDOWN
Input Pulldown Resistor
51
KΩ
84314AY
Test Conditions
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3
Minimum
Typical
Maximum
Units
REV. C JANUARY 27, 2005
ICS84314
Integrated
Circuit
Systems, Inc.
TABLE 4A. PARALLEL
AND
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR
nP_LOAD
M
S_LOAD
S_CLOCK
S_DATA
H
X
X
X
X
X
Reset. Forces outputs LOW.
L
L
Data
X
X
X
L
↑
Data
L
X
X
L
H
X
L
↑
Data
L
H
X
↑
L
Data
L
H
X
↓
L
Data
Data on M inputs passed directly to the M divider.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
L
H
X
L
X
X
L
H
X
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
↑
Data
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
125
256
M8
0
128
M7
0
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
1
2
M1
0
1
M0
1
252
254
126
127
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
256
•
128
•
0
•
1
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
VCO Frequency
(MHz)
M Divide
250
•
•
696
348
698
349
700
350
NOTE 1: These M divide values and
frequency of 16MHz.
•
•
•
•
•
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
the resulting frequencies correspond to
•
•
•
•
1
1
0
0
1
1
0
1
1
1
1
0
cr ystal or TEST_CLK input
TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (SERIAL PROGRAMMING MODE ONLY)
Input
N Logic
N Divide
0
2
1
4
84314AY
Output Frequency (MHz)
Qx, nQx
Minimum
Maximum
12 5
350
62.5
175
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4
REV. C JANUARY 27, 2005
ICS84314
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5 V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
2.375
2.5
2.625
V
I EE
Power Supply Current
150
mA
ICCA
Analog Supply Current
17
mA
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
Maximum
Units
2.35
VCC + 0.3
V
2
VCC + 0.3
V
-0.3
0.95
V
-0.3
0.8
V
VCC = VIN = 3.465V
150
µA
VCC = VIN = 3.465V
VCC = VIN = 3.465V
5
200
µA
µA
TEST_CLK; NOTE 1
VIH
Input
High Voltage
VIL
Input
Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
VCO_SEL, XTAL_SEL,
nP_LOAD, MR, M0:M8,
S_LOAD, S_DATA, S_CLOCK
TEST_CLK; NOTE 1
VCO_SEL, XTAL_SEL,
nP_LOAD, MR, M0:M8,
S_LOAD, S_DATA, S_CLOCK
M0:M7, MR, nP_LOAD,
S_CLOCK, S_DATA,
S_LOAD
M8, XTAL_SEL, VCO_SEL
TEST_CLK
M0:M7, MR, nP_LOAD,
S_CLOCK, S_DATA,
S_LOAD
VCC = 3.465V,
VIN = 0V
VCC = 3.465V,
VIN = 0V
M8, XTAL_SEL, VCO_SEL
Minimum
Typical
-5
µA
-150
µA
NOTE:1 Characterized with 1ns input edge rate.
84314AY
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5
REV. C JANUARY 27, 2005
ICS84314
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 5C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
1.0
V
Peak-to-Peak Output Voltage Swing
0.6
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit".
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
fIN
Input Frequency
Test Conditions
Minimum
Typical
Maximum
Units
TEST_CLK; NOTE 1
10
40
MHz
XTAL1, XTAL2; NOTE 1
12
40
MHz
S_CLOCK
50
MHz
NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 ≤ M ≤ 466.
Using the maximum frequency of 40MHz, valid values of M are 50 ≤ M ≤ 140.
TABLE 7. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
12
40
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
84314AY
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6
REV. C JANUARY 27, 2005
ICS84314
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
FMAX
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter ; NOTE 1, 3
tjit(per)
Period Jitter, RMS; NOTE 1
tsk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
tS
Setup Time
tH
odc
Hold Time
Minimum
Typical
23
16
20% to 80%
200
Maximum
Units
350
MHz
35
ps
8
ps
30
ps
700
ps
M to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
Output Duty Cycle
fOUT > 125MHz
48
50
52
fOUT ≤ 125MHz
49
50
51
%
1
ms
Maximum
Units
350
MHz
23
35
ps
7
ps
16
35
ps
700
ps
PLL Lock Time
tLOCK
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
%
TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 85°C
Symbol
Parameter
FMAX
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter ; NOTE 1, 3
tjit(per)
Period Jitter, RMS; NOTE 1
tsk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
tS
tH
odc
Setup Time
Hold Time
Test Conditions
20% to 80%
Minimum
Typical
200
M to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
Output Duty Cycle
fOUT > 125MHz
48
50
52
%
fOUT ≤ 125MHz
49
50
51
%
1
ms
PLL Lock Time
tLOCK
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
84314AY
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7
REV. C JANUARY 27, 2005
ICS84314
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
2V
2.8V±0.04V
V CC,
VCCA, VCCO
Qx
SCOPE
VCC,
VCCA V
CCO
LVPECL
Qx
SCOPE
LVPECL
VEE
nQx
nQx
VEE
-1.3V ± 0.165V
-0.5V ± 0.125V
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
nQx
Qx
Qx
➤
nQy
tcycle
n
➤
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
➤
tcycle n+1
➤
Qy
t jit(cc) = tcycle n –tcycle n+1
t sk(o)
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
VOH
VREF
80%
80%
VSW I N G
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Clock
Outputs
20%
20%
tR
tF
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
PERIOD JITTER
OUTPUT RISE/FALL TIME
nQx
Qx
Pulse Width
t
odc =
PERIOD
t PW
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
84314AY
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8
REV. C JANUARY 27, 2005
ICS84314
Integrated
Circuit
Systems, Inc.
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84314 provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
10Ω
VCCA
.01µF
10µF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
84314AY
125Ω
84Ω
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. C JANUARY 27, 2005
ICS84314
Integrated
Circuit
Systems, Inc.
TERMINATION
FOR
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
ground level. The R3 in Figure 4A can be eliminated and the
termination is shown in Figure 4C.
2.5V
VCCO=2.5V
2.5V
2.5V
VCCO=2.5V
Zo = 50 Ohm
R1
250
+
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
CRYSTAL INPUT INTERFACE
The ICS84314 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 5 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
XTAL2
C1
22p
X1
18pF Parallel Cry stal
XTAL1
C2
22p
Figure 5. CRYSTAL INPUt INTERFACE
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ICS84314
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350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
LAYOUT GUIDELINE
The schematic of the ICS84314 layout example used in this layout
guideline is shown in Figure 6A. The ICS84314 recommended PCB
board layout for this example is shown in Figure 6B. This layout
example is used as a general guideline. The layout in the actual
system will depend on the selected component types, the density
of the components, the density of the traces, and the stack up of
the P.C. board.
Logic Input Pin Examples
C1
C2
X1
M4
M5
M6
M7
M8
VEE
VCC
VCCO
TEST_CLK
XTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
VCCO
C4
0.1u
Set Logic
Input to
'0'
VCC
RU2
Not Install
To Logic
Input
pins
R7
10
RD1
Not Install
VCCA
To Logic
Input
pins
RD2
1K
C11
0.01u
C16
10u
VCC
C3
0.1u
9
10
11
12
13
14
15
16
C5
0.1u
RU1
1K
VCC
24
23
22
21
20
19
18
17
Set Logic
Input to
'1'
VCC
ICS84314
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
VCC
VCC
1
2
3
4
5
6
7
8
M3
M2
M1
M0
VCO_SEL
nP_LOAD
XTAL2
XTAL1
U3
32
31
30
29
28
27
26
25
VCC=3.3V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R2
50
R1
50
R3
50
C6 (Option)
0.1u
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R5
50
C7 (Option)
0.1u
FIGURE 6A. SCHEMATIC
84314AY
OF
R4
50
R6
50
3.3V/3.3V RECOMMENDED LAYOUT
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REV. C JANUARY 27, 2005
ICS84314
Integrated
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350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
• The traces with 50Ω transmission lines TL1 and TL2
at FOUT and nFOUT should have equal delay and run
adjacent to each other. Avoid sharp angles on the clock
trace. Sharp angle turns cause the characteristic
impedance to change on the transmission lines.
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER
AND
GROUNDING
Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
• Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• Make sure no other signal trace is routed between the
clock trace pair.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VCCA as possible.
CLOCK TRACES
AND
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible.
Other termination schemes can also be used but are not
shown in this example.
TERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the
pins 25 (XTAL1) and 26 (XTAL2). The trace length between
the X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces should
not be routed near the crystal traces.
X1
GND
C2
C1
VCC
VIA
U1
PIN 1
C16
C11
VCCA
R7
C5
C3
C4
FIGURE 6B. PCB BOARD LAYOUT
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ICS84314
Integrated
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350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84314.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84314 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.7mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 519.7mW + 120mW = 639.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 9 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.640W * 42.1°C/W = 111.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 9. THERMAL RESISTANCE θJA
FOR
32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS84314
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Systems, Inc.
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
=V
CCO_MAX
– 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = V
OL_MAX
(V
CCO_MAX
-V
OL_MAX
=V
CCO_MAX
– 1.7V
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
CCO_MAX
L
-V
OH_MAX
)=
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS84314
Integrated
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350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 10. θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84314 is: 3509
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REV. C JANUARY 27, 2005
ICS84314
Integrated
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Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
FOR
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
32 LEAD LQFP
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
1.60
A
A1
0.05
0.15
A2
1.35
1.40
b
0.30
0.37
c
0.09
9.00 BASIC
D1
7.00 BASIC
D2
5.60
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60
e
0.80 BASIC
L
0.45
0°
0.45
0.20
D
θ
1.45
0.60
0.75
7°
0.10
ccc
Reference Document: JEDEC Publication 95, MS-026
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REV. C JANUARY 27, 2005
ICS84314
Integrated
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Systems, Inc.
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 12. ORDERING INFORMATION
Part/Order Number
ICS84314AY
ICS84314AYT
ICS84314AYLF
Marking
ICS84314AY
ICS84314AY
ICS84314AYLF
ICS84314AYLFT
ICS84314AYLF
Package
32 Lead LQFP
32 Lead LQFP on Tape and Reel
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP on
Tape and Reel
Count
250 per tray
1000
250 per tray
Temperature
0°C to 85°C
0°C to 85°C
0°C to 85°C
1000
0°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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REV. C JANUARY 27, 2005
Integrated
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ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table
T5C
Page
6
13 - 14
1
Description of Change
LVPECL table - changed VOH max. from VCC - 1.0V to VCC - 0.9V.
Changed equations in Power Considerations to correlate with Table 5C.
LVCMOS/LVTTL TEST_CLK changed to LVCMOS TEST_CLK.
Added Lead-Free bullet .
B
T1
3
Pin Descriptions Table - Pin 24, TEST_CLK, description changed from
LVCMOS/LVTTL interface levels to LVCMOS interface levels.
T5B
5
LVCMOS DC Characteristics - TEST_CLK VIH (min.) changed from 2V to
2.35V; VIL (max.) changed from 1.3V to 0.95V.
T12
T5B
17
5
Added Lead-Free par t number to Ordering Information Table.
LVCMOS DC Characteristics Table - added VIH/VIL NOTE 1.
C
C
84314AY
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18
Date
2/4/04
11/5/04
1/27/05
REV. C JANUARY 27, 2005