TI CY74FCT821CTQCT 8-/9-/10-bit bus interface register Datasheet

CY74FCT821T
CY74FCT823T
CY74FCT825T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
8-/9-/10-Bit Bus Interface Registers
SCCS033 - May 1994 - Revised March 2000
Features
Functional Description
• Function, pinout, and drive compatible with FCT, F, and
Am29821/23/25 logic
• FCT-C speed at 6.0 ns max.
FCT-B speed at 7.5 ns max.
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
• Sink current
64 mA
Source current
32 mA
• High-speed parallel registers with positive
edge-triggered D-type flip-flops
• Buffered common clock enable (EN) and asynchronous
clear input (CLR)
• Extended commercial range of −40˚C to +85˚C
These bus interface registers are designed to eliminate the
extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses
carrying parity. The FCT821T is a buffered, 10-bit wide version
of the popular FCT374 function. The FCT823T is a 9-bit wide
buffered register with clock enable (EN) and clear (CLR) ideal
for parity bus interfacing in high-performance microprogrammed systems. The FCT825T is an 8-bit buffered register
with all the FCT823T controls plus multiple enables (OE1,
OE2, OE3) to allow multiuser control of the interface, e.g., CS,
DMA, and RD/WR. They are ideal for use as an output port
requiring high IOL/IOH.
These devices are designed for high-capacitance load drive
capability, while providing low-capacitance bus loading at both
inputs and outputs. Outputs are designed for low-capacitance
bus loading in the high-impedance state and are designed with
a power-off disable feature to allow for live insertion of boards.
Logic Block Diagram
D0
D1
D2
D4
D3
D5
DN- 1
DN
EN [1]
CLR
[1]
D
CL
CP
Q
D
CL
CP
Q
Q
D
CL
CP
Q
Q
D
CL
CP
Q
D
Q
CL
CP
Q
Q
D
CL
CP
Q
Q
D
CL
CP
Q
Q
Q
D
CL
CP
Q
Q
CP
OE
Y0
Y1
Y2
Y3
Y4
Y5
Yn- 1
Yn
Note:
1. Not on FCT821.
Copyright
© 2000, Texas Instruments Incorporated
CY74FCT821T
CY74FCT823T
CY74FCT825T
Logic Diagrams
Pin Configurations
FCT821T (10-Bit Register)
D
10
D
Q
DIP/QSOP/SOIC
Top View
10
Y
CP
CP
OE
OE
1
24
VCC
D0
2
23
Y0
D1
3
22
Y1
D2
4
21
Y2
D3
5
20
Y3
D4
6
19
Y4
D5
7
18
Y5
D6
8
17
Y6
D7
9
16
D8
10
15
Y7
Y8
D9
11
14
Y9
GND
12
13
CP
FCT821T
FCT823T (9-Bit Register)
D
9
D
CP
Q
EN
9
DIP/QSOP/SOIC
Top View
Y
CLR
CP
EN
CLR
OE
OE
1
24
VCC
D0
2
23
Y0
D1
3
22
Y1
D2
4
21
Y2
D3
5
20
Y3
D4
6
19
Y4
D5
7
18
Y5
D6
8
17
Y6
D7
9
16
D8
10
15
Y7
Y8
CLR
11
14
EN
GND
12
13
CP
FCT823T
FCT825T (8-Bit Register)
D
8
D
CP
Q
EN
8
DIP/QSOP/SOIC
Top View
Y
CLR
CP
EN
CLR
OE1
OE2
OE3
2
OE1
OE2
1
24
2
23
VCC
OE3
D0
3
22
Y0
D1
4
21
Y1
D2
5
Y2
D3
FCT825T 20
6
19
D4
7
18
Y4
D5
8
17
Y5
D6
9
16
Y6
D7
10
15
Y7
CLR
11
14
EN
GND
12
13
CP
Y3
CY74FCT821T
CY74FCT823T
CY74FCT825T
Pin Description
Name
I/O
Description
D
I
The D flip-flop data inputs.
CLR
I
When CLR is LOW and OE is LOW, the Q outputs are LOW. When CLR is HIGH, data can be
entered into the register.
CP
O
Clock Pulse for the register; enters data into the register on the LOW-to-HIGH transition.
Y
O
The register three-state outputs.
EN
I
Clock Enable. When EN is LOW, data on the D input is transferred to the Q output on the
LOW-to-HIGH clock transition. When EN is HIGH, the Q outputs do not change state,
regardless of the data or clock input transitions.
OE
I
Output Control. When OE is HIGH, the Y outputs are in the high-impedance state. When OE
is LOW, the TRUE register data is present at the Y outputs.
Function Table[2]
Inputs
Internal Outputs
OE
CLR
EN
D
H
H
H
H
L
L
L
H
H
L
L
L
X
X
X
X
H
L
H
H
H
H
X
X
H
H
L
L
H
H
H
H
L
L
L
L
L
H
L
H
CP
Maximum Ratings[3,4]
Y
Function
L
H
Z
Z
High Z
X
X
L
L
Z
L
Clear
X
X
NC
NC
Z
NC
Hold
L
H
L
H
Z
Z
L
H
Load
DC Output Current (Maximum Sink Current/Pin) ...... 120 mA
Power Dissipation .......................................................... 0.5W
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature
Q
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
............................. −65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied ........................................ −65°C to +135°C
Supply Voltage to Ground Potential ............. −0.5V to +7.0V
Range
DC Input Voltage ....................................... −0.5V to +7.0V
Commercial
DC Output Voltage ..................................... −0.5V to +7.0V
Range
All
Ambient
Temperature
VCC
−40°C to +85°C
5V ± 5%
Notes:
2.
3.
4.
H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, NC = No Change,
= LOW-to-HIGH Transition, Z = HIGH Impedance.
Unless otherwise noted, these limits are over the operating free-air temperature range.
Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
3
CY74FCT821T
CY74FCT823T
CY74FCT825T
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.[5]
VOH
Output HIGH Voltage
VCC = Min., IOH = −32 mA
2.0
VOH
Output HIGH Voltage
VCC = Min., IOH = −15 mA
2.4
VOL
Output LOW Voltage
VCC = Min., IOL = 64 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[6]
All inputs
0.2
VIK
Input Clamp Diode Voltage
VCC = Min., IIN = −18 mA
−0.7
II
Input HIGH Current
IIH
IIL
Max.
Unit
V
3.3
0.3
V
0.55
V
2.0
V
0.8
V
V
−1.2
V
VCC = Max., VIN = VCC
5
µA
Input HIGH Current
VCC = Max., VIN = 2.7V
±1
µA
Input LOW Current
VCC = Max., VIN = 0.5V
±1
µA
IOZH
Off State HIGH-Level Output
Current
VCC = Max., VOUT = 2.7V
10
µA
IOZL
Off State LOW-Level
Output Current
VCC = Max., VOUT = 0.5V
−10
µA
IOS
Output Short Circuit Current[7]
VCC = Max., VOUT = 0.0V
−225
mA
IOFF
Power-Off Disable
VCC = 0V, VOUT = 4.5V
±1
µA
−60
−120
Capacitance[6]
Parameter
Description
Typ.[5]
Max.
Unit
CIN
Input Capacitance
5
10
pF
COUT
Output Capacitance
9
12
pF
Notes:
5. Typical values are at VCC=5.0V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
4
CY74FCT821T
CY74FCT823T
CY74FCT825T
Power Supply Characteristics
Parameter
Description
Test Conditions
Typ.[5]
Max.
Unit
ICC
Quiescent Power Supply
Current
VCC=Max., VIN≤0.2V, VIN≥VCC−0.2V
0.1
0.2
mA
∆ICC
Quiescent Power Supply
Current (TTL inputs HIGH)
VCC=Max., VIN=3.4V,[8]
f1=0, Outputs Open
0.5
2.0
mA
ICCD
Dynamic Power Supply
Current[9]
VCC=Max., One Bit Toggling, 50% Duty Cycle,
Outputs Open, OE=EN=GND,
VIN≤0.2V or VIN≥VCC−0.2V
0.06
0.12
mA/MHz
IC
Total Power Supply Current[10]
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling
at f1=5 MHz, OE=EN=GND,
VIN≤0.2V or VIN≥VCC−0.2V
0.7
1.4
mA
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling at f1=5 MHz,
OE=EN=GND, VIN=3.4V or VIN=GND
1.2
3.4
mA
VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, Eight Bits Toggling
at f1=2.5 MHz, OE=EN=GND,
VIN≤0.2V or VIN≥VCC−0.2V
1.6
3.2[11]
mA
VCC=Max., f0=10 MHz,50% Duty Cycle,
Outputs Open, Eight Bits Toggling
at f1=2.5 MHz, OE=EN=GND,
VIN=3.4V or VIN=GND
3.9
12.2[11]
mA
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle for TTL inputs HIGH
NT = Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0 = Clock frequency for registered devices, otherwise zero
f1 = Input signal frequency
N1 = Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
5
CY74FCT821T
CY74FCT823T
CY74FCT825T
Switching Characteristics Over the Operating Range[12]
Param.
Description
Test Load
CY74FCT821AT
CY74FCT823AT
CY74FCT825AT
CY74FCT821BT
CY74FCT823BT
CY74FCT825BT
CY74FCT821CT
CY74FCT823CT
CY74FCT825CT
Commercial
Commercial
Commercial
Min.
Min.
Min.
Max.
Max.
Max.
Unit Fig. No.[13]
tPLH
tPHL
Propagation Delay
CP to Y, (OE=LOW)
CL=50 pF
RL=500Ω
10.0
7.5
6.0
ns
1, 5
tPLH
tPHL
Propagation Delay
CP to Y, (OE=LOW)[6]
CL=300 pF
RL=500Ω
20.0
15.0
12.5
ns
1, 5
tPLH
Propagation Delay
CLR to Y
CL=50 pF
RL=500Ω
14.0
9.0
8.0
ns
1, 5
tPZH
tPZL
Output Enable Time
OE to Y
CL=50 pF
RL=500Ω
12.0
8.0
7.0
ns
1, 7, 8
tPZH
tPZL
Output Enable Time
OE to Y[6]
CL=300 pF
RL=500Ω
23.0
15.0
12.5
ns
1, 7, 8
tPHZ
tPHL
Output Disable Time
OE to Y[6]
CL=5 pF
RL=500Ω
7.0
6.5
6.0
ns
1, 7, 8
tPHZ
tPHL
Output Disable Time
OE to Y
CL=50 pF
RL=500Ω
8.0
7.5
6.5
ns
1, 7, 8
tSU
Data to CP, Set-Up Time
4.0
3.0
3.0
ns
4
tH
Data to CP, Hold Time
2.0
1.5
1.5
ns
4
tSU
Enable EN to CP,
Set-Up Time
4.0
3.0
3.0
ns
4
tH
Enable EN to CP,
Hold Time
2.0
0.0
0.0
ns
4
tREM
Clear Recovery Time,
CLR to CP
6.0
6.0
6.0
ns
6
tW
Clock Pulse Width
7.0
6.0
6.0
ns
5
tW
CLR Pulse Width LOW
6.0
6.0
6.0
ns
5
CL=50 pF
RL=500Ω
Notes:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information.”
6
CY74FCT821T
CY74FCT823T
CY74FCT825T
Ordering Information—FCT821T
Speed
(ns)
6.0
Ordering Code
CY74FCT821CTQCT
CY74FCT821CTSOC/SOCT
7.5
10.0
CY74FCT821BTPC
Package
Name
Package Type
Q13
24-Lead (150-Mil) QSOP
S13
24-Lead (300-Mil) Molded SOIC
P13/13A
24-Lead (300-Mil) Molded DIP
CY74FCT821BTSOC/SOCT
S13
24-Lead (300-Mil) Molded SOIC
CY74FCT821ATQCT
Q13
24-Lead (150-Mil) QSOP
CY74FCT821ATSOC/SOCT
S13
24-Lead (300-Mil) Molded SOIC
Operating
Range
Commercial
Commercial
Commercial
Ordering Information—FCT823T
Speed
(ns)
6.0
Ordering Code
CY74FCT823CTQCT
CY74FCT823CTSOC/SOCT
Package
Name
Package Type
Q13
24-Lead (150-Mil) QSOP
S13
24-Lead (300-Mil) Molded SOIC
Operating
Range
Commercial
7.5
CY74FCT823BTPC
P13/13A
24-Lead (300-Mil) Molded DIP
Commercial
10.0
CY74FCT823ATPC
P13/13A
24-Lead (300-Mil) Molded DIP
Commercial
CY74FCT823ATQCT
Q13
24-Lead (150-Mil) QSOP
CY74FCT823ATSOC/SOCT
S13
24-Lead (300-Mil) Molded SOIC
Ordering Information—FCT825T
Speed
(ns)
6.0
Ordering Code
CY74FCT825CTQCT
Package
Name
Q13
Package Type
24-Lead (150-Mil) QSOP
Document #: 38−00282−B
7
Operating
Range
Commercial
CY74FCT821T
CY74FCT823T
CY74FCT825T
Package Diagrams
24-Lead (300-Mil) Molded DIP P13/P13A
24-Lead Quarter Size Outline Q13
8
CY74FCT821T
CY74FCT823T
CY74FCT825T
Package Diagrams (continued)
24-Lead (300-Mil) Molded SOIC S13
9
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