TI1 CC2630F128RHBR 6lowpan, zigbee wireless mcu Datasheet

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CC2630
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
CC2630 SimpleLink™ 6LoWPAN, ZigBee® Wireless MCU
1 Device Overview
1.1
Features
1
• Microcontroller
– Powerful ARM® Cortex®-M3
– EEMBC CoreMark® Score: 142
– Up to 48-MHz Clock Speed
– 128KB of In-System Programmable Flash
– 8KB of SRAM for Cache
– 20KB of Ultralow-Leakage SRAM
– 2-Pin cJTAG and JTAG Debugging
– Supports Over-The-Air Upgrade (OTA)
• Ultralow-Power Sensor Controller
– Can Run Autonomous From the Rest of the
System
– 16-Bit Architecture
– 2KB of Ultralow-Leakage SRAM for Code and
Data
• Efficient Code Size Architecture, Placing Drivers,
IEEE 802.15.4 MAC, and Bootloader in ROM
• RoHS-Compliant Packages
– 4-mm × 4-mm RSM VQFN32 (10 GPIOs)
– 5-mm × 5-mm RHB VQFN32 (15 GPIOs)
– 7-mm × 7-mm RGZ VQFN48 (31 GPIOs)
• Peripherals
– All Digital Peripheral Pins Can Be Routed to
Any GPIO
– Four General-Purpose Timer Modules
(Eight 16-Bit or Four 32-Bit Timers, PWM Each)
– 12-Bit ADC, 200-ksamples/s, 8-Channel Analog
MUX
– Continuous Time Comparator
– Ultralow-Power Analog Comparator
– Programmable Current Source
– UART
– 2× SSI (SPI, MICROWIRE, TI)
– I2C
– I2S
– Real-Time Clock (RTC)
– AES-128 Security Module
– True Random Number Generator (TRNG)
– 10, 15, or 31 GPIOs, Depending on Package
Option
– Support for Eight Capacitive-Sensing Buttons
– Integrated Temperature Sensor
• External System
– On-Chip internal DC-DC Converter
– Very Few External Components
– Seamless Integration With the SimpleLink™
CC2590 and CC2592 Range Extenders
– Pin Compatible With the SimpleLink CC13xx in
4-mm × 4-mm and 5-mm × 5-mm VQFN
Packages
• Low Power
– Wide Supply Voltage Range
• Normal Operation: 1.8 to 3.8 V
• External Regulator Mode: 1.7 to 1.95 V
– Active-Mode RX: 5.9 mA
– Active-Mode TX at 0 dBm: 6.1 mA
– Active-Mode TX at +5 dBm: 9.1 mA
– Active-Mode MCU: 61 µA/MHz
– Active-Mode MCU: 48.5 CoreMark/mA
– Active-Mode Sensor Controller: 8.2 µA/MHz
– Standby: 1 µA (RTC Running and RAM/CPU
Retention)
– Shutdown: 100 nA (Wake Up on External
Events)
• RF Section
– 2.4-GHz RF Transceiver Compatible With IEEE
802.15.4 PHY and MAC
– Excellent Receiver Sensitivity (–100 dBm),
Selectivity, and Blocking Performance
– Link budget of 105 dB
– Programmable Output Power up to +5 dBm
– Single-Ended or Differential RF Interface
– Suitable for Systems Targeting Compliance With
Worldwide Radio Frequency Regulations
• ETSI EN 300 328 (Europe)
• EN 300 440 Class 2 (Europe)
• FCC CFR47 Part 15 (US)
• ARIB STD-T66 (Japan)
• Tools and Development Environment
– Full-Feature and Low-Cost Development Kits
– Multiple Reference Designs for Different RF
Configurations
– Packet Sniffer PC Software
– Sensor Controller Studio
– SmartRF™ Studio
– SmartRF Flash Programmer 2
– IAR Embedded Workbench® for ARM
– Code Composer Studio™
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC2630
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
1.2
•
•
•
•
•
Applications
Home and Building Automation
Lighting Control
Alarm and Security
Electronic Shelf Labeling
Proximity Tags
1.3
www.ti.com
•
•
•
Wireless Sensor Networks
Energy Harvesting, Batteryless Sensors, and
Actuators
Smart Grid
Description
The CC2630 device is a wireless MCU targeting ZigBee® and 6LoWPAN applications.
The device is a member of the CC26xx family of cost-effective, ultralow power, 2.4-GHz RF devices. Very
low active RF and MCU current and low-power mode current consumption provide excellent battery
lifetime and allow for operation on small coin cell batteries and in energy-harvesting applications.
The CC2630 device contains a 32-bit ARM Cortex-M3 processor that runs at 48 MHz as the main
processor and a rich peripheral feature set that includes a unique ultralow power sensor controller. This
sensor controller is ideal for interfacing external sensors and for collecting analog and digital data
autonomously while the rest of the system is in sleep mode. Thus, the CC2630 device is ideal for batterypowered and energy harvesting end nodes in ZigBee and 6LoWPAN networks.
The IEEE 802.15.4 MAC is embedded into ROM and runs partly on an ARM Cortex-M0 processor. This
architecture improves overall system performance and power consumption and frees up flash memory for
the application.
The ZigBee stack is available free of charge from www.ti.com.
Device Information (1)
(1)
2
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CC2630F128RGZ
VQFN (48)
7.00 mm × 7.00 mm
CC2630F128RHB
VQFN (32)
5.00 mm × 5.00 mm
CC2630F128RSM
VQFN (32)
4.00 mm × 4.00 mm
For more information, see Section 9, Mechanical Packaging and Orderable Information.
Device Overview
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1.4
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
Functional Block Diagram
Figure 1-1 shows a block diagram for the CC2630.
SimpleLinkTM CC26xx wireless MCU
RF core
cJTAG
Main CPU
ROM
ARM®
Cortex®-M3
ADC
ADC
128KB
Flash
Digital PLL
DSP modem
8KB
cache
4KB
SRAM
ARM®
20KB
SRAM
Cortex®-M0
ROM
Sensor controller
General peripherals / modules
I2C
4× 32-bit Timers
UART
2× SSI (SPI, µW, TI)
Sensor controller
engine
12-bit ADC, 200 ks/s
I2S
Watchdog timer
2x comparator
10 / 15 / 31 GPIOs
TRNG
SPI-I2C digital sensor IF
AES
Temp. / batt. monitor
Constant current source
32 ch. µDMA
RTC
Time-to-digital converter
2KB SRAM
DC-DC converter
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. Block Diagram
Device Overview
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CC2630
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
www.ti.com
Table of Contents
1
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 2
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 3
2
3
Revision History ......................................... 5
Device Comparison ..................................... 6
4
Terminal Configuration and Functions .............. 7
Related Products ..................................... 6
3.1
........................ 7
4.2
Signal Descriptions – RGZ Package ................. 7
4.3
Pin Diagram – RHB Package ........................ 9
4.4
Signal Descriptions – RHB Package ................. 9
4.5
Pin Diagram – RSM Package ....................... 11
4.6
Signal Descriptions – RSM Package ............... 11
Specifications ........................................... 13
5.1
Absolute Maximum Ratings ......................... 13
5.2
ESD Ratings ........................................ 13
5.3
Recommended Operating Conditions ............... 13
5.4
Power Consumption Summary...................... 14
5.5
General Characteristics ............................. 14
4.1
5
6
Pin Diagram – RGZ Package
5.6
IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) –
RX ................................................... 15
IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) –
TX ................................................... 15
5.7
5.8
.............
32.768-kHz Crystal Oscillator (XOSC_LF) ..........
48-MHz RC Oscillator (RCOSC_HF) ...............
32-kHz RC Oscillator (RCOSC_LF).................
ADC Characteristics.................................
Temperature Sensor ................................
Battery Monitor ......................................
Continuous Time Comparator .......................
Low-Power Clocked Comparator ...................
Programmable Current Source .....................
Synchronous Serial Interface (SSI) ................
DC Characteristics ..................................
24-MHz Crystal Oscillator (XOSC_HF)
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
7
................
...............................
5.22 Switching Characteristics ...........................
5.23 Typical Characteristics ..............................
Detailed Description ...................................
6.1
Overview ............................................
6.2
Functional Block Diagram ...........................
6.3
Main CPU ...........................................
6.4
RF Core .............................................
6.5
Sensor Controller ...................................
6.6
Memory ..............................................
6.7
Debug ...............................................
6.8
Power Management .................................
6.9
Clock Systems ......................................
6.10 General Peripherals and Modules ..................
6.11 Voltage Supply Domains ............................
6.12 System Architecture .................................
Application, Implementation, and Layout .........
7.1
Application Information ..............................
5.20
Thermal Resistance Characteristics
23
5.21
Timing Requirements
24
7.2
7.3
8
29
29
29
30
30
31
32
32
33
34
34
35
35
36
36
5 × 5 External Differential (5XD) Application Circuit
...................................................... 38
4 × 4 External Single-ended (4XS) Application
Circuit ............................................... 40
Device and Documentation Support ............... 42
8.1
Device Nomenclature ............................... 42
16
8.2
Tools and Software
16
8.3
Documentation Support ............................. 44
17
8.4
Texas Instruments Low-Power RF Website
17
8.5
Low-Power RF eNewsletter ......................... 44
17
8.6
Community Resources .............................. 44
19
8.7
Additional Information ............................... 45
19
8.8
Trademarks.......................................... 45
19
8.9
Electrostatic Discharge Caution ..................... 45
20
8.10
Export Control Notice
20
8.11
Glossary ............................................. 45
20
22
9
.................................
........
...............................
43
44
45
Mechanical Packaging and Orderable
Information .............................................. 45
9.1
4
24
25
Packaging Information
Table of Contents
..............................
45
Copyright © 2015–2016, Texas Instruments Incorporated
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CC2630
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SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from October 15, 2015 to July 5, 2016
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Page
Added split VDDS supply rail feature .............................................................................................. 1
Added 2-Mbps Bluetooth low energy............................................................................................... 1
Added option for up to 80-Ω ESR when CL is 6 pF or lower .................................................................. 16
Added motional inductance recommendation to the 24-MHz XOSC table ................................................. 16
Added tolerance for RCOSC_LF and RTC accuracy content ................................................................ 17
Updated the Soc ADC internal voltage reference specification in Section 5.12 ........................................... 17
Moved all SSI parameters to Section 5.18 ...................................................................................... 20
Added SPI timing parameters ..................................................................................................... 20
Added VOH and VOL min and max values for 4-mA and 8-mA load ....................................................... 22
Added min and max values for VIH and VIL .................................................................................... 23
Added 0-dBm setting to the TX Current Consumption vs Supply Voltage (VDDS) graph ................................ 25
Changed Figure 5-11, Receive Mode Current vs Supply Voltage (VDDS) ................................................. 25
Added Figure 5-21, Supply Current vs Temperature .......................................................................... 26
Added application circuit schematics and layout for 5XD and 4XS .......................................................... 36
Changes from February 21, 2015 to October 15, 2015
•
•
•
•
•
•
•
•
•
•
•
Page
Removed RHB package option from CC2620 .................................................................................... 6
Added motional inductance recommendation to the 24-MHz XOSC table ................................................. 16
Added SPI timing parameters ..................................................................................................... 20
Added VOH and VOL min and max values for 4-mA and 8-mA load ....................................................... 22
Added min and max values for VIH and VIL .................................................................................... 23
Added IEEE 802.15.4 Sensitivity vs Channel Frequency ...................................................................... 25
Added RF Output Power vs Channel Frequency ............................................................................... 25
Added Figure 5-11, Receive Mode Current vs Supply Voltage (VDDS) ..................................................... 25
Changed Figure 5-20, SoC ADC ENOB vs Sampling Frequency (Input Frequency = FS / 10) .......................... 26
Clarified Brown Out Detector status and functionality in the Power Modes table. ......................................... 33
Added application circuit schematics and layout for 5XD and 4XS .......................................................... 36
Revision History
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CC2630
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
www.ti.com
3 Device Comparison
Table 3-1. Device Family Overview
DEVICE
PHY SUPPORT
FLASH
(KB)
RAM (KB)
GPIO
PACKAGE (1)
CC2650F128xxx
Multi-Protocol (2)
128
20
31, 15, 10
RGZ, RHB, RSM
CC2640F128xxx
Bluetooth low energy (Normal)
128
20
31, 15, 10
RGZ, RHB, RSM
CC2630F128xxx
IEEE 802.15.4 Zigbee(/6LoWPAN)
128
20
31, 15, 10
RGZ, RHB, RSM
CC2620F128xxx
IEEE 802.15.4 (RF4CE)
128
20
31, 10
RGZ, RSM
(1)
(2)
3.1
Package designator replaces the xxx in device name to form a complete device name, RGZ is 7-mm × 7-mm VQFN48, RHB is
5-mm × 5-mm VQFN32, and RSM is 4-mm × 4-mm VQFN32.
The CC2650 device supports all PHYs and can be reflashed to run all the supported standards.
Related Products
Wireless Connectivity The wireless connectivity portfolio offers a wide selection of low power RF
solutions suitable for a broad range of application. The offerings range from fully customized
solutions to turn key offerings with pre-certified hardware and software (protocol).
Sub-1 GHz Long-range, low power wireless connectivity solutions are offered in a wide range of Sub-1
GHz ISM bands.
Companion Products Review products that are frequently purchased or used in conjunction with this
product.
SimpleLink™ CC2650 Wireless MCU LaunchPad™ Kit The CC2650 LaunchPad kit brings easy
Bluetooth® Smart connectivity to the LaunchPad kit ecosystem with the SimpleLink ultra-low
power CC26xx family of devices. This LaunchPad kit also supports development for multiprotocol support for the SimpleLink multi-standard CC2650 wireless MCU and the rest of
CC26xx family of products: CC2630 wireless MCU for ZigBee®/6LoWPAN and CC2640
wireless MCU for Bluetooth® Smart.
Reference Designs for CC2630 TI Designs Reference Design Library is a robust reference design library
spanning analog, embedded processor and connectivity. Created by TI experts to help you
jump-start your system design, all TI Designs include schematic or block diagrams, BOMs
and design files to speed your time to market. Search and download designs at
ti.com/tidesigns.
6
Device Comparison
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CC2630
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SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
4 Terminal Configuration and Functions
25 JTAG_TCKC
26 DIO_16
27 DIO_17
28 DIO_18
29 DIO_19
30 DIO_20
31 DIO_21
32 DIO_22
33 DCDC_SW
34 VDDS_DCDC
35 RESET_N
Pin Diagram – RGZ Package
36 DIO_23
4.1
DIO_24 37
24 JTAG_TMSC
DIO_25 38
23 DCOUPL
DIO_26 39
22 VDDS3
DIO_27 40
21 DIO_15
DIO_28 41
20 DIO_14
DIO_29 42
19 DIO_13
DIO_30 43
18 DIO_12
VDDS 44
17 DIO_11
VDDR 45
16 DIO_10
X24M_N 46
15 DIO_9
X24M_P 47
14 DIO_8
13 VDDS2
Note:
DIO_7 12
9
DIO_4
DIO_6 11
8
DIO_5 10
7
5
DIO_0
DIO_3
4
X32K_Q2
DIO_2
3
X32K_Q1
6
2
RF_N
DIO_1
1
RF_P
VDDR_RF 48
I/O pins marked in bold have high drive capabilities. I/O pins marked in italics have analog capabilities.
Figure 4-1. RGZ Package
48-Pin VQFN
(7-mm × 7-mm) Pinout, 0.5-mm Pitch
4.2
Signal Descriptions – RGZ Package
Table 4-1. Signal Descriptions – RGZ Package
NAME
NO.
TYPE
DESCRIPTION
DCDC_SW
33
Power
Output from internal DC-DC (1)
DCOUPL
23
Power
1.27-V regulated digital-supply decoupling capacitor (2)
DIO_0
5
Digital I/O
GPIO, Sensor Controller
DIO_1
6
Digital I/O
GPIO, Sensor Controller
DIO_2
7
Digital I/O
GPIO, Sensor Controller
DIO_3
8
Digital I/O
GPIO, Sensor Controller
DIO_4
9
Digital I/O
GPIO, Sensor Controller
DIO_5
10
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_6
11
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_7
12
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_8
14
Digital I/O
GPIO
DIO_9
15
Digital I/O
GPIO
DIO_10
16
Digital I/O
GPIO
(1)
(2)
See technical reference manual (listed in Section 8.3) for more details.
Do not supply external circuitry from this pin.
Terminal Configuration and Functions
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CC2630
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
www.ti.com
Table 4-1. Signal Descriptions – RGZ Package (continued)
NAME
NO.
TYPE
DIO_11
17
Digital I/O
GPIO
DIO_12
18
Digital I/O
GPIO
DIO_13
19
Digital I/O
GPIO
DIO_14
20
Digital I/O
GPIO
DIO_15
21
Digital I/O
GPIO
DIO_16
26
Digital I/O
GPIO, JTAG_TDO, high-drive capability
DIO_17
27
Digital I/O
GPIO, JTAG_TDI, high-drive capability
DIO_18
28
Digital I/O
GPIO
DIO_19
29
Digital I/O
GPIO
DIO_20
30
Digital I/O
GPIO
DIO_21
31
Digital I/O
GPIO
DIO_22
32
Digital I/O
GPIO
DIO_23
36
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_24
37
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_25
38
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_26
39
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_27
40
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_28
41
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_29
42
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_30
43
Digital/Analog I/O
GPIO, Sensor Controller, Analog
JTAG_TMSC
24
Digital I/O
JTAG TMSC, high-drive capability
JTAG_TCKC
25
Digital I/O
JTAG TCKC
RESET_N
35
Digital input
RF_P
1
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RF_N
2
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
VDDR
45
Power
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC (2) (3)
VDDR_RF
48
Power
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC (2) (4)
VDDS
44
Power
1.8-V to 3.8-V main chip supply (1)
VDDS2
13
Power
1.8-V to 3.8-V DIO supply (1)
VDDS3
22
Power
1.8-V to 3.8-V DIO supply (1)
VDDS_DCDC
34
Power
1.8-V to 3.8-V DC-DC supply
X32K_Q1
3
Analog I/O
32-kHz crystal oscillator pin 1
X32K_Q2
4
Analog I/O
32-kHz crystal oscillator pin 2
X24M_N
46
Analog I/O
24-MHz crystal oscillator pin 1
X24M_P
47
Analog I/O
24-MHz crystal oscillator pin 2
EGP
(3)
(4)
8
Power
DESCRIPTION
Reset, active-low. No internal pullup.
Ground – Exposed Ground Pad
If internal DC-DC is not used, this pin is supplied internally from the main LDO.
If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
Terminal Configuration and Functions
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17 DCDC_SW
18 VDDS_DCDC
19 RESET_N
20 DIO_7
21 DIO_8
22 DIO_9
23 DIO_10
Pin Diagram – RHB Package
24 DIO_11
4.3
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
DIO_12 25
16 DIO_6
DIO_13 26
15 DIO_5
DIO_14 27
14 JTAG_TCKC
VDDS 28
13 JTAG_TMSC
VDDR 29
12 DCOUPL
X24M_N 30
11 VDDS2
X24M_P 31
10 DIO_4
Note:
1
2
3
4
5
6
7
8
RF_N
RX_TX
X32K_Q1
X32K_Q2
DIO_0
DIO_1
DIO_2
9
RF_P
VDDR_RF 32
DIO_3
I/O pins marked in bold have high drive capabilities. I/O pins marked in italics have analog capabilities.
Figure 4-2. RHB Package
32-Pin VQFN
(5-mm × 5-mm) Pinout, 0.5-mm Pitch
4.4
Signal Descriptions – RHB Package
Table 4-2. Signal Descriptions – RHB Package
NAME
NO.
TYPE
DESCRIPTION
DCDC_SW
17
Power
Output from internal DC-DC (1)
DCOUPL
12
Power
1.27-V regulated digital-supply decoupling (2)
DIO_0
6
Digital I/O
GPIO, Sensor Controller
DIO_1
7
Digital I/O
GPIO, Sensor Controller
DIO_2
8
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_3
9
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_4
10
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_5
15
Digital I/O
GPIO, High drive capability, JTAG_TDO
DIO_6
16
Digital I/O
GPIO, High drive capability, JTAG_TDI
DIO_7
20
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_8
21
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_9
22
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_10
23
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_11
24
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_12
25
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_13
26
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_14
27
Digital/Analog I/O
GPIO, Sensor Controller, Analog
JTAG_TMSC
13
Digital I/O
JTAG TMSC, high-drive capability
JTAG_TCKC
14
Digital I/O
JTAG TCKC
(1)
(2)
See technical reference manual (listed in Section 8.3) for more details.
Do not supply external circuitry from this pin.
Terminal Configuration and Functions
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SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
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Table 4-2. Signal Descriptions – RHB Package (continued)
NAME
NO.
TYPE
RESET_N
19
Digital input
RF_N
2
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
RF_P
1
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RX_TX
3
RF I/O
Optional bias pin for the RF LNA
VDDR
29
Power
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC (3) (2)
VDDR_RF
32
Power
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC (2) (4)
VDDS
28
Power
1.8-V to 3.8-V main chip supply (1)
VDDS2
11
Power
1.8-V to 3.8-V GPIO supply (1)
VDDS_DCDC
18
Power
1.8-V to 3.8-V DC-DC supply
X32K_Q1
4
Analog I/O
32-kHz crystal oscillator pin 1
X32K_Q2
5
Analog I/O
32-kHz crystal oscillator pin 2
X24M_N
30
Analog I/O
24-MHz crystal oscillator pin 1
X24M_P
31
Analog I/O
24-MHz crystal oscillator pin 2
EGP
(3)
(4)
10
Power
DESCRIPTION
Reset, active-low. No internal pullup.
Ground – Exposed Ground Pad
If internal DC-DC is not used, this pin is supplied internally from the main LDO.
If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
Terminal Configuration and Functions
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17 VSS
18 DCDC_SW
19 VDDS_DCDC
20 VSS
21 RESET_N
22 DIO_5
23 DIO_6
Pin Diagram – RSM Package
24 DIO_7
4.5
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
DIO_8 25
16 DIO_4
DIO_9 26
15 DIO_3
VDDS 27
14 JTAG_TCKC
VDDR 28
13 JTAG_TMSC
VSS 29
12 DCOUPL
X24M_N 30
11 VDDS2
X24M_P 31
10 DIO_2
Note:
5
6
7
8
X32K_Q1
X32K_Q2
VSS
DIO_0
3
VSS
4
2
RF_N
RX_TX
1
9
RF_P
VDDR_RF 32
DIO_1
I/O pins marked in bold have high drive capabilities. I/O pins marked in italics have analog capabilities.
Figure 4-3. RSM Package
32-Pin VQFN
(4-mm × 4-mm) Pinout, 0.4-mm Pitch
4.6
Signal Descriptions – RSM Package
Table 4-3. Signal Descriptions – RSM Package
NAME
NO.
TYPE
DESCRIPTION
DCDC_SW
18
Power
Output from internal DC-DC.
(1.7-V to 1.95-V operation)
DCOUPL
12
Power
1.27-V regulated digital-supply decoupling capacitor (2)
DIO_0
8
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_1
9
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_2
10
Digital I/O
GPIO, Sensor Controller, high-drive capability
DIO_3
15
Digital I/O
GPIO, High drive capability, JTAG_TDO
DIO_4
16
Digital I/O
GPIO, High drive capability, JTAG_TDI
DIO_5
22
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_6
23
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_7
24
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_8
25
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_9
26
Digital/Analog I/O
GPIO, Sensor Controller, Analog
JTAG_TMSC
13
Digital I/O
JTAG TMSC
JTAG_TCKC
14
Digital I/O
JTAG TCKC
RESET_N
21
Digital Input
RF_N
2
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
RF_P
1
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
(1)
(2)
(1)
. Tie to ground for external regulator mode
Reset, active-low. No internal pullup.
See technical reference manual (listed in Section 8.3) for more details.
Do not supply external circuitry from this pin.
Terminal Configuration and Functions
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Table 4-3. Signal Descriptions – RSM Package (continued)
NAME
NO.
TYPE
DESCRIPTION
RX_TX
4
RF I/O
Optional bias pin for the RF LNA
VDDR
28
Power
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC.
(2) (3)
(2) (4)
VDDR_RF
32
Power
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC
VDDS
27
Power
1.8-V to 3.8-V main chip supply (1)
VDDS2
11
Power
1.8-V to 3.8-V GPIO supply (1)
VDDS_DCDC
19
Power
1.8-V to 3.8-V DC-DC supply. Tie to ground for external regulator mode
(1.7-V to 1.95-V operation).
3, 7, 17, 20,
29
Power
X32K_Q1
5
Analog I/O
32-kHz crystal oscillator pin 1
X32K_Q2
6
Analog I/O
32-kHz crystal oscillator pin 2
X24M_N
30
Analog I/O
24-MHz crystal oscillator pin 1
X24M_P
31
Analog I/O
24-MHz crystal oscillator pin 2
VSS
EGP
(3)
(4)
12
Power
Ground
Ground – Exposed Ground Pad
If internal DC-DC is not used, this pin is supplied internally from the main LDO.
If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
Terminal Configuration and Functions
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SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
5 Specifications
5.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
Supply voltage (VDDS, VDDS2,
and VDDS3)
VDDR supplied by internal DC-DC regulator or
internal GLDO. VDDS_DCDC connected to VDDS on
PCB.
UNIT
–0.3
4.1
V
Supply voltage (VDDS (3) and
VDDR)
External regulator mode (VDDS and VDDR pins
connected on PCB)
–0.3
2.25
V
Voltage on any digital pin (4) (5)
–0.3
VDDSx + 0.3, max 4.1
V
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X24M_N and X24M_P
–0.3
VDDR + 0.3, max 2.25
V
Voltage scaling enabled
–0.3
VDDS
Voltage scaling disabled, internal reference
–0.3
1.49
Voltage scaling disabled, VDDS as reference
–0.3
VDDS / 2.9
Storage temperature
–40
150
Voltage on ADC input (Vin)
Input RF level
5
Tstg
(1)
(2)
(3)
(4)
(5)
°C
ESD Ratings
VALUE
VESD
5.3
dBm
All voltage values are with respect to ground, unless otherwise noted.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
In external regulator mode, VDDS2 and VDDS3 must be at the same potential as VDDS.
Including analog-capable DIO.
Each pin is referenced to a specific VDDSx (VDDS, VDDS2 or VDDS3). For a pin-to-VDDS mapping table, see Table 6-3.
5.2
(1)
(2)
V
Electrostatic discharge
(ESD) performance
Human body model (HBM), per ANSI/ESDA/JEDEC
JS001 (1)
Charged device model (CDM), per JESD22-C101 (2)
All pins
±2500
RF pins
±750
Non-RF pins
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Ambient temperature range
Operating supply voltage
(VDDS and VDDR), external
regulator mode
For operation in 1.8-V systems
(VDDS and VDDR pins connected on PCB, internal DCDC cannot be used)
Operating supply voltage VDDS For operation in battery-powered and 3.3-V systems
(internal DC-DC can be used to minimize power
Operating supply voltages
consumption)
VDDS2 and VDDS3
MIN
MAX
–40
85
°C
1.7
1.95
V
1.8
3.8
V
0.7 × VDDS, min 1.8
3.8
V
Specifications
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UNIT
13
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SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
5.4
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Power Consumption Summary
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V with internal DC-DC converter, unless
otherwise noted.
PARAMETER
Icore
Core current consumption
TEST CONDITIONS
MIN
TYP
Reset. RESET_N pin asserted or VDDS below
Power-on-Reset threshold
100
Shutdown. No clocks running, no retention
150
Standby. With RTC, CPU, RAM and (partial)
register retention. RCOSC_LF
1
Standby. With RTC, CPU, RAM and (partial)
register retention. XOSC_LF
1.2
Standby. With Cache, RTC, CPU, RAM and
(partial) register retention. RCOSC_LF
2.5
Standby. With Cache, RTC, CPU, RAM and
(partial) register retention. XOSC_LF
2.7
Idle. Supply Systems and RAM powered.
550
(1)
nA
µA
5.9
Radio RX (2)
6.1
(1)
6.1
Radio TX, 5-dBm output power (2)
9.1
Radio TX, 0-dBm output power
UNIT
1.45 mA +
31 µA/MHz
Active. Core running CoreMark
Radio RX
MAX
mA
Peripheral Current Consumption (Adds to core current Icore for each peripheral unit activated) (3)
Iperi
(1)
(2)
(3)
5.5
Peripheral power domain
Delta current with domain enabled
20
µA
Serial power domain
Delta current with domain enabled
13
µA
RF Core
Delta current with power domain enabled, clock
enabled, RF core idle
237
µA
µDMA
Delta current with clock enabled, module idle
130
µA
Timers
Delta current with clock enabled, module idle
113
µA
I2C
Delta current with clock enabled, module idle
12
µA
I2S
Delta current with clock enabled, module idle
36
µA
SSI
Delta current with clock enabled, module idle
93
µA
UART
Delta current with clock enabled, module idle
164
µA
Single-ended RF mode is optimized for size and power consumption. Measured on CC2650EM-4XS.
Differential RF mode is optimized for RF performance. Measured on CC2650EM-5XD.
Iperi is not supported in Standby or Shutdown.
General Characteristics
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FLASH MEMORY
Supported flash erase cycles before
failure
Flash page/sector erase current
100
Average delta current
12.6
4
KB
Average delta current, 4 bytes at a time
8.15
mA
8
ms
8
µs
Flash page/sector size
Flash write current
Flash page/sector erase time (1)
Flash write time
(1)
14
(1)
k Cycles
4 bytes at a time
mA
This number is dependent on Flash aging and will increase over time and erase cycles.
Specifications
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5.6
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – RX
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver sensitivity
Differential mode. Measured at the CC2650EM-5XD
SMA connector, PER = 1%
–100
dBm
Receiver sensitivity
Single-ended mode. Measured on CC2650EM-4XS,
at the SMA connector, PER = 1%
–97
dBm
Receiver saturation
Measured at the CC2650EM-5XD SMA connector,
PER = 1%
+4
dBm
Adjacent channel rejection
Wanted signal at –82 dBm, modulated interferer at
±5 MHz, PER = 1%
39
dB
Alternate channel rejection
Wanted signal at –82 dBm, modulated interferer at
±10 MHz, PER = 1%
52
dB
Channel rejection, ±15 MHz or
more
Wanted signal at –82 dBm, undesired signal is IEEE
802.15.4 modulated channel, stepped through all
channels 2405 to 2480 MHz, PER = 1%
57
dB
Blocking and desensitization,
5 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
64
dB
Blocking and desensitization,
10 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
64
dB
Blocking and desensitization,
20 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
65
dB
Blocking and desensitization,
50 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
68
dB
Blocking and desensitization,
–5 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
63
dB
Blocking and desensitization,
–10 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
63
dB
Blocking and desensitization,
–20 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
65
dB
Blocking and desensitization,
–50 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
67
dB
Spurious emissions, 30 MHz to
1000 MHz
Conducted measurement in a 50-Ω single-ended
load. Suitable for systems targeting compliance with
EN 300 328, EN 300 440 class 2, FCC CFR47, Part
15 and ARIB STD-T-66
–71
dBm
Spurious emissions, 1 GHz to
12.75 GHz
Conducted measurement in a 50 Ω single-ended
load. Suitable for systems targeting compliance with
EN 300 328, EN 300 440 class 2, FCC CFR47, Part
15 and ARIB STD-T-66
–62
dBm
Frequency error tolerance
Difference between the incoming carrier frequency
and the internally generated carrier frequency
>200
ppm
Symbol rate error tolerance
Difference between incoming symbol rate and the
internally generated symbol rate
>1000
ppm
RSSI dynamic range
RSSI accuracy
5.7
100
dB
±4
dB
IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – TX
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output power, highest setting
Delivered to a single-ended 50-Ω load through a balun
5
dBm
Output power, highest setting
Measured on CC2650EM-4XS, delivered to a singleended 50-Ω load
2
dBm
Output power, lowest setting
Delivered to a single-ended 50-Ω load through a balun
–21
dBm
Error vector magnitude
At maximum output power
2%
Specifications
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IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – TX (continued)
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Spurious emission conducted
measurement
MIN
TYP
f < 1 GHz, outside restricted bands
–43
f < 1 GHz, restricted bands ETSI
–65
f < 1 GHz, restricted bands FCC
–76
f > 1 GHz, including harmonics
–46
MAX
UNIT
dBm
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328
and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
5.8
24-MHz Crystal Oscillator (XOSC_HF)
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
ESR Equivalent series resistance (2)
ESR Equivalent series resistance
LM Motional inductance
MIN
6 pF < CL ≤ 9 pF
(2)
CL Crystal load capacitance (2)
80
Ω
< 1.6 × 10
/ CL
2
H
9
pF
24
MHz
–40
40
Start-up time (3) (5)
5.9
Ω
5
Crystal frequency tolerance (2) (4)
(5)
UNIT
60
–24
Crystal frequency (2) (3)
(1)
(2)
(3)
(4)
MAX
20
5 pF < CL ≤ 6 pF
Relates to load capacitance
(CL in Farads)
(2)
TYP
ppm
150
µs
Probing or otherwise stopping the XTAL while the DC-DC converter is enabled may cause permanent damage to the device.
The crystal manufacturer's specification must satisfy this requirement
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V
Includes initial tolerance of the crystal, drift over temperature, ageing and frequency pulling due to incorrect load capacitance. As per
IEEE 802.15.4 specification.
Kick-started based on a temperature and aging compensated RCOSC_HF using precharge injection.
32.768-kHz Crystal Oscillator (XOSC_LF)
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency (1)
ESR Equivalent series resistance
(1)
30
CL Crystal load capacitance (1)
(1)
16
TYP
MAX
32.768
6
UNIT
kHz
100
kΩ
12
pF
The crystal manufacturer's specification must satisfy this requirement
Specifications
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5.10 48-MHz RC Oscillator (RCOSC_HF)
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
Frequency
UNIT
48
Uncalibrated frequency accuracy
±1%
Calibrated frequency accuracy (1)
±0.25%
Start-up time
(1)
MAX
MHz
5
µs
Accuracy relative to the calibration source (XOSC_HF).
5.11 32-kHz RC Oscillator (RCOSC_LF)
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
Calibrated frequency (1)
32.8
Temperature coefficient
50
(1)
MAX
UNIT
kHz
ppm/°C
The frequency accuracy of the Real Time Clock (RTC) is not directly dependent on the frequency accuracy of the 32-kHz RC Oscillator.
The RTC can be calibrated to an accuracy within ±500 ppm of 32.768 kHz by measuring the frequency error of RCOSC_LF relative to
XOSC_HF and compensating the RTC tick speed. The procedure is explained in Running Bluetooth® Low Energy on CC2640 Without
32 kHz Crystal.
5.12 ADC Characteristics
Tc = 25°C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
Input voltage range
MIN
TYP
0
Resolution
VDDS
12
Sample rate
DNL (3)
INL
(4)
ENOB
Internal 4.3-V equivalent reference
2
LSB
Gain error
Internal 4.3-V equivalent reference (2)
2.4
LSB
>–1
LSB
±3
LSB
Differential nonlinearity
Integral nonlinearity
Effective number of bits
Internal 4.3-V equivalent reference (2), 200 ksps,
9.6-kHz input tone
9.8
VDDS as reference, 200 ksps, 9.6-kHz input tone
10
Signal-to-noise
and
Distortion ratio
Spurious-free dynamic
range
Bits
11.1
(2)
, 200 ksps,
Total harmonic distortion VDDS as reference, 200 ksps, 9.6-kHz input tone
–65
–69
dB
–71
Internal 4.3-V equivalent reference (2), 200 ksps,
9.6-kHz input tone
60
VDDS as reference, 200 ksps, 9.6-kHz input tone
63
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
69
Internal 4.3-V equivalent reference
9.6-kHz input tone
(1)
(2)
(3)
(4)
ksps
Offset
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
SFDR
V
Bits
200
Internal 4.3-V equivalent reference
9.6-kHz input tone
SINAD,
SNDR
UNIT
(2)
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
THD
MAX
dB
(2)
, 200 ksps,
67
VDDS as reference, 200 ksps, 9.6-kHz input tone
72
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
73
dB
Using IEEE Std 1241™-2010 for terminology and test methods.
Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V.
No missing codes. Positive DNL typically varies from +0.3 to +3.5, depending on device (see Figure 5-22).
For a typical example, see Figure 5-23.
Specifications
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ADC Characteristics (continued)
Tc = 25°C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
PARAMETER
(5)
18
TEST CONDITIONS
MIN
TYP
50
MAX
UNIT
clockcycles
Conversion time
Serial conversion, time-to-output, 24-MHz clock
Current consumption
Internal 4.3-V equivalent reference (2)
0.66
mA
Current consumption
VDDS as reference
0.75
mA
Reference voltage
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should
be initiated through the TIRTOS API in order to include the
gain/offset compensation factors stored in FCFG1.
4.3 (2) (5)
V
Reference voltage
Fixed internal reference (input voltage scaling disabled).
For best accuracy, the ADC conversion should be initiated
through the TIRTOS API in order to include the gain/offset
compensation factors stored in FCFG1. This value is
derived from the scaled value (4.3V) as follows:
Vref=4.3V*1408/4095
1.48
V
Reference voltage
VDDS as reference (Also known as RELATIVE) (input
voltage scaling enabled)
VDDS
V
Reference voltage
VDDS as reference (Also known as RELATIVE) (input
voltage scaling disabled)
VDDS /
2.82 (5)
V
Input Impedance
200 ksps, voltage scaling enabled. Capacitive input, Input
impedance depends on sampling frequency and sampling
time
>1
MΩ
Applied voltage must be within absolute maximum ratings (Section 5.1) at all times.
Specifications
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5.13 Temperature Sensor
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
4
Range
UNIT
°C
–40
85
°C
Accuracy
±5
°C
Supply voltage coefficient (1)
3.2
°C/V
(1)
Automatically compensated when using supplied driver libraries.
5.14 Battery Monitor
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
50
Range
1.8
Accuracy
UNIT
mV
3.8
13
V
mV
5.15 Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage range
0
VDDS
V
External reference voltage
0
VDDS
V
Internal reference voltage
DCOUPL as reference
Offset
Hysteresis
Decision time
Step from –10 mV to 10 mV
Current consumption when enabled (1)
(1)
1.27
V
3
mV
<2
mV
0.72
µs
8.6
µA
Additionally, the bias module must be enabled when running in standby mode.
Specifications
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5.16
www.ti.com
Low-Power Clocked Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Input voltage range
MIN
TYP
MAX
0
VDDS
Clock frequency
32
UNIT
V
kHz
Internal reference voltage, VDDS / 2
1.49 – 1.51
V
Internal reference voltage, VDDS / 3
1.01 – 1.03
V
Internal reference voltage, VDDS / 4
0.78 – 0.79
V
Internal reference voltage, DCOUPL / 1
1.25 – 1.28
V
Internal reference voltage, DCOUPL / 2
0.63 – 0.65
V
Internal reference voltage, DCOUPL / 3
0.42 – 0.44
V
Internal reference voltage, DCOUPL / 4
0.33 – 0.34
Offset
V
<2
Hysteresis
Decision time
Step from –50 mV to 50 mV
Current consumption when enabled
mV
<5
mV
<1
clock-cycle
362
nA
5.17 Programmable Current Source
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Current source programmable output range
Resolution
Current consumption (1)
(1)
TYP
MAX
UNIT
0.25 – 20
µA
0.25
µA
23
µA
Including current source at maximum
programmable output
Additionally, the bias module must be enabled when running in standby mode.
5.18 Synchronous Serial Interface (SSI)
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
S1 (1) tclk_per (SSIClk period)
S2
(1)
tclk_high (SSIClk high time)
TEST CONDITIONS
Device operating as SLAVE
MIN
TYP
12
MAX
UNIT
65024
system
clocks
Device operating as SLAVE
0.5
tclk_per
S3 (1) tclk_low (SSIClk low time)
Device operating as SLAVE
0.5
tclk_per
S1 (TX only) (1) tclk_per (SSIClk period)
One-way communication to SLAVE Device operating as MASTER
4
65024
system
clocks
S1 (TX and RX) (1) tclk_per (SSIClk period)
Normal duplex operation - Device
operating as MASTER
8
65024
system
clocks
S2
(1)
tclk_high (SSIClk high time)
Device operating as MASTER
0.5
tclk_per
S3
(1)
tclk_low(SSIClk low time)
Device operating as MASTER
0.5
tclk_per
(1)
20
Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.
Specifications
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S1
S2
SSIClk
S3
SSIFss
SSITx
SSIRx
MSB
LSB
4 to 16 bits
Figure 5-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
S2
S1
SSIClk
S3
SSIFss
SSITx
MSB
LSB
8-bit control
SSIRx
0
MSB
LSB
4 to 16 bits output data
Figure 5-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
Specifications
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S1
S2
SSIClk
(SPO = 0)
S3
SSIClk
(SPO = 1)
SSITx
(Master)
MSB
SSIRx
(Slave)
MSB
LSB
LSB
SSIFss
Figure 5-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
5.19 DC Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
1.32
1.54
MAX
UNIT
TA = 25°C, VDDS = 1.8 V
GPIO VOH at 8-mA load
IOCURR = 2, high-drive GPIOs only
GPIO VOL at 8-mA load
IOCURR = 2, high-drive GPIOs only
GPIO VOH at 4-mA load
IOCURR = 1
GPIO VOL at 4-mA load
IOCURR = 1
0.21
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
71.7
µA
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
21.1
µA
GPIO high/low input transition,
no hysteresis
IH = 0, transition between reading 0 and reading 1
0.88
V
GPIO low-to-high input transition,
with hysteresis
IH = 1, transition voltage for input read as 0 → 1
1.07
V
GPIO high-to-low input transition,
with hysteresis
IH = 1, transition voltage for input read as 1 → 0
0.74
V
GPIO input hysteresis
IH = 1, difference between 0 → 1 and 1 → 0 points
0.33
V
22
Specifications
0.26
1.32
V
0.32
1.58
V
V
0.32
V
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DC Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C, VDDS = 3.0 V
GPIO VOH at 8-mA load
IOCURR = 2, high-drive GPIOs only
2.68
V
GPIO VOL at 8-mA load
IOCURR = 2, high-drive GPIOs only
0.33
V
GPIO VOH at 4-mA load
IOCURR = 1
2.72
V
GPIO VOL at 4-mA load
IOCURR = 1
0.28
V
TA = 25°C, VDDS = 3.8 V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
277
µA
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
113
µA
GPIO high/low input transition,
no hysteresis
IH = 0, transition between reading 0 and reading 1
1.67
V
GPIO low-to-high input transition,
with hysteresis
IH = 1, transition voltage for input read as 0 → 1
1.94
V
GPIO high-to-low input transition,
with hysteresis
IH = 1, transition voltage for input read as 1 → 0
1.54
V
GPIO input hysteresis
IH = 1, difference between 0 → 1 and 1 → 0 points
0.4
V
VIH
Lowest GPIO input voltage reliably interpreted as a
«High»
VIL
Highest GPIO input voltage reliably interpreted as a
«Low»
TA = 25°C
(1)
0.8 VDDS (1)
VDDS (1)
0.2
Each GPIO is referenced to a specific VDDS pin. See the technical reference manual listed in Section 8.3 for more details.
5.20 Thermal Resistance Characteristics
NAME
RSM (°C/W) (1)
DESCRIPTION
(2)
RHB (°C/W) (1)
(2)
RGZ (°C/W) (1)
RθJA
Junction-to-ambient thermal resistance
36.9
32.8
29.6
RθJC(top)
Junction-to-case (top) thermal resistance
30.3
24.0
15.7
RθJB
Junction-to-board thermal resistance
7.6
6.8
6.2
PsiJT
Junction-to-top characterization parameter
0.4
0.3
0.3
PsiJB
Junction-to-board characterization parameter
7.4
6.8
6.2
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.1
1.9
1.9
(1)
(2)
(2)
°C/W = degrees Celsius per watt.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air).
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements.
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
Specifications
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5.21 Timing Requirements
MAX
UNIT
Rising supply-voltage slew rate
MIN
0
NOM
100
mV/µs
Falling supply-voltage slew rate
0
20
mV/µs
3
mV/µs
5
°C/s
Falling supply-voltage slew rate, with low-power flash settings (1)
Positive temperature gradient in standby (2)
No limitation for negative
temperature gradient, or
outside standby mode
CONTROL INPUT AC CHARACTERISTICS (3)
RESET_N low duration
(1)
(2)
(3)
1
µs
For smaller coin cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor (see
Figure 7-1) must be used to ensure compliance with this slew rate.
Applications using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see
Section 5.11).
TA = –40°C to 85°C, VDDS = 1.7 V to 3.8 V, unless otherwise noted.
5.22 Switching Characteristics
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKEUP AND TIMING
Idle → Active
Standby → Active
Shutdown → Active
24
Specifications
14
µs
151
µs
1015
µs
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5.23 Typical Characteristics
-95
-95
-96
IEEE 802.15.4 5XD Sensitivity
IEEE 802.15.4 4XS Sensitivity
-96
Sensitivity (dBm)
Sensitivity (dBm)
-97
-98
-99
-100
-97
-98
-99
-101
-102
-100
Sensitivity 4XS
Sensitivity 5XD
-103
-40 -30 -20 -10
0
10 20 30 40
Temperature (qC)
50
60
70
-101
1.8
80
Figure 5-4. IEEE 802.15.4 Sensitivity vs Temperature
2.8
VDDS (V)
3.3
3.8
D005
Figure 5-5. IEEE 802.15.4 Sensitivity vs Supply Voltage (VDDS)
-95
6
Sensitivity 4XS
Sensitivity 5XD
5
Output Power (dBm)
-96
Sensitivity Level (dBm)
2.3
-97
-98
-99
4
4XS 2-dBm Setting
5XD 5-dBm Setting
3
2
1
-100
-101
2400
0
-40 -30 -20 -10
2410
2420
2430 2440 2450
Frequency (MHz)
2460
2470
2480
10 20 30 40
Temperature (qC)
50
60
70
80
D019
Figure 5-6. IEEE 802.15.4 Sensitivity vs Channel Frequency
Figure 5-7. TX Output Power vs Temperature
8
6
5-dBm setting (5XD)
0-dBm setting (4XS)
7
5
6
Output Power (dBm)
Output power (dBm)
0
4
3
2
5
4
3
2
1
1
0
5XD 5 dBm Setting
4XS 2 dBm Setting
0
1.8
2.3
2.8
VDDS (V)
3.3
3.8
-1
2400
2410
D003
Figure 5-8. TX Output Power vs Supply Voltage (VDDS)
2420
2430 2440 2450
Frequency (MHz)
2460
2470
2480
D021
Figure 5-9. TX Output Power
vs Channel Frequency
Specifications
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Typical Characteristics (continued)
16
14
Current Consumption (mA)
4XS 0-dBm Setting
4XS 2-dBm Setting
5XD 5-dBm Setting
15
TX Current (mA)
13
12
11
10
9
8
7
6
5
4
1.8
2
2.2
2.4
2.6 2.8
3
VDDS (V)
3.2
3.4
3.6
3.8
2.55
2.8
3.05
Voltage (V)
3.3
3.55
3.8
D016
12
10
6.6
TX Current (mA)
RX Current (mA)
2.3
5XD RX Current
4XS RX Current
6.4
6.2
6
5.8
8
6
4
2
5.6
-40 -30 -20 -10
5XD 5 dBm Setting
4XS 2 dBm Setting
0
10 20 30 40
Temperature (qC)
50
60
70
0
-40 -30 -20 -10
80
D001
Figure 5-12. RX Mode Current Consumption vs Temperature
0
10 20 30 40
Temperature (qC)
50
60
70
80
D002
Figure 5-13. TX Mode Current Consumption vs Temperature
5
3.1
Active Mode Current
Active Mode Current
3.05
Current Consumption (mA)
Active Mode Current Consumpstion (mA)
2.05
Figure 5-11. RX Mode Current vs Supply Voltage (VDDS)
7
3
2.95
2.9
2.85
-40 -30 -20 -10
4.5
4
3.5
3
2.5
0
10 20 30 40
Temperature (qC)
50
60
70
2
1.8
80
D006
Figure 5-14. Active Mode (MCU Running, No Peripherals)
Current Consumption vs Temperature
26
4XS
5XD
D015
Figure 5-10. TX Current Consumption
vs Supply Voltage (VDDS)
6.8
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
1.8
2.3
2.8
VDDS (V)
3.3
3.8
D007
Figure 5-15. Active Mode (MCU Running, No Peripherals) Current
Consumption vs Supply Voltage (VDDS)
Specifications
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Typical Characteristics (continued)
4
11.4
Standby Mode Current
11
Effective Number of Bits
3
Current (uA)
Fs= 200 kHz, No Averaging
Fs= 200 kHz, 32 samples averaging
11.2
3.5
2.5
2
1.5
1
10.8
10.6
10.4
10.2
10
9.8
0.5
0
-20
9.6
-10
0
10
20 30 40 50
Temperature (qC)
60
70
9.4
200 300 500
80
D008
Figure 5-16. Standby Mode Current Consumption With RCOSC
RTC vs Temperature
1000 2000
5000 10000 20000
Input Frequency (Hz)
100000
D009
Figure 5-17. SoC ADC Effective Number of Bits vs Input
Frequency (Internal Reference, No Scaling)
1007.5
1006.4
1006.2
1007
1006.5
1005.8
ADC Code
ADC Code
1006
1005.6
1005.4
1006
1005.5
1005.2
1005
1005
1004.8
1.8
2.3
2.8
VDDS (V)
3.3
3.8
1004.5
-40 -30 -20 -10
D012
Figure 5-18. SoC ADC Output vs Supply Voltage (Fixed Input,
Internal Reference, No Scaling)
60
70
80
D013
4.5
4
Standby Current (PA)
10.2
ENOB
50
5
ENOB Internal Reference (No Averaging)
ENOB Internal Reference (32 Samples Averaging)
10.3
10.1
10
9.9
3.5
3
2.5
2
1.5
9.8
1
9.7
0.5
9.6
1k
10 20 30 40
Temperature (qC)
Figure 5-19. SoC ADC Output vs Temperature (Fixed Input,
Internal Reference, No Scaling)
10.5
10.4
0
10k
Sampling Frequency (Hz)
100k
200k
0
-40
D009A
Figure 5-20. SoC ADC ENOB vs Sampling Frequency
(Input Frequency = FS / 10)
-20
0
20
40
Temperature (qC)
60
80
100
D021
Figure 5-21. Standby Mode Supply Current vs Temperature
Specifications
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Typical Characteristics (continued)
3.5
3
2.5
2
DNL
1.5
1
0.5
0
-0.5
-1
ADC Code
4200
4000
3800
3600
3400
3200
3000
2800
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
-1.5
D010
Figure 5-22. SoC ADC DNL vs ADC Code (Internal Reference, No Scaling)
3
2
1
INL
0
-1
-2
-3
-4
0
200
400
600
800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 4200
ADC Code
D011
Figure 5-23. SoC ADC INL vs ADC Code (Internal Reference, No Scaling)
28
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6 Detailed Description
6.1
Overview
The core modules of the CC26xx product family are shown in the Section 6.2.
6.2
Functional Block Diagram
SimpleLinkTM CC26xx wireless MCU
RF core
cJTAG
Main CPU
ROM
ARM®
Cortex®-M3
ADC
ADC
128KB
Flash
8KB
cache
Digital PLL
DSP modem
4KB
SRAM
ARM®
20KB
SRAM
Cortex®-M0
ROM
Sensor controller
General peripherals / modules
I2C
4× 32-bit Timers
UART
2× SSI (SPI, µW, TI)
Sensor controller
engine
12-bit ADC, 200 ks/s
I2S
Watchdog timer
2x comparator
10 / 15 / 31 GPIOs
TRNG
SPI-I2C digital sensor IF
AES
Temp. / batt. monitor
Constant current source
32 ch. µDMA
RTC
Time-to-digital converter
2KB SRAM
DC-DC converter
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6.3
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Main CPU
The SimpleLink CC2630 Wireless MCU contains an ARM Cortex-M3 (CM3) 32-bit CPU, which runs the
application and the higher layers of the protocol stack.
The CM3 processor provides a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
CM3 features include the following:
• 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
• Outstanding processing performance combined with fast interrupt handling
• ARM Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the
range of a few kilobytes of memory for microcontroller-class applications:
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
– Unaligned data access, enabling data to be efficiently packed into memory
• Fast code execution permits slower processor clock or increases sleep mode time
• Harvard architecture characterized by separate buses for instruction and data
• Efficient processor core, system, and memories
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• Deterministic, high-performance interrupt handling for time-critical applications
• Enhanced system debug with extensive breakpoint and trace capabilities
• Serial wire trace reduces the number of pins required for debugging and tracing
• Migration from the ARM7™ processor family for better performance and power efficiency
• Optimized for single-cycle flash memory use
• Ultralow-power consumption with integrated sleep modes
• 1.25 DMIPS per MHz
6.4
RF Core
The RF Core contains an ARM Cortex-M0 processor that interfaces the analog RF and base-band
circuitries, handles data to and from the system side, and assembles the information bits in a given packet
structure. The RF core offers a high level, command-based API to the main CPU.
The RF core is capable of autonomously handling the time-critical aspects of the radio protocols (802.15.4
ZigBee) thus offloading the main CPU and leaving more resources for the user application.
The RF core has a dedicated 4-KB SRAM block and runs initially from separate ROM memory. The ARM
Cortex-M0 processor is not programmable by customers.
30
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Sensor Controller
The Sensor Controller contains circuitry that can be selectively enabled in standby mode. The peripherals
in this domain may be controlled by the Sensor Controller Engine which is a proprietary power-optimized
CPU. This CPU can read and monitor sensors or perform other tasks autonomously, thereby significantly
reducing power consumption and offloading the main CM3 CPU.
The Sensor Controller is set up using a PC-based configuration tool, called Sensor Controller Studio, and
potential use cases may be (but are not limited to):
• Analog sensors using integrated ADC
• Digital sensors using GPIOs, bit-banged I2C, and SPI
• UART communication for sensor reading or debugging
• Capacitive sensing
• Waveform generation
• Pulse counting
• Keyboard scan
• Quadrature decoder for polling rotation sensors
• Oscillator calibration
NOTE
Texas Instruments provides application examples for some of these use cases, but not for all
of them.
The peripherals in the Sensor Controller include the following:
• The low-power clocked comparator can be used to wake the device from any state in which the
comparator is active. A configurable internal reference can be used in conjunction with the comparator.
The output of the comparator can also be used to trigger an interrupt or the ADC.
• Capacitive sensing functionality is implemented through the use of a constant current source, a timeto-digital converter, and a comparator. The continuous time comparator in this block can also be used
as a higher-accuracy alternative to the low-power clocked comparator. The Sensor Controller will take
care of baseline tracking, hysteresis, filtering and other related functions.
• The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC
can be triggered by many different sources, including timers, I/O pins, software, the analog
comparator, and the RTC.
• The Sensor Controller also includes a SPI–I2C digital interface.
• The analog modules can be connected to up to eight different GPIOs.
The peripherals in the Sensor Controller can also be controlled from the main application processor.
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Table 6-1. GPIOs Connected to the Sensor Controller (1)
ANALOG CAPABLE
7 × 7 RGZ
DIO NUMBER
5 × 5 RHB
DIO NUMBER
Y
30
14
Y
29
13
Y
28
12
Y
27
11
9
Y
26
9
8
Y
25
10
7
Y
24
8
6
Y
23
7
5
N
7
4
2
N
6
3
1
N
5
2
0
N
4
1
N
3
0
N
2
N
1
N
0
(1)
6.6
4 × 4 RSM
DIO NUMBER
Depending on the package size, up to 16 pins can be connected to the Sensor Controller. Up to 8 of
these pins can be connected to analog modules.
Memory
The flash memory provides nonvolatile storage for code and data. The flash memory is in-system
programmable.
The SRAM (static RAM) can be used for both storage of data and execution of code and is split into two
4-KB blocks and two 6-KB blocks. Retention of the RAM contents in standby mode can be enabled or
disabled individually for each block to minimize power consumption. In addition, if flash cache is disabled,
the 8-KB cache can be used as a general-purpose RAM.
The ROM provides preprogrammed embedded TI RTOS kernel, Driverlib and lower layer protocol stack
software (802.15.4 MAC). It also contains a bootloader that can be used to reprogram the device using
SPI or UART.
6.7
Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1)
interface.
32
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6.8
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Power Management
To minimize power consumption, the CC2630 device supports a number of power modes and power
management features (see Table 6-2).
Table 6-2. Power Modes
SOFTWARE CONFIGURABLE POWER MODES
ACTIVE
IDLE
STANDBY
SHUTDOWN
RESET PIN
HELD
CPU
Active
Off
Off
Off
Off
Flash
On
Available
Off
Off
Off
SRAM
On
On
On
Off
Off
Radio
Available
Available
Off
Off
Off
MODE
Supply System
Current
Wake-up Time to CPU Active (1)
Register Retention
SRAM Retention
On
On
Duty Cycled
Off
Off
1.45 mA + 31 µA/MHz
550 µA
1 µA
0.15 µA
0.1 µA
–
14 µs
151 µs
1015 µs
1015 µs
Full
Full
Partial
No
No
Full
Full
Full
No
No
High-Speed Clock
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
Off
Off
Off
Low-Speed Clock
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Off
Off
Peripherals
Available
Available
Off
Off
Off
Sensor Controller
Available
Available
Available
Off
Off
Wake up on RTC
Available
Available
Available
Off
Off
Wake up on Pin Edge
Available
Available
Available
Available
Off
Wake up on Reset Pin
Available
Available
Available
Available
Available
Brown Out Detector (BOD)
Active
Active
Duty Cycled (2)
Off
N/A
Power On Reset (POR)
Active
Active
Active
Active
N/A
(1)
(2)
Not including RTOS overhead
The Brown Out Detector is disabled between recharge periods in STANDBY. Lowering the supply voltage below the BOD threshold
between two recharge periods while in STANDBY may cause the BOD to lock the device upon wake-up until a Reset/POR releases it.
To avoid this, it is recommended that STANDBY mode is avoided if there is a risk that the supply voltage (VDDS) may drop below the
specified operating voltage range. For the same reason, it is also good practice to ensure that a power cycling operation, such as a
battery replacement, triggers a Power-on-reset by ensuring that the VDDS decoupling network is fully depleted before applying supply
voltage again (for example, inserting new batteries).
In active mode, the application CM3 CPU is actively executing code. Active mode provides normal
operation of the processor and all of the peripherals that are currently enabled. The system clock can be
any available clock source (see Table 6-2).
In idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not
clocked and no code is executed. Any interrupt event will bring the processor back into active mode.
In standby mode, only the always-on domain (AON) is active. An external wake event, RTC event, or
sensor-controller event is required to bring the device back to active mode. MCU peripherals with retention
do not need to be reconfigured when waking up again, and the CPU continues execution from where it
went into standby mode. All GPIOs are latched in standby mode.
In shutdown mode, the device is turned off entirely, including the AON domain and the Sensor Controller.
The I/Os are latched with the value they had before entering shutdown mode. A change of state on any
I/O pin defined as a wake from Shutdown pin wakes up the device and functions as a reset trigger. The
CPU can differentiate between a reset in this way, a reset-by-reset pin, or a power-on-reset by reading the
reset status register. The only state retained in this mode is the latched I/O state and the Flash memory
contents.
Detailed Description
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The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor
Controller independently of the main CPU, which means that the main CPU does not have to wake up, for
example, to execute an ADC sample or poll a digital sensor over SPI. The main CPU saves both current
and wake-up time that would otherwise be wasted. The Sensor Controller Studio enables the user to
configure the sensor controller and choose which peripherals are controlled and which conditions wake up
the main CPU.
6.9
Clock Systems
The CC2630 supports two external and two internal clock sources.
A 24-MHz crystal is required as the frequency reference for the radio. This signal is doubled internally to
create a 48-MHz clock.
The 32-kHz crystal is optional. The low-speed crystal oscillator is designed for use with a 32-kHz watchtype crystal.
The internal high-speed oscillator (48-MHz) can be used as a clock source for the CPU subsystem.
The internal low-speed oscillator (32.768-kHz) can be used as a reference if the low-power crystal
oscillator is not used.
The 32-kHz clock source can be used as external clocking reference through GPIO.
6.10 General Peripherals and Modules
The I/O controller controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five
GPIOs have high drive capabilities (marked in bold in Section 4).
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and Texas
Instruments synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz.
The UART implements a universal asynchronous receiver/transmitter function. It supports flexible baudrate generation up to a maximum of 3 Mbps .
Timer 0 is a general-purpose timer module (GPTM), which provides two 16-bit timers. The GPTM can be
configured to operate as a single 32-bit timer, dual 16-bit timers or as a PWM module.
Timer 1, Timer 2, and Timer 3 are also GPTMs. Each of these timers is functionally equivalent to Timer 0.
In addition to these four timers, the RF core has its own timer to handle timing for RF protocols; the RF
timer can be synchronized to the RTC.
The I2C interface is used to communicate with devices compatible with the I2C standard. The I2C interface
is capable of 100-kHz and 400-kHz operation, and can serve as both I2C master and I2C slave.
The TRNG module provides a true, nondeterministic noise source for the purpose of generating keys,
initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring
oscillators that create unpredictable output to feed a complex nonlinear combinatorial circuit.
The watchdog timer is used to regain control if the system fails due to a software error after an external
device fails to respond as expected. The watchdog timer can generate an interrupt or a reset when a
predefined time-out value is reached.
34
Detailed Description
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CC2630
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The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to
offload data transfer tasks from the CM3 CPU, allowing for more efficient use of the processor and the
available bus bandwidth. The µDMA controller can perform transfer between memory and peripherals. The
µDMA controller has dedicated channels for each supported on-chip module and can be programmed to
automatically perform transfers between peripherals and memory as the peripheral is ready to transfer
more data. Some features of the µDMA controller include the following (this is not an exhaustive list):
• Highly flexible and configurable channel operation of up to 32 channels
• Transfer modes:
– Memory-to-memory
– Memory-to-peripheral
– Peripheral-to-memory
– Peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits
The AON domain contains circuitry that is always enabled, except for in Shutdown (where the digital
supply is off). This circuitry includes the following:
• The RTC can be used to wake the device from any state where it is active. The RTC contains three
compare and one capture registers. With software support, the RTC can be used for clock and
calendar operation. The RTC is clocked from the 32-kHz RC oscillator or crystal. The RTC can also be
compensated to tick at the correct frequency even when the internal 32-kHz RC oscillator is used
instead of a crystal.
• The battery monitor and temperature sensor are accessible by software and give a battery status
indication as well as a coarse temperature measure.
6.11 Voltage Supply Domains
The CC2630 device can interface to two or three different voltage domains depending on the package
type. On-chip level converters ensure correct operation as long as the signal voltage on each input/output
pin is set with respect to the corresponding supply pin (VDDS, VDDS2 or VDDS3). lists the pin-to-VDDS
mapping.
Table 6-3. Pin function to VDDS mapping table
Package
VQFN 7 × 7 (RGZ)
VQFN 5 × 5 (RHB)
VQFN 4 × 4 (RSM)
VDDS (1)
DIO 23–30
Reset_N
DIO 7–14
Reset_N
DIO 5–9
Reset_N
VDDS2
DIO 0–11
DIO 0–6
JTAG
DIO 0–4
JTAG
VDDS3
DIO 12–22
JTAG
N/A
N/A
(1)
VDDS_DCDC must be connected to VDDS on the PCB
6.12 System Architecture
Depending on the product configuration, CC26xx can function either as a Wireless Network Processor
(WNP—an IC running the wireless protocol stack, with the application running on a separate MCU), or as
a System-on-Chip (SoC), with the application and protocol stack running on the ARM CM3 core inside the
device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second
case, the application must be written according to the application framework supplied with the wireless
protocol stack.
Detailed Description
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www.ti.com
7 Application, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI's customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1
Application Information
Very few external components are required for the operation of the CC2630 device. This section provides
some general information about the various configuration options when using the CC2630 in an
application, and then shows two examples of application circuits with schematics and layout. This is only a
small selection of the many application circuit examples available as complete reference designs from the
product folder on www.ti.com.
Figure 7-1 shows the various RF front-end configuration options. The RF front end can be used in
differential- or single-ended configurations with the options of having internal or external biasing. These
options allow for various trade-offs between cost, board space, and RF performance. Differential operation
with external bias gives the best performance while single-ended operation with internal bias gives the
least amount of external components and the lowest power consumption. Reference designs exist for
each of these options.
Red = Not necessary if internal bias is used
6.8 pF
Antenna
(50 Ohm)
Pin 3 (RXTX)
2.4 nH
1 pF
10µF
To VDDR
pins
Pin 2 (RF N)
6.2±6.8 nH
Pin 1 (RF P)
Optional
inductor.
Only
needed for
10µH
DCDC
operation
2.4±2.7 nH
Differential
operation
2 nH
2 nH
12 pF
1 pF
1 pF
Antenna
(50 Ohm)
Red = Not necessary if internal bias is used
CC26xx
DCDC_SW
VDDS_DCDC
(GND exposed die
attached pad )
input
decoupling
10µF±22µF
Pin 2 (RF N)
Pin 3/4 (RXTX)
15 nH
Pin 1 (RF P)
2 nH
Pin 2 (RF N)
Pin 1 (RF P)
Single ended
operation
12 pF
1.2 pF
1.2 pF
Antenna
(50 Ohm)
Red = Not necessary if internal bias is used
Pin 3 (RXTX)
15 nH
24MHz
XTAL
(Load caps
on chip)
2 nH
Pin 2 (RF N)
12 pF
Single ended
operation with 2
antennas
1.2 pF
1.2 pF
Antenna
(50 Ohm)
15 nH
2 nH
Pin 1 (RF P)
12 pF
1.2 pF
1.2 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. CC2630 Application Circuit
36
Application, Implementation, and Layout
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Figure 7-2 shows the various supply voltage configuration options. Not all power supply decoupling
capacitors or digital I/Os are shown. Exact pin positions will vary between the different package options.
For a detailed overview of power supply decoupling and wiring, see the TI reference designs and the
CC26xx technical reference manual (Section 8.3).
Internal DC-DC Regulator
Internal LDO Regulator
To All VDDR Pins
External Regulator
To All VDDR Pins
10 F
Ext.
Regulator
1.7 V±1.95 V to All VDDR- and VDDS Pins Except VDDS_DCDC
10 F
VDDS
VDDS
2.2 F
VDDS
VDDS
10 H
CC26xx
DCDC_SW Pin
VDDS_DCDC Pin
CC26xx
Pin 3/4 (RXTX)
(GND Exposed Die
Attached Pad)
Pin 2 (RF N)
NC
VDDS_DCDC Pin
Pin 2 (RF N)
Pin 1 (RF P)
VDDS_DCDC
Input Decoupling
10 F±22 F
DCDC_SW Pin
VDDS_DCDC Pin
(GND Exposed Die
Attached Pad)
Pin 1 (RF P)
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
VDDS_DCDC
Input Decoupling
10 F±22 F
VDDR
VDDR
VDDR
VDDR
24-MHz XTAL
(Load Caps on Chip)
1.8 V±3.8 V
to All VDDS Pins
CC26xx
Pin 3/4 (RXTX)
(GND Exposed Die
Attached Pad)
24-MHz XTAL
(Load Caps
on Chip)
24-MHz XTAL
(Load Caps on Chip)
1.8 V±3.8 V
Supply Voltage
To All VDDS Pins
Copyright © 2016, Texas Instruments Incorporated
Figure 7-2. Supply Voltage Configurations
Application, Implementation, and Layout
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7.2
www.ti.com
5 × 5 External Differential (5XD) Application Circuit
VDD_EB
VDDS
BLM18HE152SN1
2
1
FL1
VDDS Decoupling Capacitors
Pin 11
VDDR
Pin 18
Pin 28
DCDC_SW 2
C2
C3
C4
C6
C7
DNM
100 nF
100 nF
10 µF
100 nF
L1
VDDR Decoupling Capacitors
Pin 29
1
10 uH
C8
C9
10 µF
100 nF
Pin 32
C10
C16
100 nF
DNM
Place L1 and
C8 close to pin 17
VDDS
VDDR
U1
VDDS
R1
100 k
nRESET
DIO_0
DIO_1
DIO_2
DIO_3
DIO_4
DIO_5/JTAG_TDO
DIO_6/JTAG_TDI
DIO_7
DIO_8
DIO_9
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
6
7
8
9
10
15
16
20
21
22
23
24
25
26
27
JTAG_TCK
J TAG_TMS
19
14
13
C20
100 nF
12
C19
1 µF
33
DIO_0
DIO_1
DIO_2
DIO_3
DIO_4
DIO_5
DIO_6
DIO_7
DIO_8
DIO_9
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
VDDS
VDDS2
VDDS_DCDC
VDDR
VDDR
28
11
18
29
32
X24M_P
X24M_N
RESET_N
JTAG_TCKC
JTAG_TMSC
X32K_Q2
X32K_Q1
3
2
1
31
30
50-Ω
Antenna
1
17 DCDC_SW
DCDC_SW
RX_TX
RF_N
RF_P
C31
6.8 pF
RX_TX
RFN
L21
2.4 nH
2
1
C21
1 pF
L10
6.2 nH
X24M_P
X24M_N
RFP
5
4
2
1
L11
1
2
2.7 nH
C11
L12
2
1 L13 2
C12 2 nH
C13
DNM
1 pF
2 nH
1 pF
DCOUPL
VSS
CC2650F128RHB
Y2
24 MHz
Y1
32.768 kHz
3
1
C17
12 pF
C18
C22
12 pF DNM
C23
2
4
DNM
Copyright © 2016, Texas Instruments Incorporated
Figure 7-3. 5 × 5 External Differential (5XD) Application Circuit
38
Application, Implementation, and Layout
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7.2.1
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
Layout
Figure 7-4. 5 × 5 External Differential (5XD) Layout
Application, Implementation, and Layout
Copyright © 2015–2016, Texas Instruments Incorporated
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7.3
www.ti.com
4 × 4 External Single-ended (4XS) Application Circuit
VDD_EB
VDDS
FL1
2
Pin 11
1
BLM18HE152SN1
VDDR
VDDS Decoupling Capacitors
Pin 19
Pin 27
C2
DCDC_SW 1
DNM
C4
100 nF
Pin 32
C8
C6
100 nF
10 µF
VDDR Decoupling Capacitors
Pin 28
2
10 µH
C5
C3
100 nF
L1
C9
100 nF
10 µF
C16
C10
100 nF
DNM
Place L1 and
C8 close to pin 18
VDDS
VDDR
U1
VDDS
R1
100 k
DIO_0
DIO_1
DIO_2
DIO_3/JTAG_TDO
DIO_4/JTAG_TDI
DIO_5
DIO_6
DIO_7
DIO_8
DIO_9
8
9
10
15
16
22
23
24
25
26
nRESET
nRESET
JTAG_TCK
JTAG_TMS
C20
100 nF
21
14
13
12
C19
1 µF
3
7
17
20
29
33
DIO_0
DIO_1
DIO_2
DIO_3
DIO_4
DIO_5
DIO_6
DIO_7
DIO_8
DIO_9
VDDS
VDDS2
VDDS_DCDC
VDDR
VDDR
DCDC_SW
27
11
19
28
32
RF_N used for RX biasing.
L21 may be removed at the
cost of 1 dB degraded
sensitivity
DCDC_SW
18
4
RX/TX
RF_N
RF_P
RESET_N
JTAG_TCKC
JTAG_TMSC
1
2
1
RF_P
31
30
X24M_P
X24M_N
L21
2
15 nH
1
C12
X24M_P
X24M_N
DCOUPL
X32K_Q2
X32K_Q1
VSS
VSS
VSS
VSS
VSS
EGP
50-Ω
Antenna
L12
2 nH
1.2 pF
C14
2
C13
12 pF
1.2 pF
6
5
CC26XX_4X4
Y2
24 MHz
Y1
32.768 kHz
C17
12 pF
3
1
C18
12 pF
C22
DNM
C23
2
4
DNM
Copyright © 2016, Texas Instruments Incorporated
Figure 7-5. 4 × 4 External Single-ended (4XS) Application Circuit
40
Application, Implementation, and Layout
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SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
Layout
Figure 7-6. 4 × 4 External Single-ended (4XS) Layout
Application, Implementation, and Layout
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www.ti.com
8 Device and Documentation Support
8.1
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and
date-code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example,
CC2630 is in production; therefore, no prefix/identification is assigned).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Production devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, RSM).
For orderable part numbers of the CC2630 device in the RSM, RHB or RGZ package types, see the
Package Option Addendum of this document, the TI website (www.ti.com), or contact your TI sales
representative.
CC26 xx
F128
yyy
(R/T)
PREFIX
X = Experimental device
Blank = Qualified device
DEVICE FAMILY
SimpleLink™ Multistandard
Wireless MCU
DEVICE
20 = RF4CE
30 = Zigbee
40 = Bluetooth
50 = Multi-Protocol
R = Large Reel
T = Small Reel
PACKAGE DESIGNATOR
RGZ = 48-pin VQFN (Very Thin Quad Flatpack No-Lead)
RHB = 32-pin VQFN (Very Thin Quad Flatpack No-Lead)
RSM = 32-pin VQFN (Very Thin Quad Flatpack No-Lead)
ROM version 1
Flash = 128KB
Figure 8-1. Device Nomenclature
42
Device and Documentation Support
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8.2
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
Tools and Software
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules.
The following products support development of the CC2630 device applications:
Software Tools:
SmartRF Studio 7:
SmartRF Studio is a PC application that helps designers of radio systems to easily evaluate the RF-IC at
an early stage in the design process.
• Test functions for sending and receiving radio packets, continuous wave transmit and receive
• Evaluate RF performance on custom boards by wiring it to a supported evaluation board or debugger
• Can also be used without any hardware, but then only to generate, edit and export radio configuration
settings
• Can be used in combination with several development kits for Texas Instruments’ CCxxxx RF-ICs
Sensor Controller Studio:
Sensor Controller Studio provides a development environment for the CC26xx Sensor Controller. The
Sensor Controller is a proprietary, power-optimized CPU in the CC26xx, which can perform simple
background tasks autonomously and independent of the System CPU state.
• Allows for Sensor Controller task algorithms to be implemented using a C-like programming language
• Outputs a Sensor Controller Interface driver, which incorporates the generated Sensor Controller
machine code and associated definitions
• Allows for rapid development by using the integrated Sensor Controller task testing and debugging
functionality. This allows for live visualization of sensor data and algorithm verification.
IDEs and Compilers:
Code Composer Studio:
• Integrated development environment with project management tools and editor
• Code Composer Studio (CCS) 6.1 and later has built-in support for the CC26xx device family
• Best support for XDS debuggers; XDS100v3, XDS110 and XDS200
• High integration with TI-RTOS with support for TI-RTOS Object View
IAR Embedded Workbench for ARM
• Integrated development environment with project management tools and editor
• IAR EWARM 7.30.3 and later has built-in support for the CC26xx device family
• Broad debugger support, supporting XDS100v3, XDS200, IAR I-Jet and Segger J-Link
• Integrated development environment with project management tools and editor
• RTOS plugin available for TI-RTOS
For a complete listing of development-support tools for the CC2630 platform, visit the Texas Instruments
website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office
or authorized distributor.
Device and Documentation Support
Copyright © 2015–2016, Texas Instruments Incorporated
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Product Folder Links: CC2630
43
CC2630
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
8.3
www.ti.com
Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com
(CC2630). In the upper right corner, click on Alert me to register and receive a weekly digest of any
product information that has changed. For change details, review the revision history included in any
revised document.
The current documentation that describes the CC2630 devices, related peripherals, and other technical
collateral is listed in the following.
Technical Reference Manual
CC13xx, CC26xx SimpleLink™ Wireless MCU Technical Reference Manual
CC26xx SimpleLink™ Wireless MCU Errata
SPACER
Errata
CC2630 and CC2650 SimpleLink™ Wireless MCU Errata
8.4
Texas Instruments Low-Power RF Website
Texas Instruments' Low-Power RF website has all the latest products, application and design notes, FAQ
section, news and events updates. Go to www.ti.com/lprf.
8.5
Low-Power RF eNewsletter
The Low-Power RF eNewsletter is up-to-date on new products, news releases, developers’ news, and
other news and events associated with low-power RF products from TI. The Low-Power RF eNewsletter
articles include links to get more online information.
Sign up at: www.ti.com/lprfnewsletter
8.6
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
Low-Power RF Online Community Wireless Connectivity Section of the TI E2E Support Community
• Forums, videos, and blogs
• RF design help
• E2E interaction
Join here.
Low-Power RF Developer Network Texas Instruments has launched an extensive network of low-power
RF development partners to help customers speed up their application development. The
network consists of recommended companies, RF consultants, and independent design
houses that provide a series of hardware module products and design services, including:
• RF circuit, low-power RF, and ZigBee design services
• Low-power RF and ZigBee module solutions and development tools
• RF certification services and RF circuit manufacturing
For help with modules, engineering services or development tools:
Search the Low-Power RF Developer Network to find a suitable partner.
www.ti.com/lprfnetwork
44
Device and Documentation Support
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Product Folder Links: CC2630
CC2630
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8.7
SWRS177B – FEBRUARY 2015 – REVISED JULY 2016
Additional Information
Texas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and
standard-based wireless applications for use in industrial and consumer applications. The selection
includes RF transceivers, RF transmitters, RF front ends, and Systems-on-Chips as well as various
software solutions for the sub-1-GHz and 2.4-GHz frequency bands.
In addition, Texas Instruments provides a large selection of support collateral such as development tools,
technical documentation, reference designs, application expertise, customer support, third-party and
university programs.
The Low-Power RF E2E Online Community provides technical support forums, videos and blogs, and the
chance to interact with engineers from all over the world.
With a broad selection of product solutions, end-application possibilities, and a range of technical support,
Texas Instruments offers the broadest low-power RF portfolio.
8.8
Trademarks
SimpleLink, SmartRF, Code Composer Studio, E2E are trademarks of Texas Instruments.
ARM7 is a trademark of ARM Limited (or its subsidiaries).
ARM, Cortex, ARM Thumb are registered trademarks of ARM Limited (or its subsidiaries).
CoreMark is a registered trademark of Embedded Microprocessor Benchmark Consortium.
IAR Embedded Workbench is a registered trademark of IAR Systems AB.
IEEE Std 1241 is a trademark of Institute of Electrical and Electronics Engineers, Incorporated.
ZigBee is a registered trademark of ZigBee Alliance, Inc.
All other trademarks are the property of their respective owners.
8.9
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.10 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from Disclosing party under
this Agreement, or any direct product of such technology, to any destination to which such export or reexport is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from
U.S. Department of Commerce and other competent Government authorities to the extent required by
those laws.
8.11 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
9 Mechanical Packaging and Orderable Information
9.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2015–2016, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
Submit Documentation Feedback
Product Folder Links: CC2630
45
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CC2630F128RGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC2630
F128
CC2630F128RGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC2630
F128
CC2630F128RHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC2630
F128
CC2630F128RHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC2630
F128
CC2630F128RSMR
ACTIVE
VQFN
RSM
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC2630
F128
CC2630F128RSMT
ACTIVE
VQFN
RSM
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
CC2630
F128
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jun-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
CC2630F128RGZR
VQFN
RGZ
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
CC2630F128RGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
CC2630F128RHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
CC2630F128RHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
CC2630F128RSMR
VQFN
RSM
32
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
CC2630F128RSMT
VQFN
RSM
32
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC2630F128RGZR
VQFN
RGZ
48
2500
367.0
367.0
38.0
CC2630F128RGZT
VQFN
RGZ
48
250
210.0
185.0
35.0
CC2630F128RHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
CC2630F128RHBT
VQFN
RHB
32
250
210.0
185.0
35.0
CC2630F128RSMR
VQFN
RSM
32
3000
367.0
367.0
35.0
CC2630F128RSMT
VQFN
RSM
32
250
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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