IRF IRS2001PBF High and low side driver Datasheet

PRELIMINARY
Data Sheet No. PD60268
IRS2001(S)PbF
HIGH AND LOW SIDE DRIVER
Features
• Floating channel designed for bootstrap operation
• Fully operational to +200 V
• Tolerant to negative transient voltage, dV/dt immune
• Gate drive supply range from 10 V to 20 V
• Undervoltage lockout
• 3.3 V, 5 V, and 15 V logic input compatible
• Matched propagation delay for both channels
• Outputs in phase with inputs
Product Summary
VOFFSET
200 V max.
IO+/-
130 mA/270 mA
VOUT
10 V - 20 V
ton/off (typ.)
160 ns/150 ns
Delay Matching
50 ns
Description
The IRS2001 is a high voltage, high speed power
MOSFET and IGBT driver with independent high and
low side referenced output channels. Proprietary
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input
is compatible with standard CMOS or LSTTL output,
down to 3.3 V logic. The output drivers feature a high
pulse current buffer stage designed for minimum driver
cross-conduction. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the high
side configuration which operates up to 200 V.
Packages
8-Lead SOIC
IRS2001S
8-Lead PDIP
IRS2001
Typical Connection
IRS2001
(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
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1
IRS2001(S)PbF
PRELIMINARY
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
VB
High side floating supply voltage
VS
Min.
Max.
-0.3
225
High side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low side and logic fixed supply voltage
-0.3
25
VLO
Low side output voltage
-0.3
VCC + 0.3
VIN
Logic input voltage (HIN & LIN)
-0.3
VCC + 0.3
—
50
dVS/dt
PD
RthJA
Allowable offset supply voltage transient
Package power dissipation @ TA ≤ +25 °C
Thermal resistance, junction to ambient
(8 lead PDIP)
—
1.0
(8 lead SOIC)
—
0.625
(8 lead PDIP)
—
125
(8 lead SOIC)
—
200
TJ
Junction temperature
—
150
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
—
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at a 15 V differential.
Symbol
Definition
VB
High side floating supply absolute voltage
VS
High side floating supply offset voltage
Min.
Max.
VS + 10
VS + 20
Note 1
200
VHO
High side floating output voltage
VS
VB
VCC
Low side and logic fixed supply voltage
10
20
VLO
Low side output voltage
0
VCC
VIN
Logic input voltage (HIN & LIN)
0
VCC
TA
Ambient temperature
-40
125
Units
V
°C
Note 1: Logic operational for VS of -5 V to +200 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design
Tip DT97-3 for more details).
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2
IRS2001(S)PbF
PRELIMINARY
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, CL = 1000 pF and TA = 25 °C unless otherwise specified.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
ton
Turn-on propagation delay
—
160
220
VS = 0 V
toff
Turn-off propagation delay
—
150
220
VS = 200 V
tr
Turn-on rise time
—
70
170
tf
Turn-off fall time
—
35
90
Delay matching, HS & LS turn-on/off
—
—
50
MT
ns
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15 V and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to
COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
VIH
Logic “1” input voltage
2.5
—
—
VIL
Logic “0” input voltage
—
—
0.8
VOH
High level output voltage, VBIAS - VO
—
0.05
0.2
VOL
Low level output voltage, VO
—
0.02
0.1
ILK
Offset supply leakage current
—
—
50
IQBS
Quiescent VBS supply current
—
30
55
IQCC
Quiescent VCC supply current
—
150
270
IIN+
Logic “1” input bias current
—
3
10
VIN = 5 V
IIN-
VIN = 0 V
Logic “0” input bias current
—
—
1
VCCUV+
VCC supply undervoltage positive going threshold
8
8.9
9.8
VCCUV-
VCC supply undervoltage negative going threshold
7.4
8.2
9
Output high short circuit pulsed current
130
290
—
VCC = 10 V to 20 V
V
IO = 2 mA
VB = VS = 200 V
µA
VIN = 0 V or 5 V
V
VO = 0 V
IO+
mA
VIN = Logic “1”
PW ≤ 10 µs
VO = 15 V
IO-
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Output low short circuit pulsed current
270
600
—
VIN = Logic “0”
PW ≤ 10 µs
3
IRS2001(S)PbF
PRELIMINARY
Functional Block Diagram
IRS2001
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4
IRS2001(S)PbF
PRELIMINARY
Lead Definitions
Symbol
Description
HIN
Logic input for high side gate driver output (HO), in phase
LIN
Logic input for low side gate driver output (LO), in phase
VB
High side floating supply
HO
High side gate drive output
VS
High side floating supply return
VCC
Low side and logic fixed supply
LO
Low side gate drive output
COM
Low side return
Lead Assignments
8 Lead PDIP
8 Lead SOIC
IRS2001PbF
IRS2001SPbF
Part Number
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5
IRS2001(S)PbF
PRELIMINARY
!
!
"!
Figure 1. Input/Output Timing Diagram
#!
"!
#!
Figure 2. Switching Time Waveform Definitions
!
!
#!
"!
Figure 3. Delay Matching Waveform Definitions
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6
IRS2001(S)PbF
PRELIMINARY
500
Turn-On Delay Time (ns)
Turn-On Delay Time (ns)
500
400
300
200
100
Max.
Typ.
0
-50
400
Max.
300
200
Typ.
100
0
-25
0
25
50
75
100
125
10
12
Temperature (°C)
18
20
Figure 6B. Turn-On Time vs. Supply Voltage
5 00
Turn-Off Delay Time (ns)
500
400
300
200
100
4 00
3 00
M ax .
2 00
1 00
T yp .
0
0
2
4
6
8
0
10 12 14 16 18 20
-50
-25
0
25
Input Voltage (V)
50
75
1 00
1 25
Temperature (°C)
Figure 6C. Turn-On Time vs. Input Voltage
Figure 7A. Turn-Off Time vs. Temperature
500
Turn-Off Delay Time (ns)
500
Turn-Off Delay Time (ns)
16
VBIAS Supply Voltage (V)
Figure 6A. Turn-On Time vs. Temperature
Turn-On Delay Time (ns)
14
400
Max.
300
200
Typ.
100
400
300
Max.
200
100
Typ.
0
0
10
12
14
16
18
20
VBIAS Supply Voltage (V)
Figure 7B. Turn-Off Time vs. Supply Voltage
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0
2
4
6
8
10
12
14
16
18
20
Input Voltage (V)
Figure 7C. Turn-Off Time vs. Input Voltage
7
IRS2001(S)PbF
PRELIMINARY
500
Turn-On Rise Time (ns)
Turn-On Rise Time (ns)
500
400
300
200
Max.
100
400
300
Max.
200
100
Typ.
Typ.
0
0
-50
-25
0
25
50
75
100
10
125
12
Temperature (°C)
Figure 9A. Turn-On Rise Time vs. Temperature
Turn-Off Fall Time (ns)
Turn-Off Fall Time (ns)
18
20
200
150
100
Max.
50
150
100
Max.
50
Typ.
Typ.
0
0
-50
-25
0
25
50
75
100
125
10
12
Temperature (°C)
14
16
18
20
VBIAS Supply Voltage (V)
Figure 10A. Turn-Off Fall Time vs. Temperature
Figure 10B. Turn-Off Fall Time vs. Voltage
8
8
7
7
Input Voltage (V)
Input Voltage (V)
16
Figure 9B. Turn-On Rise Time vs. Voltage
200
6
5
4
3
2
14
VBIAS Supply Voltage (V)
Min.
1
6
5
4
3
Min.
2
1
0
-50
0
-25
0
25
50
75
100
o
Temperature ( C)
Figure 12A. Logic "1" Input Voltage
vs. Temperature
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125
10
12
14
16
18
20
VBIAS Supply Voltage (V)
Figure 12B. Logic "1" Input Voltage
vs. Voltage
8
IRS2001(S)PbF
4
4
3 .2
3.2
Input
(V))
InputVoltage
V o ltag e (V
Input
(V))
In p u tVoltage
V o lta g e (V
PRELIMINARY
2 .4
1 .6
M ax.
0 .8
2.4
1.6
M ax .
0.8
0
0
-50
-25
0
25
50
75
1 00
10
1 25
12
14
Temperature (°C)
0.4
0.3
Max.
0.1
Typ.
0.0
-25
0
25
50
Temperature (
75
100
125
High Level Output Voltage (V)
High Level Output Voltage (V)
0.5
-50
0.4
0.3
Max.
0.2
0.1
Typ.
0.0
10
Low Level Output Voltage (V)
Low Level Output Voltage (V)
Max.
Typ.
0.0
50
Temperature
75
100
( oC)
Figure 15A. Low Level Output Voltage
vs. Temperature
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18
20
V BIAS Supply V oltage (V )
0.2
25
16
Figure 14B. High Level Output
vs. Supply Voltage
0.3
0
14
Vcc Supply Voltage (V)
0.4
-25
12
o C)
0.5
-50
20
0.5
Figure 14A. High Level Output Voltage
vs. Temperature
0.1
18
Figure 13B. Logic "0" Input Voltage
vs. Supply Voltage
Figure 13A. Logic "0" Input Voltage
vs. Temperature
0.2
16
Vcc Supply Voltage (V)
125
0.5
0.4
0.3
0.2
Max.
0.1
Typ.
0
10
12
14
16
18
20
V BIAS Supply Voltage (V)
Figure 15B. Low level Output
vs.Supply Voltage
9
IRS2001(S)PbF
500
500
400
400
300
300
200
100
Offset Supply Leakage Current (µA )
(µA)
Offset Supply Leakage Current (µA)
(µA)
PRELIMINARY
200
100
M ax.
0
-50
-25
0
25
50
75
100
125
Max.
0
0
100
1 20
90
60
M ax .
30
T yp .
0
500
600
120
90
60
Max .
30
Ty p.
0
-50
-25
0
25
50
75
1 00
1 25
10
12
Temperature (°C)
14
16
18
20
VBS Floating Supply Voltage (V)
Figure 17B. VBS Supply Current
vs. Voltage
Figure 17A. VBS Supply Current
vs. Temperature
700
700
Vcc Supply Current (µA)
Vcc Supply Current (µA)
400
150
VBS Supply Current (µA)
VBS Supply Current (µA)
1 50
600
500
400
M ax.
200
100
300
Figure 16B. Offset Supply Current
vs. Voltage
Figure 16A. Offset Supply Current
vs. Temperature
300
200
VB Boost Voltage (V)
Temperature (°C)
Typ.
600
500
400
300
M ax.
200
100
Typ.
0
0
-5 0
-2 5
0
25
50
75
100
Temperature (°C)
Figure 18A. Vcc Supply Current
vs. Temperature
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125
10
12
14
16
18
20
Vcc Supply Voltage (V)
Figure 18B. Vcc Supply Current
vs. Voltage
10
IRS2001(S)PbF
PRELIMINARY
30
Logic 1” Input Current (µA)
Logic 1” Input Current (µA)
30
25
20
15
10
M ax.
5
Typ.
25
20
15
10
M ax.
5
Typ.
0
0
-5 0
-2 5
0
25
50
75
100
125
10
12
Figure 19A. Logic"1" Input Current
vs. Temperature
Logic “0” Input Current (µA)
Logic “0” Input Current (µA)
18
20
5
4
3
2
Max.
1
0
-50
-25
0
25
50
75
Temperature (°C)
100
4
3
2
Max.
1
0
10
125
Figure 20A. Logic "0" Input Current
vs. Temperature
12
14
16
Vcc Supply Voltage (V)
18
20
Figure 20B. Logic "0" Input Current
vs. Voltage
11
11
M ax.
VCC UVLO Threshold - (V)
VCC UVLO Threshold +(V)
16
Figure 19B. Logic"1" Input Current
vs. Voltage
5
10
9
14
Vcc Supply Voltage (V)
Temperature (°C)
Typ.
M in.
8
7
6
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 21A. Vcc Undervoltage Threshold(+)
vs. Temperature
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10
Max.
9
Typ.
8
7
Min.
6
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 21B. Vcc Undervoltage Threshold(-)
vs. Temperature
11
IRS2001(S)PbF
PRELIMINARY
500
Output Source Current (mA)
( )
Output Source Current (mA)
500
400
Typ.
300
200
Min.
100
0
400
300
200
Typ.
100
Min.
0
-50
-25
0
25
50
75
100
125
10
12
Temperature (°C)
Temperature ( C)
Figure 22A. Output Source Current
vs. Temperature
16
18
20
Figure 22B. Output Source Current
vs. Supply Voltage
1000
1000
800
Output Sink Current (mA)
Output Sink Current (mA)
14
VBIAS Supply Voltage (V)
o
Typ.
600
400
Min.
200
0
-50
800
600
400
Typ.
200
Min.
0
-25
0
25
50
75
100
C)
Temperature (°C)
Figure 23A. Output Sink Current
vs. Temperature
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125
10
12
14
16
18
20
VBIAS Supply Voltage (V)
Figure 23B. Output Sink Current
vs. Supply Voltage
12
IRS2001(S)PbF
PRELIMINARY
Case Outlines
01-6014
01-3003 01 (MS-001AB)
8 Lead PDIP
D
DIM
B
5
A
FOOTPRINT
8
6
7
6
5
H
E
1
6X
2
3
0.25 [.010]
4
e
A
6.46 [.255]
3X 1.27 [.050]
e1
0.25 [.010]
A1
.0688
1.35
1.75
A1 .0040
.0098
0.10
0.25
b
.013
.020
0.33
0.51
c
.0075
.0098
0.19
0.25
D
.189
.1968
4.80
5.00
.1574
3.80
4.00
E
.1497
e
.050 BASIC
e1
MAX
1.27 BASIC
.025 BASIC
0.635 BASIC
H
.2284
.2440
5.80
6.20
K
.0099
.0196
0.25
0.50
L
.016
.050
0.40
1.27
y
0°
8°
0°
8°
y
0.10 [.004]
8X L
8X c
7
C A B
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA.
8 Lead SOIC
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MIN
.0532
K x 45°
A
C
8X b
8X 1.78 [.070]
MILLIMETERS
MAX
A
8X 0.72 [.028]
INCHES
MIN
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
01-6027
01-0021 11 (MS-012AA)
13
IRS2001(S)PbF
PRELIMINARY
Tape & Reel
8-lead SOIC
LOAD ED TA PE FEED DIRECTION
A
B
H
D
F
C
N OT E : CO NTROLLING
D IM ENSION IN MM
E
G
C A R R I E R T A P E D IM E N S I O N F O R 8 S O I C N
M etr ic
Im p er i al
Co d e
M in
M ax
M in
M ax
A
7 .9 0
8.1 0
0. 31 1
0 .3 18
B
3 .9 0
4.1 0
0. 15 3
0 .1 61
C
11 .7 0
1 2. 30
0 .4 6
0 .4 84
D
5 .4 5
5.5 5
0. 21 4
0 .2 18
E
6 .3 0
6.5 0
0. 24 8
0 .2 55
F
5 .1 0
5.3 0
0. 20 0
0 .2 08
G
1 .5 0
n/ a
0. 05 9
n/ a
H
1 .5 0
1.6 0
0. 05 9
0 .0 62
F
D
C
B
A
E
G
H
R E E L D IM E N S I O N S F O R 8 S O IC N
M etr ic
Im p er i al
Co d e
M in
M ax
M in
M ax
A
32 9. 60
3 30 .2 5
1 2 .9 76
13 .0 0 1
B
20 .9 5
2 1. 45
0. 82 4
0 .8 44
C
12 .8 0
1 3. 20
0. 50 3
0 .5 19
D
1 .9 5
2.4 5
0. 76 7
0 .0 96
E
98 .0 0
1 02 .0 0
3. 85 8
4 .0 15
F
n /a
1 8. 40
n /a
0 .7 24
G
14 .5 0
1 7. 10
0. 57 0
0 .6 73
H
12 .4 0
1 4. 40
0. 48 8
0 .5 66
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14
IRS2001(S)PbF
PRELIMINARY
LEADFREE PART MARKING INFORMATION
Part number
Date code
IRSxxxxx
YWW?
?XXXX
Pin 1
Identifier
?
P
IR logo
MARKING CODE
Lead Free Released
Non-Lead Free
Released
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
ORDER INFORMATION
8-Lead PDIP IRS2001PbF
8-Lead SOIC IRS2001SPbF
8-Lead SOIC Tape & Reel IRS2001STRPbF
The SOIC-8 is MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com <http://www.irf.com/>
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 6/28/2006
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15
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