ALSC AS7C31025-12JI 5v/3.3v 128k x8 cmos sram (revolutionary pinout) Datasheet

March 2001
AS7C1025
AS7C31025
®
5V/3.3V 128Kx8 CMOS SRAM (Revolutionary pinout)
Features
• Low power consumption: STANDBY
• AS7C1025 (5V version)
• AS7C31025 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
- 27.5 mW (AS7C1025) / max CMOS (5V)
- 1.8 mW (AS7C31025) / max CMOS (3.3V)
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin TSOP II
- 715 mW (AS7C1025) / max @ 12 ns (5V)
- 360 mW (AS7C31025) / max @ 12 ns (3.3V)
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
Pin arrangement
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
GND
I/O7
I/O0
Control
circuit
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
WE
OE
CE
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A9
A10
A11
A12
A13
A14
A15
A16
Column decoder
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AS7C1025
AS7C31025
512×256×8
Array
(1,048,576)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
A8
Row decoder
Input buffer
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AS7C1025
AS7C31025
32-pin TSOP II
VCC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
Selection guide
AS7C1025-12
AS7C31025-12
AS7C1025-15
AS7C31025-15
AS7C1025-20
AS7C31025-20
Unit
Maximum address access time
12
15
20
ns
Maximum output enable access time
3
4
5
ns
AS7C1025
130
85
80
mA
AS7C31025
100
85
80
mA
AS7C1025
5
5
5
mA
AS7C31025
5
5
5
mA
Maximum operating current
Maximum CMOS standby current
Shaded areas contain advance information.
3/23/01; v.1.0
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AS7C1025
AS7C31025
®
Functional description
The AS7C1025 and AS7C31025 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 131,072 words × 8 bits. They are designed for memory applications where fast data access, low power, and
simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6,7,8 ns are ideal
for high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank
memory systems.
When CE is high the devices enter standby mode. The standard AS7C1025 is guaranteed not to exceed 27.5 mW power
consumption in standby mode, and typically requires only 5 mW. Both devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O7 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1025) or 3.3V supply
(AS7C31025). The AS7C1025 and AS7C31025 are packaged in common industry standard packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
Max
Unit
AS7C1025
Vt1
–0.50
+7.0
V
AS7C31025
Vt1
–0.50
+5.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC + 0.5
V
Power dissipation
PD
–
1.0
Voltage on VCC relative to GND
Storage temperature (plastic)
Tstg
–65
W
+150
o
C
Ambient temperature with VCC applied
Tbias
–55
+125
oC
DC current into outputs (low)
IOUT
–
20
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
Data
Mode
H
X
X
High Z
Standby (ISB, ISB1)
L
H
H
High Z
Output disable (ICC)
L
H
L
DOUT
Read (ICC)
L
L
X
DIN
Write (ICC)
Key: X = Don’t Care, L = Low, H = High
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AS7C1025
AS7C31025
®
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Device
Symbol
Min
Nominal
Max
Unit
AS7C1025
VCC
4.5
5.0
5.5
V
AS7C31025
VCC
3.0
3.3
3.6
V
AS7C1025
VIH
2.2
–
VCC + 0.5
V
AS7C31025
VIH
2.0
–
VCC + 0.5
V
–0.5
–
0.8
V
VIL
Ambient operating temperature
†
†
commercial
TA
0
–
70
oC
industrial
TA
–40
–
85
o
C
VIL min = –3.0V for pulse width less than tRC/2.
DC operating characteristics (over the operating range)1
-12
Parameter
Sym
Test conditions
-20
Min
Max
Min
Max
Min
Max
Unit
Input leakage
| ILI | VCC = Max, VIN = GND to VCC
current
–
1
–
1
–
1
µA
Output
leakage
current
–
1
–
1
–
1
µA
AS7C1025
–
130
–
120
–
110
AS7C31025
–
100
–
85
–
80
AS7C1025
–
50
–
40
–
40
AS7C31025
–
50
–
40
–
40
AS7C1025
CE ≥ VCC–0.2V, VIN ≤ 0.2V or
VIN ≥ VCC –0.2V, f = 0, fOUT = 0 AS7C31025
–
5
–
5
–
5
–
5
–
5
–
5
| ILO |
VCC = Max, CE = VIH, Vout =
GND to VCC
ICC
CE = VIL, f = fMax, IOUT = 0 mA
Operating
power supply
current
ISB
Standby
power supply
current1
ISB1
Output
voltage
CE = VIH, f = fMax, fOUT = 0
Device
-15
mA
mA
mA
VOL
IOL = 8 mA, VCC = Min
–
0.4
–
0.4
–
0.4
V
VOH
IOH = –4 mA, VCC = Min
2.4
–
2.4
–
2.4
–
V
Shaded areas contain advance information.
Capacitance (f = 1 MHz, Ta = 25 oC, VCC = NOMINAL)2
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
A, CE, WE, OE
VIN = 0V
5
pF
I/O capacitance
CI/O
I/O
VIN = VOUT = 0V
7
pF
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AS7C1025
AS7C31025
®
Read cycle (over the operating range)3,9
-12
Parameter
-15
-20
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read cycle time
tRC
12
–
15
–
20
–
ns
Address access time
tAA
–
12
–
15
–
20
ns
3
Chip enable (CE) access time
tACE
–
12
–
15
–
20
ns
3
Output enable (OE) access time
tOE
–
6
–
7
–
8
ns
Output hold from address change
tOH
3
–
3
–
3
–
ns
5
CE Low to output in low Z
tCLZ
0
–
0
–
0
–
ns
4, 5
CE Low to output in high Z
tCHZ
–
3
–
4
–
5
ns
4, 5
OE Low to output in low Z
tOLZ
0
–
0
–
0
–
ns
4, 5
OE High to output in high Z
tOHZ
–
3
–
4
–
5
ns
4, 5
Power up time
tPU
0
–
0
–
0
–
ns
4, 5
Power down time
tPD
–
12
–
15
–
20
ns
4, 5
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
3,6,7,9
Read waveform 1 (address controlled)
tRC
Address
tAA
tOH
DOUT
Data valid
Read waveform 2 (CE and OE controlled)3,6,8,9
tRC1
CE
tOE
OE
tACE
DOUT
Data valid
tCLZ
Supply
current
3/23/01; v.1.0
tOHZ
tCHZ
tOLZ
tPU
tPD
50%
50%
Alliance Semiconductor
ICC
ISB
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AS7C1025
AS7C31025
®
Write cycle (over the operating range)11
-12
Parameter
-15
-20
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write cycle time
tWC
12
–
15
–
20
–
ns
Chip enable (CE) to write end
tCW
8
–
12
–
12
–
ns
Address setup to write end
tAW
8
–
12
–
12
–
ns
Address setup time
tAS
0
–
0
–
0
–
ns
Write pulse width
tWP
8
–
9
–
12
–
ns
Address hold from end of write
tAH
0
–
0
–
0
–
ns
Data valid to write end
tDW
6
–
8
–
12
–
ns
Data hold time
tDH
0
–
0
–
0
–
ns
4, 5
Write enable to output in high Z
tWZ
–
5
–
5
–
5
ns
4, 5
Output active from write end
tOW
3
–
3
–
3
–
ns
4, 5
Shaded areas contain advance information.
Write waveform 1 ( WE controlled)10,11
tWC
tAW
tAH
Address
tWP
WE
tAS
tDW
DIN
tDH
Data valid
tWZ
tOW
DOUT
Write waveform 2 (CE controlled)10,11
tAW
tWC
tAH
Address
tAS
tCW
CE
tWP
WE
tWZ
DIN
tDW
tDH
Data valid
DOUT
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AS7C1025
AS7C31025
®
Data retention characteristics (over the operating range)13
Parameter
Symbol
VCC for data retention
VDR
Data retention current
ICCDR
Chip enable to data retention time
tCDR
Operation recovery time
Test conditions
Max
Unit
2.0
–
V
–
500
µA
0
–
ns
tRC
–
ns
–
1
µA
VCC = 2.0V
CE ≥ VCC – 0.2V
VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V
tR
| ILI |
Input leakage current
Min
Data retention waveform
Data retention mode
VCC
VDR ≥ 2.0V
VCC
VCC
tCDR
tR
VDR
VIH
CE
VIH
AC test conditions
–
–
–
–
5V output load: see Figure B or Figure C.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
Thevenin equivalent:
168W
DOUT
+1.728V (5V and 3.3V)
+5V
+3.3V
480W
+3.0V
GND
90%
10%
90%
2 ns
Figure A: Input pulse
10%
DOUT
255W
C(14)
GND
Figure B: 5V Output load
320W
DOUT
255W
C(14)
GND
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, and C.
tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
NA.
2V data retention applies to commercial temperature operating range only.
C=30pF, except all high Z and low Z parameters, where C=5pF.
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AS7C1025
AS7C31025
®
Typical DC and AC characteristics
1.2
ICC
1.0
Normalized ICC, ISB
0.8
0.6
ISB
0.4
0.2
NOMINAL
Supply voltage (V)
0.8
0.6
ISB
0.4
Normalized access time
Ta = 25° C
1.2
1.1
1.0
0.9
NOMINAL
Supply voltage (V)
Output source current IOH
vs. output voltage VOH
140
1.3
VCC = VCC(NOMINAL)
1.2
1.1
1.0
Output sink current (mA)
VCC = VCC(NOMINAL)
100
Ta = 25° C
80
60
40
20
0
VCC
Output voltage (V)
3/23/01; v.1.0
125
Normalized supply current ICC
vs. cycle frequency 1/tRC, 1/tWC
VCC = VCC(NOMINAL)
1.0
Ta = 25° C
0.8
0.6
0.4
0.0
–10
35
80
125
Ambient temperature (°C)
0
25
50
75
Cycle frequency (MHz)
100
Typical access time change ∆tAA
vs. output capacitive loading
Output sink current IOL
vs. output voltage VOL
35
120
30
VCC = VCC(NOMINAL)
100
Ta = 25° C
80
60
40
20
VCC = VCC(NOMINAL)
25
20
15
10
5
0
0
-10
35
80
Ambient temperature (°C)
0.2
140
120
0.2
1.2
0.8
–55
MAX
1
1.4
0.9
0.8
MIN
VCC = VCC(NOMINAL)
5
-55
1.4
1.3
25
–10
35
80
125
Ambient temperature (°C)
Normalized access time tAA
vs. ambient temperature Ta
1.5
1.4
625
0.04
0.0
–55
MAX
Normalized access time tAA
vs. supply voltage VCC
1.5
Normalized access time
1.0
0.2
0.0
MIN
Output source current (mA)
ICC
Normalized ICC
Normalized ICC, ISB
1.2
Normalized supply current ISB1
vs. ambient temperature Ta
Normalized ISB1 (log scale)
1.4
Normalized supply current ICC, ISB
vs. ambient temperature Ta
Change in tAA (ns)
1.4
Normalized supply current ICC, ISB
vs. supply voltage VCC
0
0
VCC
Output voltage (V)
Alliance Semiconductor
0
250
500
750
Capacitance (pF)
P. 7 of 9
1000
AS7C1025
AS7C31025
®
Package dimensions
N
N/2+1
Symbol
Min
Max
A
–
1.2
A1
0.05
0.15
b
0.3
0.52
C
0.12
0.21
D
20.82
21.08
E1
10.03
10.29
E
11.56
11.96
E
E1
1
32-pin TSOP II (mil)
32-pin TSOP II
N/2
D
Seating plane
A
e
ZD
1.27 BSC
L
0.40
ZD
0.95 REF.
α
c
0.60
0°
5°
A1
b
L
α
c
32-pin SOJ
300 mil
32-pin SOJ
300 mil/400 mil
e
D
B
A
E1 E2 A1
Seating
Plane
b
Pin 1
c
A2
E
3/23/01; v.1.0
Alliance Semiconductor
32-pin SOJ
400 mil
Symbol
Min
Max
Min
Max
A
-
0.145
-
0.145
A1
0.025
-
0.025
-
A2
0.086
0.105
0.086
0.115
B
0.026
0.032
0.026
0.032
b
0.014
0.020
0.015
0.020
c
0.006
0.013
0.007
0.013
D
0.820
0.830
0.820
0.830
E
0.250
0.275
0.360
0.380
E1
0.292
0.305
0.395
0.405
E2
0.330
0.340
0.435
0.445
P. 8 of 9
AS7C1025
AS7C31025
®
Ordering codes
Package \ Access time
Voltage
5V
sTSOP II
3.3V
5V
300-mil SOJ
3.3V
5V
400-mil SOJ
3.3V
Temperature
12 ns
15 ns
20 ns
Commercial
AS7C1025-12TC
AS7C1025-15TC
AS7C1025-20TC
Industrial
AS7C1025-12TI
AS7C1025-15TI
AS7C1025-20TI
Commercial
AS7C31025-12TC
AS7C31025-15TC
AS7C31025-20TC
Industrial
AS7C31025-12TI
AS7C31025-15TI
AS7C31025-20TI
Commercial
AS7C1025-12TJC
AS7C1025-15TJC
AS7C1025-20TJC
Industrial
AS7C1025-12TJI
AS7C1025-15TJI
AS7C1025-20TJI
Commercial
AS7C31025-12TJC
AS7C31025-15TJC
AS7C31025-20TJC
Industrial
AS7C31025-12TJI
AS7C31025-15TJI
AS7C31025-20TJI
Commercial
AS7C1025-12JC
AS7C1025-15JC
AS7C1025-20JC
Industrial
AS7C1025-12JI
AS7C1025-15JI
AS7C1025-20JI
Commercial
AS7C31025-12JC
AS7C31025-15JC
AS7C31025-20JC
Industrial
AS7C31025-12JI
AS7C31025-15JI
AS7C31025-20JI
Part numbering system
AS7C
X
1025
–XX
X
X
SRAM
prefix
Blank=5V CMOS
3=3.3V CMOS
Device
number
Access
time
Package:
T = TSOP II
J = SOJ
Temperature range
C = Commercial, 0°C to 70°C
I = Industrial, -40°C to 85°C
3/23/01; v.1.0
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appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the
product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential
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